From 186fc4061ada2e9dd35404435c443291c4ad45fb Mon Sep 17 00:00:00 2001 From: trickybestia Date: Thu, 8 Feb 2024 11:23:30 +0300 Subject: [PATCH] Clean root directory by moving some files to resources --- .gitignore | 4 ++-- create_blueprint/yosys.py | 12 ++++++------ buf_map.sv => resources/buf_map.sv | 0 ff_map.sv => resources/ff_map.sv | 0 4 files changed, 8 insertions(+), 8 deletions(-) rename buf_map.sv => resources/buf_map.sv (100%) rename ff_map.sv => resources/ff_map.sv (100%) diff --git a/.gitignore b/.gitignore index aa0675e..7c38114 100644 --- a/.gitignore +++ b/.gitignore @@ -2,5 +2,5 @@ __pycache__ /blueprints -/scrap_mechanic_cells.lib -/scrap_mechanic_cells.sv +/resources/scrap_mechanic_cells.lib +/resources/scrap_mechanic_cells.sv diff --git a/create_blueprint/yosys.py b/create_blueprint/yosys.py index 008a8dc..1dfe421 100644 --- a/create_blueprint/yosys.py +++ b/create_blueprint/yosys.py @@ -85,13 +85,13 @@ def _create_yosys_script( dfflegalize -cell $_DFF_P_ x opt -nodffe -nosdff -full -techmap -map ff_map.sv +techmap -map resources/ff_map.sv techmap; opt -full -abc -liberty scrap_mechanic_cells.lib -dff -techmap -map buf_map.sv +abc -liberty resources/scrap_mechanic_cells.lib -dff +techmap -map resources/buf_map.sv opt -full -{f"show -lib scrap_mechanic_cells.sv -format dot -viewer none -stretch -prefix {module_flowchart_prefix} {top_module}" if module_flowchart_prefix is not None else ""} +{f"show -lib resources/scrap_mechanic_cells.sv -format dot -viewer none -stretch -prefix {module_flowchart_prefix} {top_module}" if module_flowchart_prefix is not None else ""} write_json {blueprints_path / top_module / f"{top_module}.json"} stat """ @@ -104,8 +104,8 @@ def compile( module_flowchart_prefix: Union[str, None], blueprints_path: Path, ) -> str: - Path("scrap_mechanic_cells.lib").write_text(_create_cells_liberty(cells)) - Path("scrap_mechanic_cells.sv").write_text(_create_cells_verilog(cells)) + Path("resources/scrap_mechanic_cells.lib").write_text(_create_cells_liberty(cells)) + Path("resources/scrap_mechanic_cells.sv").write_text(_create_cells_verilog(cells)) run( ["yosys", "-s", "-"], diff --git a/buf_map.sv b/resources/buf_map.sv similarity index 100% rename from buf_map.sv rename to resources/buf_map.sv diff --git a/ff_map.sv b/resources/ff_map.sv similarity index 100% rename from ff_map.sv rename to resources/ff_map.sv