A model merging project for generalizing Featured Finite State Machines (FFSMs) to unify behaviors across Software Product Lines (SPLs)
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Nov 2, 2024 - Java
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behavioral-modeling
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This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
circuit-simulation
verilog-hdl
test-bench
half-adder
hardware-description-language
digital-electronics
full-adder
verilog-project
vlsi-design
rtl-design
arithmetic-operations
fpga-verilog
logic-circuit-design
behavioral-modeling
4-bit-adder
verilog-adders
gate-level-design
dataflow-design
digital-circuit-simulation
hdl-coding
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Aug 24, 2024 - Verilog
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
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Dec 25, 2022 - Verilog
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