From 9586542cebda21e867dd05a026b5dae229e6c106 Mon Sep 17 00:00:00 2001 From: Eero Nurkkala Date: Fri, 29 Nov 2024 12:14:08 +0200 Subject: [PATCH] risc-v/mpfs: clear IPIs at boot Inter-processor interrupts (IPIs) are not cleared via mie/mip registers but rather, at the MPFS_CLINT_BASE + mhartid * 4 (a word or 4-byte offset for each hart). If there's an IPI waiting, the system will continue to boot altough it's expected to stay at the wfi loop waiting for the IPI. Signed-off-by: Eero Nurkkala --- arch/risc-v/src/mpfs/mpfs_head.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S index e691be33f56d9..77fc982d3aa42 100644 --- a/arch/risc-v/src/mpfs/mpfs_head.S +++ b/arch/risc-v/src/mpfs/mpfs_head.S @@ -49,6 +49,14 @@ __start: csrw CSR_MIE, zero csrw CSR_MIP, zero + /* Clear all IPIs (above doesn't clear them) */ + + csrr a0, CSR_MHARTID + slli t1, a0, 2 + li t0, MPFS_CLINT_BASE + add t1, t1, t0 + sw zero, 0(t1) + /* Initialize the Machine Trap Vector */ la t0, __trap_vec