From 2855c84c3af1dfe9f68bb7f7b73fbca784f5b72e Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Fri, 15 Dec 2023 12:19:50 +0200 Subject: [PATCH] mpfs_pmpcfg: Move PMPCFG registers to common location --- arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h | 98 +++++++++++++++++++++ arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h | 32 ------- arch/risc-v/src/mpfs/mpfs_ddr.c | 1 + arch/risc-v/src/mpfs/mpfs_emmcsd.c | 7 +- arch/risc-v/src/mpfs/mpfs_ethernet.c | 12 +-- arch/risc-v/src/mpfs/mpfs_ethernet.h | 2 - arch/risc-v/src/mpfs/mpfs_usb.c | 8 +- 7 files changed, 105 insertions(+), 55 deletions(-) create mode 100644 arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h b/arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h new file mode 100644 index 0000000000000..e7aaecdf798d7 --- /dev/null +++ b/arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/hardware/mpfs_mpucfg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_MPUCFG_H +#define __ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_MPUCFG_H + +/* FIC1 (FPGA) PMP configurations - for fabric memory transfers */ + +#define MPFS_PMPCFG_FIC1_0 (MPFS_MPUCFG_BASE + 0x100) +#define MPFS_PMPCFG_FIC1_1 (MPFS_MPUCFG_BASE + 0x108) +#define MPFS_PMPCFG_FIC1_2 (MPFS_MPUCFG_BASE + 0x110) +#define MPFS_PMPCFG_FIC1_3 (MPFS_MPUCFG_BASE + 0x118) +#define MPFS_PMPCFG_FIC1_4 (MPFS_MPUCFG_BASE + 0x120) +#define MPFS_PMPCFG_FIC1_5 (MPFS_MPUCFG_BASE + 0x128) +#define MPFS_PMPCFG_FIC1_6 (MPFS_MPUCFG_BASE + 0x130) +#define MPFS_PMPCFG_FIC1_7 (MPFS_MPUCFG_BASE + 0x138) +#define MPFS_PMPCFG_FIC1_8 (MPFS_MPUCFG_BASE + 0x140) +#define MPFS_PMPCFG_FIC1_9 (MPFS_MPUCFG_BASE + 0x148) +#define MPFS_PMPCFG_FIC1_10 (MPFS_MPUCFG_BASE + 0x150) +#define MPFS_PMPCFG_FIC1_11 (MPFS_MPUCFG_BASE + 0x158) +#define MPFS_PMPCFG_FIC1_12 (MPFS_MPUCFG_BASE + 0x160) +#define MPFS_PMPCFG_FIC1_13 (MPFS_MPUCFG_BASE + 0x168) +#define MPFS_PMPCFG_FIC1_14 (MPFS_MPUCFG_BASE + 0x170) +#define MPFS_PMPCFG_FIC1_15 (MPFS_MPUCFG_BASE + 0x178) + +/* Crpyto PMP configurations - for DMA transfers */ + +#define MPFS_PMPCFG_CRYPTO_0 (MPFS_MPUCFG_BASE + 0x300) +#define MPFS_PMPCFG_CRYPTO_1 (MPFS_MPUCFG_BASE + 0x308) +#define MPFS_PMPCFG_CRYPTO_2 (MPFS_MPUCFG_BASE + 0x310) +#define MPFS_PMPCFG_CRYPTO_3 (MPFS_MPUCFG_BASE + 0x318) + +/* Ethernet PMP configurations - for DMA transfers */ + +#define MPFS_PMPCFG_ETH0_0 (MPFS_MPUCFG_BASE + 0x400) +#define MPFS_PMPCFG_ETH0_1 (MPFS_MPUCFG_BASE + 0x408) +#define MPFS_PMPCFG_ETH0_2 (MPFS_MPUCFG_BASE + 0x410) +#define MPFS_PMPCFG_ETH0_3 (MPFS_MPUCFG_BASE + 0x418) +#define MPFS_PMPCFG_ETH1_0 (MPFS_MPUCFG_BASE + 0x500) +#define MPFS_PMPCFG_ETH1_1 (MPFS_MPUCFG_BASE + 0x508) +#define MPFS_PMPCFG_ETH1_2 (MPFS_MPUCFG_BASE + 0x510) +#define MPFS_PMPCFG_ETH1_3 (MPFS_MPUCFG_BASE + 0x518) + +/* USB PMP configurations - for DMA transfers */ + +#define MPFS_PMPCFG_USB_0 (MPFS_MPUCFG_BASE + 0x600) +#define MPFS_PMPCFG_USB_1 (MPFS_MPUCFG_BASE + 0x608) +#define MPFS_PMPCFG_USB_2 (MPFS_MPUCFG_BASE + 0x610) +#define MPFS_PMPCFG_USB_3 (MPFS_MPUCFG_BASE + 0x618) + +/* MMC PMP configurations - for DMA transfers */ + +#define MPFS_PMPCFG_MMC_0 (MPFS_MPUCFG_BASE + 0x700) +#define MPFS_PMPCFG_MMC_1 (MPFS_MPUCFG_BASE + 0x708) +#define MPFS_PMPCFG_MMC_2 (MPFS_MPUCFG_BASE + 0x710) +#define MPFS_PMPCFG_MMC_3 (MPFS_MPUCFG_BASE + 0x718) + +/* DDR segments - set up by mpfs_ddr.c */ + +#define MPFS_MPUCFG_SEG0_REG0 (MPFS_MPUCFG_BASE + 0xd00) +#define MPFS_MPUCFG_SEG0_REG1 (MPFS_MPUCFG_BASE + 0xd08) +#define MPFS_MPUCFG_SEG0_REG2 (MPFS_MPUCFG_BASE + 0xd10) +#define MPFS_MPUCFG_SEG0_REG3 (MPFS_MPUCFG_BASE + 0xd18) +#define MPFS_MPUCFG_SEG0_REG4 (MPFS_MPUCFG_BASE + 0xd20) +#define MPFS_MPUCFG_SEG0_REG5 (MPFS_MPUCFG_BASE + 0xd28) +#define MPFS_MPUCFG_SEG0_REG6 (MPFS_MPUCFG_BASE + 0xd30) + +#define MPFS_MPUCFG_SEG1_REG0 (MPFS_MPUCFG_BASE + 0xe00) +#define MPFS_MPUCFG_SEG1_REG1 (MPFS_MPUCFG_BASE + 0xe08) +#define MPFS_MPUCFG_SEG1_REG2 (MPFS_MPUCFG_BASE + 0xe10) +#define MPFS_MPUCFG_SEG1_REG3 (MPFS_MPUCFG_BASE + 0xe18) +#define MPFS_MPUCFG_SEG1_REG4 (MPFS_MPUCFG_BASE + 0xe20) +#define MPFS_MPUCFG_SEG1_REG5 (MPFS_MPUCFG_BASE + 0xe28) +#define MPFS_MPUCFG_SEG1_REG6 (MPFS_MPUCFG_BASE + 0xe30) + +/* Size of the register area, which is 4K */ + +#define MPFS_MPUCFG_SIZE (0x1000) +#define MPFS_MPUCFG_END (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SIZE) + +#endif /* __NUTTX_ARCH_RISC_V_SRC_MPFS_HARDWARE_MPFS_MPUCFG_H */ diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h b/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h index 126ace313667b..c8ce99761166b 100644 --- a/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h +++ b/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h @@ -31,38 +31,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define MPFS_MPUCFG_SEG0_REG0_OFFSET 0xd00 -#define MPFS_MPUCFG_SEG0_REG1_OFFSET 0xd08 -#define MPFS_MPUCFG_SEG0_REG2_OFFSET 0xd10 -#define MPFS_MPUCFG_SEG0_REG3_OFFSET 0xd18 -#define MPFS_MPUCFG_SEG0_REG4_OFFSET 0xd20 -#define MPFS_MPUCFG_SEG0_REG5_OFFSET 0xd28 -#define MPFS_MPUCFG_SEG0_REG6_OFFSET 0xd30 - -#define MPFS_MPUCFG_SEG1_REG0_OFFSET 0xe00 -#define MPFS_MPUCFG_SEG1_REG1_OFFSET 0xe08 -#define MPFS_MPUCFG_SEG1_REG2_OFFSET 0xe10 -#define MPFS_MPUCFG_SEG1_REG3_OFFSET 0xe18 -#define MPFS_MPUCFG_SEG1_REG4_OFFSET 0xe20 -#define MPFS_MPUCFG_SEG1_REG5_OFFSET 0xe28 -#define MPFS_MPUCFG_SEG1_REG6_OFFSET 0xe30 - -#define MPFS_MPUCFG_SEG0_REG0 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG0_OFFSET) -#define MPFS_MPUCFG_SEG0_REG1 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG1_OFFSET) -#define MPFS_MPUCFG_SEG0_REG2 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG2_OFFSET) -#define MPFS_MPUCFG_SEG0_REG3 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG3_OFFSET) -#define MPFS_MPUCFG_SEG0_REG4 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG4_OFFSET) -#define MPFS_MPUCFG_SEG0_REG5 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG5_OFFSET) -#define MPFS_MPUCFG_SEG0_REG6 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG0_REG6_OFFSET) - -#define MPFS_MPUCFG_SEG1_REG0 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG0_OFFSET) -#define MPFS_MPUCFG_SEG1_REG1 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG1_OFFSET) -#define MPFS_MPUCFG_SEG1_REG2 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG2_OFFSET) -#define MPFS_MPUCFG_SEG1_REG3 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG3_OFFSET) -#define MPFS_MPUCFG_SEG1_REG4 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG4_OFFSET) -#define MPFS_MPUCFG_SEG1_REG5 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG5_OFFSET) -#define MPFS_MPUCFG_SEG1_REG6 (MPFS_MPUCFG_BASE + MPFS_MPUCFG_SEG1_REG6_OFFSET) - #define MPFS_IOSCBCFG_TIMER_OFFSET 0x08 #define MPFS_SYSREGSCB_MSS_RESET_CR_OFFSET 0x100 diff --git a/arch/risc-v/src/mpfs/mpfs_ddr.c b/arch/risc-v/src/mpfs/mpfs_ddr.c index d4b2f43252ca2..3819fba3a91f5 100644 --- a/arch/risc-v/src/mpfs/mpfs_ddr.c +++ b/arch/risc-v/src/mpfs/mpfs_ddr.c @@ -48,6 +48,7 @@ #include "hardware/mpfs_sysreg.h" #include "hardware/mpfs_ddr.h" #include "hardware/mpfs_sgmii.h" +#include "hardware/mpfs_mpucfg.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/mpfs/mpfs_emmcsd.c b/arch/risc-v/src/mpfs/mpfs_emmcsd.c index 873fc4ddb09ac..267894dc81c1e 100644 --- a/arch/risc-v/src/mpfs/mpfs_emmcsd.c +++ b/arch/risc-v/src/mpfs/mpfs_emmcsd.c @@ -48,6 +48,7 @@ #include "mpfs_emmcsd.h" #include "riscv_internal.h" #include "hardware/mpfs_emmcsd.h" +#include "hardware/mpfs_mpucfg.h" /**************************************************************************** * Pre-processor Definitions @@ -83,11 +84,6 @@ #define MPFS_SYSREG_SUBBLK_CLOCK_CR (MPFS_SYSREG_BASE + \ MPFS_SYSREG_SUBBLK_CLOCK_CR_OFFSET) -#define MPFS_PMPCFG_MMC_0 (MPFS_MPUCFG_BASE + 0x700) -#define MPFS_PMPCFG_MMC_1 (MPFS_MPUCFG_BASE + 0x708) -#define MPFS_PMPCFG_MMC_2 (MPFS_MPUCFG_BASE + 0x710) -#define MPFS_PMPCFG_MMC_3 (MPFS_MPUCFG_BASE + 0x718) - #define MPFS_MMC_CLOCK_400KHZ 400u #define MPFS_MMC_CLOCK_12_5MHZ 12500u #define MPFS_MMC_CLOCK_25MHZ 25000u @@ -233,6 +229,7 @@ MPFS_EMMCSD_SRS14_TC_IE) /* SD-Card IOMUX */ + #define LIBERO_SETTING_IOMUX1_CR_SD 0x00000000UL #ifdef CONFIG_MPFS_EMMCSD_MUX_GPIO #define LIBERO_SETTING_IOMUX2_CR_SD 0X00BB0000UL diff --git a/arch/risc-v/src/mpfs/mpfs_ethernet.c b/arch/risc-v/src/mpfs/mpfs_ethernet.c index 5e4fd4c36bf42..ce2795f30a63b 100644 --- a/arch/risc-v/src/mpfs/mpfs_ethernet.c +++ b/arch/risc-v/src/mpfs/mpfs_ethernet.c @@ -58,6 +58,9 @@ #include "mpfs_dsn.h" #include "mpfs_i2c.h" +#include "hardware/mpfs_ethernet.h" +#include "hardware/mpfs_mpucfg.h" + #if defined(CONFIG_MPFS_ETH0_PHY_KSZ9477) ||\ defined(CONFIG_MPFS_ETH1_PHY_KSZ9477) # if !defined(CONFIG_MPFS_MAC_SGMII) @@ -78,15 +81,6 @@ #if defined(CONFIG_NET) && defined(CONFIG_MPFS_ETHMAC) -#define MPFS_PMPCFG_ETH0_0 (MPFS_MPUCFG_BASE + 0x400) -#define MPFS_PMPCFG_ETH0_1 (MPFS_MPUCFG_BASE + 0x408) -#define MPFS_PMPCFG_ETH0_2 (MPFS_MPUCFG_BASE + 0x410) -#define MPFS_PMPCFG_ETH0_3 (MPFS_MPUCFG_BASE + 0x418) -#define MPFS_PMPCFG_ETH1_0 (MPFS_MPUCFG_BASE + 0x500) -#define MPFS_PMPCFG_ETH1_1 (MPFS_MPUCFG_BASE + 0x508) -#define MPFS_PMPCFG_ETH1_2 (MPFS_MPUCFG_BASE + 0x510) -#define MPFS_PMPCFG_ETH1_3 (MPFS_MPUCFG_BASE + 0x518) - #if defined(CONFIG_MPFS_ETHMAC_0) && defined(CONFIG_MPFS_ETHMAC_1) # warning "Using 2 MACs is not yet supported." # define MPFS_NETHERNET (2) diff --git a/arch/risc-v/src/mpfs/mpfs_ethernet.h b/arch/risc-v/src/mpfs/mpfs_ethernet.h index fb8c89a3c7f77..ce2b1a9d58d07 100644 --- a/arch/risc-v/src/mpfs/mpfs_ethernet.h +++ b/arch/risc-v/src/mpfs/mpfs_ethernet.h @@ -27,8 +27,6 @@ #include -#include "hardware/mpfs_ethernet.h" - #ifndef __ASSEMBLY__ /**************************************************************************** diff --git a/arch/risc-v/src/mpfs/mpfs_usb.c b/arch/risc-v/src/mpfs/mpfs_usb.c index 36d1d3deab469..6cee61ba004bd 100644 --- a/arch/risc-v/src/mpfs/mpfs_usb.c +++ b/arch/risc-v/src/mpfs/mpfs_usb.c @@ -50,6 +50,7 @@ #include #include "hardware/mpfs_usb.h" +#include "hardware/mpfs_mpucfg.h" #include "mpfs_gpio.h" #include "riscv_internal.h" #include "chip.h" @@ -108,13 +109,6 @@ #define MPFS_TRACEINTID_EP0_STALLSENT 0x0014 #define MPFS_TRACEINTID_DATA_END 0x0015 -/* USB PMP configuration registers */ - -#define MPFS_PMPCFG_USB_0 (MPFS_MPUCFG_BASE + 0x600) -#define MPFS_PMPCFG_USB_1 (MPFS_MPUCFG_BASE + 0x608) -#define MPFS_PMPCFG_USB_2 (MPFS_MPUCFG_BASE + 0x610) -#define MPFS_PMPCFG_USB_3 (MPFS_MPUCFG_BASE + 0x618) - /* Reset and clock control registers */ #define MPFS_SYSREG_SOFT_RESET_CR (MPFS_SYSREG_BASE + \