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Pipeline reset value for multi-bit signals CI #17: Pull request #27 opened by lorenzschmid
November 1, 2023 07:43 37s pipeline-buffer
pipeline-buffer
November 1, 2023 07:43 37s
Lock writable register CI #16: Pull request #25 synchronize by lorenzschmid
October 23, 2023 09:12 55s lock
lock
October 23, 2023 09:12 55s
Merge pull request #24 from lorenzschmid/wmask-en CI #15: Commit 92413bc pushed by tgingold-cern
October 23, 2023 08:28 1m 3s master
master
October 23, 2023 08:28 1m 3s
Add x-hdl attribute to control write mask generation CI #14: Pull request #24 synchronize by lorenzschmid
October 20, 2023 11:47 49s wmask-en
wmask-en
October 20, 2023 11:47 49s
Add x-hdl attribute to control write mask generation CI #13: Pull request #24 synchronize by lorenzschmid
October 20, 2023 11:45 50s wmask-en
wmask-en
October 20, 2023 11:45 50s
Lock writable register CI #12: Pull request #25 synchronize by lorenzschmid
October 20, 2023 11:44 1m 8s lock
lock
October 20, 2023 11:44 1m 8s
Merge pull request #26 from lorenzschmid/virtual CI #11: Commit 78fcb95 pushed by tgingold-cern
October 20, 2023 11:28 51s master
master
October 20, 2023 11:28 51s
No port register type CI #10: Pull request #26 synchronize by lorenzschmid
October 20, 2023 09:40 48s virtual
virtual
October 20, 2023 09:40 48s
No port register type CI #9: Pull request #26 opened by lorenzschmid
October 19, 2023 14:44 53s virtual
virtual
October 19, 2023 14:44 53s
Lock writable register CI #8: Pull request #25 synchronize by lorenzschmid
October 19, 2023 14:07 1m 3s lock
lock
October 19, 2023 14:07 1m 3s
Lock writable register CI #7: Pull request #25 opened by lorenzschmid
October 19, 2023 13:31 1m 5s lock
lock
October 19, 2023 13:31 1m 5s