diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml
index 78360181d4e..2d067bdac87 100644
--- a/.gitlab/ci/target-test.yml
+++ b/.gitlab/ci/target-test.yml
@@ -926,6 +926,60 @@ pytest_components_esp32_psramv0:
       artifacts: false
   tags: [ esp32, psramv0 ]
 
+pytest_components_esp32_twai_std:
+  extends:
+    - .pytest_components_dir_template
+    - .rules:test:component_ut-esp32
+  needs:
+    - job: build_pytest_components_esp32
+      artifacts: false
+  tags: [ esp32, twai_std ]
+
+pytest_components_esp32s2_twai_std:
+  extends:
+    - .pytest_components_dir_template
+    - .rules:test:component_ut-esp32s2
+  needs:
+    - job: build_pytest_components_esp32s2
+      artifacts: false
+  tags: [ esp32s2, twai_std ]
+
+pytest_components_esp32s3_twai_std:
+  extends:
+    - .pytest_components_dir_template
+    - .rules:test:component_ut-esp32s3
+  needs:
+    - job: build_pytest_components_esp32s3
+      artifacts: false
+  tags: [ esp32s3, twai_std ]
+
+pytest_components_esp32c3_twai_std:
+  extends:
+    - .pytest_components_dir_template
+    - .rules:test:component_ut-esp32c3
+  needs:
+    - job: build_pytest_components_esp32c3
+      artifacts: false
+  tags: [ esp32c3, twai_std ]
+
+pytest_components_esp32c6_twai_std:
+  extends:
+    - .pytest_components_dir_template
+    - .rules:test:component_ut-esp32c6
+  needs:
+    - job: build_pytest_components_esp32c6
+      artifacts: false
+  tags: [ esp32c6, twai_std ]
+
+pytest_components_esp32h2_twai_std:
+  extends:
+    - .pytest_components_dir_template
+    - .rules:test:component_ut-esp32h2
+  needs:
+    - job: build_pytest_components_esp32h2
+      artifacts: false
+  tags: [ esp32h2, twai_std ]
+
 pytest_components_esp32s2_generic:
   extends:
     - .pytest_components_dir_template
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
index 3dbaa03f382..8be9693175c 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,16 +13,21 @@
 #include "hal/efuse_ll.h"
 #include "hal/efuse_hal.h"
 
+#include "hal/spi_flash_ll.h"
+#include "rom/spi_flash.h"
 #if CONFIG_IDF_TARGET_ESP32
 #   include "soc/spi_struct.h"
 #   include "soc/spi_reg.h"
     /* SPI flash controller */
 #   define SPIFLASH SPI1
+#   define SPI0     SPI0
 #else
+#   include "hal/spimem_flash_ll.h"
 #   include "soc/spi_mem_struct.h"
 #   include "soc/spi_mem_reg.h"
     /* SPI flash controller */
 #   define SPIFLASH SPIMEM1
+#   define SPI0     SPIMEM0
 #endif
 
 // This dependency will be removed in the future.  IDF-5025
@@ -581,10 +586,12 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
     uint32_t old_user_reg = SPIFLASH.user.val;
     uint32_t old_user1_reg = SPIFLASH.user1.val;
     uint32_t old_user2_reg = SPIFLASH.user2.val;
+    // Clear ctrl regs.
+    SPIFLASH.ctrl.val = 0;
 #if CONFIG_IDF_TARGET_ESP32
-    SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
+    spi_flash_ll_set_wp_level(&SPIFLASH, true);
 #else
-    SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
+    spimem_flash_ll_set_wp_level(&SPIFLASH, true);
 #endif
     //command phase
     SPIFLASH.user.usr_command = 1;
@@ -832,8 +839,8 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
 esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
 {
     esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
+    uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0);
 #if CONFIG_IDF_TARGET_ESP32
-    uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
     if (spi_ctrl & SPI_FREAD_QIO) {
         spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
     } else if (spi_ctrl & SPI_FREAD_QUAD) {
@@ -848,7 +855,6 @@ esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
         spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
     }
 #else
-    uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
     if (spi_ctrl & SPI_MEM_FREAD_QIO) {
         spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
     } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
index 89894d5edd0..5e9433ca3ff 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,9 +30,9 @@ void bootloader_flash_update_id()
 
 void IRAM_ATTR bootloader_flash_cs_timing_config()
 {
-    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
-    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
-    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
+    SET_PERI_REG_MASK(SPI_MEM_C_USER_REG, SPI_MEM_C_CS_HOLD_M | SPI_MEM_C_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_HOLD_TIME_V, 0, SPI_MEM_C_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
 }
 
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
diff --git a/components/bt/host/bluedroid/Kconfig.in b/components/bt/host/bluedroid/Kconfig.in
index 0d5e18d1781..d710198611f 100644
--- a/components/bt/host/bluedroid/Kconfig.in
+++ b/components/bt/host/bluedroid/Kconfig.in
@@ -29,7 +29,7 @@ config BT_BLUEDROID_PINNED_TO_CORE
 config BT_BTU_TASK_STACK_SIZE
     int "Bluetooth Bluedroid Host Stack task stack size"
     depends on BT_BLUEDROID_ENABLED
-    default 4096
+    default 4352
     help
         This select btu task stack size
 
diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c
index 86914f50fa3..54689cef229 100644
--- a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c
+++ b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c
@@ -2090,7 +2090,7 @@ UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT8 type, UINT8 *p_length)
 
     STREAM_TO_UINT8(length, p);
 
-    while ( length && (p - p_adv <= BTM_BLE_CACHE_ADV_DATA_MAX)) {
+    while ( length && (p - p_adv < BTM_BLE_CACHE_ADV_DATA_MAX)) {
         STREAM_TO_UINT8(adv_type, p);
 
         if ( adv_type == type ) {
@@ -2098,7 +2098,15 @@ UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT8 type, UINT8 *p_length)
             *p_length = length - 1; /* minus the length of type */
             return p;
         }
+
         p += length - 1; /* skip the length of data */
+
+        /* Break loop if advertising data is in an incorrect format,
+           as it may lead to memory overflow */
+        if (p >= p_adv + BTM_BLE_CACHE_ADV_DATA_MAX) {
+            break;
+        }
+
         STREAM_TO_UINT8(length, p);
     }
 
diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble
index c3e0414b280..20d3df32c2b 160000
--- a/components/bt/host/nimble/nimble
+++ b/components/bt/host/nimble/nimble
@@ -1 +1 @@
-Subproject commit c3e0414b280911c5be56896d5159f6e54a0a52b4
+Subproject commit 20d3df32c2b569ed51010a396167d4b097fac7ca
diff --git a/components/console/CMakeLists.txt b/components/console/CMakeLists.txt
index f0aaabb3400..ab3f99cf269 100644
--- a/components/console/CMakeLists.txt
+++ b/components/console/CMakeLists.txt
@@ -29,5 +29,5 @@ idf_component_register(SRCS "commands.c"
                     INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}
                     REQUIRES vfs
                     PRIV_REQUIRES esp_driver_uart
-                                  driver # to be replaced by esp_driver_usj
+                                  esp_driver_usb_serial_jtag
                     )
diff --git a/components/console/esp_console_repl.c b/components/console/esp_console_repl.c
index 00d93242d38..07bb6569b87 100644
--- a/components/console/esp_console_repl.c
+++ b/components/console/esp_console_repl.c
@@ -12,9 +12,8 @@
 #include "esp_err.h"
 #include "esp_log.h"
 #include "esp_console.h"
-#include "esp_vfs_dev.h"
 #include "esp_vfs_cdcacm.h"
-#include "esp_vfs_usb_serial_jtag.h"
+#include "driver/usb_serial_jtag_vfs.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "driver/uart.h"
@@ -144,9 +143,9 @@ esp_err_t esp_console_new_repl_usb_serial_jtag(const esp_console_dev_usb_serial_
     }
 
     /* Minicom, screen, idf_monitor send CR when ENTER key is pressed */
-    esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
+    usb_serial_jtag_vfs_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
     /* Move the caret to the beginning of the next line on '\n' */
-    esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
+    usb_serial_jtag_vfs_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
 
     /* Enable blocking mode on stdin and stdout */
     fcntl(fileno(stdout), F_SETFL, 0);
@@ -167,7 +166,7 @@ esp_err_t esp_console_new_repl_usb_serial_jtag(const esp_console_dev_usb_serial_
     }
 
     /* Tell vfs to use usb-serial-jtag driver */
-    esp_vfs_usb_serial_jtag_use_driver();
+    usb_serial_jtag_vfs_use_driver();
 
     // setup history
     ret = esp_console_setup_history(repl_config->history_save_path, repl_config->max_history_len, &usb_serial_jtag_repl->repl_com);
@@ -466,7 +465,7 @@ static esp_err_t esp_console_repl_usb_serial_jtag_delete(esp_console_repl_t *rep
     }
     repl_com->state = CONSOLE_REPL_STATE_DEINIT;
     esp_console_deinit();
-    esp_vfs_usb_serial_jtag_use_nonblocking();
+    usb_serial_jtag_vfs_use_nonblocking();
     usb_serial_jtag_driver_uninstall();
     free(usb_serial_jtag_repl);
 _exit:
diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt
index 3c65725a0e3..4e09ae6c656 100644
--- a/components/driver/CMakeLists.txt
+++ b/components/driver/CMakeLists.txt
@@ -11,8 +11,7 @@ set(srcs)
 set(includes "deprecated"
              "i2c/include"
              "touch_sensor/include"
-             "twai/include"
-             "usb_serial_jtag/include")
+             "twai/include")
 
 # Always included linker fragments
 set(ldfragments "")
@@ -86,12 +85,6 @@ if(CONFIG_SOC_TWAI_SUPPORTED)
     list(APPEND ldfragments "twai/linker.lf")
 endif()
 
-# USB Serial JTAG related source files
-if(CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED)
-    list(APPEND srcs "usb_serial_jtag/usb_serial_jtag.c"
-                     "usb_serial_jtag/usb_serial_jtag_connection_monitor.c")
-endif()
-
 # Other source files
 if(${target} STREQUAL "esp32")
     list(APPEND srcs "deprecated/adc_i2s_deprecated.c")
@@ -113,14 +106,7 @@ else()
                                     esp_driver_gpio esp_driver_pcnt esp_driver_gptimer esp_driver_spi esp_driver_mcpwm
                                     esp_driver_ana_cmpr esp_driver_i2s esp_driver_sdmmc esp_driver_sdspi esp_driver_sdio
                                     esp_driver_dac esp_driver_rmt esp_driver_tsens esp_driver_sdm esp_driver_i2c
-                                    esp_driver_uart esp_driver_ledc esp_driver_parlio
+                                    esp_driver_uart esp_driver_ledc esp_driver_parlio esp_driver_usb_serial_jtag
                            LDFRAGMENTS ${ldfragments}
                           )
 endif()
-
-# If system needs to monitor USJ connection status, then usb_serial_jtag_connection_monitor object file has to be linked
-# to the binary, to allow tick hook to be registered
-if(CONFIG_USJ_NO_AUTO_LS_ON_CONNECTION OR
-   (CONFIG_SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP AND CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED))
-    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u usb_serial_jtag_connection_monitor_include")
-endif()
diff --git a/components/driver/Kconfig b/components/driver/Kconfig
index 96f30ad32c9..6a1dc917049 100644
--- a/components/driver/Kconfig
+++ b/components/driver/Kconfig
@@ -64,21 +64,4 @@ menu "Driver Configurations"
 
     orsource "./twai/Kconfig.twai"
 
-    menu "USB Serial/JTAG Configuration"
-        depends on SOC_USB_SERIAL_JTAG_SUPPORTED
-        config USJ_NO_AUTO_LS_ON_CONNECTION
-            bool "Don't enter the automatic light sleep when USB Serial/JTAG port is connected"
-            depends on PM_ENABLE && ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
-            default n
-            help
-                If enabled, the chip will constantly monitor the connection status of the USB Serial/JTAG port. As long
-                as the USB Serial/JTAG is connected, a ESP_PM_NO_LIGHT_SLEEP power management lock will be acquired to
-                prevent the system from entering light sleep.
-                This option can be useful if serial monitoring is needed via USB Serial/JTAG while power management is
-                enabled, as the USB Serial/JTAG cannot work under light sleep and after waking up from light sleep.
-                Note. This option can only control the automatic Light-Sleep behavior. If esp_light_sleep_start() is
-                called manually from the program, enabling this option will not prevent light sleep entry even if the
-                USB Serial/JTAG is in use.
-    endmenu # USB Serial/JTAG Configuration
-
 endmenu  # Driver configurations
diff --git a/components/driver/deprecated/adc_dma_legacy.c b/components/driver/deprecated/adc_dma_legacy.c
index 846276c17fb..03c7ba5e585 100644
--- a/components/driver/deprecated/adc_dma_legacy.c
+++ b/components/driver/deprecated/adc_dma_legacy.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -177,7 +177,7 @@ esp_err_t adc_digi_deinitialize(void)
     free(s_adc_digi_ctx);
     s_adc_digi_ctx = NULL;
 
-    periph_module_disable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_free();
 
     return ESP_OK;
 }
@@ -321,10 +321,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
     };
     adc_hal_dma_ctx_config(&s_adc_digi_ctx->hal, &config);
 
-    //enable ADC digital part
-    periph_module_enable(PERIPH_SARADC_MODULE);
-    //reset ADC digital part
-    periph_module_reset(PERIPH_SARADC_MODULE);
+    adc_apb_periph_claim();
 
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_hal_calibration_init(ADC_UNIT_1);
diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c
index a88c42465d3..9afbf4fec51 100644
--- a/components/driver/deprecated/adc_legacy.c
+++ b/components/driver/deprecated/adc_legacy.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -777,7 +777,7 @@ int adc1_get_raw(adc1_channel_t channel)
         return ESP_ERR_TIMEOUT;
     }
 
-    periph_module_enable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_claim();
     sar_periph_ctrl_adc_oneshot_power_acquire();
     adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
 
@@ -792,7 +792,7 @@ int adc1_get_raw(adc1_channel_t channel)
     ADC_REG_LOCK_EXIT();
 
     sar_periph_ctrl_adc_oneshot_power_release();
-    periph_module_disable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_free();
     adc_lock_release(ADC_UNIT_1);
 
     return raw_out;
@@ -834,7 +834,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
         return ESP_ERR_TIMEOUT;
     }
 
-    periph_module_enable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_claim();
     sar_periph_ctrl_adc_oneshot_power_acquire();
     adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
 
@@ -852,7 +852,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     ADC_REG_LOCK_EXIT();
 
     sar_periph_ctrl_adc_oneshot_power_release();
-    periph_module_disable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_free();
     adc_lock_release(ADC_UNIT_2);
 
     return ret;
diff --git a/components/driver/test_apps/.build-test-rules.yml b/components/driver/test_apps/.build-test-rules.yml
index 7fa7eca8b35..7696651dbce 100644
--- a/components/driver/test_apps/.build-test-rules.yml
+++ b/components/driver/test_apps/.build-test-rules.yml
@@ -93,14 +93,7 @@ components/driver/test_apps/twai:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: test not pass, should be re-enable # TODO: IDF-8966
-
-components/driver/test_apps/usb_serial_jtag:
-  disable:
-    - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1
   depends_filepatterns:
-    - components/driver/usb_serial_jtag/**/*
+    - components/driver/twai/**/*
   depends_components:
-    - hal
-    - esp_hw_support # for clock
-    - vfs
     - esp_driver_gpio
diff --git a/components/driver/test_apps/twai/main/test_twai_interactive.c b/components/driver/test_apps/twai/main/test_twai_interactive.c
index 88b74af55bb..78ee6605556 100644
--- a/components/driver/test_apps/twai/main/test_twai_interactive.c
+++ b/components/driver/test_apps/twai/main/test_twai_interactive.c
@@ -27,7 +27,7 @@ TEST_CASE("twai_listen_only", "[twai]")
 {
     twai_timing_config_t t_config = TWAI_TIMING_CONFIG_250KBITS();
     twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL();
-    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(0, 2, TWAI_MODE_LISTEN_ONLY);
+    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(4, 5, TWAI_MODE_LISTEN_ONLY);
 #if CONFIG_TWAI_ISR_IN_IRAM
     g_config.intr_flags |= ESP_INTR_FLAG_IRAM;
 #endif
@@ -60,8 +60,10 @@ TEST_CASE("twai_remote_request", "[twai]")
     twai_handle_t bus_handle;
     twai_timing_config_t t_config = TWAI_TIMING_CONFIG_250KBITS();
     twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL();
-    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(0, 2, TWAI_MODE_NORMAL);
-    g_config.controller_id = 2;
+    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(4, 5, TWAI_MODE_NORMAL);
+#if CONFIG_IDF_TARGET_ESP32C6
+    g_config.controller_id = 1;
+#endif
     TEST_ESP_OK(twai_driver_install_v2(&g_config, &t_config, &f_config, &bus_handle));
     TEST_ESP_OK(twai_start_v2(bus_handle));
 
diff --git a/components/driver/test_apps/twai/pytest_twai.py b/components/driver/test_apps/twai/pytest_twai.py
index 95595646e5a..5b05e08fb3c 100644
--- a/components/driver/test_apps/twai/pytest_twai.py
+++ b/components/driver/test_apps/twai/pytest_twai.py
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: CC0-1.0
 
 import logging
+import subprocess
 from time import sleep
 
 import pytest
@@ -29,10 +30,14 @@ def test_twai_self(dut: Dut) -> None:
 
 @pytest.fixture(name='socket_can', scope='module')
 def fixture_create_socket_can() -> Bus:
-    # See README.md for instructions on how to set up the socket CAN with the bitrate
+    # Set up the socket CAN with the bitrate
+    start_command = 'sudo ip link set can0 up type can bitrate 250000 restart-ms 100'
+    stop_command = 'sudo ip link set can0 down'
+    subprocess.run(start_command, shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE, text=True)
     bus = Bus(interface='socketcan', channel='can0', bitrate=250000)
-    yield bus
+    yield bus   # test invoked here
     bus.shutdown()
+    subprocess.run(stop_command, shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE, text=True)
 
 
 @pytest.mark.esp32
@@ -41,7 +46,7 @@ def fixture_create_socket_can() -> Bus:
 @pytest.mark.esp32h2
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
-@pytest.mark.skip(reason='Runner not set up yet')
+@pytest.mark.twai_std
 @pytest.mark.parametrize(
     'config',
     [
@@ -50,6 +55,7 @@ def fixture_create_socket_can() -> Bus:
     indirect=True,
 )
 def test_twai_listen_only(dut: Dut, socket_can: Bus) -> None:
+    dut.serial.hard_reset()
     dut.expect_exact('Press ENTER to see the list of tests')
 
     # TEST_CASE("twai_listen_only", "[twai]")
@@ -73,7 +79,7 @@ def test_twai_listen_only(dut: Dut, socket_can: Bus) -> None:
 @pytest.mark.esp32h2
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
-@pytest.mark.skip(reason='Runner not set up yet')
+@pytest.mark.twai_std
 @pytest.mark.parametrize(
     'config',
     [
@@ -82,6 +88,7 @@ def test_twai_listen_only(dut: Dut, socket_can: Bus) -> None:
     indirect=True,
 )
 def test_twai_remote_request(dut: Dut, socket_can: Bus) -> None:
+    dut.serial.hard_reset()
     dut.expect_exact('Press ENTER to see the list of tests')
 
     # TEST_CASE("twai_remote_request", "[twai]")
diff --git a/components/esp_adc/adc_common.c b/components/esp_adc/adc_common.c
index 4a2da9625b0..01301c310ff 100644
--- a/components/esp_adc/adc_common.c
+++ b/components/esp_adc/adc_common.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,42 +18,6 @@
 #include "soc/adc_periph.h"
 
 static const char *TAG = "adc_common";
-static portMUX_TYPE s_spinlock = portMUX_INITIALIZER_UNLOCKED;
-extern portMUX_TYPE rtc_spinlock;
-
-/*------------------------------------------------------------------------------
-* For those who use APB_SARADC periph
-*----------------------------------------------------------------------------*/
-static int s_adc_digi_ctrlr_cnt;
-
-void adc_apb_periph_claim(void)
-{
-    portENTER_CRITICAL(&s_spinlock);
-    s_adc_digi_ctrlr_cnt++;
-    if (s_adc_digi_ctrlr_cnt == 1) {
-        //enable ADC digital part
-        periph_module_enable(PERIPH_SARADC_MODULE);
-        //reset ADC digital part
-        periph_module_reset(PERIPH_SARADC_MODULE);
-    }
-
-    portEXIT_CRITICAL(&s_spinlock);
-}
-
-void adc_apb_periph_free(void)
-{
-    portENTER_CRITICAL(&s_spinlock);
-    s_adc_digi_ctrlr_cnt--;
-    if (s_adc_digi_ctrlr_cnt == 0) {
-        periph_module_disable(PERIPH_SARADC_MODULE);
-    } else if (s_adc_digi_ctrlr_cnt < 0) {
-        portEXIT_CRITICAL(&s_spinlock);
-        ESP_LOGE(TAG, "%s called, but `s_adc_digi_ctrlr_cnt == 0`", __func__);
-        abort();
-    }
-
-    portEXIT_CRITICAL(&s_spinlock);
-}
 
 /*---------------------------------------------------------------
             ADC IOs
diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c
index 71d405ccb81..36e4a29fd49 100644
--- a/components/esp_adc/adc_continuous.c
+++ b/components/esp_adc/adc_continuous.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -247,10 +247,7 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi
     adc_ctx->fsm = ADC_FSM_INIT;
     *ret_handle = adc_ctx;
 
-    //enable ADC digital part
-    periph_module_enable(PERIPH_SARADC_MODULE);
-    //reset ADC digital part
-    periph_module_reset(PERIPH_SARADC_MODULE);
+    adc_apb_periph_claim();
 
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_hal_calibration_init(ADC_UNIT_1);
@@ -504,7 +501,7 @@ esp_err_t adc_continuous_deinit(adc_continuous_handle_t handle)
     free(handle);
     handle = NULL;
 
-    periph_module_disable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_free();
 
     return ESP_OK;
 }
diff --git a/components/esp_adc/include/esp_private/adc_private.h b/components/esp_adc/include/esp_private/adc_private.h
index 805614a976a..a714181e2e1 100644
--- a/components/esp_adc/include/esp_private/adc_private.h
+++ b/components/esp_adc/include/esp_private/adc_private.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,23 +15,6 @@
 extern "C" {
 #endif
 
-/*------------------------------------------------------------------------------
-* For those who use APB_SARADC periph
-*----------------------------------------------------------------------------*/
-/**
- * @brief Claim the usage of the APB_SARADC periph
- *
- * Reference count inside
- */
-void adc_apb_periph_claim(void);
-
-/**
- * @brief Free the usage of the APB_SARADC periph
- *
- * Reference count inside
- */
-void adc_apb_periph_free(void);
-
 /*---------------------------------------------------------------
             ADC IOs
 ---------------------------------------------------------------*/
diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml
index 9c6297a2ffd..aa97546c7d4 100644
--- a/components/esp_adc/test_apps/.build-test-rules.yml
+++ b/components/esp_adc/test_apps/.build-test-rules.yml
@@ -10,3 +10,4 @@ components/esp_adc/test_apps/adc:
     - esp_driver_i2s  # ADC continuous driver relies on I2S on ESP32
     - efuse
     - esp_driver_spi  # ADC continuous driver relies on SPI on ESP32S2
+    - esp_driver_tsens
diff --git a/components/esp_adc/test_apps/adc/main/CMakeLists.txt b/components/esp_adc/test_apps/adc/main/CMakeLists.txt
index 8b8cc4b0856..e7eed57470a 100644
--- a/components/esp_adc/test_apps/adc/main/CMakeLists.txt
+++ b/components/esp_adc/test_apps/adc/main/CMakeLists.txt
@@ -4,10 +4,12 @@ set(srcs "test_app_main.c"
          "test_adc_driver.c"
          "test_adc_driver_iram.c"
          "test_adc_wifi.c"
+         "test_adc_tsens.c"
          "test_common_adc.c")
 
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
                        PRIV_REQUIRES esp_driver_gptimer esp_driver_gpio esp_wifi nvs_flash esp_adc test_utils efuse
+                                     esp_driver_tsens
                        WHOLE_ARCHIVE)
diff --git a/components/esp_adc/test_apps/adc/main/test_adc_tsens.c b/components/esp_adc/test_apps/adc/main/test_adc_tsens.c
new file mode 100644
index 00000000000..159fa1b7efa
--- /dev/null
+++ b/components/esp_adc/test_apps/adc/main/test_adc_tsens.c
@@ -0,0 +1,83 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "esp_log.h"
+#include "soc/adc_periph.h"
+#include "esp_adc/adc_oneshot.h"
+#include "driver/gpio.h"
+#include "driver/rtc_io.h"
+#include "driver/temperature_sensor.h"
+#include "nvs_flash.h"
+#include "esp_event.h"
+#include "esp_wifi.h"
+#include "test_common_adc.h"
+#include "test_utils.h"
+
+#if SOC_TEMP_SENSOR_SUPPORTED && SOC_ADC_SUPPORTED
+
+static const char *TAG = "adc_tsens";
+
+#define EXAMPLE_ADC1_CHAN0          ADC_CHANNEL_2
+#define EXAMPLE_ADC1_CHAN1          ADC_CHANNEL_4
+#define EXAMPLE_ADC_ATTEN           ADC_ATTEN_DB_12
+
+static int adc_raw[2][10];
+
+TEST_CASE("Test temperature sensor cannot be influenced by ADC", "[adc]")
+{
+    ESP_LOGI(TAG, "Install temperature sensor, expected temp ranger range: 10~50 ℃");
+    temperature_sensor_handle_t temp_sensor = NULL;
+    temperature_sensor_config_t temp_sensor_config = TEMPERATURE_SENSOR_CONFIG_DEFAULT(-10, 80);
+    TEST_ESP_OK(temperature_sensor_install(&temp_sensor_config, &temp_sensor));
+    int cnt = 2;
+    float tsens_value;
+    while (cnt--) {
+        temperature_sensor_enable(temp_sensor);
+        TEST_ESP_OK(temperature_sensor_get_celsius(temp_sensor, &tsens_value));
+        ESP_LOGI(TAG, "Temperature value %.02f ℃", tsens_value);
+        vTaskDelay(pdMS_TO_TICKS(100));
+        TEST_ESP_OK(temperature_sensor_disable(temp_sensor));
+    }
+
+    adc_oneshot_unit_handle_t adc1_handle;
+    adc_oneshot_unit_init_cfg_t init_config1 = {
+        .unit_id = ADC_UNIT_1,
+    };
+    TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &adc1_handle));
+
+    //-------------ADC1 Config---------------//
+    adc_oneshot_chan_cfg_t config = {
+        .bitwidth = ADC_BITWIDTH_DEFAULT,
+        .atten = EXAMPLE_ADC_ATTEN,
+    };
+    TEST_ESP_OK(adc_oneshot_config_channel(adc1_handle, EXAMPLE_ADC1_CHAN0, &config));
+    TEST_ESP_OK(adc_oneshot_config_channel(adc1_handle, EXAMPLE_ADC1_CHAN1, &config));
+
+    cnt = 2;
+    while (cnt--) {
+        TEST_ESP_OK(adc_oneshot_read(adc1_handle, EXAMPLE_ADC1_CHAN0, &adc_raw[0][0]));
+        ESP_LOGI(TAG, "ADC%d Channel[%d] Raw Data: %d", ADC_UNIT_1 + 1, EXAMPLE_ADC1_CHAN0, adc_raw[0][0]);
+        vTaskDelay(pdMS_TO_TICKS(100));
+    }
+
+    TEST_ESP_OK(adc_oneshot_del_unit(adc1_handle));
+
+    cnt = 2;
+    while (cnt--) {
+        temperature_sensor_enable(temp_sensor);
+        TEST_ESP_OK(temperature_sensor_get_celsius(temp_sensor, &tsens_value));
+        ESP_LOGI(TAG, "Temperature value %.02f ℃", tsens_value);
+        vTaskDelay(pdMS_TO_TICKS(100));
+        TEST_ESP_OK(temperature_sensor_disable(temp_sensor));
+    }
+
+    TEST_ESP_OK(temperature_sensor_uninstall(temp_sensor));
+}
+
+#endif
diff --git a/components/esp_driver_dac/esp32s2/dac_dma.c b/components/esp_driver_dac/esp32s2/dac_dma.c
index 6e715bc4dc3..52b250fbce1 100644
--- a/components/esp_driver_dac/esp32s2/dac_dma.c
+++ b/components/esp_driver_dac/esp32s2/dac_dma.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,7 @@
 #include "sdkconfig.h"
 #include "esp_private/spi_common_internal.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/adc_share_hw_ctrl.h"
 #include "hal/spi_ll.h"
 #include "hal/dac_ll.h"
 #include "hal/adc_ll.h"
@@ -130,7 +131,7 @@ esp_err_t dac_dma_periph_init(uint32_t freq_hz, bool is_alternate, bool is_apll)
     esp_err_t ret = ESP_OK;
     /* Acquire DMA peripheral */
     ESP_RETURN_ON_FALSE(spicommon_periph_claim(DAC_DMA_PERIPH_SPI_HOST, "dac_dma"), ESP_ERR_NOT_FOUND, TAG, "Failed to acquire DAC DMA peripheral");
-    periph_module_enable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_claim();
     /* Allocate DAC DMA peripheral object */
     s_ddp = (dac_dma_periph_spi_t *)heap_caps_calloc(1, sizeof(dac_dma_periph_spi_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     ESP_GOTO_ON_FALSE(s_ddp, ESP_ERR_NO_MEM, err, TAG, "No memory for DAC DMA object");
@@ -163,7 +164,7 @@ esp_err_t dac_dma_periph_deinit(void)
     }
     ESP_RETURN_ON_FALSE(spicommon_periph_free(DAC_DMA_PERIPH_SPI_HOST), ESP_FAIL, TAG, "Failed to release DAC DMA peripheral");
     spi_ll_disable_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_OUT_TOTAL_EOF);
-    periph_module_disable(PERIPH_SARADC_MODULE);
+    adc_apb_periph_free();
     if (s_ddp) {
         if (s_ddp->use_apll) {
             periph_rtc_apll_release();
diff --git a/components/esp_driver_rmt/CMakeLists.txt b/components/esp_driver_rmt/CMakeLists.txt
index df2b8dbf82e..c4cb98ce799 100644
--- a/components/esp_driver_rmt/CMakeLists.txt
+++ b/components/esp_driver_rmt/CMakeLists.txt
@@ -9,6 +9,6 @@ endif()
 
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS ${public_include}
-                       PRIV_REQUIRES "esp_pm" "esp_driver_gpio"
+                       PRIV_REQUIRES "esp_pm" "esp_driver_gpio" "esp_mm"
                        LDFRAGMENTS "linker.lf"
                       )
diff --git a/components/esp_driver_rmt/src/rmt_encoder.c b/components/esp_driver_rmt/src/rmt_encoder.c
index a5183586617..04e6f2d558e 100644
--- a/components/esp_driver_rmt/src/rmt_encoder.c
+++ b/components/esp_driver_rmt/src/rmt_encoder.c
@@ -66,7 +66,7 @@ static size_t IRAM_ATTR rmt_encode_bytes(rmt_encoder_t *encoder, rmt_channel_han
     // where to put the encoded symbols? DMA buffer or RMT HW memory
     rmt_symbol_word_t *mem_to_nc = NULL;
     if (channel->dma_chan) {
-        mem_to_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(channel->dma_mem_base);
+        mem_to_nc = tx_chan->dma_mem_base_nc;
     } else {
         mem_to_nc = channel->hw_mem_base;
     }
@@ -176,7 +176,7 @@ static size_t IRAM_ATTR rmt_encode_copy(rmt_encoder_t *encoder, rmt_channel_hand
     // where to put the encoded symbols? DMA buffer or RMT HW memory
     rmt_symbol_word_t *mem_to_nc = NULL;
     if (channel->dma_chan) {
-        mem_to_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(channel->dma_mem_base);
+        mem_to_nc = tx_chan->dma_mem_base_nc;
     } else {
         mem_to_nc = channel->hw_mem_base;
     }
diff --git a/components/esp_driver_rmt/src/rmt_private.h b/components/esp_driver_rmt/src/rmt_private.h
index 6fa1b6388dc..0915aae23ad 100644
--- a/components/esp_driver_rmt/src/rmt_private.h
+++ b/components/esp_driver_rmt/src/rmt_private.h
@@ -127,7 +127,6 @@ struct rmt_channel_t {
     _Atomic rmt_fsm_t fsm;  // channel life cycle specific FSM
     rmt_channel_direction_t direction; // channel direction
     rmt_symbol_word_t *hw_mem_base;    // base address of RMT channel hardware memory
-    rmt_symbol_word_t *dma_mem_base;   // base address of RMT channel DMA buffer
     gdma_channel_handle_t dma_chan;    // DMA channel
     esp_pm_lock_handle_t pm_lock;      // power management lock
 #if CONFIG_PM_ENABLE
@@ -157,6 +156,8 @@ typedef struct {
 
 struct rmt_tx_channel_t {
     rmt_channel_t base; // channel base class
+    rmt_symbol_word_t *dma_mem_base;    // base address of RMT channel DMA buffer
+    rmt_symbol_word_t *dma_mem_base_nc; // base address of RMT channel DMA buffer, accessed in non-cached way
     size_t mem_off;     // runtime argument, indicating the next writing position in the RMT hardware memory
     size_t mem_end;     // runtime argument, indicating the end of current writing region
     size_t ping_pong_symbols;  // ping-pong size (half of the RMT channel memory)
diff --git a/components/esp_driver_rmt/src/rmt_rx.c b/components/esp_driver_rmt/src/rmt_rx.c
index b27ac639b4b..6dcf1d5a510 100644
--- a/components/esp_driver_rmt/src/rmt_rx.c
+++ b/components/esp_driver_rmt/src/rmt_rx.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,7 @@
 #include "esp_log.h"
 #include "esp_check.h"
 #include "esp_memory_utils.h"
+#include "esp_cache.h"
 #include "esp_rom_gpio.h"
 #include "soc/rmt_periph.h"
 #include "soc/rtc.h"
@@ -26,7 +27,6 @@
 #include "driver/gpio.h"
 #include "driver/rmt_rx.h"
 #include "rmt_private.h"
-#include "rom/cache.h"
 
 #define ALIGN_UP(num, align)    (((num) + ((align) - 1)) & ~((align) - 1))
 #define ALIGN_DOWN(num, align)  ((num) & ~((align) - 1))
@@ -199,7 +199,10 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_
         num_dma_nodes = config->mem_block_symbols * sizeof(rmt_symbol_word_t) / RMT_DMA_DESC_BUF_MAX_SIZE + 1;
         num_dma_nodes = MAX(2, num_dma_nodes); // at least 2 DMA nodes for ping-pong
         // DMA descriptors must be placed in internal SRAM
-        rx_channel->dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, num_dma_nodes, sizeof(rmt_dma_descriptor_t), mem_caps);
+        uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
+        // the alignment should meet both the DMA and cache requirement
+        size_t alignment = MAX(data_cache_line_size, RMT_DMA_DESC_ALIGN);
+        rx_channel->dma_nodes = heap_caps_aligned_calloc(alignment, num_dma_nodes, sizeof(rmt_dma_descriptor_t), mem_caps);
         ESP_GOTO_ON_FALSE(rx_channel->dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no mem for rx channel DMA nodes");
         // we will use the non-cached address to manipulate the DMA descriptor, for simplicity
         rx_channel->dma_nodes_nc = (rmt_dma_descriptor_t *)RMT_GET_NON_CACHE_ADDR(rx_channel->dma_nodes);
@@ -345,13 +348,14 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_
     size_t last_dma_block_size = 0;
 
     if (channel->dma_chan) {
-        ESP_RETURN_ON_FALSE_ISR(esp_ptr_internal(buffer), ESP_ERR_INVALID_ARG, TAG, "buffer must locate in internal RAM for DMA use");
-
-#if CONFIG_IDF_TARGET_ESP32P4
-        uint32_t data_cache_line_mask = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA) - 1;
-        ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buffer & data_cache_line_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer must be aligned to cache line size");
-        ESP_RETURN_ON_FALSE_ISR((buffer_size & data_cache_line_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer size must be aligned to cache line size");
-#endif
+        // Currently we assume the user buffer is allocated from internal RAM, PSRAM is not supported yet.
+        ESP_RETURN_ON_FALSE_ISR(esp_ptr_internal(buffer), ESP_ERR_INVALID_ARG, TAG, "user buffer not allocated from internal RAM");
+        uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
+        // DMA doesn't have alignment requirement for SRAM buffer if the burst mode is not enabled,
+        // but we need to make sure the buffer is aligned to cache line size
+        uint32_t align_mask = data_cache_line_size ? (data_cache_line_size - 1) : 0;
+        ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buffer & align_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer address not aligned");
+        ESP_RETURN_ON_FALSE_ISR((buffer_size & align_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer size not aligned");
         ESP_RETURN_ON_FALSE_ISR(buffer_size <= rx_chan->num_dma_nodes * RMT_DMA_DESC_BUF_MAX_SIZE,
                                 ESP_ERR_INVALID_ARG, TAG, "buffer size exceeds DMA capacity");
         per_dma_block_size = buffer_size / rx_chan->num_dma_nodes;
@@ -752,13 +756,11 @@ static bool IRAM_ATTR rmt_dma_rx_one_block_cb(gdma_channel_handle_t dma_chan, gd
     rmt_rx_trans_desc_t *trans_desc = &rx_chan->trans_desc;
     uint32_t channel_id = channel->channel_id;
 
-#if CONFIG_IDF_TARGET_ESP32P4
-    int invalidate_map = CACHE_MAP_L1_DCACHE;
-    if (esp_ptr_external_ram((const void *)trans_desc->buffer)) {
-        invalidate_map |= CACHE_MAP_L2_CACHE;
+    uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
+    if (data_cache_line_size) {
+        // invalidate the user buffer, so that the DMA modified data can be seen by CPU
+        esp_cache_msync(trans_desc->buffer, trans_desc->buffer_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
     }
-    Cache_Invalidate_Addr(invalidate_map, (uint32_t)trans_desc->buffer, trans_desc->buffer_size);
-#endif
 
     if (event_data->flags.normal_eof) {
         // if the DMA received an EOF, it means the RMT peripheral has received an "end marker"
diff --git a/components/esp_driver_rmt/src/rmt_tx.c b/components/esp_driver_rmt/src/rmt_tx.c
index b4d3a246920..5208f557eae 100644
--- a/components/esp_driver_rmt/src/rmt_tx.c
+++ b/components/esp_driver_rmt/src/rmt_tx.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,8 @@
 #include "soc/rtc.h"
 #include "hal/rmt_ll.h"
 #include "hal/gpio_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/cache_ll.h"
 #include "driver/gpio.h"
 #include "driver/rmt_tx.h"
 #include "rmt_private.h"
@@ -47,10 +49,16 @@ static bool rmt_dma_tx_eof_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t
 
 static esp_err_t rmt_tx_init_dma_link(rmt_tx_channel_t *tx_channel, const rmt_tx_channel_config_t *config)
 {
-    rmt_symbol_word_t *dma_mem_base = heap_caps_calloc(1, sizeof(rmt_symbol_word_t) * config->mem_block_symbols,
-                                                       RMT_MEM_ALLOC_CAPS | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    // For simplicity, the encoder will access the dma_mem_base in a non-cached way
+    // and we allocate the dma_mem_base from the internal SRAM for performance
+    uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
+    // the alignment should meet both the DMA and cache requirement
+    size_t alignment = MAX(data_cache_line_size, sizeof(rmt_symbol_word_t));
+    rmt_symbol_word_t *dma_mem_base = heap_caps_aligned_calloc(alignment, config->mem_block_symbols, sizeof(rmt_symbol_word_t),
+                                                               RMT_MEM_ALLOC_CAPS | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
     ESP_RETURN_ON_FALSE(dma_mem_base, ESP_ERR_NO_MEM, TAG, "no mem for tx DMA buffer");
-    tx_channel->base.dma_mem_base = dma_mem_base;
+    tx_channel->dma_mem_base = dma_mem_base;
+    tx_channel->dma_mem_base_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(dma_mem_base);
     for (int i = 0; i < RMT_DMA_NODES_PING_PONG; i++) {
         // each descriptor shares half of the DMA buffer
         tx_channel->dma_nodes_nc[i].buffer = dma_mem_base + tx_channel->ping_pong_symbols * i;
@@ -193,8 +201,8 @@ static esp_err_t rmt_tx_destroy(rmt_tx_channel_t *tx_channel)
             vQueueDeleteWithCaps(tx_channel->trans_queues[i]);
         }
     }
-    if (tx_channel->base.dma_mem_base) {
-        free(tx_channel->base.dma_mem_base);
+    if (tx_channel->dma_mem_base) {
+        free(tx_channel->dma_mem_base);
     }
     if (tx_channel->base.group) {
         // de-register channel from RMT group
@@ -239,9 +247,12 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_
     ESP_GOTO_ON_FALSE(tx_channel, ESP_ERR_NO_MEM, err, TAG, "no mem for tx channel");
     // create DMA descriptors
     if (config->flags.with_dma) {
-        // DMA descriptors must be placed in internal SRAM
         mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA;
-        tx_channel->dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, RMT_DMA_NODES_PING_PONG, sizeof(rmt_dma_descriptor_t), mem_caps);
+        // DMA descriptors must be placed in internal SRAM
+        uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
+        // the alignment should meet both the DMA and cache requirement
+        size_t alignment = MAX(data_cache_line_size, RMT_DMA_DESC_ALIGN);
+        tx_channel->dma_nodes = heap_caps_aligned_calloc(alignment, RMT_DMA_NODES_PING_PONG, sizeof(rmt_dma_descriptor_t), mem_caps);
         ESP_GOTO_ON_FALSE(tx_channel->dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no mem for tx DMA nodes");
         // we will use the non-cached address to manipulate the DMA descriptor, for simplicity
         tx_channel->dma_nodes_nc = (rmt_dma_descriptor_t *)RMT_GET_NON_CACHE_ADDR(tx_channel->dma_nodes);
@@ -327,9 +338,9 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_
     tx_channel->base.disable = rmt_tx_disable;
     // return general channel handle
     *ret_chan = &tx_channel->base;
-    ESP_LOGD(TAG, "new tx channel(%d,%d) at %p, gpio=%d, res=%"PRIu32"Hz, hw_mem_base=%p, dma_mem_base=%p, dma_nodes_nc=%p,ping_pong_size=%zu, queue_depth=%zu",
+    ESP_LOGD(TAG, "new tx channel(%d,%d) at %p, gpio=%d, res=%"PRIu32"Hz, hw_mem_base=%p, dma_mem_base=%p, dma_nodes=%p, ping_pong_size=%zu, queue_depth=%zu",
              group_id, channel_id, tx_channel, config->gpio_num, tx_channel->base.resolution_hz,
-             tx_channel->base.hw_mem_base, tx_channel->base.dma_mem_base, tx_channel->dma_nodes_nc, tx_channel->ping_pong_symbols, tx_channel->queue_size);
+             tx_channel->base.hw_mem_base, tx_channel->dma_mem_base, tx_channel->dma_nodes, tx_channel->ping_pong_symbols, tx_channel->queue_size);
     return ESP_OK;
 
 err:
@@ -569,7 +580,7 @@ static void IRAM_ATTR rmt_tx_mark_eof(rmt_tx_channel_t *tx_chan)
     rmt_tx_trans_desc_t *cur_trans = tx_chan->cur_trans;
     rmt_dma_descriptor_t *desc_nc = NULL;
     if (channel->dma_chan) {
-        mem_to_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(channel->dma_mem_base);
+        mem_to_nc = tx_chan->dma_mem_base_nc;
     } else {
         mem_to_nc = channel->hw_mem_base;
     }
@@ -646,7 +657,7 @@ static void IRAM_ATTR rmt_tx_do_transaction(rmt_tx_channel_t *tx_chan, rmt_tx_tr
             tx_chan->dma_nodes_nc[i].next = &tx_chan->dma_nodes[i + 1]; // note, we must use the cache address for the next pointer
             tx_chan->dma_nodes_nc[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
         }
-        tx_chan->dma_nodes_nc[1].next = &tx_chan->dma_nodes[0];
+        tx_chan->dma_nodes_nc[RMT_DMA_NODES_PING_PONG - 1].next = &tx_chan->dma_nodes[0];
     }
 #endif // SOC_RMT_SUPPORT_DMA
 
diff --git a/components/esp_driver_rmt/test_apps/.build-test-rules.yml b/components/esp_driver_rmt/test_apps/.build-test-rules.yml
index 7360259435d..2a97c6cdec1 100644
--- a/components/esp_driver_rmt/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_rmt/test_apps/.build-test-rules.yml
@@ -3,9 +3,5 @@
 components/esp_driver_rmt/test_apps/rmt:
   disable:
     - if: SOC_RMT_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: test not passing, should be re-enabled # TODO: IDF-8961
   depends_components:
     - esp_driver_rmt
diff --git a/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_iram.c b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_iram.c
index 985ea2a7a33..2bab22f3f20 100644
--- a/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_iram.c
+++ b/components/esp_driver_rmt/test_apps/rmt/main/test_rmt_iram.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -107,7 +107,8 @@ typedef struct {
     TaskHandle_t task_to_notify;
     size_t received_symbol_num;
     rmt_receive_config_t rx_config;
-    rmt_symbol_word_t remote_codes[128];
+    rmt_symbol_word_t* remote_codes;
+    size_t remote_codes_mem_size;
 } test_rx_user_data_t;
 
 IRAM_ATTR
@@ -121,7 +122,7 @@ static bool test_rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx
         if (test_user_data->received_symbol_num == TEST_RMT_SYMBOLS) {
             vTaskNotifyGiveFromISR(test_user_data->task_to_notify, &high_task_wakeup);
         } else {
-            rmt_receive(channel, test_user_data->remote_codes, sizeof(test_user_data->remote_codes), &test_user_data->rx_config);
+            rmt_receive(channel, test_user_data->remote_codes, test_user_data->remote_codes_mem_size, &test_user_data->rx_config);
         }
     }
     return high_task_wakeup == pdTRUE;
@@ -129,6 +130,11 @@ static bool test_rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx
 
 static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_clock_source_t clk_src)
 {
+    uint32_t const test_rx_buffer_symbols = 128;
+    rmt_symbol_word_t *remote_codes = heap_caps_aligned_calloc(64, test_rx_buffer_symbols, sizeof(rmt_symbol_word_t),
+                                                               MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
+    TEST_ASSERT_NOT_NULL(remote_codes);
+
     rmt_rx_channel_config_t rx_channel_cfg = {
         .clk_src = clk_src,
         .resolution_hz = 1000000, // 1MHz, 1 tick = 1us
@@ -155,6 +161,8 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c
             .signal_range_min_ns = 1250,
             .signal_range_max_ns = 12000000,
         },
+        .remote_codes = remote_codes,
+        .remote_codes_mem_size = test_rx_buffer_symbols * sizeof(rmt_symbol_word_t),
     };
     TEST_ESP_OK(rmt_rx_register_event_callbacks(rx_channel, &cbs, &test_user_data));
 
@@ -162,7 +170,7 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c
     TEST_ESP_OK(rmt_enable(rx_channel));
 
     // ready to receive
-    TEST_ESP_OK(rmt_receive(rx_channel, test_user_data.remote_codes, sizeof(test_user_data.remote_codes), &test_user_data.rx_config));
+    TEST_ESP_OK(rmt_receive(rx_channel, remote_codes, test_user_data.remote_codes_mem_size, &test_user_data.rx_config));
 
     // disable the flash cache, and simulate input signal by GPIO
     unity_utils_run_cache_disable_stub(test_simulate_input_post_cache_disable, TEST_RMT_GPIO_NUM_A);
@@ -174,6 +182,7 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c
     TEST_ESP_OK(rmt_disable(rx_channel));
     printf("delete channels and encoder\r\n");
     TEST_ESP_OK(rmt_del_channel(rx_channel));
+    free(remote_codes);
 }
 
 TEST_CASE("rmt rx iram safe", "[rmt]")
diff --git a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py
index 95e33cf3168..d800e611ba3 100644
--- a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py
+++ b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py
@@ -10,6 +10,7 @@
 @pytest.mark.esp32c3
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
+@pytest.mark.esp32p4
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/components/esp_driver_sdmmc/src/sdmmc_host.c b/components/esp_driver_sdmmc/src/sdmmc_host.c
index cbfe397aa88..2f79ef30b9c 100644
--- a/components/esp_driver_sdmmc/src/sdmmc_host.c
+++ b/components/esp_driver_sdmmc/src/sdmmc_host.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,6 +19,7 @@
 #include "driver/gpio.h"
 #include "driver/sdmmc_host.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/esp_ldo.h"
 #include "sdmmc_private.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
@@ -54,6 +55,7 @@ typedef struct slot_ctx_t {
     size_t slot_width;
     sdmmc_slot_io_info_t slot_gpio_num;
     bool use_gpio_matrix;
+    esp_ldo_unit_handle_t ldo_unit;
 } slot_ctx_t;
 
 /**
@@ -662,6 +664,21 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
     if (ret != ESP_OK) {
         return ret;
     }
+
+#if SOC_MULTI_USAGE_LDO_SUPPORTED
+    esp_ldo_unit_init_cfg_t init_ldo_cfg = {
+        .unit_id = LDO_UNIT_4,
+        .cfg = {
+            .voltage_mv = 3300,
+        },
+        .flags.shared_ldo = true,
+    };
+    esp_ldo_unit_handle_t ldo_unit = NULL;
+    ESP_RETURN_ON_ERROR(esp_ldo_init_unit(&init_ldo_cfg, &ldo_unit), TAG, "LDO init failed");
+    ESP_RETURN_ON_ERROR(esp_ldo_enable_unit(ldo_unit), TAG, "LDO enable failed");
+    s_host_ctx.slot_ctx[slot].ldo_unit = ldo_unit;
+#endif
+
     return ESP_OK;
 }
 
@@ -683,6 +700,16 @@ esp_err_t sdmmc_host_deinit(void)
         sdmmc_ll_enable_bus_clock(s_host_ctx.hal.dev, false);
     }
 
+#if SOC_MULTI_USAGE_LDO_SUPPORTED
+    for (int i = 0; i < SOC_SDMMC_NUM_SLOTS; i++) {
+        if (s_host_ctx.slot_ctx[i].ldo_unit) {
+            ESP_RETURN_ON_ERROR(esp_ldo_disable_unit(s_host_ctx.slot_ctx[i].ldo_unit), TAG, "LDO disable failed");
+            ESP_RETURN_ON_ERROR(esp_ldo_deinit_unit(s_host_ctx.slot_ctx[i].ldo_unit), TAG, "LDO deinit failed");
+            s_host_ctx.slot_ctx[i].ldo_unit = NULL;
+        }
+    }
+#endif
+
     return ESP_OK;
 }
 
diff --git a/components/esp_driver_uart/src/uart_vfs.c b/components/esp_driver_uart/src/uart_vfs.c
index c3e1bca87b2..a2ec035e278 100644
--- a/components/esp_driver_uart/src/uart_vfs.c
+++ b/components/esp_driver_uart/src/uart_vfs.c
@@ -1071,7 +1071,7 @@ void uart_vfs_dev_use_driver(int uart_num)
     _lock_release_recursive(&s_ctx[uart_num]->read_lock);
 }
 
-#if CONFIG_VFS_SUPPORT_IO && CONFIG_ESP_CONSOLE_UART
+#if CONFIG_ESP_CONSOLE_UART
 ESP_SYSTEM_INIT_FN(init_vfs_uart, CORE, BIT(0), 110)
 {
     esp_vfs_set_primary_dev_vfs_def_struct(&uart_vfs);
diff --git a/components/esp_driver_usb_serial_jtag/CMakeLists.txt b/components/esp_driver_usb_serial_jtag/CMakeLists.txt
new file mode 100644
index 00000000000..48856a7bb3a
--- /dev/null
+++ b/components/esp_driver_usb_serial_jtag/CMakeLists.txt
@@ -0,0 +1,25 @@
+set(srcs)
+set(include "include")
+
+# USB Serial JTAG related source files
+if(CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED)
+    list(APPEND srcs "src/usb_serial_jtag.c"
+                     "src/usb_serial_jtag_connection_monitor.c")
+endif()
+
+idf_component_register(SRCS ${srcs}
+                    INCLUDE_DIRS ${include}
+                    PRIV_REQUIRES esp_driver_gpio esp_ringbuf esp_pm esp_timer
+                    )
+
+if(CONFIG_VFS_SUPPORT_IO AND CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED)
+    target_link_libraries(${COMPONENT_LIB} PUBLIC idf::vfs)
+    target_sources(${COMPONENT_LIB} PRIVATE "src/usb_serial_jtag_vfs.c")
+    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u usb_serial_jtag_vfs_include_dev_init")
+endif()
+
+# If system needs to monitor USJ connection status, then usb_serial_jtag_connection_monitor object file has to be linked
+# to the binary, to allow tick hook to be registered
+if(CONFIG_USJ_NO_AUTO_LS_ON_CONNECTION OR CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED)
+    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u usb_serial_jtag_connection_monitor_include")
+endif()
diff --git a/components/esp_driver_usb_serial_jtag/Kconfig b/components/esp_driver_usb_serial_jtag/Kconfig
new file mode 100644
index 00000000000..f0c72cde491
--- /dev/null
+++ b/components/esp_driver_usb_serial_jtag/Kconfig
@@ -0,0 +1,16 @@
+menu "ESP-Driver:USB Serial/JTAG Configuration"
+    depends on SOC_USB_SERIAL_JTAG_SUPPORTED
+    config USJ_NO_AUTO_LS_ON_CONNECTION
+        bool "Don't enter the automatic light sleep when USB Serial/JTAG port is connected"
+        depends on PM_ENABLE && ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
+        default n
+        help
+            If enabled, the chip will constantly monitor the connection status of the USB Serial/JTAG port. As long
+            as the USB Serial/JTAG is connected, a ESP_PM_NO_LIGHT_SLEEP power management lock will be acquired to
+            prevent the system from entering light sleep.
+            This option can be useful if serial monitoring is needed via USB Serial/JTAG while power management is
+            enabled, as the USB Serial/JTAG cannot work under light sleep and after waking up from light sleep.
+            Note. This option can only control the automatic Light-Sleep behavior. If esp_light_sleep_start() is
+            called manually from the program, enabling this option will not prevent light sleep entry even if the
+            USB Serial/JTAG is in use.
+endmenu # USB Serial/JTAG Configuration
diff --git a/components/driver/usb_serial_jtag/include/driver/usb_serial_jtag.h b/components/esp_driver_usb_serial_jtag/include/driver/usb_serial_jtag.h
similarity index 98%
rename from components/driver/usb_serial_jtag/include/driver/usb_serial_jtag.h
rename to components/esp_driver_usb_serial_jtag/include/driver/usb_serial_jtag.h
index fec968a5bfc..db2c00f544d 100644
--- a/components/driver/usb_serial_jtag/include/driver/usb_serial_jtag.h
+++ b/components/esp_driver_usb_serial_jtag/include/driver/usb_serial_jtag.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/esp_driver_usb_serial_jtag/include/driver/usb_serial_jtag_vfs.h b/components/esp_driver_usb_serial_jtag/include/driver/usb_serial_jtag_vfs.h
new file mode 100644
index 00000000000..c5a790ee4b7
--- /dev/null
+++ b/components/esp_driver_usb_serial_jtag/include/driver/usb_serial_jtag_vfs.h
@@ -0,0 +1,72 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_err.h"
+#include "esp_vfs.h"
+#include "esp_vfs_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief add /dev/usbserjtag virtual filesystem driver
+ *
+ * This function is called from startup code to enable console output
+ */
+esp_err_t usb_serial_jtag_vfs_register(void);
+
+/**
+ * @brief Set the line endings expected to be received
+ *
+ * This specifies the conversion between line endings received and
+ * newlines ('\n', LF) passed into stdin:
+ *
+ * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF
+ * - ESP_LINE_ENDINGS_CR: convert CR to LF
+ * - ESP_LINE_ENDINGS_LF: no modification
+ *
+ * @note this function is not thread safe w.r.t. reading
+ *
+ * @param mode line endings expected
+ */
+void usb_serial_jtag_vfs_set_rx_line_endings(esp_line_endings_t mode);
+
+/**
+ * @brief Set the line endings to sent
+ *
+ * This specifies the conversion between newlines ('\n', LF) on stdout and line
+ * endings sent:
+ *
+ * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF
+ * - ESP_LINE_ENDINGS_CR: convert LF to CR
+ * - ESP_LINE_ENDINGS_LF: no modification
+ *
+ * @note this function is not thread safe w.r.t. writing
+ *
+ * @param mode line endings to send
+ */
+void usb_serial_jtag_vfs_set_tx_line_endings(esp_line_endings_t mode);
+
+/**
+ * @brief set VFS to use USB-SERIAL-JTAG driver for reading and writing
+ * @note application must configure USB-SERIAL-JTAG driver before calling these functions
+ * With these functions, read and write are blocking and interrupt-driven.
+ */
+void usb_serial_jtag_vfs_use_driver(void);
+
+/**
+ * @brief set VFS to use simple functions for reading and writing UART
+ * Read is non-blocking, write is busy waiting until TX FIFO has enough space.
+ * These functions are used by default.
+ */
+void usb_serial_jtag_vfs_use_nonblocking(void);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/driver/usb_serial_jtag/usb_serial_jtag.c b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c
similarity index 95%
rename from components/driver/usb_serial_jtag/usb_serial_jtag.c
rename to components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c
index c6c8951d3f1..06130db5b36 100644
--- a/components/driver/usb_serial_jtag/usb_serial_jtag.c
+++ b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,7 +35,7 @@ typedef enum {
 #define USB_SER_JTAG_ENDP_SIZE          (64)
 #define USB_SER_JTAG_RX_MAX_SIZE        (64)
 
-typedef struct{
+typedef struct {
     intr_handle_t intr_handle;          /*!< USB-SERIAL-JTAG interrupt handler */
     portMUX_TYPE spinlock;              /*!< Spinlock for usb_serial_jtag */
     _Atomic fifo_status_t fifo_status;  /*!< Record the status of fifo */
@@ -63,7 +63,8 @@ static size_t usb_serial_jtag_write_and_flush(const uint8_t *buf, uint32_t wr_le
     return size;
 }
 
-static void usb_serial_jtag_isr_handler_default(void *arg) {
+static void usb_serial_jtag_isr_handler_default(void *arg)
+{
     BaseType_t xTaskWoken = 0;
     uint32_t usbjtag_intr_status = 0;
     usbjtag_intr_status = usb_serial_jtag_ll_get_intsts_mask();
@@ -154,7 +155,7 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
     ESP_RETURN_ON_FALSE((usb_serial_jtag_config->rx_buffer_size > 0), ESP_ERR_INVALID_ARG, USB_SERIAL_JTAG_TAG, "RX buffer is not prepared");
     ESP_RETURN_ON_FALSE((usb_serial_jtag_config->rx_buffer_size > USB_SER_JTAG_RX_MAX_SIZE), ESP_ERR_INVALID_ARG, USB_SERIAL_JTAG_TAG, "RX buffer prepared is so small, should larger than 64");
     ESP_RETURN_ON_FALSE((usb_serial_jtag_config->tx_buffer_size > 0), ESP_ERR_INVALID_ARG, USB_SERIAL_JTAG_TAG, "TX buffer is not prepared");
-    p_usb_serial_jtag_obj = (usb_serial_jtag_obj_t*) heap_caps_calloc(1, sizeof(usb_serial_jtag_obj_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
+    p_usb_serial_jtag_obj = (usb_serial_jtag_obj_t*) heap_caps_calloc(1, sizeof(usb_serial_jtag_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     p_usb_serial_jtag_obj->rx_buf_size = usb_serial_jtag_config->rx_buffer_size;
     p_usb_serial_jtag_obj->tx_buf_size = usb_serial_jtag_config->tx_buffer_size;
     p_usb_serial_jtag_obj->tx_stash_cnt = 0;
@@ -188,9 +189,9 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
     // Configure PHY
     usb_fsls_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
 
-    usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY|
-                                         USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
-    usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY|
+    usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY |
+                                       USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
+    usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY |
                                      USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
 
     err = esp_intr_alloc(ETS_USB_SERIAL_JTAG_INTR_SOURCE, 0, usb_serial_jtag_isr_handler_default, NULL, &p_usb_serial_jtag_obj->intr_handle);
@@ -245,7 +246,7 @@ int usb_serial_jtag_write_bytes(const void* src, size_t size, TickType_t ticks_t
 
     // Blocking method, Sending data to ringbuffer, and handle the data in ISR.
     if (size - sent_data > 0) {
-        result = xRingbufferSend(p_usb_serial_jtag_obj->tx_ring_buf, (void*) (buff+sent_data), size-sent_data, ticks_to_wait);
+        result = xRingbufferSend(p_usb_serial_jtag_obj->tx_ring_buf, (void*)(buff + sent_data), size - sent_data, ticks_to_wait);
     } else {
         atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_IDLE);
     }
@@ -255,7 +256,7 @@ int usb_serial_jtag_write_bytes(const void* src, size_t size, TickType_t ticks_t
 
 esp_err_t usb_serial_jtag_driver_uninstall(void)
 {
-    if(p_usb_serial_jtag_obj == NULL) {
+    if (p_usb_serial_jtag_obj == NULL) {
         ESP_LOGI(USB_SERIAL_JTAG_TAG, "ALREADY NULL");
         return ESP_OK;
     }
@@ -265,11 +266,11 @@ esp_err_t usb_serial_jtag_driver_uninstall(void)
     usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
     esp_intr_free(p_usb_serial_jtag_obj->intr_handle);
 
-    if(p_usb_serial_jtag_obj->rx_ring_buf) {
+    if (p_usb_serial_jtag_obj->rx_ring_buf) {
         vRingbufferDelete(p_usb_serial_jtag_obj->rx_ring_buf);
         p_usb_serial_jtag_obj->rx_ring_buf = NULL;
     }
-    if(p_usb_serial_jtag_obj->tx_ring_buf) {
+    if (p_usb_serial_jtag_obj->tx_ring_buf) {
         vRingbufferDelete(p_usb_serial_jtag_obj->tx_ring_buf);
         p_usb_serial_jtag_obj->tx_ring_buf = NULL;
     }
diff --git a/components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_connection_monitor.c
similarity index 95%
rename from components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c
rename to components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_connection_monitor.c
index a3d9b0f78bb..eb38a267e68 100644
--- a/components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c
+++ b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_connection_monitor.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,7 +29,6 @@ static uint32_t remaining_allowed_no_sof_ticks;
 
 static __attribute__((unused)) const char *USB_SERIAL_JTAG_CONN_MONITOR_TAG = "usb_serial_jtag";
 
-
 bool usb_serial_jtag_is_connected(void)
 {
     return s_usb_serial_jtag_conn_status;
@@ -76,7 +75,7 @@ ESP_SYSTEM_INIT_FN(usb_serial_jtag_conn_status_init, SECONDARY, BIT(0), 230)
 {
 #if CONFIG_USJ_NO_AUTO_LS_ON_CONNECTION
     ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "usb_serial_jtag", &s_usb_serial_jtag_pm_lock),
-                            USB_SERIAL_JTAG_CONN_MONITOR_TAG, "create NO_LIGHT_SLEEP lock failed");
+                        USB_SERIAL_JTAG_CONN_MONITOR_TAG, "create NO_LIGHT_SLEEP lock failed");
     // We always assume it is connected at first, so acquires the lock to avoid auto light sleep
     esp_pm_lock_acquire(s_usb_serial_jtag_pm_lock);
 #endif
diff --git a/components/vfs/vfs_usb_serial_jtag.c b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c
similarity index 85%
rename from components/vfs/vfs_usb_serial_jtag.c
rename to components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c
index afbb9dccd00..1976d4bfb79 100644
--- a/components/vfs/vfs_usb_serial_jtag.c
+++ b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,14 +16,17 @@
 #include <sys/param.h>
 #include "esp_timer.h"
 #include "esp_vfs.h"
-#include "esp_vfs_dev.h"
+#include "esp_vfs_dev.h" // Old headers for the aliasing functions
+#include "esp_vfs_usb_serial_jtag.h" // Old headers for the aliasing functions
+#include "esp_private/esp_vfs_console.h"
 #include "esp_attr.h"
 #include "esp_log.h"
 #include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/usb_serial_jtag_ll.h"
-#include "esp_vfs_usb_serial_jtag.h"
+#include "driver/usb_serial_jtag_vfs.h"
 #include "driver/usb_serial_jtag.h"
+#include "esp_private/startup_internal.h"
 
 // Token signifying that no character is available
 #define NONE -1
@@ -53,7 +56,6 @@ typedef int (*rx_func_t)(int);
 static void usb_serial_jtag_tx_char(int fd, int c);
 static int usb_serial_jtag_rx_char(int fd);
 
-
 //If no host is listening to the CDCACM port, the TX buffer
 //will never be able to flush to the host. Instead of the Tx
 //routines waiting forever, if the buffer hasn't been flushed
@@ -89,11 +91,11 @@ typedef struct {
     rx_func_t rx_func;
     // Timestamp of last time we managed to write something to the tx buffer
     int64_t last_tx_ts;
-} vfs_usb_serial_jtag_context_t;
+} usb_serial_jtag_vfs_context_t;
 
 //If the context should be dynamically initialized, remove this structure
 //and point s_ctx to allocated data.
-static vfs_usb_serial_jtag_context_t s_ctx = {
+static usb_serial_jtag_vfs_context_t s_ctx = {
     .peek_char = NONE,
     .tx_mode = DEFAULT_TX_MODE,
     .rx_mode = DEFAULT_RX_MODE,
@@ -109,7 +111,7 @@ static int usb_serial_jtag_open(const char * path, int flags, int mode)
 
 static void usb_serial_jtag_tx_char(int fd, int c)
 {
-    uint8_t cc=(uint8_t)c;
+    uint8_t cc = (uint8_t)c;
     // Try to write to the buffer as long as we still expect the buffer to have
     // a chance of being emptied by an active host. Just drop the data if there's
     // no chance anymore.
@@ -163,7 +165,6 @@ static ssize_t usb_serial_jtag_write(int fd, const void * data, size_t size)
     return size;
 }
 
-
 /* Helper function which returns a previous character or reads a new one from
  * the port. Previous character can be returned ("pushed back") using
  * usb_serial_jtag_return_char function.
@@ -281,7 +282,6 @@ static int usb_serial_jtag_fsync(int fd)
     return 0;
 }
 
-
 #ifdef CONFIG_VFS_SUPPORT_TERMIOS
 static int usb_serial_jtag_tcsetattr(int fd, int optional_actions, const struct termios *p)
 {
@@ -291,18 +291,18 @@ static int usb_serial_jtag_tcsetattr(int fd, int optional_actions, const struct
     }
 
     switch (optional_actions) {
-        case TCSANOW:
-            // nothing to do
-            break;
-        case TCSADRAIN:
-            usb_serial_jtag_fsync(fd);
-            break;
-        case TCSAFLUSH:
-            // Not applicable.
-            break;
-        default:
-            errno = EINVAL;
-            return -1;
+    case TCSANOW:
+        // nothing to do
+        break;
+    case TCSADRAIN:
+        usb_serial_jtag_fsync(fd);
+        break;
+    case TCSAFLUSH:
+        // Not applicable.
+        break;
+    default:
+        errno = EINVAL;
+        return -1;
     }
 
     if (p->c_iflag & IGNCR) {
@@ -354,17 +354,17 @@ static int usb_serial_jtag_tcflush(int fd, int select)
 }
 #endif // CONFIG_VFS_SUPPORT_TERMIOS
 
-void esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(esp_line_endings_t mode)
+void usb_serial_jtag_vfs_set_tx_line_endings(esp_line_endings_t mode)
 {
     s_ctx.tx_mode = mode;
 }
 
-void esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(esp_line_endings_t mode)
+void usb_serial_jtag_vfs_set_rx_line_endings(esp_line_endings_t mode)
 {
     s_ctx.rx_mode = mode;
 }
 
-static const esp_vfs_t vfs = {
+static const esp_vfs_t usj_vfs = {
     .flags = ESP_VFS_FLAG_DEFAULT,
     .write = &usb_serial_jtag_write,
     .open = &usb_serial_jtag_open,
@@ -383,14 +383,30 @@ static const esp_vfs_t vfs = {
 
 const esp_vfs_t* esp_vfs_usb_serial_jtag_get_vfs(void)
 {
-    return &vfs;
+    return &usj_vfs;
 }
 
-esp_err_t esp_vfs_dev_usb_serial_jtag_register(void)
+esp_err_t usb_serial_jtag_vfs_register(void)
 {
     // "/dev/usb_serial_jtag" unfortunately is too long for vfs
-    return esp_vfs_register("/dev/usbserjtag", &vfs, NULL);
+    return esp_vfs_register("/dev/usbserjtag", &usj_vfs, NULL);
+}
+
+#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
+ESP_SYSTEM_INIT_FN(init_vfs_usj, CORE, BIT(0), 111)
+{
+    esp_vfs_set_primary_dev_vfs_def_struct(&usj_vfs);
+    return ESP_OK;
 }
+#endif
+
+#if CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
+ESP_SYSTEM_INIT_FN(init_vfs_usj_sec, CORE, BIT(0), 112)
+{
+    esp_vfs_set_secondary_dev_vfs_def_struct(&usj_vfs);
+    return ESP_OK;
+}
+#endif
 
 /***********************************************************
  * VFS uses USB-SERIAL-JTAG driver part.
@@ -425,7 +441,7 @@ static void usbjtag_tx_char_via_driver(int fd, int c)
     }
 }
 
-void esp_vfs_usb_serial_jtag_use_nonblocking(void)
+void usb_serial_jtag_vfs_use_nonblocking(void)
 {
     _lock_acquire_recursive(&s_ctx.read_lock);
     _lock_acquire_recursive(&s_ctx.write_lock);
@@ -435,7 +451,7 @@ void esp_vfs_usb_serial_jtag_use_nonblocking(void)
     _lock_release_recursive(&s_ctx.read_lock);
 }
 
-void esp_vfs_usb_serial_jtag_use_driver(void)
+void usb_serial_jtag_vfs_use_driver(void)
 {
     _lock_acquire_recursive(&s_ctx.read_lock);
     _lock_acquire_recursive(&s_ctx.write_lock);
@@ -444,3 +460,20 @@ void esp_vfs_usb_serial_jtag_use_driver(void)
     _lock_release_recursive(&s_ctx.write_lock);
     _lock_release_recursive(&s_ctx.read_lock);
 }
+
+void usb_serial_jtag_vfs_include_dev_init(void)
+{
+    // Linker hook function, exists to make the linker examine this file
+}
+
+// -------------------------- esp_vfs_usb_serial_jtag_xxx ALIAS (deprecated) ----------------------------
+
+esp_err_t esp_vfs_dev_usb_serial_jtag_register(void) __attribute__((alias("usb_serial_jtag_vfs_register")));
+
+void esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(esp_line_endings_t mode) __attribute__((alias("usb_serial_jtag_vfs_set_rx_line_endings")));
+
+void esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(esp_line_endings_t mode) __attribute__((alias("usb_serial_jtag_vfs_set_tx_line_endings")));
+
+void esp_vfs_usb_serial_jtag_use_nonblocking(void) __attribute__((alias("usb_serial_jtag_vfs_use_nonblocking")));
+
+void esp_vfs_usb_serial_jtag_use_driver(void) __attribute__((alias("usb_serial_jtag_vfs_use_driver")));
diff --git a/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml
new file mode 100644
index 00000000000..5605004cfc9
--- /dev/null
+++ b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml
@@ -0,0 +1,9 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag:
+  disable:
+    - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1
+  depends_components:
+    - vfs
+    - esp_driver_gpio
+    - esp_driver_usb_serial_jtag
diff --git a/components/driver/test_apps/usb_serial_jtag/CMakeLists.txt b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/CMakeLists.txt
similarity index 100%
rename from components/driver/test_apps/usb_serial_jtag/CMakeLists.txt
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/CMakeLists.txt
diff --git a/components/driver/test_apps/usb_serial_jtag/README.md b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md
similarity index 100%
rename from components/driver/test_apps/usb_serial_jtag/README.md
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md
diff --git a/components/driver/test_apps/usb_serial_jtag/main/CMakeLists.txt b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/CMakeLists.txt
similarity index 100%
rename from components/driver/test_apps/usb_serial_jtag/main/CMakeLists.txt
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/CMakeLists.txt
diff --git a/components/driver/test_apps/usb_serial_jtag/main/test_app_main.c b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_app_main.c
similarity index 100%
rename from components/driver/test_apps/usb_serial_jtag/main/test_app_main.c
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_app_main.c
diff --git a/components/driver/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
similarity index 90%
rename from components/driver/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
index 9d55d6f1e6c..b1bdb9c6066 100644
--- a/components/driver/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
+++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,7 @@
 #include "driver/usb_serial_jtag.h"
 #include "esp_log.h"
 #include "esp_vfs_dev.h"
-#include "esp_vfs_usb_serial_jtag.h"
+#include "driver/usb_serial_jtag_vfs.h"
 #include "driver/usb_serial_jtag.h"
 #include <freertos/FreeRTOS.h>
 #include <freertos/semphr.h>
@@ -41,7 +41,6 @@ static void test_task_driver2(void *pvParameters)
     vTaskDelete(NULL);
 }
 
-
 TEST_CASE("test print via usb_serial_jtag driver multiple times in different tasks", "[usb_serial_jtag]")
 {
     usb_serial_jtag_driver_config_t cfg = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT();
@@ -50,7 +49,7 @@ TEST_CASE("test print via usb_serial_jtag driver multiple times in different tas
     TEST_ESP_OK(usb_serial_jtag_driver_install(&cfg));
 
     // Tell vfs to use usb-serial-jtag driver
-    esp_vfs_usb_serial_jtag_use_driver();
+    usb_serial_jtag_vfs_use_driver();
 
     xTaskCreate(test_task_driver2, "usj_print_1", 4096, sem, 10, NULL);
     xTaskCreate(test_task_driver1, "usj_print_2", 4096, sem, 10, NULL);
@@ -61,6 +60,6 @@ TEST_CASE("test print via usb_serial_jtag driver multiple times in different tas
     vSemaphoreDelete(sem);
     vTaskDelay(5);
 
-    esp_vfs_usb_serial_jtag_use_nonblocking();
+    usb_serial_jtag_vfs_use_nonblocking();
     usb_serial_jtag_driver_uninstall();
 }
diff --git a/components/driver/test_apps/usb_serial_jtag/pytest_usb_serial_jtag.py b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/pytest_usb_serial_jtag.py
similarity index 100%
rename from components/driver/test_apps/usb_serial_jtag/pytest_usb_serial_jtag.py
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/pytest_usb_serial_jtag.py
diff --git a/components/driver/test_apps/usb_serial_jtag/sdkconfig.ci.release b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/sdkconfig.ci.release
similarity index 100%
rename from components/driver/test_apps/usb_serial_jtag/sdkconfig.ci.release
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/sdkconfig.ci.release
diff --git a/components/driver/test_apps/usb_serial_jtag/sdkconfig.defaults b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/sdkconfig.defaults
similarity index 100%
rename from components/driver/test_apps/usb_serial_jtag/sdkconfig.defaults
rename to components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/sdkconfig.defaults
diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c
index 1b120532c54..0ef7b022b37 100644
--- a/components/esp_http_client/esp_http_client.c
+++ b/components/esp_http_client/esp_http_client.c
@@ -1141,7 +1141,7 @@ static int esp_http_client_get_data(esp_http_client_handle_t client)
     esp_http_buffer_t *res_buffer = client->response->buffer;
 
     ESP_LOGD(TAG, "data_process=%"PRId64", content_length=%"PRId64, client->response->data_process, client->response->content_length);
-
+    errno = 0;
     int rlen = esp_transport_read(client->transport, res_buffer->data, client->buffer_size_rx, client->timeout_ms);
     if (rlen >= 0) {
         // When tls error is ESP_TLS_ERR_SSL_WANT_READ (-0x6900), esp_trasnport_read returns ERR_TCP_TRANSPORT_CONNECTION_TIMEOUT (0x0).
@@ -1380,6 +1380,7 @@ int64_t esp_http_client_fetch_headers(esp_http_client_handle_t client)
     client->response->status_code = -1;
 
     while (client->state < HTTP_STATE_RES_COMPLETE_HEADER) {
+        errno = 0;
         buffer->len = esp_transport_read(client->transport, buffer->data, client->buffer_size_rx, client->timeout_ms);
         if (buffer->len <= 0) {
             if (buffer->len == ERR_TCP_TRANSPORT_CONNECTION_TIMEOUT) {
diff --git a/components/esp_hw_support/adc_share_hw_ctrl.c b/components/esp_hw_support/adc_share_hw_ctrl.c
index f9b8167258e..c993797e1df 100644
--- a/components/esp_hw_support/adc_share_hw_ctrl.c
+++ b/components/esp_hw_support/adc_share_hw_ctrl.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -28,6 +28,8 @@
 #include "hal/adc_ll.h"
 #include "esp_private/adc_share_hw_ctrl.h"
 #include "esp_private/sar_periph_ctrl.h"
+#include "esp_private/periph_ctrl.h"
+#include "soc/periph_defs.h"
 //For calibration
 #if CONFIG_IDF_TARGET_ESP32S2
 #include "esp_efuse_rtc_table.h"
@@ -190,3 +192,39 @@ esp_err_t adc2_wifi_release(void)
 
     return ESP_OK;
 }
+
+static portMUX_TYPE s_spinlock = portMUX_INITIALIZER_UNLOCKED;
+
+/*------------------------------------------------------------------------------
+* For those who use APB_SARADC periph
+*----------------------------------------------------------------------------*/
+static int s_adc_digi_ctrlr_cnt;
+
+void adc_apb_periph_claim(void)
+{
+    portENTER_CRITICAL(&s_spinlock);
+    s_adc_digi_ctrlr_cnt++;
+    if (s_adc_digi_ctrlr_cnt == 1) {
+        //enable ADC digital part
+        periph_module_enable(PERIPH_SARADC_MODULE);
+        //reset ADC digital part
+        periph_module_reset(PERIPH_SARADC_MODULE);
+    }
+
+    portEXIT_CRITICAL(&s_spinlock);
+}
+
+void adc_apb_periph_free(void)
+{
+    portENTER_CRITICAL(&s_spinlock);
+    s_adc_digi_ctrlr_cnt--;
+    if (s_adc_digi_ctrlr_cnt == 0) {
+        periph_module_disable(PERIPH_SARADC_MODULE);
+    } else if (s_adc_digi_ctrlr_cnt < 0) {
+        portEXIT_CRITICAL(&s_spinlock);
+        ESP_LOGE(TAG, "%s called, but `s_adc_digi_ctrlr_cnt == 0`", __func__);
+        abort();
+    }
+
+    portEXIT_CRITICAL(&s_spinlock);
+}
diff --git a/components/esp_hw_support/dma/esp_dma_utils.c b/components/esp_hw_support/dma/esp_dma_utils.c
index 5db42309c2d..6dd01cf8635 100644
--- a/components/esp_hw_support/dma/esp_dma_utils.c
+++ b/components/esp_hw_support/dma/esp_dma_utils.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -69,41 +69,54 @@ esp_err_t esp_dma_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr,
     return ret;
 }
 
+static bool s_buf_in_region(const void *ptr, size_t size, esp_dma_buf_location_t location, uint32_t *in_out_flags)
+{
+    bool found = false;
+    if (location == ESP_DMA_BUF_LOCATION_INTERNAL) {
+        if (esp_ptr_dma_capable(ptr) && esp_ptr_dma_capable(ptr + size - 1)) {
+            found = true;
+        }
+    } else if (location == ESP_DMA_BUF_LOCATION_PSRAM) {
+#if SOC_PSRAM_DMA_CAPABLE
+        if (esp_ptr_external_ram(ptr) && esp_ptr_external_ram(ptr + size - 1)) {
+            *in_out_flags |= ESP_DMA_MALLOC_FLAG_PSRAM;
+            found = true;
+        }
+#endif
+    }
+    return found;
+}
+
 bool esp_dma_is_buffer_aligned(const void *ptr, size_t size, esp_dma_buf_location_t location)
 {
     assert(ptr);
     uint32_t flags = ESP_CACHE_MALLOC_FLAG_DMA;
 
-    if (location == ESP_DMA_BUF_LOCATION_INTERNAL) {
-        if (!esp_ptr_dma_capable(ptr) || !esp_ptr_dma_capable(ptr + size - 1)) {
-            return false;
+    bool found = false;
+    if (location == ESP_DMA_BUF_LOCATION_AUTO) {
+        for (int i = ESP_DMA_BUF_LOCATION_INTERNAL; i < ESP_DMA_BUF_LOCATION_AUTO; i++) {
+            if (s_buf_in_region(ptr, size, i, &flags)) {
+                found = true;
+                break;
+            }
         }
+    } else if (location == ESP_DMA_BUF_LOCATION_INTERNAL) {
+        found = s_buf_in_region(ptr, size, ESP_DMA_BUF_LOCATION_INTERNAL, &flags);
     } else {
-#if !SOC_PSRAM_DMA_CAPABLE
+        found = s_buf_in_region(ptr, size, ESP_DMA_BUF_LOCATION_PSRAM, &flags);
+    }
+    if (!found) {
         return false;
-#endif
-        if (!esp_ptr_external_ram(ptr) || !esp_ptr_external_ram(ptr + size - 1)) {
-            return false;
-        }
-
-        flags |= ESP_DMA_MALLOC_FLAG_PSRAM;
     }
 
     bool is_aligned = false;
-
-#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+    size_t dma_alignment = 0;
     size_t cache_alignment = 0;
+    size_t alignment = 0;
     esp_err_t ret = esp_cache_get_alignment(flags, &cache_alignment);
     assert(ret == ESP_OK);
-    if (((intptr_t)ptr % cache_alignment == 0) && (size % cache_alignment == 0)) {
-        is_aligned = true;
-    }
-#else
-    (void)size;
-    if ((intptr_t)ptr % 4 == 0) {
-        is_aligned = true;
-    }
-#endif
+    alignment = MAX(dma_alignment, cache_alignment);
+    is_aligned = ((intptr_t)ptr % alignment == 0) && (size % alignment == 0);
 
     return is_aligned;
 }
diff --git a/components/esp_hw_support/include/esp_dma_utils.h b/components/esp_hw_support/include/esp_dma_utils.h
index 3c59db90080..747cd1b31b4 100644
--- a/components/esp_hw_support/include/esp_dma_utils.h
+++ b/components/esp_hw_support/include/esp_dma_utils.h
@@ -59,6 +59,7 @@ esp_err_t esp_dma_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr,
 typedef enum {
     ESP_DMA_BUF_LOCATION_INTERNAL,    ///< DMA buffer is in internal memory
     ESP_DMA_BUF_LOCATION_PSRAM,       ///< DMA buffer is in PSRAM
+    ESP_DMA_BUF_LOCATION_AUTO,        ///< Auto detect buffer location, under this condition API will loop to search the buffer location
 } esp_dma_buf_location_t;
 
 /**
diff --git a/components/esp_hw_support/include/esp_private/adc_share_hw_ctrl.h b/components/esp_hw_support/include/esp_private/adc_share_hw_ctrl.h
index 4d9de5270c6..5bf1084730f 100644
--- a/components/esp_hw_support/include/esp_private/adc_share_hw_ctrl.h
+++ b/components/esp_hw_support/include/esp_private/adc_share_hw_ctrl.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -156,6 +156,24 @@ void adc2_cal_include(void);
 #define adc2_cal_include()
 #endif //CONFIG_IDF_TARGET_*
 
+/*------------------------------------------------------------------------------
+* For those who use APB_SARADC periph
+*----------------------------------------------------------------------------*/
+/**
+ * @brief Claim the usage of the APB_SARADC periph
+ *
+ * Reference count inside
+ */
+void adc_apb_periph_claim(void);
+
+/**
+ * @brief Free the usage of the APB_SARADC periph
+ *
+ * Reference count inside
+ */
+void adc_apb_periph_free(void);
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hw_support/include/esp_private/esp_ldo.h b/components/esp_hw_support/include/esp_private/esp_ldo.h
index 9cbe9cd4e97..98486659112 100644
--- a/components/esp_hw_support/include/esp_private/esp_ldo.h
+++ b/components/esp_hw_support/include/esp_private/esp_ldo.h
@@ -9,16 +9,12 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include "esp_err.h"
+#include "hal/ldo_types.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define ESP_LDO_ID_1    0    ///< See datasheet `VFB/VO1`
-#define ESP_LDO_ID_2    1    ///< See datasheet `VFB/VO2`
-#define ESP_LDO_ID_3    2    ///< See datasheet `VFB/VO3`
-#define ESP_LDO_ID_4    3    ///< See datasheet `VFB/VO4`
-
 /**
  * @brief Type of LDO unit handle
  */
@@ -35,7 +31,7 @@ typedef struct {
  * @brief LDO driver initial configurations
  */
 typedef struct {
-    int unit_id;               ///< LDO unit
+    int unit_id;                    ///< LDO ID, this is aligned with datasheet, e.g. you should set this to 1, if using LDO ID 1
     esp_ldo_unit_cfg_t cfg;         ///< LDO unit configuration
     struct {
         uint32_t enable_unit: 1;    ///< Enable the LDO unit after it's initialised
diff --git a/components/esp_hw_support/include/esp_private/rtc_clk.h b/components/esp_hw_support/include/esp_private/rtc_clk.h
index 86faa8e9e1f..c71491d569f 100644
--- a/components/esp_hw_support/include/esp_private/rtc_clk.h
+++ b/components/esp_hw_support/include/esp_private/rtc_clk.h
@@ -67,6 +67,12 @@ void rtc_clk_mpll_disable(void);
 void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq);
 #endif  //#if SOC_CLK_MPLL_SUPPORTED
 
+/**
+ * @brief Workaround for C2, S3, C6, H2. Trigger the calibration of PLL. Should be called when the bootloader doesn't provide a good enough PLL accuracy.
+*/
+void rtc_clk_recalib_bbpll(void);
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hw_support/ldo/esp_ldo.c b/components/esp_hw_support/ldo/esp_ldo.c
index 6003fec4f8d..dfc139fe82f 100644
--- a/components/esp_hw_support/ldo/esp_ldo.c
+++ b/components/esp_hw_support/ldo/esp_ldo.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -47,22 +47,23 @@ static bool s_ldo_unit_needs_claim(const esp_ldo_unit_init_cfg_t *init_config);
 esp_ldo_unit_handle_t esp_ldo_init_unit_early(const esp_ldo_unit_init_cfg_t *init_config)
 {
     assert(init_config);
-    assert(init_config->unit_id < LDO_LL_UNIT_NUM);
+    assert(ldo_ll_is_valid_ldo_id(init_config->unit_id));
 
-    ldo_unit_ctx_t *unit = &s_ctx.units[init_config->unit_id];
+    int unit_id = LDO_ID2UNIT(init_config->unit_id);
+    ldo_unit_ctx_t *unit = &s_ctx.units[unit_id];
     bool needs_claim = s_ldo_unit_needs_claim(init_config);
     bool success_claim = false;
 
     if (needs_claim) {
-        success_claim = s_ldo_unit_claim(init_config->unit_id);
+        success_claim = s_ldo_unit_claim(unit_id);
         assert(success_claim);
-        unit->unit_id = init_config->unit_id;
+        unit->unit_id = unit_id;
         unit->voltage_mv = init_config->cfg.voltage_mv;
         unit->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
-        ldo_ll_set_output_voltage_mv(init_config->unit_id, init_config->cfg.voltage_mv);
+        ldo_ll_set_output_voltage_mv(unit_id, init_config->cfg.voltage_mv);
 
         if (init_config->flags.enable_unit) {
-            ldo_ll_enable(init_config->unit_id, true);
+            ldo_ll_enable(unit_id, true);
             unit->enabled = true;
         }
     } else {
@@ -78,28 +79,29 @@ esp_ldo_unit_handle_t esp_ldo_init_unit_early(const esp_ldo_unit_init_cfg_t *ini
 esp_err_t esp_ldo_init_unit(const esp_ldo_unit_init_cfg_t *init_config, esp_ldo_unit_handle_t *ret_unit)
 {
     ESP_RETURN_ON_FALSE(init_config && ret_unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
-    ESP_RETURN_ON_FALSE(init_config->unit_id < LDO_LL_UNIT_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid unit");
+    ESP_RETURN_ON_FALSE(ldo_ll_is_valid_ldo_id(init_config->unit_id), ESP_ERR_INVALID_ARG, TAG, "invalid ldo id");
 
-    ldo_unit_ctx_t *unit = &s_ctx.units[init_config->unit_id];
+    int unit_id = LDO_ID2UNIT(init_config->unit_id);
+    ldo_unit_ctx_t *unit = &s_ctx.units[unit_id];
     bool needs_claim = s_ldo_unit_needs_claim(init_config);
     bool success_claim = false;
 
     if (needs_claim) {
-        success_claim = s_ldo_unit_claim(init_config->unit_id);
-        ESP_RETURN_ON_FALSE(success_claim, ESP_ERR_NOT_FOUND, TAG, "ldo%d is already in use", init_config->unit_id + 1);
-        unit->unit_id = init_config->unit_id;
+        success_claim = s_ldo_unit_claim(unit_id);
+        ESP_RETURN_ON_FALSE(success_claim, ESP_ERR_NOT_FOUND, TAG, "ldo%d is already in use", init_config->unit_id);
+        unit->unit_id = unit_id;
         unit->voltage_mv = init_config->cfg.voltage_mv;
         unit->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
-        ldo_ll_set_output_voltage_mv(init_config->unit_id, init_config->cfg.voltage_mv);
+        ldo_ll_set_output_voltage_mv(unit_id, init_config->cfg.voltage_mv);
         if (init_config->flags.enable_unit) {
-            ldo_ll_enable(init_config->unit_id, true);
+            ldo_ll_enable(unit_id, true);
             unit->enabled = true;
         }
-        ESP_LOGD(TAG, "new ldo unit%d is created", unit->unit_id);
+        ESP_LOGD(TAG, "new ldo %d is created", unit->unit_id + 1);
     } else {
         bool same_voltage = init_config->cfg.voltage_mv == unit->voltage_mv;
-        ESP_RETURN_ON_FALSE(same_voltage, ESP_ERR_INVALID_ARG, TAG, "not same voltage, cannot share ldo%d", init_config->unit_id + 1);
-        ESP_LOGD(TAG, "new ldo unit%d is shared", unit->unit_id);
+        ESP_RETURN_ON_FALSE(same_voltage, ESP_ERR_INVALID_ARG, TAG, "not same voltage, cannot share ldo%d", init_config->unit_id);
+        ESP_LOGD(TAG, "new ldo %d is shared", unit->unit_id + 1);
     }
 
     portENTER_CRITICAL(&unit->spinlock);
@@ -195,8 +197,9 @@ static bool s_ldo_unit_free(uint32_t unit)
 static bool s_ldo_unit_needs_claim(const esp_ldo_unit_init_cfg_t *init_config)
 {
     bool needs_claim = false;
+    int unit_id = LDO_ID2UNIT(init_config->unit_id);
 
-    if (s_ctx.units[init_config->unit_id].ref_cnt == 0) {
+    if (s_ctx.units[unit_id].ref_cnt == 0) {
         needs_claim = true;
     } else {
         if (!init_config->flags.shared_ldo) {
diff --git a/components/esp_hw_support/ldo/esp_ldo_psram.c b/components/esp_hw_support/ldo/esp_ldo_psram.c
index f65a0ce0af9..b329fd21719 100644
--- a/components/esp_hw_support/ldo/esp_ldo_psram.c
+++ b/components/esp_hw_support/ldo/esp_ldo_psram.c
@@ -19,7 +19,7 @@ void esp_ldo_vdd_psram_early_init(void)
 {
     if (CONFIG_ESP_VDD_PSRAM_LDO_ID != -1) {
         esp_ldo_unit_init_cfg_t unit_cfg = {
-            .unit_id = LDO_ID2UNIT(CONFIG_ESP_VDD_PSRAM_LDO_ID),
+            .unit_id = CONFIG_ESP_VDD_PSRAM_LDO_ID,
             .cfg = {
                 .voltage_mv = CONFIG_ESP_VDD_PSRAM_LDO_VOLTAGE_MV,
             },
diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c
index db7734f20f3..82c44d5778c 100644
--- a/components/esp_hw_support/port/esp32c2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c
@@ -126,6 +126,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
     /* WAIT CALIBRATION DONE */
     while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+    esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
 
@@ -355,6 +356,24 @@ bool rtc_dig_8m_enabled(void)
     return clk_ll_rc_fast_digi_is_enabled();
 }
 
+// Workaround for bootloader not calibrated well issue.
+// Placed in IRAM because disabling BBPLL may influence the cache
+void rtc_clk_recalib_bbpll(void)
+{
+    rtc_cpu_freq_config_t old_config;
+    rtc_clk_cpu_freq_get_config(&old_config);
+
+    // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
+    // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
+    //   Turn off the BBPLL and do calibration again to fix the issue.
+    // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
+    //   requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
+    if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
+        rtc_clk_cpu_freq_set_xtal();
+        rtc_clk_cpu_freq_set_config(&old_config);
+    }
+}
+
 /* Name used in libphy.a:phy_chip_v7.o
  * TODO: update the library to use rtc_clk_xtal_freq_get
  */
diff --git a/components/esp_hw_support/port/esp32c6/pmu_sleep.c b/components/esp_hw_support/port/esp32c6/pmu_sleep.c
index 9628cc794f8..2f0ab685f5b 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_sleep.c
@@ -289,5 +289,6 @@ void pmu_sleep_enable_hp_sleep_sysclk(bool enable)
 
 uint32_t pmu_sleep_get_wakup_retention_cost(void)
 {
-    return PMU_REGDMA_S2A_WORK_TIME_US;
+    const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
+    return mc->hp.regdma_s2a_work_time_us;
 }
diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c
index 53644617ca3..da6ab452f12 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c
@@ -168,6 +168,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
     /* WAIT CALIBRATION DONE */
     while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+    esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
     rtc_clk_enable_i2c_ana_master_clock(false);
@@ -421,6 +422,25 @@ bool rtc_dig_8m_enabled(void)
     return clk_ll_rc_fast_digi_is_enabled();
 }
 
+// Workaround for bootloader not calibrated well issue.
+// Placed in IRAM because disabling BBPLL may influence the cache
+void rtc_clk_recalib_bbpll(void)
+{
+    rtc_cpu_freq_config_t old_config;
+    rtc_clk_cpu_freq_get_config(&old_config);
+
+    // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
+    // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
+    //   Turn off the BBPLL and do calibration again to fix the issue.
+    // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
+    //   requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
+    if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
+        rtc_clk_cpu_freq_set_xtal();
+        rtc_clk_cpu_freq_set_config(&old_config);
+    }
+}
+
+
 /* Name used in libphy.a:phy_chip_v7.o
  * TODO: update the library to use rtc_clk_xtal_freq_get
  */
diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c
index 75a170d6a4c..80c39d80d5f 100644
--- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c
@@ -24,20 +24,22 @@
 
 void pmu_sleep_enable_regdma_backup(void)
 {
-    /* ESP32H2 does not have PMU HP_AON power domain. because the registers
-     * of PAU REGDMA is included to PMU TOP power domain, cause the contents
-     * of PAU REGDMA registers will be lost when the TOP domain is powered down
-     * during light sleep, so we does not need to enable REGDMA backup here.
-     * We will use the software to trigger REGDMA to backup or restore. */
+    assert(PMU_instance()->hal);
+    /* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP
+        * and HP_MODEM or HP_MODEM and HP_ACTIVE states switching,
+        * respectively. entry 3 is reserved, not used yet! */
+    pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal);
 }
 
 void pmu_sleep_disable_regdma_backup(void)
 {
+    assert(PMU_instance()->hal);
+    pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
 }
 
 uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
 {
-    const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
+    pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
     /* LP core hardware wait time, microsecond */
     const int lp_clk_switch_time_us         = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
@@ -49,6 +51,11 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
 
     /* HP core hardware wait time, microsecond */
     const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us;
+    if (pd_flags & PMU_SLEEP_PD_TOP) {
+        mc->hp.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US;
+    } else {
+        mc->hp.regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US;
+    }
     const int hp_regdma_wait_time_us = mc->hp.regdma_s2a_work_time_us;
     const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us;
 
@@ -231,5 +238,6 @@ bool pmu_sleep_finish(void)
 
 uint32_t pmu_sleep_get_wakup_retention_cost(void)
 {
-    return PMU_REGDMA_S2A_WORK_TIME_US;
+    const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
+    return mc->hp.regdma_s2a_work_time_us;
 }
diff --git a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
index 50f55ed258c..f66827d0a0a 100644
--- a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
@@ -41,7 +41,9 @@ extern "C" {
 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1
 #define PMU_LP_DBIAS_LIGHTSLEEP_0V7 6
 
-#define PMU_REGDMA_S2A_WORK_TIME_US     0
+#define PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US     0
+// The current value of this depends on the restoration time overhead of the longest chain in regdma
+#define PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US     390
 
 // FOR DEEPSLEEP
 #define PMU_HP_XPD_DEEPSLEEP    0
@@ -440,7 +442,7 @@ typedef struct pmu_sleep_machine_constant {
         .analog_wait_time_us            = 154,  \
         .power_supply_wait_time_us      = 2,    \
         .power_up_wait_time_us          = 2,    \
-        .regdma_s2a_work_time_us        = PMU_REGDMA_S2A_WORK_TIME_US, \
+        .regdma_s2a_work_time_us        = PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US, \
         .regdma_a2s_work_time_us        = 0,    \
         .xtal_wait_stable_time_us       = 250,  \
         .pll_wait_stable_time_us        = 1     \
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c
index 4c657513c0a..e2012a42b6b 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c
@@ -184,6 +184,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
     /* WAIT CALIBRATION DONE */
     while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+    esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
     rtc_clk_enable_i2c_ana_master_clock(false);
@@ -473,3 +474,21 @@ bool rtc_dig_8m_enabled(void)
 {
     return clk_ll_rc_fast_digi_is_enabled();
 }
+
+// Workaround for bootloader not calibrated well issue.
+// Placed in IRAM because disabling BBPLL may influence the cache
+void rtc_clk_recalib_bbpll(void)
+{
+    rtc_cpu_freq_config_t old_config;
+    rtc_clk_cpu_freq_get_config(&old_config);
+
+    // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
+    // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
+    //   Turn off the BBPLL and do calibration again to fix the issue. Flash_PLL comes from the same source as PLL.
+    // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
+    //   requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
+    if (old_config.source == SOC_CPU_CLK_SRC_PLL || old_config.source == SOC_CPU_CLK_SRC_FLASH_PLL) {
+        rtc_clk_cpu_freq_set_xtal();
+        rtc_clk_cpu_freq_set_config(&old_config);
+    }
+}
diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c
index bfa6fc79874..68a0b9368a2 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c
@@ -172,6 +172,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
     /* WAIT CALIBRATION DONE */
     while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+    esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
 
@@ -459,6 +460,25 @@ bool rtc_dig_8m_enabled(void)
     return clk_ll_rc_fast_digi_is_enabled();
 }
 
+// Workaround for bootloader not calibrated well issue.
+// Placed in IRAM because disabling BBPLL may influence the cache
+void rtc_clk_recalib_bbpll(void)
+{
+    rtc_cpu_freq_config_t old_config;
+    rtc_clk_cpu_freq_get_config(&old_config);
+
+    // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons.
+    // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues.
+    //   Turn off the BBPLL and do calibration again to fix the issue.
+    // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's
+    //   requirements. In this case, we don't touch BBPLL to avoid USJ disconnection.
+    if (old_config.source == SOC_CPU_CLK_SRC_PLL) {
+        rtc_clk_cpu_freq_set_xtal();
+        rtc_clk_cpu_freq_set_config(&old_config);
+    }
+}
+
+
 /* Name used in libphy.a:phy_chip_v7.o
  * TODO: update the library to use rtc_clk_xtal_freq_get
  */
diff --git a/components/esp_hw_support/sar_periph_ctrl_common.c b/components/esp_hw_support/sar_periph_ctrl_common.c
index 90b55d66089..f13ca428699 100644
--- a/components/esp_hw_support/sar_periph_ctrl_common.c
+++ b/components/esp_hw_support/sar_periph_ctrl_common.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,7 @@
 #include "soc/temperature_sensor_periph.h"
 #include "soc/periph_defs.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/adc_share_hw_ctrl.h"
 
 extern __attribute__((unused)) portMUX_TYPE rtc_spinlock;
 
@@ -44,6 +45,9 @@ void temperature_sensor_power_acquire(void)
     s_temperature_sensor_power_cnt++;
     if (s_temperature_sensor_power_cnt == 1) {
         regi2c_saradc_enable();
+#if !SOC_TEMPERATURE_SENSOR_IS_INDEPENDENT_FROM_ADC
+        adc_apb_periph_claim();
+#endif
         TSENS_RCC_ATOMIC() {
             temperature_sensor_ll_bus_clk_enable(true);
             temperature_sensor_ll_reset_module();
@@ -71,6 +75,9 @@ void temperature_sensor_power_release(void)
         TSENS_RCC_ATOMIC() {
             temperature_sensor_ll_bus_clk_enable(false);
         }
+#if !SOC_TEMPERATURE_SENSOR_IS_INDEPENDENT_FROM_ADC
+        adc_apb_periph_free();
+#endif
         regi2c_saradc_disable();
     }
     portEXIT_CRITICAL(&rtc_spinlock);
diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c
index 744b9808635..3228840e38e 100644
--- a/components/esp_hw_support/sleep_retention.c
+++ b/components/esp_hw_support/sleep_retention.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -523,6 +523,8 @@ void IRAM_ATTR sleep_retention_do_system_retention(bool backup_or_restore)
         s_retention.highpri <= SLEEP_RETENTION_REGDMA_LINK_LOWEST_PRIORITY) {
         // Set extra linked list head pointer to hardware
         pau_regdma_set_system_link_addr(s_retention.lists[s_retention.highpri].entries[SYSTEM_LINK_NUM]);
+        // When PD TOP, we need to prevent the PMU from triggering the REGDMA backup, because REGDMA will power off
+        pmu_sleep_disable_regdma_backup();
         if (backup_or_restore) {
             pau_regdma_trigger_system_link_backup();
         } else {
diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml
index 962e2599296..6d22ad88502 100644
--- a/components/esp_hw_support/test_apps/.build-test-rules.yml
+++ b/components/esp_hw_support/test_apps/.build-test-rules.yml
@@ -55,3 +55,7 @@ components/esp_hw_support/test_apps/rtc_power_modes:
     - if: IDF_TARGET in ["esp32s2", "esp32s3", "esp32c2", "esp32c3"]
       temporary: true
       reason: the other targets are not tested yet
+
+components/esp_hw_support/test_apps/wakeup_tests:
+  disable:
+    - if: IDF_TARGET in ["esp32c5", "esp32p4", "linux"]
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c
index 47c806bcb3d..546f9baed4c 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c
@@ -15,7 +15,7 @@
 TEST_CASE("LDO unit early / normal allocation", "[LDO]")
 {
     esp_ldo_unit_init_cfg_t init_early_unit_cfg = {
-        .unit_id = ESP_LDO_ID_3,
+        .unit_id = LDO_UNIT_3,
         .cfg = {
             .voltage_mv = 1800,
         },
@@ -27,7 +27,7 @@ TEST_CASE("LDO unit early / normal allocation", "[LDO]")
 
     esp_ldo_unit_handle_t unit = NULL;
     esp_ldo_unit_init_cfg_t init_unit_cfg = {
-        .unit_id = ESP_LDO_ID_4,
+        .unit_id = LDO_UNIT_4,
         .cfg = {
             .voltage_mv = 2500,
         },
@@ -48,21 +48,22 @@ TEST_CASE("LDO unit early / normal allocation", "[LDO]")
 TEST_CASE("LDO unit output", "[LDO][mannual][ignore]")
 {
     esp_ldo_unit_init_cfg_t early_unit_cfg = {
-        .unit_id = ESP_LDO_ID_2,
+        .unit_id = LDO_UNIT_2,
         .cfg = {
-            .voltage_mv = 2500,
+            .voltage_mv = 1800,
         },
+        .flags.shared_ldo = true,
         .flags.enable_unit = true,
     };
     esp_ldo_unit_handle_t early_unit2 = esp_ldo_init_unit_early(&early_unit_cfg);
     assert(early_unit2);
 
-    early_unit_cfg.unit_id = ESP_LDO_ID_3;
+    early_unit_cfg.unit_id = LDO_UNIT_3;
     early_unit_cfg.cfg.voltage_mv = 3300;
     esp_ldo_unit_handle_t early_unit3 = esp_ldo_init_unit_early(&early_unit_cfg);
     assert(early_unit3);
 
-    early_unit_cfg.unit_id = ESP_LDO_ID_4;
+    early_unit_cfg.unit_id = LDO_UNIT_4;
     early_unit_cfg.cfg.voltage_mv = 1100;
     esp_ldo_unit_handle_t early_unit4 = esp_ldo_init_unit_early(&early_unit_cfg);
     assert(early_unit4);
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/CMakeLists.txt b/components/esp_hw_support/test_apps/wakeup_tests/CMakeLists.txt
new file mode 100644
index 00000000000..703608f645a
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/CMakeLists.txt
@@ -0,0 +1,13 @@
+# The following lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+list(PREPEND SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers" "sdkconfig.defaults")
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
+set(COMPONENTS main)
+set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components")
+
+project(wakeup_tests)
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/README.md b/components/esp_hw_support/test_apps/wakeup_tests/README.md
new file mode 100644
index 00000000000..a8b7833fa30
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/README.md
@@ -0,0 +1,2 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/main/CMakeLists.txt b/components/esp_hw_support/test_apps/wakeup_tests/main/CMakeLists.txt
new file mode 100644
index 00000000000..dc2dfd74e71
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/main/CMakeLists.txt
@@ -0,0 +1,12 @@
+set(srcs "test_app_main.c"
+         "src/io_wakeup_cmd.c")
+
+set(include "."
+            "include")
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       INCLUDE_DIRS include
+                       REQUIRES unity esp_driver_gpio console test_utils efuse
+                       WHOLE_ARCHIVE)
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/main/include/io_wakeup_cmd.h b/components/esp_hw_support/test_apps/wakeup_tests/main/include/io_wakeup_cmd.h
new file mode 100644
index 00000000000..5f6e0966b16
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/main/include/io_wakeup_cmd.h
@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void register_io_wakeup_cmd(void);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/main/src/io_wakeup_cmd.c b/components/esp_hw_support/test_apps/wakeup_tests/main/src/io_wakeup_cmd.c
new file mode 100644
index 00000000000..c327f000118
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/main/src/io_wakeup_cmd.c
@@ -0,0 +1,358 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "test_utils.h"
+#include "esp_sleep.h"
+#include "driver/rtc_io.h"
+#include "driver/gpio.h"
+#include "esp_console.h"
+#include "linenoise/linenoise.h"
+#include "argtable3/argtable3.h"
+#include "esp_log.h"
+
+static const char* TAG = "io_wakeup_test";
+
+typedef enum {
+    IO_WAKEUP_LEVEL_LOW = 0,
+    IO_WAKEUP_LEVEL_HIGH,
+    IO_WAKEUP_LEVEL_MAX,
+} io_wakeup_level_t;
+
+static struct {
+    struct arg_int *mode;
+    struct arg_end *end;
+} sleep_args;
+
+static int process_sleep(int argc, char **argv)
+{
+    int nerrors = arg_parse(argc, argv, (void **) &sleep_args);
+    if (nerrors != 0) {
+        arg_print_errors(stderr, sleep_args.end, argv[0]);
+        return 1;
+    }
+
+    if (sleep_args.mode->count == 1) {
+        if (sleep_args.mode->ival[0] == 0) {
+            esp_light_sleep_start();
+            ESP_LOGI(TAG, "esp_light_sleep_start");
+        } else if (sleep_args.mode->ival[0] == 1) {
+            esp_deep_sleep_start();
+        } else {
+            ESP_LOGE(TAG, "no valid arguments");
+            return 1;
+        }
+    } else {
+        ESP_LOGE(TAG, "no valid arguments");
+        return 1;
+    }
+    return 0;
+}
+
+static void register_sleep(void)
+{
+    sleep_args.mode =
+        arg_int0("m", "mode", "<mode>", "configure the sleep mode, 0: light; 1: deep");
+    sleep_args.end = arg_end(2);
+
+    const esp_console_cmd_t cmd = {
+        .command = "sleep",
+        .help = "select the sleep mode",
+        .hint = NULL,
+        .func = &process_sleep,
+        .argtable = &sleep_args
+    };
+    ESP_ERROR_CHECK(esp_console_cmd_register(&cmd));
+}
+
+#if SOC_PM_SUPPORT_EXT1_WAKEUP
+static struct {
+    struct arg_int *pin;
+    struct arg_int *mode;
+    struct arg_lit *disable;
+    struct arg_end *end;
+} ext1_wakeup_args;
+
+static int process_ext1_wakeup(int argc, char **argv)
+{
+    int nerrors = arg_parse(argc, argv, (void **) &ext1_wakeup_args);
+    int io_wakeup_num = 0, io_wakeup_level = 0;
+    if (nerrors != 0) {
+        arg_print_errors(stderr, ext1_wakeup_args.end, argv[0]);
+        return 1;
+    }
+
+    if (ext1_wakeup_args.pin->count == 1) {
+        io_wakeup_num = ext1_wakeup_args.pin->ival[0];
+        ESP_LOGI(TAG, "io_wakeup_num = %d\n", io_wakeup_num);
+    } else {
+        ESP_LOGE(TAG, "no valid arguments");
+        return 1;
+    }
+
+    if (ext1_wakeup_args.mode->count) {
+        if (ext1_wakeup_args.mode->count == 1) {
+            io_wakeup_level = ext1_wakeup_args.mode->ival[0];
+        } else {
+            ESP_LOGE(TAG, "no valid arguments");
+            return 1;
+        }
+    }
+    ESP_LOGI(TAG, "io_wakeup_level = %d\n", io_wakeup_level);
+
+    if (ext1_wakeup_args.disable->count) {
+        ESP_ERROR_CHECK(esp_sleep_disable_ext1_wakeup_io(1ULL << io_wakeup_num));
+    } else {
+#if CONFIG_IDF_TARGET_ESP32
+        ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(1ULL << io_wakeup_num, io_wakeup_level == 0 ? ESP_EXT1_WAKEUP_ALL_LOW : ESP_EXT1_WAKEUP_ANY_HIGH));
+#else
+        ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(1ULL << io_wakeup_num, io_wakeup_level == 0 ? ESP_EXT1_WAKEUP_ANY_LOW : ESP_EXT1_WAKEUP_ANY_HIGH));
+#endif
+    }
+    return 0;
+}
+
+static void register_ext1_wakeup(void)
+{
+    ext1_wakeup_args.pin =
+        arg_int0("p", "pin", "<pin>", "configure the ext1 wakeup pin num");
+    ext1_wakeup_args.mode =
+        arg_int0("m", "mode", "<mode>", "configure the ext1 wakeup mode");
+    ext1_wakeup_args.disable =
+        arg_lit0("d", "disable", "disable the ext1 wakeup on certain pin");
+    ext1_wakeup_args.end = arg_end(4);
+
+    const esp_console_cmd_t cmd = {
+        .command = "ext1",
+        .help = "configue ext1 wakeup",
+        .hint = NULL,
+        .func = &process_ext1_wakeup,
+        .argtable = &ext1_wakeup_args
+    };
+    ESP_ERROR_CHECK(esp_console_cmd_register(&cmd));
+}
+#endif
+
+#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+static struct {
+    struct arg_int *pin;
+    struct arg_int *level;
+    struct arg_lit *disable;
+    struct arg_end *end;
+} rtcio_wakeup_args;
+static int process_rtcio_wakeup(int argc, char **argv)
+{
+    int nerrors = arg_parse(argc, argv, (void **) &rtcio_wakeup_args);
+    int io_wakeup_num = 0, io_wakeup_level = 0;
+    if (nerrors != 0) {
+        arg_print_errors(stderr, rtcio_wakeup_args.end, argv[0]);
+        return 1;
+    }
+
+    if (rtcio_wakeup_args.pin->count == 1) {
+        io_wakeup_num = rtcio_wakeup_args.pin->ival[0];
+        ESP_LOGI(TAG, "io_wakeup_num = %d\n", io_wakeup_num);
+    } else {
+        ESP_LOGE(TAG, "no valid arguments");
+        return 1;
+    }
+
+    if (rtcio_wakeup_args.level->count) {
+        if (rtcio_wakeup_args.level->count == 1) {
+            io_wakeup_level = rtcio_wakeup_args.level->ival[0];
+        } else {
+            ESP_LOGE(TAG, "no valid arguments");
+            return 1;
+        }
+    }
+    ESP_LOGI(TAG, "io_wakeup_level = %d\n", io_wakeup_level);
+
+    if (rtcio_wakeup_args.disable->count) {
+        ESP_ERROR_CHECK(gpio_deep_sleep_wakeup_disable(io_wakeup_num));
+    } else {
+        gpio_config_t config = {
+            .pin_bit_mask = BIT64(io_wakeup_num),
+            .mode = GPIO_MODE_INPUT,
+            .pull_down_en = false,
+            .pull_up_en = false,
+            .intr_type = GPIO_INTR_DISABLE
+        };
+        ESP_ERROR_CHECK(gpio_config(&config));
+
+        /* Enable wake up from GPIO */
+        ESP_ERROR_CHECK(esp_deep_sleep_enable_gpio_wakeup(BIT64(io_wakeup_num), io_wakeup_level));
+    }
+
+    return 0;
+}
+
+static void register_rtcio_wakeup(void)
+{
+    rtcio_wakeup_args.pin =
+        arg_int0("p", "pin", "<pin>", "configure the rtcio wakeup pin num");
+    rtcio_wakeup_args.level =
+        arg_int0("l", "level", "<level>", "configure the rtcio wakeup level");
+    rtcio_wakeup_args.disable =
+        arg_lit0("d", "disable", "disable the rtcio wakeup on certain pin");
+    rtcio_wakeup_args.end = arg_end(4);
+
+    const esp_console_cmd_t cmd = {
+        .command = "rtcio",
+        .help = "configue rtcio wakeup",
+        .hint = NULL,
+        .func = &process_rtcio_wakeup,
+        .argtable = &rtcio_wakeup_args
+    };
+    ESP_ERROR_CHECK(esp_console_cmd_register(&cmd));
+}
+#endif
+
+static struct {
+    struct arg_int *pin;
+    struct arg_int *level;
+    struct arg_lit *disable;
+    struct arg_end *end;
+} gpio_wakeup_args;
+
+static int process_gpio_wakeup(int argc, char **argv)
+{
+    int nerrors = arg_parse(argc, argv, (void **) &gpio_wakeup_args);
+    int io_wakeup_num = 0, io_wakeup_level = 0;
+    if (nerrors != 0) {
+        arg_print_errors(stderr, gpio_wakeup_args.end, argv[0]);
+        return 1;
+    }
+
+    if (gpio_wakeup_args.pin->count == 1) {
+        io_wakeup_num = gpio_wakeup_args.pin->ival[0];
+        ESP_LOGI(TAG, "io_wakeup_num = %d\n", io_wakeup_num);
+    } else {
+        ESP_LOGE(TAG, "no valid arguments");
+        return 1;
+    }
+
+    if (gpio_wakeup_args.level->count) {
+        if (gpio_wakeup_args.level->count == 1) {
+            io_wakeup_level = gpio_wakeup_args.level->ival[0];
+        } else {
+            ESP_LOGE(TAG, "no valid arguments");
+            return 1;
+        }
+    }
+    ESP_LOGI(TAG, "io_wakeup_level = %d\n", io_wakeup_level);
+
+    if (gpio_wakeup_args.disable->count) {
+        ESP_ERROR_CHECK(gpio_wakeup_disable(io_wakeup_num));
+    } else {
+        gpio_config_t config = {
+            .pin_bit_mask = BIT64(io_wakeup_num),
+            .mode = GPIO_MODE_INPUT,
+            .pull_down_en = false,
+            .pull_up_en = false,
+            .intr_type = GPIO_INTR_DISABLE
+        };
+        ESP_ERROR_CHECK(gpio_config(&config));
+
+        /* Enable wake up from GPIO */
+        ESP_ERROR_CHECK(gpio_wakeup_enable(io_wakeup_num, io_wakeup_level == 0 ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL));
+        ESP_ERROR_CHECK(esp_sleep_enable_gpio_wakeup());
+    }
+
+    return 0;
+}
+
+static void register_gpio_wakeup(void)
+{
+    gpio_wakeup_args.pin =
+        arg_int0("p", "pin", "<pin>", "configure the gpio wakeup pin num");
+    gpio_wakeup_args.level =
+        arg_int0("l", "level", "<level>", "configure the gpio wakeup level");
+    gpio_wakeup_args.disable =
+        arg_lit0("d", "disable", "disable the gpio wakeup on certain pin");
+    gpio_wakeup_args.end = arg_end(4);
+
+    const esp_console_cmd_t cmd = {
+        .command = "gpio",
+        .help = "configue gpio wakeup",
+        .hint = NULL,
+        .func = &process_gpio_wakeup,
+        .argtable = &gpio_wakeup_args
+    };
+    ESP_ERROR_CHECK(esp_console_cmd_register(&cmd));
+}
+
+static struct {
+    struct arg_int *pin;
+    struct arg_int *level;
+    struct arg_end *end;
+} gpio_control_args;
+
+static int process_gpio_control(int argc, char **argv)
+{
+    int nerrors = arg_parse(argc, argv, (void **) &gpio_control_args);
+    int io_num = 0, io_level = 0;
+    if (nerrors != 0) {
+        arg_print_errors(stderr, gpio_control_args.end, argv[0]);
+        return 1;
+    }
+
+    if (gpio_control_args.pin->count == 1) {
+        io_num = gpio_control_args.pin->ival[0];
+        ESP_LOGI(TAG, "io_num = %d\n", io_num);
+    } else {
+        ESP_LOGE(TAG, "no valid arguments");
+        return 1;
+    }
+
+    gpio_config_t io_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = (1ULL << io_num)
+    };
+    ESP_ERROR_CHECK(gpio_config(&io_conf));
+    if (gpio_control_args.level->count == 1) {
+        io_level = gpio_control_args.level->ival[0];
+        ESP_LOGI(TAG, "io_level = %d\n", io_level);
+    } else {
+        ESP_LOGI(TAG, "io_num = %d\n", io_num);
+        ESP_LOGE(TAG, "no valid io_level argument");
+    }
+
+    ESP_ERROR_CHECK(gpio_set_level(io_num, io_level == 0 ? 0 : 1));
+
+    return 0;
+}
+
+static void register_gpio_control(void)
+{
+    gpio_control_args.pin =
+        arg_int0("p", "pin", "<pin>", "configure the gpio control pin num");
+    gpio_control_args.level =
+        arg_int0("l", "level", "<level>", "configure the gpio control pin level");
+    gpio_control_args.end = arg_end(3);
+
+    const esp_console_cmd_t cmd = {
+        .command = "gpio_control",
+        .help = "configue gpio control",
+        .hint = NULL,
+        .func = &process_gpio_control,
+        .argtable = &gpio_control_args
+    };
+    ESP_ERROR_CHECK(esp_console_cmd_register(&cmd));
+}
+
+void register_io_wakeup_cmd(void)
+{
+    register_sleep();
+#if SOC_PM_SUPPORT_EXT1_WAKEUP
+    register_ext1_wakeup();
+#endif
+    register_gpio_control();
+    register_gpio_wakeup();
+#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+    register_rtcio_wakeup();
+#endif
+}
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/main/test_app_main.c b/components/esp_hw_support/test_apps/wakeup_tests/main/test_app_main.c
new file mode 100644
index 00000000000..7317c4d4013
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/main/test_app_main.c
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "esp_heap_caps.h"
+#include "esp_log.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "unity_test_utils_memory.h"
+#include "esp_console.h"
+#include "linenoise/linenoise.h"
+#include "argtable3/argtable3.h"
+#include "io_wakeup_cmd.h"
+
+static const char* TAG = "esp_hw_support_test_app";
+#define PROMPT_STR "io_wakeup_test"
+
+#define LEAKS (100)
+
+void setUp(void)
+{
+    unity_utils_record_free_mem();
+}
+
+void tearDown(void)
+{
+    unity_utils_evaluate_leaks_direct(LEAKS);
+}
+
+void app_main(void)
+{
+    ESP_LOGI(TAG, "Running esp-hw-support test app");
+    esp_console_repl_t *repl = NULL;
+    esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT();
+    /* Prompt to be printed before each line.
+     * This can be customized, made dynamic, etc.
+     */
+    repl_config.prompt = PROMPT_STR ">";
+    repl_config.max_cmdline_length = 256;
+    /* Register commands */
+    esp_console_register_help_command();
+    register_io_wakeup_cmd();
+
+    esp_console_dev_uart_config_t hw_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT();
+    ESP_ERROR_CHECK(esp_console_new_repl_uart(&hw_config, &repl_config, &repl));
+
+    ESP_ERROR_CHECK(esp_console_start_repl(repl));
+}
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py
new file mode 100644
index 00000000000..4cf4f5400ae
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py
@@ -0,0 +1,174 @@
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+from time import sleep
+from typing import Tuple
+
+import pytest
+from pytest_embedded_idf.dut import IdfDut
+
+TEST_CONFIGS = [
+    pytest.param('default'),
+]
+
+# TODO: PM-66
+# ESP32: need to fix GPIO16 and GPIO17 bug
+# ESP32S2: need to fix GPIO43 bug
+# ESP32S3: need to fix GPIO33, GPIO34 and GPIO43 bug
+available_gpio_nums = {
+    'esp32': [0, 2, 4, 5, 12, 13, 14, 15, 18, 19, 21, 22, 23, 27],
+    'esp32s2': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 21, 33, 34, 35, 36, 37, 38, 39, 40, 42, 45],
+    'esp32s3': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 21, 35, 36, 37, 39, 40, 42, 45, 46],
+    'esp32c2': [0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 18],
+    'esp32c3': [0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 18, 19],
+    'esp32c6': [0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 15, 18, 19, 20, 21, 22, 23],
+    'esp32h2': [0, 1, 2, 3, 4, 5, 9, 10, 11, 12, 22, 25, 26, 27],
+}
+
+available_rtcio_nums = {
+    'esp32': [36, 37, 38, 39, 34, 35, 4, 0, 2, 15, 13, 12, 14, 27],
+    'esp32s2': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21],
+    'esp32s3': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21],
+    'esp32c2': [0, 1, 2, 3, 4, 5],
+    'esp32c3': [0, 1, 2, 3, 4, 5],
+    'esp32c6': [0, 1, 2, 3, 4, 5, 6, 7],
+    'esp32h2': [7, 8, 9, 10, 11, 12, 13, 14],
+}
+
+
+@pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.generic_multi_device
+@pytest.mark.parametrize('count', [2], indirect=True)
+@pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
+def test_ext1_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None:
+    wakee = dut[0]
+    waker = dut[1]
+
+    chip_type = wakee.app.target
+    gpio_nums = available_gpio_nums.get(chip_type, [])
+    rtcio_nums = available_rtcio_nums.get(chip_type, [])
+
+    for wakeup_level in [0, 1]:
+        for gpio_num in rtcio_nums:
+            if gpio_num not in gpio_nums:
+                continue
+
+            wakee.write('\r\n')
+            sleep(0.1)
+            wakee.expect('io_wakeup_test>', timeout=10)
+            wakee.write(f'ext1 -p {gpio_num} -m {wakeup_level}')
+            wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
+            wakee.expect(f'io_wakeup_level = {wakeup_level}', timeout=10)
+
+            waker.expect('io_wakeup_test>', timeout=10)
+            sleep_level = 1 - wakeup_level
+            waker.write(f'gpio_control -p {gpio_num} -l {sleep_level}')
+            waker.expect(f'io_num = {gpio_num}', timeout=10)
+            waker.expect(f'io_level = {sleep_level}', timeout=10)
+
+            wakee.write('sleep -m 1')
+
+            waker.write(f'gpio_control -p {gpio_num} -l {wakeup_level}')
+            waker.expect(f'io_num = {gpio_num}', timeout=10)
+            waker.expect(f'io_level = {wakeup_level}', timeout=10)
+
+            wakee.expect('io_wakeup_test>', timeout=10)
+
+            sleep(2)
+
+            wakee.write(f'ext1 -p {gpio_num} -d')
+            wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
+
+
+@pytest.mark.esp32c2
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.generic_multi_device
+@pytest.mark.parametrize('count', [2], indirect=True)
+@pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
+def test_rtcio_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None:
+    wakee = dut[0]
+    waker = dut[1]
+
+    chip_type = wakee.app.target
+    gpio_nums = available_gpio_nums.get(chip_type, [])
+    rtcio_nums = available_rtcio_nums.get(chip_type, [])
+
+    for wakeup_level in [0, 1]:
+        for gpio_num in rtcio_nums:
+            if gpio_num not in gpio_nums:
+                continue
+
+            wakee.write('\r\n')
+            sleep(0.1)
+            wakee.expect('io_wakeup_test>', timeout=10)
+            wakee.write(f'rtcio -p {gpio_num} -l {wakeup_level}')
+            wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
+            wakee.expect(f'io_wakeup_level = {wakeup_level}', timeout=10)
+
+            waker.expect('io_wakeup_test>', timeout=10)
+            sleep_level = 1 - wakeup_level
+            waker.write(f'gpio_control -p {gpio_num} -l {sleep_level}')
+            waker.expect(f'io_num = {gpio_num}', timeout=10)
+            waker.expect(f'io_level = {sleep_level}', timeout=10)
+
+            wakee.write('sleep -m 1')
+
+            waker.write(f'gpio_control -p {gpio_num} -l {wakeup_level}')
+            waker.expect(f'io_num = {gpio_num}', timeout=10)
+            waker.expect(f'io_level = {wakeup_level}', timeout=10)
+
+            wakee.expect('io_wakeup_test>', timeout=10)
+
+            sleep(2)
+
+            wakee.write(f'rtcio -p {gpio_num} -d')
+            wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
+
+
+@pytest.mark.esp32
+@pytest.mark.esp32c2
+@pytest.mark.esp32c3
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.generic_multi_device
+@pytest.mark.parametrize('count', [2], indirect=True)
+@pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
+def test_gpio_wakeup_enable_lightsleep(dut: Tuple[IdfDut, IdfDut]) -> None:
+    wakee = dut[0]
+    waker = dut[1]
+
+    chip_type = wakee.app.target
+    gpio_nums = available_gpio_nums.get(chip_type, [])
+
+    for wakeup_level in [1, 0]:
+        for gpio_num in gpio_nums:
+
+            wakee.write('\r\n')
+            wakee.expect('io_wakeup_test>', timeout=10)
+            wakee.write(f'gpio -p {gpio_num} -l {wakeup_level}')
+            wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
+            wakee.expect(f'io_wakeup_level = {wakeup_level}', timeout=10)
+
+            waker.expect('io_wakeup_test>', timeout=10)
+            sleep_level = 1 - wakeup_level
+            waker.write(f'gpio_control -p {gpio_num} -l {sleep_level}')
+            waker.expect(f'io_num = {gpio_num}', timeout=10)
+            waker.expect(f'io_level = {sleep_level}', timeout=10)
+
+            wakee.write('sleep -m 0')
+
+            waker.write(f'gpio_control -p {gpio_num} -l {wakeup_level}')
+            waker.expect(f'io_num = {gpio_num}', timeout=10)
+            waker.expect(f'io_level = {wakeup_level}', timeout=10)
+
+            wakee.expect('esp_light_sleep_start', timeout=10)
+
+            wakee.write(f'gpio -p {gpio_num} -d')
+            wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/sdkconfig.ci.default b/components/esp_hw_support/test_apps/wakeup_tests/sdkconfig.ci.default
new file mode 100644
index 00000000000..7a9bc9908a7
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/sdkconfig.ci.default
@@ -0,0 +1,3 @@
+# Default configuration
+CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=n
+CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=n
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/sdkconfig.defaults b/components/esp_hw_support/test_apps/wakeup_tests/sdkconfig.defaults
new file mode 100644
index 00000000000..fb76bc2e1b0
--- /dev/null
+++ b/components/esp_hw_support/test_apps/wakeup_tests/sdkconfig.defaults
@@ -0,0 +1,2 @@
+CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=n
+CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=n
diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c
index 09e42125adc..9a7cb5ead0c 100644
--- a/components/esp_pm/pm_impl.c
+++ b/components/esp_pm/pm_impl.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/esp_rom/include/esp32p4/rom/spi_flash.h b/components/esp_rom/include/esp32p4/rom/spi_flash.h
index 2c22307971a..761fc46bc7f 100644
--- a/components/esp_rom/include/esp32p4/rom/spi_flash.h
+++ b/components/esp_rom/include/esp32p4/rom/spi_flash.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,23 +15,34 @@
 extern "C" {
 #endif
 
-#define PERIPHS_SPI_FLASH_CMD                 SPI_MEM_CMD_REG(1)
-#define PERIPHS_SPI_FLASH_ADDR                SPI_MEM_ADDR_REG(1)
-#define PERIPHS_SPI_FLASH_CTRL                SPI_MEM_CTRL_REG(1)
-#define PERIPHS_SPI_FLASH_CTRL1               SPI_MEM_CTRL1_REG(1)
-#define PERIPHS_SPI_FLASH_STATUS              SPI_MEM_RD_STATUS_REG(1)
-#define PERIPHS_SPI_FLASH_USRREG              SPI_MEM_USER_REG(1)
-#define PERIPHS_SPI_FLASH_USRREG1             SPI_MEM_USER1_REG(1)
-#define PERIPHS_SPI_FLASH_USRREG2             SPI_MEM_USER2_REG(1)
-#define PERIPHS_SPI_FLASH_C0                  SPI_MEM_W0_REG(1)
-#define PERIPHS_SPI_FLASH_C1                  SPI_MEM_W1_REG(1)
-#define PERIPHS_SPI_FLASH_C2                  SPI_MEM_W2_REG(1)
-#define PERIPHS_SPI_FLASH_C3                  SPI_MEM_W3_REG(1)
-#define PERIPHS_SPI_FLASH_C4                  SPI_MEM_W4_REG(1)
-#define PERIPHS_SPI_FLASH_C5                  SPI_MEM_W5_REG(1)
-#define PERIPHS_SPI_FLASH_C6                  SPI_MEM_W6_REG(1)
-#define PERIPHS_SPI_FLASH_C7                  SPI_MEM_W7_REG(1)
-#define PERIPHS_SPI_FLASH_TX_CRC              SPI_MEM_TX_CRC_REG(1)
+#define PERIPHS_SPI_FLASH_CMD                 SPI1_MEM_C_CMD_REG
+#define PERIPHS_SPI_FLASH_ADDR                SPI1_MEM_C_ADDR_REG
+#define PERIPHS_SPI_FLASH_CTRL                SPI1_MEM_C_CTRL_REG
+#define PERIPHS_SPI_FLASH_CTRL1               SPI1_MEM_C_CTRL1_REG
+#define PERIPHS_SPI_FLASH_STATUS              SPI1_MEM_C_RD_STATUS_REG
+#define PERIPHS_SPI_FLASH_USRREG              SPI1_MEM_C_USER_REG
+#define PERIPHS_SPI_FLASH_USRREG1             SPI1_MEM_C_USER1_REG
+#define PERIPHS_SPI_FLASH_USRREG2             SPI1_MEM_C_USER2_REG
+#define PERIPHS_SPI_FLASH_C0                  SPI1_MEM_C_W0_REG
+#define PERIPHS_SPI_FLASH_C1                  SPI1_MEM_C_W1_REG
+#define PERIPHS_SPI_FLASH_C2                  SPI1_MEM_C_W2_REG
+#define PERIPHS_SPI_FLASH_C3                  SPI1_MEM_C_W3_REG
+#define PERIPHS_SPI_FLASH_C4                  SPI1_MEM_C_W4_REG
+#define PERIPHS_SPI_FLASH_C5                  SPI1_MEM_C_W5_REG
+#define PERIPHS_SPI_FLASH_C6                  SPI1_MEM_C_W6_REG
+#define PERIPHS_SPI_FLASH_C7                  SPI1_MEM_C_W7_REG
+#define PERIPHS_SPI_FLASH_TX_CRC              SPI1_MEM_C_TX_CRC_REG
+
+#define SPI_MEM_FREAD_QIO  SPI1_MEM_C_FREAD_QIO
+#define SPI_MEM_FREAD_DIO  SPI1_MEM_C_FREAD_DIO
+#define SPI_MEM_FREAD_QUAD  SPI1_MEM_C_FREAD_QUAD
+#define SPI_MEM_FREAD_DUAL  SPI1_MEM_C_FREAD_DUAL
+#define SPI_MEM_FWRITE_QIO  SPI1_MEM_C_FWRITE_QIO
+#define SPI_MEM_FWRITE_DIO  SPI1_MEM_C_FWRITE_DIO
+#define SPI_MEM_FWRITE_QUAD  SPI1_MEM_C_FWRITE_QUAD
+#define SPI_MEM_FWRITE_DUAL  SPI1_MEM_C_FWRITE_DUAL
+#define SPI_MEM_FASTRD_MODE  SPI1_MEM_C_FASTRD_MODE
+
 
 #define SPI0_R_QIO_DUMMY_CYCLELEN             5
 #define SPI0_R_QIO_ADDR_BITSLEN               23
diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
index 0f944aaac44..8add9899b38 100644
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@@ -564,6 +564,15 @@ menu "ESP System Settings"
             This config allows to trigger a panic interrupt when Stack Pointer register goes out of allocated stack
             memory bounds.
 
+    config ESP_SYSTEM_BBPLL_RECALIB
+        bool "Re-calibration BBPLL at startup"
+        depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
+        default y
+        help
+            This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
+            which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
+            ESP-IDF version v5.2 and above.
+
 endmenu  # ESP System Settings
 
 menu "IPC (Inter-Processor Call)"
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index f4167b124c4..a2f546f3eca 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -544,7 +544,14 @@ void IRAM_ATTR call_start_cpu0(void)
      * In this stage, we re-configure the Flash (and MSPI) to required configuration
      */
     spi_flash_init_chip_state();
+
+    // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
+    // Do calibration again here so that we can use better clock for the timing tuning.
+#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
+    rtc_clk_recalib_bbpll();
+#endif
 #if SOC_MEMSPI_SRC_FREQ_120M
+    // This function needs to be called when PLL is enabled
     mspi_timing_flash_tuning();
 #endif
 
diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt
index 921bb5cbd40..a8cfa09986a 100644
--- a/components/esp_system/system_init_fn.txt
+++ b/components/esp_system/system_init_fn.txt
@@ -45,6 +45,8 @@ CORE: 105: init_newlib_time in components/esp_system/startup_funcs.c on BIT(0)
 # Peripheral-specific implementation operators should be filled first
 # Then register vfs console, and follow by newlib stdio initialization
 CORE: 110: init_vfs_uart in components/esp_driver_uart/src/uart_vfs.c on BIT(0)
+CORE: 111: init_vfs_usj in components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c on BIT(0)
+CORE: 112: init_vfs_usj_sec in components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c on BIT(0)
 CORE: 114: init_vfs_console in components/vfs/vfs_console.c on BIT(0)
 CORE: 115: init_newlib_stdio in components/newlib/newlib_init.c on BIT(0)
 
@@ -88,7 +90,7 @@ SECONDARY: 220: esp_usb_console_init_restart_timer in components/esp_system/port
 
 # usb_serial_jtag needs to create and acquire a PM lock at startup.
 # This makes more sense to be done after esp_pm_impl_init (called from init_pm).
-SECONDARY: 230: usb_serial_jtag_conn_status_init in components/driver/usb_serial_jtag/usb_serial_jtag_connection_monitor.c on BIT(0)
+SECONDARY: 230: usb_serial_jtag_conn_status_init in components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_connection_monitor.c on BIT(0)
 
 # Has to be the last step!
 # Now that the application is about to start, disable boot watchdog
diff --git a/components/esp_system/test_apps/.build-test-rules.yml b/components/esp_system/test_apps/.build-test-rules.yml
index 8f79155fb33..1eebf6ca171 100644
--- a/components/esp_system/test_apps/.build-test-rules.yml
+++ b/components/esp_system/test_apps/.build-test-rules.yml
@@ -3,10 +3,6 @@
 components/esp_system/test_apps/esp_system_unity_tests:
   disable:
     - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: test not pass, should be re-enable # TODO: IDF-8978
 
 components/esp_system/test_apps/linux_apis:
   enable:
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
index 860b9f87067..396c8dde03e 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
+++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -14,6 +14,9 @@
 #if CONFIG_IDF_TARGET_ARCH_RISCV
 #include "riscv/rv_utils.h"
 #endif
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+#include "hal/cache_ll.h"
+#endif
 
 #define RTC_BSS_ATTR __attribute__((section(".rtc.bss")))
 
@@ -131,6 +134,12 @@ static void setup_values(void)
     s_rtc_force_fast_val = CHECK_VALUE;
     s_rtc_force_slow_val = CHECK_VALUE;
 #endif //CHECK_RTC_MEM
+
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+    /* If internal data is behind a cache it might not be written to the physical memory when we crash
+       force a full writeback here to ensure this */
+    cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
+#endif
 }
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7529
@@ -166,7 +175,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][rese
 static void do_exception(void)
 {
     setup_values();
-    *(int*) (0x40000001) = 0;
+    *(int*) (0x0) = 0;
 }
 
 static void do_abort(void)
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
index d830f3f27c4..5430cee590e 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
+++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -41,7 +41,6 @@
 
 #define ESP_EXT0_WAKEUP_LEVEL_LOW 0
 #define ESP_EXT0_WAKEUP_LEVEL_HIGH 1
-
 __attribute__((unused)) static struct timeval tv_start, tv_stop;
 
 
@@ -391,72 +390,6 @@ TEST_CASE_MULTIPLE_STAGES("can set sleep wake stub from stack in RTC RAM", "[dee
 
 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
-#if SOC_PM_SUPPORT_EXT0_WAKEUP
-TEST_CASE("wake up using ext0 (13 high)", "[deepsleep][ignore]")
-{
-    ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pullup_dis(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pulldown_en(GPIO_NUM_13));
-    ESP_ERROR_CHECK(esp_sleep_enable_ext0_wakeup(GPIO_NUM_13, ESP_EXT0_WAKEUP_LEVEL_HIGH));
-    esp_deep_sleep_start();
-}
-
-TEST_CASE("wake up using ext0 (13 low)", "[deepsleep][ignore]")
-{
-    ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pullup_en(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13));
-    ESP_ERROR_CHECK(esp_sleep_enable_ext0_wakeup(GPIO_NUM_13, ESP_EXT0_WAKEUP_LEVEL_LOW));
-    esp_deep_sleep_start();
-}
-#endif // SOC_PM_SUPPORT_EXT0_WAKEUP
-
-#if SOC_PM_SUPPORT_EXT1_WAKEUP
-TEST_CASE("wake up using ext1 when RTC_PERIPH is off (13 high)", "[deepsleep][ignore]")
-{
-    // This test needs external pulldown
-    ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
-    ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_HIGH));
-    esp_deep_sleep_start();
-}
-
-TEST_CASE("wake up using ext1 when RTC_PERIPH is off (13 low)", "[deepsleep][ignore]")
-{
-    // This test needs external pullup
-    ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
-#if CONFIG_IDF_TARGET_ESP32
-    ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW));
-#else
-    ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW));
-#endif
-    esp_deep_sleep_start();
-}
-
-TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 high)", "[deepsleep][ignore]")
-{
-    ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pullup_dis(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pulldown_en(GPIO_NUM_13));
-    ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON));
-    ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_HIGH));
-    esp_deep_sleep_start();
-}
-
-TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 low)", "[deepsleep][ignore]")
-{
-    ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pullup_en(GPIO_NUM_13));
-    ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13));
-    ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON));
-#if CONFIG_IDF_TARGET_ESP32
-    ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ALL_LOW));
-#else
-    ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(BIT(GPIO_NUM_13), ESP_EXT1_WAKEUP_ANY_LOW));
-#endif
-    esp_deep_sleep_start();
-}
-#endif // SOC_PM_SUPPORT_EXT1_WAKEUP
-
 __attribute__((unused)) static float get_time_ms(void)
 {
     gettimeofday(&tv_stop, NULL);
@@ -647,29 +580,4 @@ static void check_time_deepsleep(void)
 
 TEST_CASE_MULTIPLE_STAGES("check a time after wakeup from deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep);
 
-#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
-static void gpio_deepsleep_wakeup_config(void)
-{
-    gpio_config_t io_conf = {
-        .mode = GPIO_MODE_INPUT,
-        .pin_bit_mask = ((1ULL << 2) | (1ULL << 4))
-    };
-    ESP_ERROR_CHECK(gpio_config(&io_conf));
-}
-
-TEST_CASE("wake up using GPIO (2 or 4 high)", "[deepsleep][ignore]")
-{
-    gpio_deepsleep_wakeup_config();
-    ESP_ERROR_CHECK(esp_deep_sleep_enable_gpio_wakeup(((1ULL << 2) | (1ULL << 4)) , ESP_GPIO_WAKEUP_GPIO_HIGH));
-    esp_deep_sleep_start();
-}
-
-TEST_CASE("wake up using GPIO (2 or 4 low)", "[deepsleep][ignore]")
-{
-    gpio_deepsleep_wakeup_config();
-    ESP_ERROR_CHECK(esp_deep_sleep_enable_gpio_wakeup(((1ULL << 2) | (1ULL << 4)) , ESP_GPIO_WAKEUP_GPIO_LOW));
-    esp_deep_sleep_start();
-}
-#endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
-
 #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4)
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py
index a0d329287fd..a646795589f 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py
+++ b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py
@@ -5,14 +5,13 @@
 from pytest_embedded import Dut
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD')  # TODO: IDF-8978
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
     [
         pytest.param('default', marks=[pytest.mark.supported_targets]),
         pytest.param('pd_vddsdio', marks=[pytest.mark.supported_targets]),
-        pytest.param('psram', marks=[pytest.mark.esp32, pytest.mark.esp32s2, pytest.mark.esp32s3]),
+        pytest.param('psram', marks=[pytest.mark.esp32, pytest.mark.esp32s2, pytest.mark.esp32s3, pytest.mark.esp32p4]),
         pytest.param('single_core_esp32', marks=[pytest.mark.esp32]),
     ]
 )
@@ -20,7 +19,6 @@ def test_esp_system(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD')  # TODO: IDF-8978
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
index f0f992e6222..6f6e34ba09e 160000
--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit f0f992e62223596f226d3e43d871821247d4df55
+Subproject commit 6f6e34ba09ee39817276e4886bc868705f8062d8
diff --git a/components/fatfs/diskio/diskio_sdmmc.c b/components/fatfs/diskio/diskio_sdmmc.c
index 751729d9010..3e61eb00dd0 100644
--- a/components/fatfs/diskio/diskio_sdmmc.c
+++ b/components/fatfs/diskio/diskio_sdmmc.c
@@ -105,6 +105,9 @@ DRESULT ff_sdmmc_ioctl (BYTE pdrv, BYTE cmd, void* buff)
             return RES_ERROR;
 #if FF_USE_TRIM
         case CTRL_TRIM:
+            if (sdmmc_can_trim(card) != ESP_OK) {
+                return RES_PARERR;
+            }
             return ff_sdmmc_trim (pdrv, *((DWORD*)buff), //start_sector
                     (*((DWORD*)buff + 1) - *((DWORD*)buff) + 1)); //sector_count
 #endif //FF_USE_TRIM
diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h
index b4405606d28..ebb5f396cde 100644
--- a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h
+++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h
@@ -6,7 +6,7 @@
  *
  * SPDX-License-Identifier: MIT
  *
- * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -466,7 +466,7 @@ void vPortTCBPreDeleteHook( void *pxTCB );
 // --------------------- Interrupts ------------------------
 
 #define portDISABLE_INTERRUPTS()            portSET_INTERRUPT_MASK_FROM_ISR()
-#define portENABLE_INTERRUPTS()             portCLEAR_INTERRUPT_MASK_FROM_ISR(1)
+#define portENABLE_INTERRUPTS()             portCLEAR_INTERRUPT_MASK_FROM_ISR(RVHAL_INTR_ENABLE_THRESH)
 
 /**
  * ISR versions to enable/disable interrupts
diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
index 5e30219b19f..cb6ace1700a 100644
--- a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
+++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
@@ -6,7 +6,7 @@
  *
  * SPDX-License-Identifier: MIT
  *
- * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -144,11 +144,7 @@ BaseType_t xPortStartScheduler(void)
     /* Setup the hardware to generate the tick. */
     vPortSetupTimer();
 
-#if !SOC_INT_CLIC_SUPPORTED
-    esprv_intc_int_set_threshold(1); /* set global INTC masking level */
-#else
-    esprv_intc_int_set_threshold(0); /* set global CLIC masking level. When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */
-#endif /* !SOC_INT_CLIC_SUPPORTED */
+    esprv_intc_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
     rv_utils_intr_global_enable();
 
     vPortYield();
diff --git a/components/freertos/FreeRTOS-Kernel/tasks.c b/components/freertos/FreeRTOS-Kernel/tasks.c
index f8cb7a4819b..941b0635470 100644
--- a/components/freertos/FreeRTOS-Kernel/tasks.c
+++ b/components/freertos/FreeRTOS-Kernel/tasks.c
@@ -6,7 +6,7 @@
  *
  * SPDX-License-Identifier: MIT
  *
- * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -3284,15 +3284,52 @@ BaseType_t xTaskIncrementTick( void )
                              * For SMP, since this function is only run on core
                              * 0, we only need to context switch if the unblocked
                              * task can run on core 0 and has a higher priority
-                             * than the current task. */
-                            if( ( taskIS_AFFINITY_COMPATIBLE( 0, pxTCB ) == pdTRUE ) && ( pxTCB->uxPriority > pxCurrentTCBs[ 0 ]->uxPriority ) )
-                            {
-                                xSwitchRequired = pdTRUE;
-                            }
-                            else
+                             * than the current task.
+                             *
+                             * If the unblocked task has affinity to the other
+                             * core or no affinity then we need to set xYieldPending
+                             * for the other core if the unblocked task has a priority
+                             * higher than the priority of the currently running task
+                             * on the other core. */
+                            if( taskIS_AFFINITY_COMPATIBLE( 0, pxTCB ) == pdTRUE )
                             {
-                                mtCOVERAGE_TEST_MARKER();
+                                if( pxTCB->uxPriority > pxCurrentTCBs[ 0 ]->uxPriority )
+                                {
+                                    xSwitchRequired = pdTRUE;
+                                }
+
+                                #if ( configNUMBER_OF_CORES > 1 )
+                                    else if( pxTCB->xCoreID == tskNO_AFFINITY )
+                                    {
+                                        if( pxTCB->uxPriority > pxCurrentTCBs[ 1 ]->uxPriority )
+                                        {
+                                            xYieldPending[ 1 ] = pdTRUE;
+                                        }
+                                        else
+                                        {
+                                            mtCOVERAGE_TEST_MARKER();
+                                        }
+                                    }
+                                #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
                             }
+
+                            #if ( configNUMBER_OF_CORES > 1 )
+                                else
+                                {
+                                    if( pxTCB->uxPriority > pxCurrentTCBs[ 1 ]->uxPriority )
+                                    {
+                                        xYieldPending[ 1 ] = pdTRUE;
+                                    }
+                                    else
+                                    {
+                                        mtCOVERAGE_TEST_MARKER();
+                                    }
+                                }
+                            #endif /* if ( configNUMBER_OF_CORES > 1 ) */
                         }
                         #endif /* configUSE_PREEMPTION */
                     }
@@ -5440,7 +5477,7 @@ static void prvResetNextTaskUnblockTime( void )
                 /* Write the rest of the string. */
                 #if ( configTASKLIST_INCLUDE_COREID == 1 )
                 {
-                    const BaseType_t xCoreID = ( pxTaskStatusArray[ x ].xCoreID == tskNO_AFFINITY ) ? -1 : pxTaskStatusArray[ x ].xCoreID ;
+                    const BaseType_t xCoreID = ( pxTaskStatusArray[ x ].xCoreID == tskNO_AFFINITY ) ? -1 : pxTaskStatusArray[ x ].xCoreID;
                     sprintf( pcWriteBuffer, "\t%c\t%u\t%d\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( int ) xCoreID, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
                 }
                 #else /* configTASKLIST_INCLUDE_COREID == 1 */
diff --git a/components/freertos/esp_additions/freertos_tasks_c_additions.h b/components/freertos/esp_additions/freertos_tasks_c_additions.h
index ce15b52f0cd..9fe76f0169b 100644
--- a/components/freertos/esp_additions/freertos_tasks_c_additions.h
+++ b/components/freertos/esp_additions/freertos_tasks_c_additions.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -87,9 +87,8 @@ _Static_assert( tskNO_AFFINITY == ( BaseType_t ) CONFIG_FREERTOS_NO_AFFINITY, "C
         /* This function should never be called by Core 0. */
         configASSERT( xCoreID != 0 );
 
-        /* Called by the portable layer each time a tick interrupt occurs.
-         * Increments the tick then checks to see if the new tick value will
-         * cause any tasks to be unblocked. */
+        /* Called by the portable layer each time a tick interrupt occurs
+         * on a core other than core 0. */
         traceTASK_INCREMENT_TICK( xTickCount );
 
         if( uxSchedulerSuspended[ xCoreID ] == ( UBaseType_t ) 0U )
@@ -98,23 +97,6 @@ _Static_assert( tskNO_AFFINITY == ( BaseType_t ) CONFIG_FREERTOS_NO_AFFINITY, "C
              * kernel data structures. */
             taskENTER_CRITICAL_ISR( &xKernelLock );
 
-            /* A task being unblocked cannot cause an immediate context switch
-             * if preemption is turned off. */
-            #if ( configUSE_PREEMPTION == 1 )
-            {
-                /* Check if core 0 calling xTaskIncrementTick() has
-                 * unblocked a task that can be run. */
-                if( uxTopReadyPriority > pxCurrentTCBs[ xCoreID ]->uxPriority )
-                {
-                    xSwitchRequired = pdTRUE;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            #endif /* if ( configUSE_PREEMPTION == 1 ) */
-
             /* Tasks of equal priority to the currently running task will share
              * processing time (time slice) if preemption is on, and the application
              * writer has not explicitly turned time slicing off. */
@@ -891,7 +873,8 @@ uint8_t * pxTaskGetStackStart( TaskHandle_t xTask )
  *
  * @note There are currently differing number of task list between SMP FreeRTOS and ESP-IDF FreeRTOS
  */
-static List_t * non_ready_task_lists[] = {
+static List_t * non_ready_task_lists[] =
+{
     #ifdef CONFIG_FREERTOS_SMP
         &xPendingReadyList,
     #else /* CONFIG_FREERTOS_SMP */
@@ -1104,7 +1087,8 @@ UBaseType_t uxTaskGetSnapshotAll( TaskSnapshot_t * const pxTaskSnapshotArray,
         pxCurTaskList = pxGetNextTaskList( pxCurTaskList );
     }
 
-    if (pxTCBSize != NULL) {
+    if( pxTCBSize != NULL )
+    {
         *pxTCBSize = sizeof( TCB_t );
     }
 
@@ -1151,7 +1135,8 @@ void * pvTaskGetCurrentTCBForCore( BaseType_t xCoreID )
         ESP_FREERTOS_DEBUG_TABLE_END,
     };
 
-    const DRAM_ATTR uint8_t FreeRTOS_openocd_params[ ESP_FREERTOS_DEBUG_TABLE_END ] = {
+    const DRAM_ATTR uint8_t FreeRTOS_openocd_params[ ESP_FREERTOS_DEBUG_TABLE_END ] =
+    {
         ESP_FREERTOS_DEBUG_TABLE_END, /* table size */
         1,                            /* table version */
         tskKERNEL_VERSION_MAJOR,
diff --git a/components/hal/esp32/include/hal/spi_flash_ll.h b/components/hal/esp32/include/hal/spi_flash_ll.h
index c8190818953..3a6cf9522d8 100644
--- a/components/hal/esp32/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32/include/hal/spi_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -447,6 +447,26 @@ static inline void spi_flash_ll_set_extra_address(spi_dev_t *dev, uint32_t extra
     // Not supported on ESP32.
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spi_flash_ll_set_wp_level(spi_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spi_flash_ll_get_ctrl_val(spi_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c2/include/hal/spi_flash_ll.h b/components/hal/esp32c2/include/hal/spi_flash_ll.h
index 0a617a30aa3..611c16f5dcd 100644
--- a/components/hal/esp32c2/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32c2/include/hal/spi_flash_ll.h
@@ -91,6 +91,7 @@ typedef union  {
 #define spi_flash_ll_set_dummy_out(dev, en, lev)             spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
 
 #endif
 
diff --git a/components/hal/esp32c2/include/hal/spimem_flash_ll.h b/components/hal/esp32c2/include/hal/spimem_flash_ll.h
index 23bddd1ba2f..de92fc45cc6 100644
--- a/components/hal/esp32c2/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32c2/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -647,6 +647,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c3/include/hal/spi_flash_ll.h b/components/hal/esp32c3/include/hal/spi_flash_ll.h
index 0a617a30aa3..611c16f5dcd 100644
--- a/components/hal/esp32c3/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32c3/include/hal/spi_flash_ll.h
@@ -91,6 +91,7 @@ typedef union  {
 #define spi_flash_ll_set_dummy_out(dev, en, lev)             spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
 
 #endif
 
diff --git a/components/hal/esp32c3/include/hal/spimem_flash_ll.h b/components/hal/esp32c3/include/hal/spimem_flash_ll.h
index 73df69e3e18..873142de39d 100644
--- a/components/hal/esp32c3/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32c3/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -662,6 +662,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c5/include/hal/spi_flash_ll.h b/components/hal/esp32c5/include/hal/spi_flash_ll.h
index b8dde2bf34c..b6d332d5d5e 100644
--- a/components/hal/esp32c5/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32c5/include/hal/spi_flash_ll.h
@@ -94,6 +94,7 @@ typedef union  {
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
 #define spi_flash_ll_set_extra_address(dev, extra_addr)      spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
 
 #endif
 
diff --git a/components/hal/esp32c5/include/hal/spimem_flash_ll.h b/components/hal/esp32c5/include/hal/spimem_flash_ll.h
index f1195261a7d..63d02eca744 100644
--- a/components/hal/esp32c5/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32c5/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -651,6 +651,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c6/include/hal/spi_flash_ll.h b/components/hal/esp32c6/include/hal/spi_flash_ll.h
index 77f495447b7..cb328bffaf0 100644
--- a/components/hal/esp32c6/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32c6/include/hal/spi_flash_ll.h
@@ -92,6 +92,7 @@ typedef union  {
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
 #define spi_flash_ll_set_extra_address(dev, extra_addr)      spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
 
 #endif
 
diff --git a/components/hal/esp32c6/include/hal/spimem_flash_ll.h b/components/hal/esp32c6/include/hal/spimem_flash_ll.h
index b80187f2e01..dae851b685b 100644
--- a/components/hal/esp32c6/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32c6/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -681,6 +681,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32h2/include/hal/spi_flash_ll.h b/components/hal/esp32h2/include/hal/spi_flash_ll.h
index 2dcdf16187e..2af2105a63a 100644
--- a/components/hal/esp32h2/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32h2/include/hal/spi_flash_ll.h
@@ -92,6 +92,7 @@ typedef union  {
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
 #define spi_flash_ll_set_extra_address(dev, extra_addr)      spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
 
 #endif
 
diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h
index 76fca20e788..95cee518a80 100644
--- a/components/hal/esp32h2/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -683,6 +683,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32h2/pau_hal.c b/components/hal/esp32h2/pau_hal.c
index 59f13e633e2..6eeaaef002c 100644
--- a/components/hal/esp32h2/pau_hal.c
+++ b/components/hal/esp32h2/pau_hal.c
@@ -15,11 +15,7 @@
 
 void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
 {
-    /* ESP32H2 does not have PMU HP_AON power domain. because the registers
-     * of PAU REGDMA is included to PMU TOP power domain, cause the contents
-     * of PAU REGDMA registers will be lost when the TOP domain is powered down
-     * during light sleep, so we does not need to enable REGDMA backup here.
-     * We will use the software to trigger REGDMA to backup or restore. */
+    pau_ll_set_regdma_link0_addr(hal->dev, (*link_addr)[0]);
 }
 
 void IRAM_ATTR pau_hal_start_regdma_system_link(pau_hal_context_t *hal, bool backup_or_restore)
diff --git a/components/hal/esp32p4/include/hal/ldo_ll.h b/components/hal/esp32p4/include/hal/ldo_ll.h
index e3d2ce4bd0c..5e58532039b 100644
--- a/components/hal/esp32p4/include/hal/ldo_ll.h
+++ b/components/hal/esp32p4/include/hal/ldo_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -54,6 +54,17 @@ extern "C" {
  */
 #define LDO_ID2UNIT(ldo_id)    ((ldo_id) - 1)
 
+/**
+ * @brief Check if a LDO ID is valid
+ *
+ * @return True for valid
+ */
+__attribute__((always_inline))
+static inline bool ldo_ll_is_valid_ldo_id(int ldo_id)
+{
+    return ((ldo_id > 0) && (ldo_id <= LDO_LL_UNIT_NUM));
+}
+
 /**
  * @brief Enable a LDO
  *
diff --git a/components/hal/esp32p4/include/hal/sdmmc_ll.h b/components/hal/esp32p4/include/hal/sdmmc_ll.h
index 4397c10fbeb..07125faf5a7 100644
--- a/components/hal/esp32p4/include/hal/sdmmc_ll.h
+++ b/components/hal/esp32p4/include/hal/sdmmc_ll.h
@@ -31,7 +31,6 @@ extern "C" {
 /**
  * SDMMC capabilities
  */
-#define SDMMC_LL_MAX_FREQ_KHZ_FPGA                    (4*1000)
 #define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID)    ((SLOT_ID == 0) ? 0 : 1)
 
 #define SDMMC_LL_IOMUX_FUNC    0
diff --git a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
index fbdb8990988..9c3304832bf 100644
--- a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
+++ b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,7 @@
 #include <stdbool.h>
 #include <string.h>
 #include "soc/hp_system_reg.h"
-#include "soc/spi_mem_reg.h"
+#include "soc/spi_mem_c_reg.h"
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
@@ -61,7 +61,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
 {
     // Our hardware only support flash encryption
     HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
-    REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_SPI_XTS_DESTINATION, type);
+    REG_SET_FIELD(SPI_MEM_C_XTS_DESTINATION_REG, SPI_MEM_C_XTS_DESTINATION, type);
 }
 
 /**
@@ -72,7 +72,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
 static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
 {
     // Desired block should not be larger than the block size.
-    REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_SPI_XTS_LINESIZE, size >> 5);
+    REG_SET_FIELD(SPI_MEM_C_XTS_LINESIZE_REG, SPI_MEM_C_XTS_LINESIZE, size >> 5);
 }
 
 /**
@@ -87,7 +87,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
 {
     uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
     HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
-    memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
+    memcpy((void *)(SPI_MEM_C_XTS_PLAIN_BASE_REG + plaintext_offs), buffer, size);
 }
 
 /**
@@ -97,7 +97,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
  */
 static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
 {
-    REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS, flash_addr);
+    REG_SET_FIELD(SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG, SPI_MEM_C_XTS_PHYSICAL_ADDRESS, flash_addr);
 }
 
 /**
@@ -105,7 +105,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
  */
 static inline void spi_flash_encrypt_ll_calculate_start(void)
 {
-    REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_SPI_XTS_TRIGGER, 1);
+    REG_SET_FIELD(SPI_MEM_C_XTS_TRIGGER_REG, SPI_XTS_TRIGGER, 1);
 }
 
 /**
@@ -113,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
  */
 static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
 {
-    while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) == 0x1) {
+    while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) == 0x1) {
     }
 }
 
@@ -122,8 +122,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
  */
 static inline void spi_flash_encrypt_ll_done(void)
 {
-    REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_SPI_XTS_RELEASE);
-    while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) != 0x3) {
+    REG_SET_BIT(SPI_MEM_C_XTS_RELEASE_REG, SPI_MEM_C_XTS_RELEASE);
+    while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) != 0x3) {
     }
 }
 
@@ -132,7 +132,7 @@ static inline void spi_flash_encrypt_ll_done(void)
  */
 static inline void spi_flash_encrypt_ll_destroy(void)
 {
-    REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_SPI_XTS_DESTROY);
+    REG_SET_BIT(SPI_MEM_C_XTS_DESTROY_REG, SPI_MEM_C_XTS_DESTROY);
 }
 
 /**
diff --git a/components/hal/esp32p4/include/hal/spi_flash_ll.h b/components/hal/esp32p4/include/hal/spi_flash_ll.h
index 7c50962cb32..444099fead6 100644
--- a/components/hal/esp32p4/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32p4/include/hal/spi_flash_ll.h
@@ -92,6 +92,7 @@ typedef union  {
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
 #define spi_flash_ll_set_extra_address(dev, extra_addr)      spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
 
 #endif
 
diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h
index f428edde56c..74bd4567264 100644
--- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,7 +20,8 @@
 #include <string.h>
 
 #include "soc/spi_periph.h"
-#include "soc/spi_mem_struct.h"
+#include "soc/spi1_mem_c_struct.h"
+#include "soc/spi1_mem_c_reg.h"
 #include "hal/assert.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
@@ -208,7 +209,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
  */
 static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
 {
-    dev->flash_sus_ctrl.frd_sus_2b = 0;
+    dev->flash_sus_ctrl.fmem_rd_sus_2b = 0;
     HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
 }
 
@@ -454,8 +455,8 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
 {
     typeof (dev->ctrl) ctrl;
     ctrl.val = dev->ctrl.val;
-    ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
-    ctrl.val |= SPI_MEM_FASTRD_MODE_M;
+    ctrl.val &= ~(SPI1_MEM_C_FREAD_QIO_M | SPI1_MEM_C_FREAD_QUAD_M | SPI1_MEM_C_FREAD_DIO_M | SPI1_MEM_C_FREAD_DUAL_M);
+    ctrl.val |= SPI1_MEM_C_FASTRD_MODE_M;
     switch (read_mode) {
     case SPI_FLASH_FASTRD:
         //the default option
@@ -565,7 +566,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
  */
 static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
 {
-    dev->cache_fctrl.usr_addr_4byte = 0;
+    dev->cache_fctrl.cache_usr_addr_4byte = 0;
     dev->rd_status.wb_mode = extra_addr;
 }
 
@@ -612,10 +613,7 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
  */
 static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
 {
-    if (hold_n > 0) {
-        dev->ctrl2.cs_hold_time = hold_n - 1;
-    }
-    dev->user.cs_hold = hold_n > 0;
+    // Not supported on esp32p4
 }
 
 /**
@@ -626,10 +624,7 @@ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
  */
 static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
 {
-    if (cs_setup_time > 0) {
-        dev->ctrl2.cs_setup_time = cs_setup_time - 1;
-    }
-    dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    // Not supported on esp32p4
 }
 
 /**
@@ -664,6 +659,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp_reg = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32s2/include/hal/spi_flash_ll.h b/components/hal/esp32s2/include/hal/spi_flash_ll.h
index ed4fdf64afc..99cdd090dfd 100644
--- a/components/hal/esp32s2/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32s2/include/hal/spi_flash_ll.h
@@ -94,6 +94,7 @@ typedef union  {
 #define spi_flash_ll_set_dummy_out(dev, en, lev)             spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
 
 #endif
 
diff --git a/components/hal/esp32s2/include/hal/spimem_flash_ll.h b/components/hal/esp32s2/include/hal/spimem_flash_ll.h
index ea0ca5da4c3..3b5611146ac 100644
--- a/components/hal/esp32s2/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32s2/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -596,6 +596,25 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
 
 #ifdef __cplusplus
 }
diff --git a/components/hal/esp32s3/include/hal/spi_flash_ll.h b/components/hal/esp32s3/include/hal/spi_flash_ll.h
index a77f031b617..5ca1349ad1c 100644
--- a/components/hal/esp32s3/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32s3/include/hal/spi_flash_ll.h
@@ -91,6 +91,8 @@ typedef union  {
 #define spi_flash_ll_set_dummy_out(dev, en, lev)             spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_get_ctrl_val(dev)                       spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
+
 #endif
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32s3/include/hal/spimem_flash_ll.h b/components/hal/esp32s3/include/hal/spimem_flash_ll.h
index eee9d0851db..9b07256b4de 100644
--- a/components/hal/esp32s3/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32s3/include/hal/spimem_flash_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -683,6 +683,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
     return div_parameter;
 }
 
+/**
+ * @brief Write protect signal output when SPI is idle
+
+ * @param level 1: 1: output high, 0: output low
+ */
+static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
+{
+    dev->ctrl.wp = level;
+}
+
+/**
+ * @brief Get the ctrl value of mspi
+ *
+ * @return uint32_t The value of ctrl register
+ */
+static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
+{
+    return dev->ctrl.val;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/include/hal/ldo_types.h b/components/hal/include/hal/ldo_types.h
new file mode 100644
index 00000000000..600e2c43664
--- /dev/null
+++ b/components/hal/include/hal/ldo_types.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LDO Unit
+ *
+ * @note See datasheet to know LDO, alias includes but not least to `VFB/VOn`
+ */
+typedef enum {
+    LDO_UNIT_1 = 1,    ///< LDO 1
+    LDO_UNIT_2,        ///< LDO 2
+    LDO_UNIT_3,        ///< LDO 3
+    LDO_UNIT_4,        ///< LDO 4
+} ldo_unit_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/lwip/Kconfig b/components/lwip/Kconfig
index 5268f2482c9..3132fae6b60 100644
--- a/components/lwip/Kconfig
+++ b/components/lwip/Kconfig
@@ -465,7 +465,7 @@ menu "LWIP"
         default y
         help
             Enable IPv6 function. If not use IPv6 function, set this option to n.
-            If disabling LWIP_IPV6 then some other components (coap and asio) will
+            If disabling LWIP_IPV6 then some other components (asio) will
             no longer be available.
 
     config LWIP_IPV6_AUTOCONFIG
diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt
index a162a0a3abd..28428f25d8a 100644
--- a/components/mbedtls/CMakeLists.txt
+++ b/components/mbedtls/CMakeLists.txt
@@ -242,7 +242,7 @@ if(CONFIG_MBEDTLS_HARDWARE_SHA)
     )
 endif()
 
-if(CONFIG_MBEDTLS_HARDWARE_GCM OR (NOT CONFIG_SOC_AES_SUPPORT_GCM AND CONFIG_MBEDTLS_HARDWARE_AES))
+if(CONFIG_MBEDTLS_HARDWARE_GCM OR CONFIG_MBEDTLS_HARDWARE_AES)
     target_sources(mbedcrypto PRIVATE  "${COMPONENT_DIR}/port/aes/esp_aes_gcm.c")
 endif()
 
diff --git a/components/mbedtls/port/aes/dma/esp_aes.c b/components/mbedtls/port/aes/dma/esp_aes.c
index 693586813b7..c2e4d33e103 100644
--- a/components/mbedtls/port/aes/dma/esp_aes.c
+++ b/components/mbedtls/port/aes/dma/esp_aes.c
@@ -53,10 +53,6 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 
-#if SOC_AES_SUPPORT_GCM
-#include "aes/esp_aes_gcm.h"
-#endif
-
 #if SOC_AES_GDMA
 #define AES_LOCK() esp_crypto_sha_aes_lock_acquire()
 #define AES_RELEASE() esp_crypto_sha_aes_lock_release()
@@ -488,7 +484,7 @@ static int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input,
 }
 
 
-#if SOC_AES_SUPPORT_GCM
+#if CONFIG_MBEDTLS_HARDWARE_GCM
 
 /* Encrypt/decrypt with AES-GCM the input using DMA
  * The function esp_aes_process_dma_gcm zeroises the output buffer in the case of following conditions:
@@ -623,7 +619,7 @@ int esp_aes_process_dma_gcm(esp_aes_context *ctx, const unsigned char *input, un
     return ret;
 }
 
-#endif //SOC_AES_SUPPORT_GCM
+#endif //CONFIG_MBEDTLS_HARDWARE_GCM
 
 static int esp_aes_validate_input(esp_aes_context *ctx, const unsigned char *input,
                                   unsigned char *output )
diff --git a/components/mbedtls/port/aes/esp_aes_gcm.c b/components/mbedtls/port/aes/esp_aes_gcm.c
index c91b4fdce1c..0ed37cb2768 100644
--- a/components/mbedtls/port/aes/esp_aes_gcm.c
+++ b/components/mbedtls/port/aes/esp_aes_gcm.c
@@ -371,7 +371,7 @@ int esp_aes_gcm_starts( esp_gcm_context *ctx,
     /* H and the lookup table are only generated once per ctx */
     if (ctx->gcm_state == ESP_AES_GCM_STATE_INIT) {
         /* Lock the AES engine to calculate ghash key H in hardware */
-#if SOC_AES_SUPPORT_GCM
+#if CONFIG_MBEDTLS_HARDWARE_GCM
         esp_aes_acquire_hardware();
         ctx->aes_ctx.key_in_hardware = aes_hal_setkey(ctx->aes_ctx.key, ctx->aes_ctx.key_bytes, mode);
         aes_hal_mode_init(ESP_AES_BLOCK_MODE_GCM);
@@ -529,7 +529,7 @@ int esp_aes_gcm_finish( esp_gcm_context *ctx,
     return esp_aes_crypt_ctr(&ctx->aes_ctx, tag_len, &nc_off, ctx->ori_j0, stream, ctx->ghash, tag);
 }
 
-#if SOC_AES_SUPPORT_GCM
+#if CONFIG_MBEDTLS_HARDWARE_GCM
 /* Due to restrictions in the hardware (e.g. need to do the whole conversion in one go),
    some combinations of inputs are not supported */
 static bool esp_aes_gcm_input_support_hw_accel(size_t length, const unsigned char *aad, size_t aad_len,
@@ -607,7 +607,7 @@ int esp_aes_gcm_crypt_and_tag( esp_gcm_context *ctx,
                                size_t tag_len,
                                unsigned char *tag )
 {
-#if SOC_AES_SUPPORT_GCM
+#if CONFIG_MBEDTLS_HARDWARE_GCM
     int ret;
     lldesc_t aad_desc[2] = {};
     lldesc_t *aad_head_desc = NULL;
diff --git a/components/mbedtls/port/dynamic/esp_ssl_cli.c b/components/mbedtls/port/dynamic/esp_ssl_cli.c
index 9fb224419cf..0ea78df59d2 100644
--- a/components/mbedtls/port/dynamic/esp_ssl_cli.c
+++ b/components/mbedtls/port/dynamic/esp_ssl_cli.c
@@ -185,6 +185,11 @@ static int manage_resource(mbedtls_ssl_context *ssl, bool add)
         case MBEDTLS_SSL_FLUSH_BUFFERS:
             break;
         case MBEDTLS_SSL_HANDSHAKE_WRAPUP:
+#if defined(MBEDTLS_SSL_RENEGOTIATION)
+            if (add && ssl->MBEDTLS_PRIVATE(renego_status)) {
+                CHECK_OK(esp_mbedtls_add_rx_buffer(ssl));
+            }
+#endif
             break;
         default:
             break;
diff --git a/components/openthread/sbom.yml b/components/openthread/sbom.yml
new file mode 100644
index 00000000000..c4f2ae6377c
--- /dev/null
+++ b/components/openthread/sbom.yml
@@ -0,0 +1,7 @@
+name: 'openthread component'
+version: '2023-07-06'
+supplier: 'Organization: Espressif Systems (Shanghai) CO LTD'
+description: Espressif fork of OpenThread project, used to maintain ESP-specific patches and release branches
+manifests:
+   - path: sbom_openthread.yml
+     dest: openthread
diff --git a/components/openthread/sbom_openthread.yml b/components/openthread/sbom_openthread.yml
new file mode 100644
index 00000000000..c518ee3bc05
--- /dev/null
+++ b/components/openthread/sbom_openthread.yml
@@ -0,0 +1,8 @@
+name: 'openthread'
+version: '2023-07-06'
+cpe: cpe:2.3:o:google:openthread:{}:*:*:*:*:*:*:*
+supplier: 'Organization: Espressif Systems (Shanghai) CO LTD'
+originator: 'Organization: Google LLC'
+description: OpenThread released by Google is an open-source implementation of the Thread networking
+url: https://github.com/espressif/openthread
+hash: 41ef80717f4b757440125932723cc8721ef42f7f
diff --git a/components/openthread/src/port/esp_openthread_uart.c b/components/openthread/src/port/esp_openthread_uart.c
index cd5fe9d61cc..fc33cd1f93b 100644
--- a/components/openthread/src/port/esp_openthread_uart.c
+++ b/components/openthread/src/port/esp_openthread_uart.c
@@ -22,7 +22,7 @@
 #include "driver/uart.h"
 #include "driver/uart_vfs.h"
 #include "utils/uart.h"
-#include "esp_vfs_usb_serial_jtag.h"
+#include "driver/usb_serial_jtag_vfs.h"
 #include "driver/usb_serial_jtag.h"
 
 static int s_uart_port;
@@ -81,16 +81,16 @@ esp_err_t esp_openthread_host_cli_usb_init(const esp_openthread_platform_config_
     setvbuf(stdin, NULL, _IONBF, 0);
 
     /* Minicom, screen, idf_monitor send CR when ENTER key is pressed */
-    esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
+    usb_serial_jtag_vfs_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
     /* Move the caret to the beginning of the next line on '\n' */
-    esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
+    usb_serial_jtag_vfs_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
 
     /* Enable non-blocking mode on stdin and stdout */
     fcntl(fileno(stdout), F_SETFL, O_NONBLOCK);
     fcntl(fileno(stdin), F_SETFL, O_NONBLOCK);
 
     ret = usb_serial_jtag_driver_install((usb_serial_jtag_driver_config_t *)&config->host_config.host_usb_config);
-    esp_vfs_usb_serial_jtag_use_driver();
+    usb_serial_jtag_vfs_use_driver();
     uart_vfs_dev_register();
     return ret;
 }
diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h
index 9048f52785e..b2906739f63 100644
--- a/components/riscv/include/riscv/rv_utils.h
+++ b/components/riscv/include/riscv/rv_utils.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,6 +43,14 @@ extern "C" {
    and spinlocks */
 #define RVHAL_EXCM_LEVEL    4
 
+/* SW defined interrupt threshold level to allow all interrupts */
+#if SOC_INT_CLIC_SUPPORTED
+/* set global CLIC masking level. When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */
+#define RVHAL_INTR_ENABLE_THRESH    0
+#else
+#define RVHAL_INTR_ENABLE_THRESH    1
+#endif /* SOC_INT_CLIC_SUPPORTED */
+
 /* --------------------------------------------------- CPU Control -----------------------------------------------------
  *
  * ------------------------------------------------------------------------------------------------------------------ */
diff --git a/components/sdmmc/CMakeLists.txt b/components/sdmmc/CMakeLists.txt
index 243b26c4d60..d435540f3a1 100644
--- a/components/sdmmc/CMakeLists.txt
+++ b/components/sdmmc/CMakeLists.txt
@@ -11,4 +11,4 @@ idf_component_register(SRCS "sdmmc_cmd.c"
                             "sdmmc_mmc.c"
                             "sdmmc_sd.c"
                     INCLUDE_DIRS include
-                    PRIV_REQUIRES soc esp_timer)
+                    PRIV_REQUIRES soc esp_timer esp_mm)
diff --git a/components/sdmmc/sdmmc_sd.c b/components/sdmmc/sdmmc_sd.c
index 6275e7cf7ff..464ab1362b1 100644
--- a/components/sdmmc/sdmmc_sd.c
+++ b/components/sdmmc/sdmmc_sd.c
@@ -17,6 +17,7 @@
 
 #include <inttypes.h>
 #include "esp_timer.h"
+#include "esp_cache.h"
 #include "sdmmc_common.h"
 
 static const char* TAG = "sdmmc_sd";
@@ -191,12 +192,14 @@ esp_err_t sdmmc_send_cmd_switch_func(sdmmc_card_t* card,
     uint32_t other_func_mask = (0x00ffffff & ~(0xf << group_shift));
     uint32_t func_val = (function << group_shift) | other_func_mask;
 
+    size_t datalen = sizeof(sdmmc_switch_func_rsp_t);
     sdmmc_command_t cmd = {
             .opcode = MMC_SWITCH,
             .flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1,
             .blklen = sizeof(sdmmc_switch_func_rsp_t),
             .data = resp->data,
-            .datalen = sizeof(sdmmc_switch_func_rsp_t),
+            .datalen = datalen,
+            .buflen = datalen,
             .arg = (!!mode << 31) | func_val
     };
 
@@ -233,13 +236,16 @@ esp_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card)
         ((card->csd.card_command_class & SD_CSD_CCC_SWITCH) == 0)) {
             return ESP_ERR_NOT_SUPPORTED;
     }
-    sdmmc_switch_func_rsp_t* response = (sdmmc_switch_func_rsp_t*)
-            heap_caps_malloc(sizeof(*response), MALLOC_CAP_DMA);
-    if (response == NULL) {
-        return ESP_ERR_NO_MEM;
+
+    size_t actual_size = 0;
+    sdmmc_switch_func_rsp_t *response = NULL;
+    esp_err_t err = esp_dma_malloc(sizeof(*response), 0, (void *)&response, &actual_size);
+    assert(actual_size == sizeof(*response));
+    if (err != ESP_OK) {
+        return err;
     }
 
-    esp_err_t err = sdmmc_send_cmd_switch_func(card, 0, SD_ACCESS_MODE, 0, response);
+    err = sdmmc_send_cmd_switch_func(card, 0, SD_ACCESS_MODE, 0, response);
     if (err != ESP_OK) {
         ESP_LOGD(TAG, "%s: sdmmc_send_cmd_switch_func (1) returned 0x%x", __func__, err);
         goto out;
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index 361d7bd73e3..8644c0c61a6 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1339,6 +1339,10 @@ config SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
     bool
     default y
 
+config SOC_TEMPERATURE_SENSOR_IS_INDEPENDENT_FROM_ADC
+    bool
+    default y
+
 config SOC_MEM_TCM_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index b936723f940..f6d7aa645fb 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -214,11 +214,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of RMT
  */
-#if SOC_CLK_TREE_SUPPORTED
 #define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
-#else
-#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL}
-#endif
 
 /**
  * @brief Type of RMT clock source
@@ -227,11 +223,7 @@ typedef enum {
     RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
     RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
     RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-#if SOC_CLK_TREE_SUPPORTED
     RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
-#else
-    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default choice */
-#endif
 } soc_periph_rmt_clk_src_t;
 
 /**
@@ -240,11 +232,7 @@ typedef enum {
 typedef enum {
     RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
     RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,         /*!< RMT source clock is XTAL */
-#if SOC_CLK_TREE_SUPPORTED
     RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< RMT source clock default choice is PLL_F80M */
-#else
-    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< RMT source clock default choice is XTAL */
-#endif
 } soc_periph_rmt_clk_src_legacy_t;
 
 //////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
diff --git a/components/soc/esp32p4/include/soc/h264_dma_struct.h b/components/soc/esp32p4/include/soc/h264_dma_struct.h
index bbc704f0348..8153929570e 100644
--- a/components/soc/esp32p4/include/soc/h264_dma_struct.h
+++ b/components/soc/esp32p4/include/soc/h264_dma_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,5915 +10,1403 @@
 extern "C" {
 #endif
 
-/** Group: Configuration Registers */
-/** Type of out_conf0_ch0 register
- *  TX CH0 config0 register
- */
-typedef union {
-    struct {
-        /** out_auto_wrback_ch0 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
-         *  outlink descriptor has been received.
-         */
-        uint32_t out_auto_wrback_ch0:1;
-        /** out_eof_mode_ch0 : R/W; bitpos: [1]; default: 1;
-         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
-         *  generated when data need to read has been popped from FIFO in DMA
-         */
-        uint32_t out_eof_mode_ch0:1;
-        /** outdscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
-         *  descriptor when accessing internal SRAM.
-         */
-        uint32_t outdscr_burst_en_ch0:1;
-        /** out_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
-         */
-        uint32_t out_ecc_aes_en_ch0:1;
-        /** out_check_owner_ch0 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t out_check_owner_ch0:1;
-        uint32_t reserved_5:1;
-        /** out_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
-         */
-        uint32_t out_mem_burst_length_ch0:3;
-        uint32_t reserved_9:3;
-        /** out_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
-         *  define by mem_burst_length
-         */
-        uint32_t out_page_bound_en_ch0:1;
-        uint32_t reserved_13:3;
-        /** out_reorder_en_ch0 : R/W; bitpos: [16]; default: 0;
-         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
-         *  selection
-         */
-        uint32_t out_reorder_en_ch0:1;
-        uint32_t reserved_17:7;
-        /** out_rst_ch0 : R/W; bitpos: [24]; default: 0;
-         *  Write 1 then write 0 to this bit to reset TX channel
-         */
-        uint32_t out_rst_ch0:1;
-        /** out_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0;
-         *  Write 1 before reset and write 0 after reset
-         */
-        uint32_t out_cmd_disable_ch0:1;
-        /** out_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
-         */
-        uint32_t out_arb_weight_opt_dis_ch0:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} h264_dma_out_conf0_ch0_reg_t;
-
-/** Type of out_push_ch0 register
- *  TX CH0 outfifo push register
- */
-typedef union {
-    struct {
-        /** outfifo_wdata_ch0 : R/W; bitpos: [9:0]; default: 0;
-         *  This register stores the data that need to be pushed into DMA Tx FIFO.
-         */
-        uint32_t outfifo_wdata_ch0:10;
-        /** outfifo_push_ch0 : R/W/SC; bitpos: [10]; default: 0;
-         *  Set this bit to push data into DMA Tx FIFO.
-         */
-        uint32_t outfifo_push_ch0:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} h264_dma_out_push_ch0_reg_t;
-
-/** Type of out_link_conf_ch0 register
- *  TX CH0 out_link dscr ctrl register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** outlink_stop_ch0 : R/W/SC; bitpos: [20]; default: 0;
-         *  Set this bit to stop dealing with the outlink descriptors.
-         */
-        uint32_t outlink_stop_ch0:1;
-        /** outlink_start_ch0 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to start dealing with the outlink descriptors.
-         */
-        uint32_t outlink_start_ch0:1;
-        /** outlink_restart_ch0 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to restart a new outlink from the last address.
-         */
-        uint32_t outlink_restart_ch0:1;
-        /** outlink_park_ch0 : RO; bitpos: [23]; default: 1;
-         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
-         *  is working.
-         */
-        uint32_t outlink_park_ch0:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_out_link_conf_ch0_reg_t;
-
-/** Type of out_ro_pd_conf_ch0 register
- *  TX CH0 reorder power config register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** out_ro_ram_force_pd_ch0 : R/W; bitpos: [4]; default: 0;
-         *  dma reorder ram power down
-         */
-        uint32_t out_ro_ram_force_pd_ch0:1;
-        /** out_ro_ram_force_pu_ch0 : R/W; bitpos: [5]; default: 1;
-         *  dma reorder ram power up
-         */
-        uint32_t out_ro_ram_force_pu_ch0:1;
-        /** out_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0;
-         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
-         *  0: A gate-clock will be used when accessing the RAM in DMA.
-         */
-        uint32_t out_ro_ram_clk_fo_ch0:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} h264_dma_out_ro_pd_conf_ch0_reg_t;
-
-/** Type of out_push_ch1 register
- *  TX CH1 outfifo push register
- */
-typedef union {
-    struct {
-        /** outfifo_wdata_ch1 : R/W; bitpos: [9:0]; default: 0;
-         *  This register stores the data that need to be pushed into DMA Tx FIFO.
-         */
-        uint32_t outfifo_wdata_ch1:10;
-        /** outfifo_push_ch1 : R/W/SC; bitpos: [10]; default: 0;
-         *  Set this bit to push data into DMA Tx FIFO.
-         */
-        uint32_t outfifo_push_ch1:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} h264_dma_out_push_ch1_reg_t;
-
-/** Type of out_link_conf_ch1 register
- *  TX CH1 out_link dscr ctrl register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** outlink_stop_ch1 : R/W/SC; bitpos: [20]; default: 0;
-         *  Set this bit to stop dealing with the outlink descriptors.
-         */
-        uint32_t outlink_stop_ch1:1;
-        /** outlink_start_ch1 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to start dealing with the outlink descriptors.
-         */
-        uint32_t outlink_start_ch1:1;
-        /** outlink_restart_ch1 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to restart a new outlink from the last address.
-         */
-        uint32_t outlink_restart_ch1:1;
-        /** outlink_park_ch1 : RO; bitpos: [23]; default: 1;
-         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
-         *  is working.
-         */
-        uint32_t outlink_park_ch1:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_out_link_conf_ch1_reg_t;
-
-/** Type of out_push_ch2 register
- *  TX CH2 outfifo push register
- */
-typedef union {
-    struct {
-        /** outfifo_wdata_ch2 : R/W; bitpos: [9:0]; default: 0;
-         *  This register stores the data that need to be pushed into DMA Tx FIFO.
-         */
-        uint32_t outfifo_wdata_ch2:10;
-        /** outfifo_push_ch2 : R/W/SC; bitpos: [10]; default: 0;
-         *  Set this bit to push data into DMA Tx FIFO.
-         */
-        uint32_t outfifo_push_ch2:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} h264_dma_out_push_ch2_reg_t;
-
-/** Type of out_link_conf_ch2 register
- *  TX CH2 out_link dscr ctrl register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** outlink_stop_ch2 : R/W/SC; bitpos: [20]; default: 0;
-         *  Set this bit to stop dealing with the outlink descriptors.
-         */
-        uint32_t outlink_stop_ch2:1;
-        /** outlink_start_ch2 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to start dealing with the outlink descriptors.
-         */
-        uint32_t outlink_start_ch2:1;
-        /** outlink_restart_ch2 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to restart a new outlink from the last address.
-         */
-        uint32_t outlink_restart_ch2:1;
-        /** outlink_park_ch2 : RO; bitpos: [23]; default: 1;
-         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
-         *  is working.
-         */
-        uint32_t outlink_park_ch2:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_out_link_conf_ch2_reg_t;
-
-/** Type of out_push_ch3 register
- *  TX CH3 outfifo push register
- */
-typedef union {
-    struct {
-        /** outfifo_wdata_ch3 : R/W; bitpos: [9:0]; default: 0;
-         *  This register stores the data that need to be pushed into DMA Tx FIFO.
-         */
-        uint32_t outfifo_wdata_ch3:10;
-        /** outfifo_push_ch3 : R/W/SC; bitpos: [10]; default: 0;
-         *  Set this bit to push data into DMA Tx FIFO.
-         */
-        uint32_t outfifo_push_ch3:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} h264_dma_out_push_ch3_reg_t;
-
-/** Type of out_link_conf_ch3 register
- *  TX CH3 out_link dscr ctrl register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** outlink_stop_ch3 : R/W/SC; bitpos: [20]; default: 0;
-         *  Set this bit to stop dealing with the outlink descriptors.
-         */
-        uint32_t outlink_stop_ch3:1;
-        /** outlink_start_ch3 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to start dealing with the outlink descriptors.
-         */
-        uint32_t outlink_start_ch3:1;
-        /** outlink_restart_ch3 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to restart a new outlink from the last address.
-         */
-        uint32_t outlink_restart_ch3:1;
-        /** outlink_park_ch3 : RO; bitpos: [23]; default: 1;
-         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
-         *  is working.
-         */
-        uint32_t outlink_park_ch3:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_out_link_conf_ch3_reg_t;
 
-/** Type of out_push_ch4 register
- *  TX CH4 outfifo push register
+/** Type of out_push register
+ *  TX CHn outfifo push register
  */
 typedef union {
     struct {
-        /** outfifo_wdata_ch4 : R/W; bitpos: [9:0]; default: 0;
+        /** outfifo_wdata : R/W; bitpos: [9:0]; default: 0;
          *  This register stores the data that need to be pushed into DMA Tx FIFO.
          */
-        uint32_t outfifo_wdata_ch4:10;
-        /** outfifo_push_ch4 : R/W/SC; bitpos: [10]; default: 0;
+        uint32_t outfifo_wdata:10;
+        /** outfifo_push : R/W/SC; bitpos: [10]; default: 0;
          *  Set this bit to push data into DMA Tx FIFO.
          */
-        uint32_t outfifo_push_ch4:1;
+        uint32_t outfifo_push:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} h264_dma_out_push_ch4_reg_t;
+} h264_dma_out_push_chn_reg_t;
 
-/** Type of out_link_conf_ch4 register
- *  TX CH4 out_link dscr ctrl register
+/** Type of out_link_conf register
+ *  TX CHn out_link dscr ctrl register
  */
 typedef union {
     struct {
         uint32_t reserved_0:20;
-        /** outlink_stop_ch4 : R/W/SC; bitpos: [20]; default: 0;
+        /** outlink_stop : R/W/SC; bitpos: [20]; default: 0;
          *  Set this bit to stop dealing with the outlink descriptors.
          */
-        uint32_t outlink_stop_ch4:1;
-        /** outlink_start_ch4 : R/W/SC; bitpos: [21]; default: 0;
+        uint32_t outlink_stop:1;
+        /** outlink_start : R/W/SC; bitpos: [21]; default: 0;
          *  Set this bit to start dealing with the outlink descriptors.
          */
-        uint32_t outlink_start_ch4:1;
-        /** outlink_restart_ch4 : R/W/SC; bitpos: [22]; default: 0;
+        uint32_t outlink_start:1;
+        /** outlink_restart : R/W/SC; bitpos: [22]; default: 0;
          *  Set this bit to restart a new outlink from the last address.
          */
-        uint32_t outlink_restart_ch4:1;
-        /** outlink_park_ch4 : RO; bitpos: [23]; default: 1;
+        uint32_t outlink_restart:1;
+        /** outlink_park : RO; bitpos: [23]; default: 1;
          *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
          *  is working.
          */
-        uint32_t outlink_park_ch4:1;
+        uint32_t outlink_park:1;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} h264_dma_out_link_conf_ch4_reg_t;
+} h264_dma_out_link_conf_chn_reg_t;
 
-/** Type of in_conf0_ch0 register
- *  RX CH0 config0 register
+/** Type of in_conf0 register
+ *  RX CHn config0 register
  */
 typedef union {
     struct {
         uint32_t reserved_0:2;
-        /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
+        /** indscr_burst_en : R/W; bitpos: [2]; default: 0;
          *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
          *  when accessing SRAM.
          */
-        uint32_t indscr_burst_en_ch0:1;
-        /** in_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0;
+        uint32_t indscr_burst_en:1;
+        /** in_ecc_aes_en : R/W; bitpos: [3]; default: 0;
          *  When access address space is ecc/aes area, this bit should be set to 1. In this
          *  case, the start address of square should be 16-bit aligned. The width of square
          *  multiply byte number of one pixel should be 16-bit aligned.
          */
-        uint32_t in_ecc_aes_en_ch0:1;
-        /** in_check_owner_ch0 : R/W; bitpos: [4]; default: 0;
+        uint32_t in_ecc_aes_en:1;
+        /** in_check_owner : R/W; bitpos: [4]; default: 0;
          *  Set this bit to enable checking the owner attribute of the link descriptor.
          */
-        uint32_t in_check_owner_ch0:1;
+        uint32_t in_check_owner:1;
         uint32_t reserved_5:1;
-        /** in_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0;
+        /** in_mem_burst_length : R/W; bitpos: [8:6]; default: 0;
          *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
          *  bytes    4: 128 bytes
          */
-        uint32_t in_mem_burst_length_ch0:3;
+        uint32_t in_mem_burst_length:3;
         uint32_t reserved_9:3;
-        /** in_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0;
+        /** in_page_bound_en : R/W; bitpos: [12]; default: 0;
          *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
          *  which define by mem_burst_length
          */
-        uint32_t in_page_bound_en_ch0:1;
+        uint32_t in_page_bound_en:1;
         uint32_t reserved_13:11;
-        /** in_rst_ch0 : R/W; bitpos: [24]; default: 0;
+        /** in_rst : R/W; bitpos: [24]; default: 0;
          *  Write 1 then write 0 to this bit to reset Rx channel
          */
-        uint32_t in_rst_ch0:1;
-        /** in_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0;
+        uint32_t in_rst:1;
+        /** in_cmd_disable : R/W; bitpos: [25]; default: 0;
          *  Write 1 before reset and write 0 after reset
          */
-        uint32_t in_cmd_disable_ch0:1;
-        /** in_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0;
+        uint32_t in_cmd_disable:1;
+        /** in_arb_weight_opt_dis : R/W; bitpos: [26]; default: 0;
          *  Set this bit to 1 to disable arbiter optimum weight function.
          */
-        uint32_t in_arb_weight_opt_dis_ch0:1;
+        uint32_t in_arb_weight_opt_dis:1;
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} h264_dma_in_conf0_ch0_reg_t;
+} h264_dma_in_conf0_chn_reg_t;
 
-/** Type of in_pop_ch0 register
- *  RX CH0 INFIFO pop register
+/** Type of in_pop register
+ *  RX CHn INFIFO pop register
  */
 typedef union {
     struct {
-        /** infifo_rdata_ch0 : RO; bitpos: [10:0]; default: 1024;
+        /** infifo_rdata : RO; bitpos: [10:0]; default: 1024;
          *  This register stores the data popping from DMA Rx FIFO.
          */
-        uint32_t infifo_rdata_ch0:11;
-        /** infifo_pop_ch0 : R/W/SC; bitpos: [11]; default: 0;
+        uint32_t infifo_rdata:11;
+        /** infifo_pop : R/W/SC; bitpos: [11]; default: 0;
          *  Set this bit to pop data from DMA Rx FIFO.
          */
-        uint32_t infifo_pop_ch0:1;
+        uint32_t infifo_pop:1;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} h264_dma_in_pop_ch0_reg_t;
+} h264_dma_in_pop_chn_reg_t;
 
-/** Type of in_link_conf_ch0 register
- *  RX CH0 in_link dscr ctrl register
+/** Type of in_link_conf register
+ *  RX CHn in_link dscr ctrl register
  */
 typedef union {
     struct {
         uint32_t reserved_0:20;
-        /** inlink_auto_ret_ch0 : R/W; bitpos: [20]; default: 1;
+        /** inlink_auto_ret : R/W; bitpos: [20]; default: 1;
          *  Set this bit to return to current inlink descriptor's address, when there are some
          *  errors in current receiving data.
          */
-        uint32_t inlink_auto_ret_ch0:1;
-        /** inlink_stop_ch0 : R/W/SC; bitpos: [21]; default: 0;
+        uint32_t inlink_auto_ret:1;
+        /** inlink_stop : R/W/SC; bitpos: [21]; default: 0;
          *  Set this bit to stop dealing with the inlink descriptors.
          */
-        uint32_t inlink_stop_ch0:1;
-        /** inlink_start_ch0 : R/W/SC; bitpos: [22]; default: 0;
+        uint32_t inlink_stop:1;
+        /** inlink_start : R/W/SC; bitpos: [22]; default: 0;
          *  Set this bit to start dealing with the inlink descriptors.
          */
-        uint32_t inlink_start_ch0:1;
-        /** inlink_restart_ch0 : R/W/SC; bitpos: [23]; default: 0;
+        uint32_t inlink_start:1;
+        /** inlink_restart : R/W/SC; bitpos: [23]; default: 0;
          *  Set this bit to mount a new inlink descriptor.
          */
-        uint32_t inlink_restart_ch0:1;
-        /** inlink_park_ch0 : RO; bitpos: [24]; default: 1;
+        uint32_t inlink_restart:1;
+        /** inlink_park : RO; bitpos: [24]; default: 1;
          *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
          *  working.
          */
-        uint32_t inlink_park_ch0:1;
+        uint32_t inlink_park:1;
         uint32_t reserved_25:7;
     };
     uint32_t val;
-} h264_dma_in_link_conf_ch0_reg_t;
+} h264_dma_in_link_conf_chn_reg_t;
 
-/** Type of in_ro_pd_conf_ch0 register
- *  RX CH0 reorder power config register
+/** Type of in_ro_pd_conf register
+ *  RX CHn reorder power config register
  */
 typedef union {
     struct {
         uint32_t reserved_0:6;
-        /** in_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0;
+        /** in_ro_ram_clk_fo : R/W; bitpos: [6]; default: 0;
          *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
          *  0: A gate-clock will be used when accessing the RAM in DMA.
          */
-        uint32_t in_ro_ram_clk_fo_ch0:1;
+        uint32_t in_ro_ram_clk_fo:1;
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} h264_dma_in_ro_pd_conf_ch0_reg_t;
+} h264_dma_in_ro_pd_conf_chn_reg_t;
 
-/** Type of in_conf0_ch1 register
- *  RX CH1 config0 register
+/** Type of in_conf0_ch5 register
+ *  RX CH5 config0 register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:2;
-        /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
-         *  when accessing SRAM.
-         */
-        uint32_t indscr_burst_en_ch1:1;
-        /** in_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0;
+        uint32_t reserved_0:3;
+        /** in_ecc_aes_en : R/W; bitpos: [3]; default: 0;
          *  When access address space is ecc/aes area, this bit should be set to 1. In this
          *  case, the start address of square should be 16-bit aligned. The width of square
          *  multiply byte number of one pixel should be 16-bit aligned.
          */
-        uint32_t in_ecc_aes_en_ch1:1;
-        /** in_check_owner_ch1 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t in_check_owner_ch1:1;
-        uint32_t reserved_5:1;
-        /** in_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0;
+        uint32_t in_ecc_aes_en:1;
+        uint32_t reserved_4:2;
+        /** in_mem_burst_length : R/W; bitpos: [8:6]; default: 0;
          *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
          *  bytes    4: 128 bytes
          */
-        uint32_t in_mem_burst_length_ch1:3;
+        uint32_t in_mem_burst_length:3;
         uint32_t reserved_9:3;
-        /** in_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0;
+        /** in_page_bound_en : R/W; bitpos: [12]; default: 0;
          *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
          *  which define by mem_burst_length
          */
-        uint32_t in_page_bound_en_ch1:1;
+        uint32_t in_page_bound_en:1;
         uint32_t reserved_13:11;
-        /** in_rst_ch1 : R/W; bitpos: [24]; default: 0;
+        /** in_rst : R/W; bitpos: [24]; default: 0;
          *  Write 1 then write 0 to this bit to reset Rx channel
          */
-        uint32_t in_rst_ch1:1;
-        /** in_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0;
+        uint32_t in_rst:1;
+        /** in_cmd_disable : R/W; bitpos: [25]; default: 0;
          *  Write 1 before reset and write 0 after reset
          */
-        uint32_t in_cmd_disable_ch1:1;
-        /** in_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
-         */
-        uint32_t in_arb_weight_opt_dis_ch1:1;
-        uint32_t reserved_27:5;
+        uint32_t in_cmd_disable:1;
+        uint32_t reserved_26:6;
     };
     uint32_t val;
-} h264_dma_in_conf0_ch1_reg_t;
+} h264_dma_in_conf0_ch5_reg_t;
 
-/** Type of in_pop_ch1 register
- *  RX CH1 INFIFO pop register
+/** Type of in_pop_ch5 register
+ *  RX CH5 INFIFO pop register
  */
 typedef union {
     struct {
-        /** infifo_rdata_ch1 : RO; bitpos: [10:0]; default: 1024;
+        /** infifo_rdata : RO; bitpos: [10:0]; default: 1024;
          *  This register stores the data popping from DMA Rx FIFO.
          */
-        uint32_t infifo_rdata_ch1:11;
-        /** infifo_pop_ch1 : R/W/SC; bitpos: [11]; default: 0;
+        uint32_t infifo_rdata:11;
+        /** infifo_pop : R/W/SC; bitpos: [11]; default: 0;
          *  Set this bit to pop data from DMA Rx FIFO.
          */
-        uint32_t infifo_pop_ch1:1;
+        uint32_t infifo_pop:1;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} h264_dma_in_pop_ch1_reg_t;
+} h264_dma_in_pop_ch5_reg_t;
 
-/** Type of in_link_conf_ch1 register
- *  RX CH1 in_link dscr ctrl register
+/** Type of rst_conf register
+ *  axi reset config register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:20;
-        /** inlink_auto_ret_ch1 : R/W; bitpos: [20]; default: 1;
-         *  Set this bit to return to current inlink descriptor's address, when there are some
-         *  errors in current receiving data.
+        /** inter_axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
          */
-        uint32_t inlink_auto_ret_ch1:1;
-        /** inlink_stop_ch1 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to stop dealing with the inlink descriptors.
+        uint32_t inter_axim_rd_rst:1;
+        /** inter_axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
          */
-        uint32_t inlink_stop_ch1:1;
-        /** inlink_start_ch1 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to start dealing with the inlink descriptors.
+        uint32_t inter_axim_wr_rst:1;
+        /** exter_axim_rd_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
          */
-        uint32_t inlink_start_ch1:1;
-        /** inlink_restart_ch1 : R/W/SC; bitpos: [23]; default: 0;
-         *  Set this bit to mount a new inlink descriptor.
+        uint32_t exter_axim_rd_rst:1;
+        /** exter_axim_wr_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
          */
-        uint32_t inlink_restart_ch1:1;
-        /** inlink_park_ch1 : RO; bitpos: [24]; default: 1;
-         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
-         *  working.
+        uint32_t exter_axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
          */
-        uint32_t inlink_park_ch1:1;
-        uint32_t reserved_25:7;
+        uint32_t clk_en:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
-} h264_dma_in_link_conf_ch1_reg_t;
+} h264_dma_rst_conf_reg_t;
+
 
-/** Type of in_conf0_ch2 register
- *  RX CH2 config0 register
+/** Type of out_int_raw register
+ *  TX CHn  interrupt raw register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:2;
-        /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
-         *  when accessing SRAM.
+        /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
          */
-        uint32_t indscr_burst_en_ch2:1;
-        /** in_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
+        uint32_t done_int_raw:1;
+        /** eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
          */
-        uint32_t in_ecc_aes_en_ch2:1;
-        /** in_check_owner_ch2 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
+        uint32_t eof_int_raw:1;
+        /** dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
          */
-        uint32_t in_check_owner_ch2:1;
-        uint32_t reserved_5:1;
-        /** in_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Rx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
+        uint32_t dscr_err_int_raw:1;
+        /** total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
          */
-        uint32_t in_mem_burst_length_ch2:3;
-        uint32_t reserved_9:3;
-        /** in_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
-         *  which define by mem_burst_length
+        uint32_t total_eof_int_raw:1;
+        /** outfifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
          */
-        uint32_t in_page_bound_en_ch2:1;
-        uint32_t reserved_13:11;
-        /** in_rst_ch2 : R/W; bitpos: [24]; default: 0;
-         *  Write 1 then write 0 to this bit to reset Rx channel
+        uint32_t outfifo_ovf_l1_int_raw:1;
+        /** outfifo_udf_l1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
          */
-        uint32_t in_rst_ch2:1;
-        /** in_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0;
-         *  Write 1 before reset and write 0 after reset
+        uint32_t outfifo_udf_l1_int_raw:1;
+        /** outfifo_ovf_l2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
          */
-        uint32_t in_cmd_disable_ch2:1;
-        /** in_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
+        uint32_t outfifo_ovf_l2_int_raw:1;
+        /** outfifo_udf_l2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
          */
-        uint32_t in_arb_weight_opt_dis_ch2:1;
-        uint32_t reserved_27:5;
+        uint32_t outfifo_udf_l2_int_raw:1;
+        /** dscr_task_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t dscr_task_ovf_int_raw:1;
+        uint32_t reserved_9:23;
     };
     uint32_t val;
-} h264_dma_in_conf0_ch2_reg_t;
+} h264_dma_out_int_raw_chn_reg_t;
 
-/** Type of in_pop_ch2 register
- *  RX CH2 INFIFO pop register
+/** Type of out_int_ena register
+ *  TX CHn  interrupt ena register
  */
 typedef union {
     struct {
-        /** infifo_rdata_ch2 : RO; bitpos: [10:0]; default: 1024;
-         *  This register stores the data popping from DMA Rx FIFO.
+        /** done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t infifo_rdata_ch2:11;
-        /** infifo_pop_ch2 : R/W/SC; bitpos: [11]; default: 0;
-         *  Set this bit to pop data from DMA Rx FIFO.
+        uint32_t done_int_ena:1;
+        /** eof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t infifo_pop_ch2:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} h264_dma_in_pop_ch2_reg_t;
-
-/** Type of in_link_conf_ch2 register
- *  RX CH2 in_link dscr ctrl register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** inlink_auto_ret_ch2 : R/W; bitpos: [20]; default: 1;
-         *  Set this bit to return to current inlink descriptor's address, when there are some
-         *  errors in current receiving data.
+        uint32_t eof_int_ena:1;
+        /** dscr_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t inlink_auto_ret_ch2:1;
-        /** inlink_stop_ch2 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to stop dealing with the inlink descriptors.
+        uint32_t dscr_err_int_ena:1;
+        /** total_eof_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t inlink_stop_ch2:1;
-        /** inlink_start_ch2 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to start dealing with the inlink descriptors.
+        uint32_t total_eof_int_ena:1;
+        /** outfifo_ovf_l1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t inlink_start_ch2:1;
-        /** inlink_restart_ch2 : R/W/SC; bitpos: [23]; default: 0;
-         *  Set this bit to mount a new inlink descriptor.
+        uint32_t outfifo_ovf_l1_int_ena:1;
+        /** outfifo_udf_l1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t inlink_restart_ch2:1;
-        /** inlink_park_ch2 : RO; bitpos: [24]; default: 1;
-         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
-         *  working.
+        uint32_t outfifo_udf_l1_int_ena:1;
+        /** outfifo_ovf_l2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t inlink_park_ch2:1;
-        uint32_t reserved_25:7;
+        uint32_t outfifo_ovf_l2_int_ena:1;
+        /** outfifo_udf_l2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_int_ena:1;
+        /** dscr_task_ovf_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t dscr_task_ovf_int_ena:1;
+        uint32_t reserved_9:23;
     };
     uint32_t val;
-} h264_dma_in_link_conf_ch2_reg_t;
+} h264_dma_out_int_ena_chn_reg_t;
 
-/** Type of in_conf0_ch3 register
- *  RX CH3 config0 register
+/** Type of out_int_st register
+ *  TX CHn  interrupt st register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:2;
-        /** indscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
-         *  when accessing SRAM.
+        /** done_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t indscr_burst_en_ch3:1;
-        /** in_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
+        uint32_t done_int_st:1;
+        /** eof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t in_ecc_aes_en_ch3:1;
-        /** in_check_owner_ch3 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
+        uint32_t eof_int_st:1;
+        /** dscr_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_check_owner_ch3:1;
-        uint32_t reserved_5:1;
-        /** in_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
+        uint32_t dscr_err_int_st:1;
+        /** total_eof_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
          */
-        uint32_t in_mem_burst_length_ch3:3;
-        uint32_t reserved_9:3;
-        /** in_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
-         *  which define by mem_burst_length
+        uint32_t total_eof_int_st:1;
+        /** outfifo_ovf_l1_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t in_page_bound_en_ch3:1;
-        uint32_t reserved_13:11;
-        /** in_rst_ch3 : R/W; bitpos: [24]; default: 0;
-         *  Write 1 then write 0 to this bit to reset Rx channel
+        uint32_t outfifo_ovf_l1_int_st:1;
+        /** outfifo_udf_l1_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t in_rst_ch3:1;
-        /** in_cmd_disable_ch3 : R/W; bitpos: [25]; default: 0;
-         *  Write 1 before reset and write 0 after reset
+        uint32_t outfifo_udf_l1_int_st:1;
+        /** outfifo_ovf_l2_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t in_cmd_disable_ch3:1;
-        /** in_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
+        uint32_t outfifo_ovf_l2_int_st:1;
+        /** outfifo_udf_l2_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t in_arb_weight_opt_dis_ch3:1;
-        uint32_t reserved_27:5;
+        uint32_t outfifo_udf_l2_int_st:1;
+        /** dscr_task_ovf_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t dscr_task_ovf_int_st:1;
+        uint32_t reserved_9:23;
     };
     uint32_t val;
-} h264_dma_in_conf0_ch3_reg_t;
+} h264_dma_out_int_st_chn_reg_t;
 
-/** Type of in_pop_ch3 register
- *  RX CH3 INFIFO pop register
+/** Type of out_int_clr register
+ *  TX CHn  interrupt clr register
  */
 typedef union {
     struct {
-        /** infifo_rdata_ch3 : RO; bitpos: [10:0]; default: 1024;
-         *  This register stores the data popping from DMA Rx FIFO.
+        /** done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
          */
-        uint32_t infifo_rdata_ch3:11;
-        /** infifo_pop_ch3 : R/W/SC; bitpos: [11]; default: 0;
-         *  Set this bit to pop data from DMA Rx FIFO.
+        uint32_t done_int_clr:1;
+        /** eof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
          */
-        uint32_t infifo_pop_ch3:1;
-        uint32_t reserved_12:20;
+        uint32_t eof_int_clr:1;
+        /** dscr_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t dscr_err_int_clr:1;
+        /** total_eof_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t total_eof_int_clr:1;
+        /** outfifo_ovf_l1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_int_clr:1;
+        /** outfifo_udf_l1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_int_clr:1;
+        /** outfifo_ovf_l2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_int_clr:1;
+        /** outfifo_udf_l2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_int_clr:1;
+        /** dscr_task_ovf_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t dscr_task_ovf_int_clr:1;
+        uint32_t reserved_9:23;
     };
     uint32_t val;
-} h264_dma_in_pop_ch3_reg_t;
+} h264_dma_out_int_clr_chn_reg_t;
+
 
-/** Type of in_link_conf_ch3 register
- *  RX CH3 in_link dscr ctrl register
+/** Type of in_int_raw register
+ *  RX CH0  interrupt raw register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:20;
-        /** inlink_auto_ret_ch3 : R/W; bitpos: [20]; default: 1;
-         *  Set this bit to return to current inlink descriptor's address, when there are some
-         *  errors in current receiving data.
+        /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
          */
-        uint32_t inlink_auto_ret_ch3:1;
-        /** inlink_stop_ch3 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to stop dealing with the inlink descriptors.
+        uint32_t in_done_int_raw:1;
+        /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
          */
-        uint32_t inlink_stop_ch3:1;
-        /** inlink_start_ch3 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to start dealing with the inlink descriptors.
+        uint32_t in_suc_eof_int_raw:1;
+        /** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
          */
-        uint32_t inlink_start_ch3:1;
-        /** inlink_restart_ch3 : R/W/SC; bitpos: [23]; default: 0;
-         *  Set this bit to mount a new inlink descriptor.
+        uint32_t in_err_eof_int_raw:1;
+        /** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
          */
-        uint32_t inlink_restart_ch3:1;
-        /** inlink_park_ch3 : RO; bitpos: [24]; default: 1;
-         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
-         *  working.
+        uint32_t in_dscr_err_int_raw:1;
+        /** infifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
          */
-        uint32_t inlink_park_ch3:1;
-        uint32_t reserved_25:7;
+        uint32_t infifo_ovf_l1_int_raw:1;
+        /** infifo_udf_l1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_int_raw:1;
+        /** infifo_ovf_l2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_int_raw:1;
+        /** infifo_udf_l2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_int_raw:1;
+        /** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_int_raw:1;
+        /** in_dscr_task_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_int_raw:1;
+        uint32_t reserved_10:22;
     };
     uint32_t val;
-} h264_dma_in_link_conf_ch3_reg_t;
+} h264_dma_in_int_raw_chn_reg_t;
 
-/** Type of in_conf0_ch4 register
- *  RX CH4 config0 register
+/** Type of in_int_ena register
+ *  RX CH0  interrupt ena register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:2;
-        /** indscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
-         *  when accessing SRAM.
+        /** in_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t indscr_burst_en_ch4:1;
-        /** in_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
+        uint32_t in_done_int_ena:1;
+        /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t in_ecc_aes_en_ch4:1;
-        /** in_check_owner_ch4 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
+        uint32_t in_suc_eof_int_ena:1;
+        /** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t in_check_owner_ch4:1;
-        uint32_t reserved_5:1;
-        /** in_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
+        uint32_t in_err_eof_int_ena:1;
+        /** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
          */
-        uint32_t in_mem_burst_length_ch4:3;
-        uint32_t reserved_9:3;
-        /** in_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
-         *  which define by mem_burst_length
+        uint32_t in_dscr_err_int_ena:1;
+        /** infifo_ovf_l1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t in_page_bound_en_ch4:1;
-        uint32_t reserved_13:11;
-        /** in_rst_ch4 : R/W; bitpos: [24]; default: 0;
-         *  Write 1 then write 0 to this bit to reset Rx channel
+        uint32_t infifo_ovf_l1_int_ena:1;
+        /** infifo_udf_l1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t in_rst_ch4:1;
-        /** in_cmd_disable_ch4 : R/W; bitpos: [25]; default: 0;
-         *  Write 1 before reset and write 0 after reset
+        uint32_t infifo_udf_l1_int_ena:1;
+        /** infifo_ovf_l2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
          */
-        uint32_t in_cmd_disable_ch4:1;
-        /** in_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
+        uint32_t infifo_ovf_l2_int_ena:1;
+        /** infifo_udf_l2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
          */
-        uint32_t in_arb_weight_opt_dis_ch4:1;
-        uint32_t reserved_27:5;
+        uint32_t infifo_udf_l2_int_ena:1;
+        /** in_dscr_empty_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_int_ena:1;
+        /** in_dscr_task_ovf_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_int_ena:1;
+        uint32_t reserved_10:22;
     };
     uint32_t val;
-} h264_dma_in_conf0_ch4_reg_t;
+} h264_dma_in_int_ena_chn_reg_t;
 
-/** Type of in_pop_ch4 register
- *  RX CH4 INFIFO pop register
+/** Type of in_int_st register
+ *  RX CH0  interrupt st register
  */
 typedef union {
     struct {
-        /** infifo_rdata_ch4 : RO; bitpos: [10:0]; default: 1024;
-         *  This register stores the data popping from DMA Rx FIFO.
+        /** in_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t infifo_rdata_ch4:11;
-        /** infifo_pop_ch4 : R/W/SC; bitpos: [11]; default: 0;
-         *  Set this bit to pop data from DMA Rx FIFO.
+        uint32_t in_done_int_st:1;
+        /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t infifo_pop_ch4:1;
-        uint32_t reserved_12:20;
+        uint32_t in_suc_eof_int_st:1;
+        /** in_err_eof_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_int_st:1;
+        /** in_dscr_err_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_int_st:1;
+        /** infifo_ovf_l1_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_int_st:1;
+        /** infifo_udf_l1_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_int_st:1;
+        /** infifo_ovf_l2_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_int_st:1;
+        /** infifo_udf_l2_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_int_st:1;
+        /** in_dscr_empty_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_int_st:1;
+        /** in_dscr_task_ovf_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_int_st:1;
+        uint32_t reserved_10:22;
     };
     uint32_t val;
-} h264_dma_in_pop_ch4_reg_t;
+} h264_dma_in_int_st_chn_reg_t;
 
-/** Type of in_link_conf_ch4 register
- *  RX CH4 in_link dscr ctrl register
+/** Type of in_int_clr register
+ *  RX CH0  interrupt clr register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:20;
-        /** inlink_auto_ret_ch4 : R/W; bitpos: [20]; default: 1;
-         *  Set this bit to return to current inlink descriptor's address, when there are some
-         *  errors in current receiving data.
+        /** in_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
          */
-        uint32_t inlink_auto_ret_ch4:1;
-        /** inlink_stop_ch4 : R/W/SC; bitpos: [21]; default: 0;
-         *  Set this bit to stop dealing with the inlink descriptors.
+        uint32_t in_done_int_clr:1;
+        /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t inlink_stop_ch4:1;
-        /** inlink_start_ch4 : R/W/SC; bitpos: [22]; default: 0;
-         *  Set this bit to start dealing with the inlink descriptors.
+        uint32_t in_suc_eof_int_clr:1;
+        /** in_err_eof_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
          */
-        uint32_t inlink_start_ch4:1;
-        /** inlink_restart_ch4 : R/W/SC; bitpos: [23]; default: 0;
-         *  Set this bit to mount a new inlink descriptor.
+        uint32_t in_err_eof_int_clr:1;
+        /** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
          */
-        uint32_t inlink_restart_ch4:1;
-        /** inlink_park_ch4 : RO; bitpos: [24]; default: 1;
-         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
-         *  working.
+        uint32_t in_dscr_err_int_clr:1;
+        /** infifo_ovf_l1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t inlink_park_ch4:1;
-        uint32_t reserved_25:7;
+        uint32_t infifo_ovf_l1_int_clr:1;
+        /** infifo_udf_l1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_int_clr:1;
+        /** infifo_ovf_l2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_int_clr:1;
+        /** infifo_udf_l2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_int_clr:1;
+        /** in_dscr_empty_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_int_clr:1;
+        /** in_dscr_task_ovf_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_int_clr:1;
+        uint32_t reserved_10:22;
     };
     uint32_t val;
-} h264_dma_in_link_conf_ch4_reg_t;
+} h264_dma_in_int_clr_chn_reg_t;
 
-/** Type of in_conf0_ch5 register
- *  RX CH5 config0 register
+
+/** Type of in_int_raw_ch5 register
+ *  RX CH5  interrupt raw register
  */
 typedef union {
     struct {
-        uint32_t reserved_0:3;
-        /** in_ecc_aes_en_ch5 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
+        /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
          */
-        uint32_t in_ecc_aes_en_ch5:1;
-        uint32_t reserved_4:2;
-        /** in_mem_burst_length_ch5 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
+        uint32_t in_done_int_raw:1;
+        /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
          */
-        uint32_t in_mem_burst_length_ch5:3;
-        uint32_t reserved_9:3;
-        /** in_page_bound_en_ch5 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
-         *  which define by mem_burst_length
+        uint32_t in_suc_eof_int_raw:1;
+        /** infifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
          */
-        uint32_t in_page_bound_en_ch5:1;
-        uint32_t reserved_13:11;
-        /** in_rst_ch5 : R/W; bitpos: [24]; default: 0;
-         *  Write 1 then write 0 to this bit to reset Rx channel
+        uint32_t infifo_ovf_l1_int_raw:1;
+        /** infifo_udf_l1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
          */
-        uint32_t in_rst_ch5:1;
-        /** in_cmd_disable_ch5 : R/W; bitpos: [25]; default: 0;
-         *  Write 1 before reset and write 0 after reset
+        uint32_t infifo_udf_l1_int_raw:1;
+        /** fetch_mb_col_cnt_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
          */
-        uint32_t in_cmd_disable_ch5:1;
-        uint32_t reserved_26:6;
+        uint32_t fetch_mb_col_cnt_ovf_int_raw:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
-} h264_dma_in_conf0_ch5_reg_t;
+} h264_dma_in_int_raw_ch5_reg_t;
 
-/** Type of in_pop_ch5 register
- *  RX CH5 INFIFO pop register
+/** Type of in_int_ena_ch5 register
+ *  RX CH5  interrupt ena register
  */
 typedef union {
     struct {
-        /** infifo_rdata_ch5 : RO; bitpos: [10:0]; default: 1024;
-         *  This register stores the data popping from DMA Rx FIFO.
+        /** in_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t infifo_rdata_ch5:11;
-        /** infifo_pop_ch5 : R/W/SC; bitpos: [11]; default: 0;
-         *  Set this bit to pop data from DMA Rx FIFO.
+        uint32_t in_done_int_ena:1;
+        /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t infifo_pop_ch5:1;
-        uint32_t reserved_12:20;
+        uint32_t in_suc_eof_int_ena:1;
+        /** infifo_ovf_l1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_int_ena:1;
+        /** infifo_udf_l1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_int_ena:1;
+        /** fetch_mb_col_cnt_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_int_ena:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
-} h264_dma_in_pop_ch5_reg_t;
+} h264_dma_in_int_ena_ch5_reg_t;
 
-/** Type of rst_conf register
- *  axi reset config register
+/** Type of in_int_st_ch5 register
+ *  RX CH5  interrupt st register
  */
 typedef union {
     struct {
-        /** inter_axim_rd_rst : R/W; bitpos: [0]; default: 0;
-         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+        /** in_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
          */
-        uint32_t inter_axim_rd_rst:1;
-        /** inter_axim_wr_rst : R/W; bitpos: [1]; default: 0;
-         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+        uint32_t in_done_int_st:1;
+        /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t inter_axim_wr_rst:1;
-        /** exter_axim_rd_rst : R/W; bitpos: [2]; default: 0;
-         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+        uint32_t in_suc_eof_int_st:1;
+        /** infifo_ovf_l1_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t exter_axim_rd_rst:1;
-        /** exter_axim_wr_rst : R/W; bitpos: [3]; default: 0;
-         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+        uint32_t infifo_ovf_l1_int_st:1;
+        /** infifo_udf_l1_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t exter_axim_wr_rst:1;
-        /** clk_en : R/W; bitpos: [4]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
+        uint32_t infifo_udf_l1_int_st:1;
+        /** fetch_mb_col_cnt_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t clk_en:1;
+        uint32_t fetch_mb_col_cnt_ovf_int_st:1;
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} h264_dma_rst_conf_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of out_int_raw_ch0 register
- *  TX CH0  interrupt raw register
- */
-typedef union {
-    struct {
-        /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been transmitted to peripherals for Tx channel 0.
-         */
-        uint32_t out_done_ch0_int_raw:1;
-        /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been read from memory for Tx channel 0.
-         */
-        uint32_t out_eof_ch0_int_raw:1;
-        /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
-         *  including owner error, the second and third word error of outlink descriptor for Tx
-         *  channel 0.
-         */
-        uint32_t out_dscr_err_ch0_int_raw:1;
-        /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when data corresponding a outlink
-         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
-         *  channel 0.
-         */
-        uint32_t out_total_eof_ch0_int_raw:1;
-        /** outfifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l1_ch0_int_raw:1;
-        /** outfifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l1_ch0_int_raw:1;
-        /** outfifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l2_ch0_int_raw:1;
-        /** outfifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l2_ch0_int_raw:1;
-        /** out_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t out_dscr_task_ovf_ch0_int_raw:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_raw_ch0_reg_t;
-
-/** Type of out_int_ena_ch0 register
- *  TX CH0  interrupt ena register
- */
-typedef union {
-    struct {
-        /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch0_int_ena:1;
-        /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch0_int_ena:1;
-        /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch0_int_ena:1;
-        /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch0_int_ena:1;
-        /** outfifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch0_int_ena:1;
-        /** outfifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch0_int_ena:1;
-        /** outfifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch0_int_ena:1;
-        /** outfifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch0_int_ena:1;
-        /** out_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch0_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_ena_ch0_reg_t;
-
-/** Type of out_int_st_ch0 register
- *  TX CH0  interrupt st register
- */
-typedef union {
-    struct {
-        /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch0_int_st:1;
-        /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch0_int_st:1;
-        /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch0_int_st:1;
-        /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch0_int_st:1;
-        /** outfifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch0_int_st:1;
-        /** outfifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch0_int_st:1;
-        /** outfifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch0_int_st:1;
-        /** outfifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch0_int_st:1;
-        /** out_dscr_task_ovf_ch0_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch0_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_st_ch0_reg_t;
-
-/** Type of out_int_clr_ch0 register
- *  TX CH0  interrupt clr register
- */
-typedef union {
-    struct {
-        /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch0_int_clr:1;
-        /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch0_int_clr:1;
-        /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch0_int_clr:1;
-        /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch0_int_clr:1;
-        /** outfifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch0_int_clr:1;
-        /** outfifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch0_int_clr:1;
-        /** outfifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch0_int_clr:1;
-        /** outfifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch0_int_clr:1;
-        /** out_dscr_task_ovf_ch0_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch0_int_clr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_clr_ch0_reg_t;
-
-/** Type of out_int_raw_ch1 register
- *  TX CH1  interrupt raw register
- */
-typedef union {
-    struct {
-        /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been transmitted to peripherals for Tx channel 0.
-         */
-        uint32_t out_done_ch1_int_raw:1;
-        /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been read from memory for Tx channel 0.
-         */
-        uint32_t out_eof_ch1_int_raw:1;
-        /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
-         *  including owner error, the second and third word error of outlink descriptor for Tx
-         *  channel 0.
-         */
-        uint32_t out_dscr_err_ch1_int_raw:1;
-        /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when data corresponding a outlink
-         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
-         *  channel 0.
-         */
-        uint32_t out_total_eof_ch1_int_raw:1;
-        /** outfifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l1_ch1_int_raw:1;
-        /** outfifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l1_ch1_int_raw:1;
-        /** outfifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l2_ch1_int_raw:1;
-        /** outfifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l2_ch1_int_raw:1;
-        /** out_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t out_dscr_task_ovf_ch1_int_raw:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_raw_ch1_reg_t;
-
-/** Type of out_int_ena_ch1 register
- *  TX CH1  interrupt ena register
- */
-typedef union {
-    struct {
-        /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch1_int_ena:1;
-        /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch1_int_ena:1;
-        /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch1_int_ena:1;
-        /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch1_int_ena:1;
-        /** outfifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch1_int_ena:1;
-        /** outfifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch1_int_ena:1;
-        /** outfifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch1_int_ena:1;
-        /** outfifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch1_int_ena:1;
-        /** out_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch1_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_ena_ch1_reg_t;
-
-/** Type of out_int_st_ch1 register
- *  TX CH1  interrupt st register
- */
-typedef union {
-    struct {
-        /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch1_int_st:1;
-        /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch1_int_st:1;
-        /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch1_int_st:1;
-        /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch1_int_st:1;
-        /** outfifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch1_int_st:1;
-        /** outfifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch1_int_st:1;
-        /** outfifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch1_int_st:1;
-        /** outfifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch1_int_st:1;
-        /** out_dscr_task_ovf_ch1_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch1_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_st_ch1_reg_t;
-
-/** Type of out_int_clr_ch1 register
- *  TX CH1  interrupt clr register
- */
-typedef union {
-    struct {
-        /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch1_int_clr:1;
-        /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch1_int_clr:1;
-        /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch1_int_clr:1;
-        /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch1_int_clr:1;
-        /** outfifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch1_int_clr:1;
-        /** outfifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch1_int_clr:1;
-        /** outfifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch1_int_clr:1;
-        /** outfifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch1_int_clr:1;
-        /** out_dscr_task_ovf_ch1_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch1_int_clr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_clr_ch1_reg_t;
-
-/** Type of out_int_raw_ch2 register
- *  TX CH2  interrupt raw register
- */
-typedef union {
-    struct {
-        /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been transmitted to peripherals for Tx channel 0.
-         */
-        uint32_t out_done_ch2_int_raw:1;
-        /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been read from memory for Tx channel 0.
-         */
-        uint32_t out_eof_ch2_int_raw:1;
-        /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
-         *  including owner error, the second and third word error of outlink descriptor for Tx
-         *  channel 0.
-         */
-        uint32_t out_dscr_err_ch2_int_raw:1;
-        /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when data corresponding a outlink
-         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
-         *  channel 0.
-         */
-        uint32_t out_total_eof_ch2_int_raw:1;
-        /** outfifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l1_ch2_int_raw:1;
-        /** outfifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l1_ch2_int_raw:1;
-        /** outfifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l2_ch2_int_raw:1;
-        /** outfifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l2_ch2_int_raw:1;
-        /** out_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t out_dscr_task_ovf_ch2_int_raw:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_raw_ch2_reg_t;
-
-/** Type of out_int_ena_ch2 register
- *  TX CH2  interrupt ena register
- */
-typedef union {
-    struct {
-        /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch2_int_ena:1;
-        /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch2_int_ena:1;
-        /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch2_int_ena:1;
-        /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch2_int_ena:1;
-        /** outfifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch2_int_ena:1;
-        /** outfifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch2_int_ena:1;
-        /** outfifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch2_int_ena:1;
-        /** outfifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch2_int_ena:1;
-        /** out_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch2_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_ena_ch2_reg_t;
-
-/** Type of out_int_st_ch2 register
- *  TX CH2  interrupt st register
- */
-typedef union {
-    struct {
-        /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch2_int_st:1;
-        /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch2_int_st:1;
-        /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch2_int_st:1;
-        /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch2_int_st:1;
-        /** outfifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch2_int_st:1;
-        /** outfifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch2_int_st:1;
-        /** outfifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch2_int_st:1;
-        /** outfifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch2_int_st:1;
-        /** out_dscr_task_ovf_ch2_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch2_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_st_ch2_reg_t;
-
-/** Type of out_int_clr_ch2 register
- *  TX CH2  interrupt clr register
- */
-typedef union {
-    struct {
-        /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch2_int_clr:1;
-        /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch2_int_clr:1;
-        /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch2_int_clr:1;
-        /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch2_int_clr:1;
-        /** outfifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch2_int_clr:1;
-        /** outfifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch2_int_clr:1;
-        /** outfifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch2_int_clr:1;
-        /** outfifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch2_int_clr:1;
-        /** out_dscr_task_ovf_ch2_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch2_int_clr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_clr_ch2_reg_t;
-
-/** Type of out_int_raw_ch3 register
- *  TX CH3  interrupt raw register
- */
-typedef union {
-    struct {
-        /** out_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been transmitted to peripherals for Tx channel 0.
-         */
-        uint32_t out_done_ch3_int_raw:1;
-        /** out_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been read from memory for Tx channel 0.
-         */
-        uint32_t out_eof_ch3_int_raw:1;
-        /** out_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
-         *  including owner error, the second and third word error of outlink descriptor for Tx
-         *  channel 0.
-         */
-        uint32_t out_dscr_err_ch3_int_raw:1;
-        /** out_total_eof_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when data corresponding a outlink
-         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
-         *  channel 0.
-         */
-        uint32_t out_total_eof_ch3_int_raw:1;
-        /** outfifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l1_ch3_int_raw:1;
-        /** outfifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l1_ch3_int_raw:1;
-        /** outfifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l2_ch3_int_raw:1;
-        /** outfifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l2_ch3_int_raw:1;
-        /** out_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t out_dscr_task_ovf_ch3_int_raw:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_raw_ch3_reg_t;
-
-/** Type of out_int_ena_ch3 register
- *  TX CH3  interrupt ena register
- */
-typedef union {
-    struct {
-        /** out_done_ch3_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch3_int_ena:1;
-        /** out_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch3_int_ena:1;
-        /** out_dscr_err_ch3_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch3_int_ena:1;
-        /** out_total_eof_ch3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch3_int_ena:1;
-        /** outfifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch3_int_ena:1;
-        /** outfifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch3_int_ena:1;
-        /** outfifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch3_int_ena:1;
-        /** outfifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch3_int_ena:1;
-        /** out_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch3_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_ena_ch3_reg_t;
-
-/** Type of out_int_st_ch3 register
- *  TX CH3  interrupt st register
- */
-typedef union {
-    struct {
-        /** out_done_ch3_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch3_int_st:1;
-        /** out_eof_ch3_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch3_int_st:1;
-        /** out_dscr_err_ch3_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch3_int_st:1;
-        /** out_total_eof_ch3_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch3_int_st:1;
-        /** outfifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch3_int_st:1;
-        /** outfifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch3_int_st:1;
-        /** outfifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch3_int_st:1;
-        /** outfifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch3_int_st:1;
-        /** out_dscr_task_ovf_ch3_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch3_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_st_ch3_reg_t;
-
-/** Type of out_int_clr_ch3 register
- *  TX CH3  interrupt clr register
- */
-typedef union {
-    struct {
-        /** out_done_ch3_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch3_int_clr:1;
-        /** out_eof_ch3_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch3_int_clr:1;
-        /** out_dscr_err_ch3_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch3_int_clr:1;
-        /** out_total_eof_ch3_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch3_int_clr:1;
-        /** outfifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch3_int_clr:1;
-        /** outfifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch3_int_clr:1;
-        /** outfifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch3_int_clr:1;
-        /** outfifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch3_int_clr:1;
-        /** out_dscr_task_ovf_ch3_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch3_int_clr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_clr_ch3_reg_t;
-
-/** Type of out_int_raw_ch4 register
- *  TX CH4  interrupt raw register
- */
-typedef union {
-    struct {
-        /** out_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been transmitted to peripherals for Tx channel 0.
-         */
-        uint32_t out_done_ch4_int_raw:1;
-        /** out_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been read from memory for Tx channel 0.
-         */
-        uint32_t out_eof_ch4_int_raw:1;
-        /** out_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
-         *  including owner error, the second and third word error of outlink descriptor for Tx
-         *  channel 0.
-         */
-        uint32_t out_dscr_err_ch4_int_raw:1;
-        /** out_total_eof_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when data corresponding a outlink
-         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
-         *  channel 0.
-         */
-        uint32_t out_total_eof_ch4_int_raw:1;
-        /** outfifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l1_ch4_int_raw:1;
-        /** outfifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l1_ch4_int_raw:1;
-        /** outfifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is overflow.
-         */
-        uint32_t outfifo_ovf_l2_ch4_int_raw:1;
-        /** outfifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo is underflow.
-         */
-        uint32_t outfifo_udf_l2_ch4_int_raw:1;
-        /** out_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t out_dscr_task_ovf_ch4_int_raw:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_raw_ch4_reg_t;
-
-/** Type of out_int_ena_ch4 register
- *  TX CH4  interrupt ena register
- */
-typedef union {
-    struct {
-        /** out_done_ch4_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch4_int_ena:1;
-        /** out_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch4_int_ena:1;
-        /** out_dscr_err_ch4_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch4_int_ena:1;
-        /** out_total_eof_ch4_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch4_int_ena:1;
-        /** outfifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch4_int_ena:1;
-        /** outfifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch4_int_ena:1;
-        /** outfifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch4_int_ena:1;
-        /** outfifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch4_int_ena:1;
-        /** out_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch4_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_ena_ch4_reg_t;
-
-/** Type of out_int_st_ch4 register
- *  TX CH4  interrupt st register
- */
-typedef union {
-    struct {
-        /** out_done_ch4_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch4_int_st:1;
-        /** out_eof_ch4_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch4_int_st:1;
-        /** out_dscr_err_ch4_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch4_int_st:1;
-        /** out_total_eof_ch4_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch4_int_st:1;
-        /** outfifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch4_int_st:1;
-        /** outfifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch4_int_st:1;
-        /** outfifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch4_int_st:1;
-        /** outfifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch4_int_st:1;
-        /** out_dscr_task_ovf_ch4_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch4_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_st_ch4_reg_t;
-
-/** Type of out_int_clr_ch4 register
- *  TX CH4  interrupt clr register
- */
-typedef union {
-    struct {
-        /** out_done_ch4_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_ch4_int_clr:1;
-        /** out_eof_ch4_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_ch4_int_clr:1;
-        /** out_dscr_err_ch4_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_ch4_int_clr:1;
-        /** out_total_eof_ch4_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_ch4_int_clr:1;
-        /** outfifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l1_ch4_int_clr:1;
-        /** outfifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l1_ch4_int_clr:1;
-        /** outfifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_l2_ch4_int_clr:1;
-        /** outfifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_l2_ch4_int_clr:1;
-        /** out_dscr_task_ovf_ch4_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t out_dscr_task_ovf_ch4_int_clr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} h264_dma_out_int_clr_ch4_reg_t;
-
-/** Type of in_int_raw_ch0 register
- *  RX CH0  interrupt raw register
- */
-typedef union {
-    struct {
-        /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been transmitted to peripherals for Rx channel 0.
-         */
-        uint32_t in_done_ch0_int_raw:1;
-        /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and no data error is detected for Rx channel 0.
-         */
-        uint32_t in_suc_eof_ch0_int_raw:1;
-        /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and data error is detected
-         */
-        uint32_t in_err_eof_ch0_int_raw:1;
-        /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
-         *  including owner error, the second and third word error of inlink descriptor for Rx
-         *  channel 0.
-         */
-        uint32_t in_dscr_err_ch0_int_raw:1;
-        /** infifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l1_ch0_int_raw:1;
-        /** infifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l1_ch0_int_raw:1;
-        /** infifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l2_ch0_int_raw:1;
-        /** infifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l2_ch0_int_raw:1;
-        /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
-         *  also remain data.
-         */
-        uint32_t in_dscr_empty_ch0_int_raw:1;
-        /** in_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t in_dscr_task_ovf_ch0_int_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_raw_ch0_reg_t;
-
-/** Type of in_int_ena_ch0 register
- *  RX CH0  interrupt ena register
- */
-typedef union {
-    struct {
-        /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch0_int_ena:1;
-        /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch0_int_ena:1;
-        /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch0_int_ena:1;
-        /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch0_int_ena:1;
-        /** infifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch0_int_ena:1;
-        /** infifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch0_int_ena:1;
-        /** infifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch0_int_ena:1;
-        /** infifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch0_int_ena:1;
-        /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch0_int_ena:1;
-        /** in_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch0_int_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_ena_ch0_reg_t;
-
-/** Type of in_int_st_ch0 register
- *  RX CH0  interrupt st register
- */
-typedef union {
-    struct {
-        /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch0_int_st:1;
-        /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch0_int_st:1;
-        /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch0_int_st:1;
-        /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch0_int_st:1;
-        /** infifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch0_int_st:1;
-        /** infifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch0_int_st:1;
-        /** infifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch0_int_st:1;
-        /** infifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch0_int_st:1;
-        /** in_dscr_empty_ch0_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch0_int_st:1;
-        /** in_dscr_task_ovf_ch0_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch0_int_st:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_st_ch0_reg_t;
-
-/** Type of in_int_clr_ch0 register
- *  RX CH0  interrupt clr register
- */
-typedef union {
-    struct {
-        /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch0_int_clr:1;
-        /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch0_int_clr:1;
-        /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch0_int_clr:1;
-        /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch0_int_clr:1;
-        /** infifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch0_int_clr:1;
-        /** infifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch0_int_clr:1;
-        /** infifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch0_int_clr:1;
-        /** infifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch0_int_clr:1;
-        /** in_dscr_empty_ch0_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch0_int_clr:1;
-        /** in_dscr_task_ovf_ch0_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch0_int_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_clr_ch0_reg_t;
-
-/** Type of in_int_raw_ch1 register
- *  RX CH1  interrupt raw register
- */
-typedef union {
-    struct {
-        /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been transmitted to peripherals for Rx channel 1.
-         */
-        uint32_t in_done_ch1_int_raw:1;
-        /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and no data error is detected for Rx channel 1.
-         */
-        uint32_t in_suc_eof_ch1_int_raw:1;
-        /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and data error is detected
-         */
-        uint32_t in_err_eof_ch1_int_raw:1;
-        /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
-         *  including owner error, the second and third word error of inlink descriptor for Rx
-         *  channel 1.
-         */
-        uint32_t in_dscr_err_ch1_int_raw:1;
-        /** infifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l1_ch1_int_raw:1;
-        /** infifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l1_ch1_int_raw:1;
-        /** infifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l2_ch1_int_raw:1;
-        /** infifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l2_ch1_int_raw:1;
-        /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
-         *  also remain data.
-         */
-        uint32_t in_dscr_empty_ch1_int_raw:1;
-        /** in_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t in_dscr_task_ovf_ch1_int_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_raw_ch1_reg_t;
-
-/** Type of in_int_ena_ch1 register
- *  RX CH1  interrupt ena register
- */
-typedef union {
-    struct {
-        /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch1_int_ena:1;
-        /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch1_int_ena:1;
-        /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch1_int_ena:1;
-        /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch1_int_ena:1;
-        /** infifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch1_int_ena:1;
-        /** infifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch1_int_ena:1;
-        /** infifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch1_int_ena:1;
-        /** infifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch1_int_ena:1;
-        /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch1_int_ena:1;
-        /** in_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch1_int_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_ena_ch1_reg_t;
-
-/** Type of in_int_st_ch1 register
- *  RX CH1  interrupt st register
- */
-typedef union {
-    struct {
-        /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch1_int_st:1;
-        /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch1_int_st:1;
-        /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch1_int_st:1;
-        /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch1_int_st:1;
-        /** infifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch1_int_st:1;
-        /** infifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch1_int_st:1;
-        /** infifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch1_int_st:1;
-        /** infifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch1_int_st:1;
-        /** in_dscr_empty_ch1_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch1_int_st:1;
-        /** in_dscr_task_ovf_ch1_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch1_int_st:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_st_ch1_reg_t;
-
-/** Type of in_int_clr_ch1 register
- *  RX CH1  interrupt clr register
- */
-typedef union {
-    struct {
-        /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch1_int_clr:1;
-        /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch1_int_clr:1;
-        /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch1_int_clr:1;
-        /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch1_int_clr:1;
-        /** infifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch1_int_clr:1;
-        /** infifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch1_int_clr:1;
-        /** infifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch1_int_clr:1;
-        /** infifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch1_int_clr:1;
-        /** in_dscr_empty_ch1_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch1_int_clr:1;
-        /** in_dscr_task_ovf_ch1_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch1_int_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_clr_ch1_reg_t;
-
-/** Type of in_int_raw_ch2 register
- *  RX CH2  interrupt raw register
- */
-typedef union {
-    struct {
-        /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been transmitted to peripherals for Rx channel 1.
-         */
-        uint32_t in_done_ch2_int_raw:1;
-        /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and no data error is detected for Rx channel 1.
-         */
-        uint32_t in_suc_eof_ch2_int_raw:1;
-        /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and data error is detected
-         */
-        uint32_t in_err_eof_ch2_int_raw:1;
-        /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
-         *  including owner error, the second and third word error of inlink descriptor for Rx
-         *  channel 1.
-         */
-        uint32_t in_dscr_err_ch2_int_raw:1;
-        /** infifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l1_ch2_int_raw:1;
-        /** infifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l1_ch2_int_raw:1;
-        /** infifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l2_ch2_int_raw:1;
-        /** infifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l2_ch2_int_raw:1;
-        /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
-         *  also remain data.
-         */
-        uint32_t in_dscr_empty_ch2_int_raw:1;
-        /** in_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t in_dscr_task_ovf_ch2_int_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_raw_ch2_reg_t;
-
-/** Type of in_int_ena_ch2 register
- *  RX CH2  interrupt ena register
- */
-typedef union {
-    struct {
-        /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch2_int_ena:1;
-        /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch2_int_ena:1;
-        /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch2_int_ena:1;
-        /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch2_int_ena:1;
-        /** infifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch2_int_ena:1;
-        /** infifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch2_int_ena:1;
-        /** infifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch2_int_ena:1;
-        /** infifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch2_int_ena:1;
-        /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch2_int_ena:1;
-        /** in_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch2_int_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_ena_ch2_reg_t;
-
-/** Type of in_int_st_ch2 register
- *  RX CH2  interrupt st register
- */
-typedef union {
-    struct {
-        /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch2_int_st:1;
-        /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch2_int_st:1;
-        /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch2_int_st:1;
-        /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch2_int_st:1;
-        /** infifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch2_int_st:1;
-        /** infifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch2_int_st:1;
-        /** infifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch2_int_st:1;
-        /** infifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch2_int_st:1;
-        /** in_dscr_empty_ch2_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch2_int_st:1;
-        /** in_dscr_task_ovf_ch2_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch2_int_st:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_st_ch2_reg_t;
-
-/** Type of in_int_clr_ch2 register
- *  RX CH2  interrupt clr register
- */
-typedef union {
-    struct {
-        /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch2_int_clr:1;
-        /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch2_int_clr:1;
-        /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch2_int_clr:1;
-        /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch2_int_clr:1;
-        /** infifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch2_int_clr:1;
-        /** infifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch2_int_clr:1;
-        /** infifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch2_int_clr:1;
-        /** infifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch2_int_clr:1;
-        /** in_dscr_empty_ch2_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch2_int_clr:1;
-        /** in_dscr_task_ovf_ch2_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch2_int_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_clr_ch2_reg_t;
-
-/** Type of in_int_raw_ch3 register
- *  RX CH3  interrupt raw register
- */
-typedef union {
-    struct {
-        /** in_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been transmitted to peripherals for Rx channel 1.
-         */
-        uint32_t in_done_ch3_int_raw:1;
-        /** in_suc_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and no data error is detected for Rx channel 1.
-         */
-        uint32_t in_suc_eof_ch3_int_raw:1;
-        /** in_err_eof_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and data error is detected
-         */
-        uint32_t in_err_eof_ch3_int_raw:1;
-        /** in_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
-         *  including owner error, the second and third word error of inlink descriptor for Rx
-         *  channel 1.
-         */
-        uint32_t in_dscr_err_ch3_int_raw:1;
-        /** infifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l1_ch3_int_raw:1;
-        /** infifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l1_ch3_int_raw:1;
-        /** infifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l2_ch3_int_raw:1;
-        /** infifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l2_ch3_int_raw:1;
-        /** in_dscr_empty_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
-         *  also remain data.
-         */
-        uint32_t in_dscr_empty_ch3_int_raw:1;
-        /** in_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t in_dscr_task_ovf_ch3_int_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_raw_ch3_reg_t;
-
-/** Type of in_int_ena_ch3 register
- *  RX CH3  interrupt ena register
- */
-typedef union {
-    struct {
-        /** in_done_ch3_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch3_int_ena:1;
-        /** in_suc_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch3_int_ena:1;
-        /** in_err_eof_ch3_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch3_int_ena:1;
-        /** in_dscr_err_ch3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch3_int_ena:1;
-        /** infifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch3_int_ena:1;
-        /** infifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch3_int_ena:1;
-        /** infifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch3_int_ena:1;
-        /** infifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch3_int_ena:1;
-        /** in_dscr_empty_ch3_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch3_int_ena:1;
-        /** in_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch3_int_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_ena_ch3_reg_t;
-
-/** Type of in_int_st_ch3 register
- *  RX CH3  interrupt st register
- */
-typedef union {
-    struct {
-        /** in_done_ch3_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch3_int_st:1;
-        /** in_suc_eof_ch3_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch3_int_st:1;
-        /** in_err_eof_ch3_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch3_int_st:1;
-        /** in_dscr_err_ch3_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch3_int_st:1;
-        /** infifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch3_int_st:1;
-        /** infifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch3_int_st:1;
-        /** infifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch3_int_st:1;
-        /** infifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch3_int_st:1;
-        /** in_dscr_empty_ch3_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch3_int_st:1;
-        /** in_dscr_task_ovf_ch3_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch3_int_st:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_st_ch3_reg_t;
-
-/** Type of in_int_clr_ch3 register
- *  RX CH3  interrupt clr register
- */
-typedef union {
-    struct {
-        /** in_done_ch3_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch3_int_clr:1;
-        /** in_suc_eof_ch3_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch3_int_clr:1;
-        /** in_err_eof_ch3_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch3_int_clr:1;
-        /** in_dscr_err_ch3_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch3_int_clr:1;
-        /** infifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch3_int_clr:1;
-        /** infifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch3_int_clr:1;
-        /** infifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch3_int_clr:1;
-        /** infifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch3_int_clr:1;
-        /** in_dscr_empty_ch3_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch3_int_clr:1;
-        /** in_dscr_task_ovf_ch3_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch3_int_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_clr_ch3_reg_t;
-
-/** Type of in_int_raw_ch4 register
- *  RX CH4  interrupt raw register
- */
-typedef union {
-    struct {
-        /** in_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been transmitted to peripherals for Rx channel 1.
-         */
-        uint32_t in_done_ch4_int_raw:1;
-        /** in_suc_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and no data error is detected for Rx channel 1.
-         */
-        uint32_t in_suc_eof_ch4_int_raw:1;
-        /** in_err_eof_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and data error is detected
-         */
-        uint32_t in_err_eof_ch4_int_raw:1;
-        /** in_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
-         *  including owner error, the second and third word error of inlink descriptor for Rx
-         *  channel 1.
-         */
-        uint32_t in_dscr_err_ch4_int_raw:1;
-        /** infifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l1_ch4_int_raw:1;
-        /** infifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l1_ch4_int_raw:1;
-        /** infifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l2_ch4_int_raw:1;
-        /** infifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l2_ch4_int_raw:1;
-        /** in_dscr_empty_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
-         *  also remain data.
-         */
-        uint32_t in_dscr_empty_ch4_int_raw:1;
-        /** in_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
-         */
-        uint32_t in_dscr_task_ovf_ch4_int_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_raw_ch4_reg_t;
-
-/** Type of in_int_ena_ch4 register
- *  RX CH4  interrupt ena register
- */
-typedef union {
-    struct {
-        /** in_done_ch4_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch4_int_ena:1;
-        /** in_suc_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch4_int_ena:1;
-        /** in_err_eof_ch4_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch4_int_ena:1;
-        /** in_dscr_err_ch4_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch4_int_ena:1;
-        /** infifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch4_int_ena:1;
-        /** infifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch4_int_ena:1;
-        /** infifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch4_int_ena:1;
-        /** infifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch4_int_ena:1;
-        /** in_dscr_empty_ch4_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch4_int_ena:1;
-        /** in_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch4_int_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_ena_ch4_reg_t;
-
-/** Type of in_int_st_ch4 register
- *  RX CH4  interrupt st register
- */
-typedef union {
-    struct {
-        /** in_done_ch4_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch4_int_st:1;
-        /** in_suc_eof_ch4_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch4_int_st:1;
-        /** in_err_eof_ch4_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch4_int_st:1;
-        /** in_dscr_err_ch4_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch4_int_st:1;
-        /** infifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch4_int_st:1;
-        /** infifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch4_int_st:1;
-        /** infifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch4_int_st:1;
-        /** infifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch4_int_st:1;
-        /** in_dscr_empty_ch4_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch4_int_st:1;
-        /** in_dscr_task_ovf_ch4_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch4_int_st:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_st_ch4_reg_t;
-
-/** Type of in_int_clr_ch4 register
- *  RX CH4  interrupt clr register
- */
-typedef union {
-    struct {
-        /** in_done_ch4_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch4_int_clr:1;
-        /** in_suc_eof_ch4_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch4_int_clr:1;
-        /** in_err_eof_ch4_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_ch4_int_clr:1;
-        /** in_dscr_err_ch4_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_ch4_int_clr:1;
-        /** infifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch4_int_clr:1;
-        /** infifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch4_int_clr:1;
-        /** infifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l2_ch4_int_clr:1;
-        /** infifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l2_ch4_int_clr:1;
-        /** in_dscr_empty_ch4_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_ch4_int_clr:1;
-        /** in_dscr_task_ovf_ch4_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
-         */
-        uint32_t in_dscr_task_ovf_ch4_int_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_int_clr_ch4_reg_t;
-
-/** Type of in_int_raw_ch5 register
- *  RX CH5  interrupt raw register
- */
-typedef union {
-    struct {
-        /** in_done_ch5_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been transmitted to peripherals for Rx channel 1.
-         */
-        uint32_t in_done_ch5_int_raw:1;
-        /** in_suc_eof_ch5_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received and no data error is detected for Rx channel 1.
-         */
-        uint32_t in_suc_eof_ch5_int_raw:1;
-        /** infifo_ovf_l1_ch5_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
-         */
-        uint32_t infifo_ovf_l1_ch5_int_raw:1;
-        /** infifo_udf_l1_ch5_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t infifo_udf_l1_ch5_int_raw:1;
-        /** fetch_mb_col_cnt_ovf_ch5_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
-         */
-        uint32_t fetch_mb_col_cnt_ovf_ch5_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} h264_dma_in_int_raw_ch5_reg_t;
-
-/** Type of in_int_ena_ch5 register
- *  RX CH5  interrupt ena register
- */
-typedef union {
-    struct {
-        /** in_done_ch5_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch5_int_ena:1;
-        /** in_suc_eof_ch5_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch5_int_ena:1;
-        /** infifo_ovf_l1_ch5_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch5_int_ena:1;
-        /** infifo_udf_l1_ch5_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch5_int_ena:1;
-        /** fetch_mb_col_cnt_ovf_ch5_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t fetch_mb_col_cnt_ovf_ch5_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} h264_dma_in_int_ena_ch5_reg_t;
-
-/** Type of in_int_st_ch5 register
- *  RX CH5  interrupt st register
- */
-typedef union {
-    struct {
-        /** in_done_ch5_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch5_int_st:1;
-        /** in_suc_eof_ch5_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch5_int_st:1;
-        /** infifo_ovf_l1_ch5_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch5_int_st:1;
-        /** infifo_udf_l1_ch5_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch5_int_st:1;
-        /** fetch_mb_col_cnt_ovf_ch5_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t fetch_mb_col_cnt_ovf_ch5_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} h264_dma_in_int_st_ch5_reg_t;
-
-/** Type of in_int_clr_ch5 register
- *  RX CH5  interrupt clr register
- */
-typedef union {
-    struct {
-        /** in_done_ch5_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_ch5_int_clr:1;
-        /** in_suc_eof_ch5_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_ch5_int_clr:1;
-        /** infifo_ovf_l1_ch5_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_l1_ch5_int_clr:1;
-        /** infifo_udf_l1_ch5_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_l1_ch5_int_clr:1;
-        /** fetch_mb_col_cnt_ovf_ch5_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t fetch_mb_col_cnt_ovf_ch5_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} h264_dma_in_int_clr_ch5_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of outfifo_status_ch0 register
- *  TX CH0 outfifo status register
- */
-typedef union {
-    struct {
-        /** outfifo_full_l2_ch0 : RO; bitpos: [0]; default: 0;
-         *  Tx FIFO full signal for Tx channel 0.
-         */
-        uint32_t outfifo_full_l2_ch0:1;
-        /** outfifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 0.
-         */
-        uint32_t outfifo_empty_l2_ch0:1;
-        /** outfifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
-         */
-        uint32_t outfifo_cnt_l2_ch0:4;
-        /** outfifo_full_l1_ch0 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 0.
-         */
-        uint32_t outfifo_full_l1_ch0:1;
-        /** outfifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 0.
-         */
-        uint32_t outfifo_empty_l1_ch0:1;
-        /** outfifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
-         */
-        uint32_t outfifo_cnt_l1_ch0:5;
-        uint32_t reserved_13:3;
-        /** outfifo_full_l3_ch0 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 0.
-         */
-        uint32_t outfifo_full_l3_ch0:1;
-        /** outfifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 0.
-         */
-        uint32_t outfifo_empty_l3_ch0:1;
-        /** outfifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
-         */
-        uint32_t outfifo_cnt_l3_ch0:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_outfifo_status_ch0_reg_t;
-
-/** Type of out_state_ch0 register
- *  TX CH0 state register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current outlink descriptor's address.
-         */
-        uint32_t outlink_dscr_addr_ch0:18;
-        /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t out_dscr_state_ch0:2;
-        /** out_state_ch0 : RO; bitpos: [23:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t out_state_ch0:4;
-        /** out_reset_avail_ch0 : RO; bitpos: [24]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t out_reset_avail_ch0:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} h264_dma_out_state_ch0_reg_t;
-
-/** Type of out_eof_des_addr_ch0 register
- *  TX CH0 eof des addr register
- */
-typedef union {
-    struct {
-        /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the outlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t out_eof_des_addr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_out_eof_des_addr_ch0_reg_t;
-
-/** Type of out_dscr_ch0 register
- *  TX CH0 next dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next outlink descriptor address y.
-         */
-        uint32_t outlink_dscr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_ch0_reg_t;
-
-/** Type of out_dscr_bf0_ch0 register
- *  TX CH0 last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last outlink descriptor's next address y-1.
-         */
-        uint32_t outlink_dscr_bf0_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf0_ch0_reg_t;
-
-/** Type of out_dscr_bf1_ch0 register
- *  TX CH0 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last outlink descriptor's next address y-2.
-         */
-        uint32_t outlink_dscr_bf1_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf1_ch0_reg_t;
-
-/** Type of out_ro_status_ch0 register
- *  TX CH0 reorder status register
- */
-typedef union {
-    struct {
-        /** outfifo_ro_cnt_ch0 : RO; bitpos: [1:0]; default: 0;
-         *  The register stores the 8byte number of the data in reorder Tx FIFO for channel 0.
-         */
-        uint32_t outfifo_ro_cnt_ch0:2;
-        uint32_t reserved_2:4;
-        /** out_ro_wr_state_ch0 : RO; bitpos: [7:6]; default: 0;
-         *  The register stores the state of read ram of reorder
-         */
-        uint32_t out_ro_wr_state_ch0:2;
-        /** out_ro_rd_state_ch0 : RO; bitpos: [9:8]; default: 0;
-         *  The register stores the state of write ram of reorder
-         */
-        uint32_t out_ro_rd_state_ch0:2;
-        /** out_pixel_byte_ch0 : RO; bitpos: [13:10]; default: 2;
-         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
-         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
-         */
-        uint32_t out_pixel_byte_ch0:4;
-        /** out_burst_block_num_ch0 : RO; bitpos: [17:14]; default: 0;
-         *  the number of macro blocks contained in a burst of data at TX channel
-         */
-        uint32_t out_burst_block_num_ch0:4;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} h264_dma_out_ro_status_ch0_reg_t;
-
-/** Type of outfifo_status_ch1 register
- *  TX CH1 outfifo status register
- */
-typedef union {
-    struct {
-        /** outfifo_full_l2_ch1 : RO; bitpos: [0]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t outfifo_full_l2_ch1:1;
-        /** outfifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t outfifo_empty_l2_ch1:1;
-        /** outfifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t outfifo_cnt_l2_ch1:4;
-        /** outfifo_full_l1_ch1 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t outfifo_full_l1_ch1:1;
-        /** outfifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t outfifo_empty_l1_ch1:1;
-        /** outfifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t outfifo_cnt_l1_ch1:5;
-        uint32_t reserved_13:3;
-        /** outfifo_full_l3_ch1 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t outfifo_full_l3_ch1:1;
-        /** outfifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t outfifo_empty_l3_ch1:1;
-        /** outfifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t outfifo_cnt_l3_ch1:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_outfifo_status_ch1_reg_t;
-
-/** Type of out_state_ch1 register
- *  TX CH1 state register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current outlink descriptor's address.
-         */
-        uint32_t outlink_dscr_addr_ch1:18;
-        /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t out_dscr_state_ch1:2;
-        /** out_state_ch1 : RO; bitpos: [23:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t out_state_ch1:4;
-        /** out_reset_avail_ch1 : RO; bitpos: [24]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t out_reset_avail_ch1:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} h264_dma_out_state_ch1_reg_t;
-
-/** Type of out_eof_des_addr_ch1 register
- *  TX CH1 eof des addr register
- */
-typedef union {
-    struct {
-        /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the outlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t out_eof_des_addr_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_out_eof_des_addr_ch1_reg_t;
-
-/** Type of out_dscr_ch1 register
- *  TX CH1 next dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next outlink descriptor address y.
-         */
-        uint32_t outlink_dscr_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_ch1_reg_t;
-
-/** Type of out_dscr_bf0_ch1 register
- *  TX CH1 last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last outlink descriptor's next address y-1.
-         */
-        uint32_t outlink_dscr_bf0_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf0_ch1_reg_t;
-
-/** Type of out_dscr_bf1_ch1 register
- *  TX CH1 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last outlink descriptor's next address y-2.
-         */
-        uint32_t outlink_dscr_bf1_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf1_ch1_reg_t;
-
-/** Type of outfifo_status_ch2 register
- *  TX CH2 outfifo status register
- */
-typedef union {
-    struct {
-        /** outfifo_full_l2_ch2 : RO; bitpos: [0]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l2_ch2:1;
-        /** outfifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l2_ch2:1;
-        /** outfifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l2_ch2:4;
-        /** outfifo_full_l1_ch2 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l1_ch2:1;
-        /** outfifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l1_ch2:1;
-        /** outfifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l1_ch2:5;
-        uint32_t reserved_13:3;
-        /** outfifo_full_l3_ch2 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l3_ch2:1;
-        /** outfifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l3_ch2:1;
-        /** outfifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l3_ch2:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_outfifo_status_ch2_reg_t;
-
-/** Type of out_state_ch2 register
- *  TX CH2 state register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current outlink descriptor's address.
-         */
-        uint32_t outlink_dscr_addr_ch2:18;
-        /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t out_dscr_state_ch2:2;
-        /** out_state_ch2 : RO; bitpos: [23:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t out_state_ch2:4;
-        /** out_reset_avail_ch2 : RO; bitpos: [24]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t out_reset_avail_ch2:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} h264_dma_out_state_ch2_reg_t;
-
-/** Type of out_eof_des_addr_ch2 register
- *  TX CH2 eof des addr register
- */
-typedef union {
-    struct {
-        /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t out_eof_des_addr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_out_eof_des_addr_ch2_reg_t;
-
-/** Type of out_dscr_ch2 register
- *  TX CH2 next dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next outlink descriptor address y.
-         */
-        uint32_t outlink_dscr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_ch2_reg_t;
-
-/** Type of out_dscr_bf0_ch2 register
- *  TX CH2 last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last outlink descriptor's next address y-1.
-         */
-        uint32_t outlink_dscr_bf0_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf0_ch2_reg_t;
-
-/** Type of out_dscr_bf1_ch2 register
- *  TX CH2 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last outlink descriptor's next address y-2.
-         */
-        uint32_t outlink_dscr_bf1_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf1_ch2_reg_t;
-
-/** Type of outfifo_status_ch3 register
- *  TX CH3 outfifo status register
- */
-typedef union {
-    struct {
-        /** outfifo_full_l2_ch3 : RO; bitpos: [0]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l2_ch3:1;
-        /** outfifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l2_ch3:1;
-        /** outfifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l2_ch3:4;
-        /** outfifo_full_l1_ch3 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l1_ch3:1;
-        /** outfifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l1_ch3:1;
-        /** outfifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l1_ch3:5;
-        uint32_t reserved_13:3;
-        /** outfifo_full_l3_ch3 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l3_ch3:1;
-        /** outfifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l3_ch3:1;
-        /** outfifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l3_ch3:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_outfifo_status_ch3_reg_t;
-
-/** Type of out_state_ch3 register
- *  TX CH3 state register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current outlink descriptor's address.
-         */
-        uint32_t outlink_dscr_addr_ch3:18;
-        /** out_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t out_dscr_state_ch3:2;
-        /** out_state_ch3 : RO; bitpos: [23:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t out_state_ch3:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_out_state_ch3_reg_t;
-
-/** Type of out_eof_des_addr_ch3 register
- *  TX CH3 eof des addr register
- */
-typedef union {
-    struct {
-        /** out_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t out_eof_des_addr_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_out_eof_des_addr_ch3_reg_t;
-
-/** Type of out_dscr_ch3 register
- *  TX CH3 next dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next outlink descriptor address y.
-         */
-        uint32_t outlink_dscr_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_ch3_reg_t;
-
-/** Type of out_dscr_bf0_ch3 register
- *  TX CH3 last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last outlink descriptor's next address y-1.
-         */
-        uint32_t outlink_dscr_bf0_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf0_ch3_reg_t;
-
-/** Type of out_dscr_bf1_ch3 register
- *  TX CH3 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last outlink descriptor's next address y-2.
-         */
-        uint32_t outlink_dscr_bf1_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf1_ch3_reg_t;
-
-/** Type of outfifo_status_ch4 register
- *  TX CH4 outfifo status register
- */
-typedef union {
-    struct {
-        /** outfifo_full_l2_ch4 : RO; bitpos: [0]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l2_ch4:1;
-        /** outfifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l2_ch4:1;
-        /** outfifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l2_ch4:4;
-        /** outfifo_full_l1_ch4 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l1_ch4:1;
-        /** outfifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l1_ch4:1;
-        /** outfifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l1_ch4:5;
-        uint32_t reserved_13:3;
-        /** outfifo_full_l3_ch4 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 2.
-         */
-        uint32_t outfifo_full_l3_ch4:1;
-        /** outfifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 2.
-         */
-        uint32_t outfifo_empty_l3_ch4:1;
-        /** outfifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
-         */
-        uint32_t outfifo_cnt_l3_ch4:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_outfifo_status_ch4_reg_t;
-
-/** Type of out_state_ch4 register
- *  TX CH4 state register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current outlink descriptor's address.
-         */
-        uint32_t outlink_dscr_addr_ch4:18;
-        /** out_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t out_dscr_state_ch4:2;
-        /** out_state_ch4 : RO; bitpos: [23:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t out_state_ch4:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_out_state_ch4_reg_t;
-
-/** Type of out_eof_des_addr_ch4 register
- *  TX CH4 eof des addr register
- */
-typedef union {
-    struct {
-        /** out_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t out_eof_des_addr_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_out_eof_des_addr_ch4_reg_t;
-
-/** Type of out_dscr_ch4 register
- *  TX CH4 next dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next outlink descriptor address y.
-         */
-        uint32_t outlink_dscr_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_ch4_reg_t;
-
-/** Type of out_dscr_bf0_ch4 register
- *  TX CH4 last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last outlink descriptor's next address y-1.
-         */
-        uint32_t outlink_dscr_bf0_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf0_ch4_reg_t;
-
-/** Type of out_dscr_bf1_ch4 register
- *  TX CH4 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last outlink descriptor's next address y-2.
-         */
-        uint32_t outlink_dscr_bf1_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_out_dscr_bf1_ch4_reg_t;
-
-/** Type of infifo_status_ch0 register
- *  RX CH0 INFIFO status register
- */
-typedef union {
-    struct {
-        /** infifo_full_l2_ch0 : RO; bitpos: [0]; default: 0;
-         *  Rx FIFO full signal for Rx channel.
-         */
-        uint32_t infifo_full_l2_ch0:1;
-        /** infifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1;
-         *  Rx FIFO empty signal for Rx channel.
-         */
-        uint32_t infifo_empty_l2_ch0:1;
-        /** infifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
-         */
-        uint32_t infifo_cnt_l2_ch0:4;
-        /** infifo_full_l1_ch0 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 0.
-         */
-        uint32_t infifo_full_l1_ch0:1;
-        /** infifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 0.
-         */
-        uint32_t infifo_empty_l1_ch0:1;
-        /** infifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
-         */
-        uint32_t infifo_cnt_l1_ch0:5;
-        uint32_t reserved_13:3;
-        /** infifo_full_l3_ch0 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 0.
-         */
-        uint32_t infifo_full_l3_ch0:1;
-        /** infifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 0.
-         */
-        uint32_t infifo_empty_l3_ch0:1;
-        /** infifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
-         */
-        uint32_t infifo_cnt_l3_ch0:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_infifo_status_ch0_reg_t;
-
-/** Type of in_state_ch0 register
- *  RX CH0 state register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current inlink descriptor's address.
-         */
-        uint32_t inlink_dscr_addr_ch0:18;
-        /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t in_dscr_state_ch0:2;
-        /** in_state_ch0 : RO; bitpos: [22:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t in_state_ch0:3;
-        /** in_reset_avail_ch0 : RO; bitpos: [23]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t in_reset_avail_ch0:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_in_state_ch0_reg_t;
-
-/** Type of in_suc_eof_des_addr_ch0 register
- *  RX CH0 eof des addr register
- */
-typedef union {
-    struct {
-        /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t in_suc_eof_des_addr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_in_suc_eof_des_addr_ch0_reg_t;
-
-/** Type of in_err_eof_des_addr_ch0 register
- *  RX CH0 err eof des addr register
- */
-typedef union {
-    struct {
-        /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when there are some
-         *  errors in current receiving data.
-         */
-        uint32_t in_err_eof_des_addr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_in_err_eof_des_addr_ch0_reg_t;
-
-/** Type of in_dscr_ch0 register
- *  RX CH0 next dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next inlink descriptor address x.
-         */
-        uint32_t inlink_dscr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_ch0_reg_t;
-
-/** Type of in_dscr_bf0_ch0 register
- *  RX CH0 last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last inlink descriptor's next address x-1.
-         */
-        uint32_t inlink_dscr_bf0_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf0_ch0_reg_t;
-
-/** Type of in_dscr_bf1_ch0 register
- *  RX CH0 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last inlink descriptor's next address x-2.
-         */
-        uint32_t inlink_dscr_bf1_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf1_ch0_reg_t;
-
-/** Type of infifo_status_ch1 register
- *  RX CH1 INFIFO status register
- */
-typedef union {
-    struct {
-        /** infifo_full_l2_ch1 : RO; bitpos: [0]; default: 0;
-         *  Rx FIFO full signal for Rx channel.
-         */
-        uint32_t infifo_full_l2_ch1:1;
-        /** infifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1;
-         *  Rx FIFO empty signal for Rx channel.
-         */
-        uint32_t infifo_empty_l2_ch1:1;
-        /** infifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
-         */
-        uint32_t infifo_cnt_l2_ch1:4;
-        /** infifo_full_l1_ch1 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l1_ch1:1;
-        /** infifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l1_ch1:1;
-        /** infifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l1_ch1:5;
-        uint32_t reserved_13:3;
-        /** infifo_full_l3_ch1 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l3_ch1:1;
-        /** infifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l3_ch1:1;
-        /** infifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l3_ch1:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_infifo_status_ch1_reg_t;
-
-/** Type of in_state_ch1 register
- *  RX CH1 state register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current inlink descriptor's address.
-         */
-        uint32_t inlink_dscr_addr_ch1:18;
-        /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t in_dscr_state_ch1:2;
-        /** in_state_ch1 : RO; bitpos: [22:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t in_state_ch1:3;
-        /** in_reset_avail_ch1 : RO; bitpos: [23]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t in_reset_avail_ch1:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_in_state_ch1_reg_t;
-
-/** Type of in_suc_eof_des_addr_ch1 register
- *  RX CH1 eof des addr register
- */
-typedef union {
-    struct {
-        /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t in_suc_eof_des_addr_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_in_suc_eof_des_addr_ch1_reg_t;
-
-/** Type of in_err_eof_des_addr_ch1 register
- *  RX CH1 err eof des addr register
- */
-typedef union {
-    struct {
-        /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when there are some
-         *  errors in current receiving data.
-         */
-        uint32_t in_err_eof_des_addr_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_in_err_eof_des_addr_ch1_reg_t;
-
-/** Type of in_dscr_ch1 register
- *  RX CH1 next dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next inlink descriptor address x.
-         */
-        uint32_t inlink_dscr_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_ch1_reg_t;
-
-/** Type of in_dscr_bf0_ch1 register
- *  RX CH1 last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last inlink descriptor's next address x-1.
-         */
-        uint32_t inlink_dscr_bf0_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf0_ch1_reg_t;
-
-/** Type of in_dscr_bf1_ch1 register
- *  RX CH1 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last inlink descriptor's next address x-2.
-         */
-        uint32_t inlink_dscr_bf1_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf1_ch1_reg_t;
-
-/** Type of infifo_status_ch2 register
- *  RX CH2 INFIFO status register
- */
-typedef union {
-    struct {
-        /** infifo_full_l2_ch2 : RO; bitpos: [0]; default: 0;
-         *  Rx FIFO full signal for Rx channel.
-         */
-        uint32_t infifo_full_l2_ch2:1;
-        /** infifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1;
-         *  Rx FIFO empty signal for Rx channel.
-         */
-        uint32_t infifo_empty_l2_ch2:1;
-        /** infifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
-         */
-        uint32_t infifo_cnt_l2_ch2:4;
-        /** infifo_full_l1_ch2 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l1_ch2:1;
-        /** infifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l1_ch2:1;
-        /** infifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l1_ch2:5;
-        uint32_t reserved_13:3;
-        /** infifo_full_l3_ch2 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l3_ch2:1;
-        /** infifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l3_ch2:1;
-        /** infifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l3_ch2:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_infifo_status_ch2_reg_t;
-
-/** Type of in_state_ch2 register
- *  RX CH2 state register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current inlink descriptor's address.
-         */
-        uint32_t inlink_dscr_addr_ch2:18;
-        /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t in_dscr_state_ch2:2;
-        /** in_state_ch2 : RO; bitpos: [22:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t in_state_ch2:3;
-        /** in_reset_avail_ch2 : RO; bitpos: [23]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t in_reset_avail_ch2:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_in_state_ch2_reg_t;
-
-/** Type of in_suc_eof_des_addr_ch2 register
- *  RX CH2 eof des addr register
- */
-typedef union {
-    struct {
-        /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t in_suc_eof_des_addr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_in_suc_eof_des_addr_ch2_reg_t;
-
-/** Type of in_err_eof_des_addr_ch2 register
- *  RX CH2 err eof des addr register
- */
-typedef union {
-    struct {
-        /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when there are some
-         *  errors in current receiving data.
-         */
-        uint32_t in_err_eof_des_addr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_in_err_eof_des_addr_ch2_reg_t;
-
-/** Type of in_dscr_ch2 register
- *  RX CH2 next dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next inlink descriptor address x.
-         */
-        uint32_t inlink_dscr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_ch2_reg_t;
-
-/** Type of in_dscr_bf0_ch2 register
- *  RX CH2 last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last inlink descriptor's next address x-1.
-         */
-        uint32_t inlink_dscr_bf0_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf0_ch2_reg_t;
-
-/** Type of in_dscr_bf1_ch2 register
- *  RX CH2 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last inlink descriptor's next address x-2.
-         */
-        uint32_t inlink_dscr_bf1_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf1_ch2_reg_t;
-
-/** Type of infifo_status_ch3 register
- *  RX CH3 INFIFO status register
- */
-typedef union {
-    struct {
-        /** infifo_full_l2_ch3 : RO; bitpos: [0]; default: 0;
-         *  Rx FIFO full signal for Rx channel.
-         */
-        uint32_t infifo_full_l2_ch3:1;
-        /** infifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1;
-         *  Rx FIFO empty signal for Rx channel.
-         */
-        uint32_t infifo_empty_l2_ch3:1;
-        /** infifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
-         */
-        uint32_t infifo_cnt_l2_ch3:4;
-        /** infifo_full_l1_ch3 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l1_ch3:1;
-        /** infifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l1_ch3:1;
-        /** infifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l1_ch3:5;
-        uint32_t reserved_13:3;
-        /** infifo_full_l3_ch3 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l3_ch3:1;
-        /** infifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l3_ch3:1;
-        /** infifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l3_ch3:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_infifo_status_ch3_reg_t;
-
-/** Type of in_state_ch3 register
- *  RX CH3 state register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current inlink descriptor's address.
-         */
-        uint32_t inlink_dscr_addr_ch3:18;
-        /** in_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t in_dscr_state_ch3:2;
-        /** in_state_ch3 : RO; bitpos: [22:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t in_state_ch3:3;
-        /** in_reset_avail_ch3 : RO; bitpos: [23]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t in_reset_avail_ch3:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_in_state_ch3_reg_t;
-
-/** Type of in_suc_eof_des_addr_ch3 register
- *  RX CH3 eof des addr register
- */
-typedef union {
-    struct {
-        /** in_suc_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t in_suc_eof_des_addr_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_in_suc_eof_des_addr_ch3_reg_t;
-
-/** Type of in_err_eof_des_addr_ch3 register
- *  RX CH3 err eof des addr register
- */
-typedef union {
-    struct {
-        /** in_err_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when there are some
-         *  errors in current receiving data.
-         */
-        uint32_t in_err_eof_des_addr_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_in_err_eof_des_addr_ch3_reg_t;
-
-/** Type of in_dscr_ch3 register
- *  RX CH3 next dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next inlink descriptor address x.
-         */
-        uint32_t inlink_dscr_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_ch3_reg_t;
-
-/** Type of in_dscr_bf0_ch3 register
- *  RX CH3 last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last inlink descriptor's next address x-1.
-         */
-        uint32_t inlink_dscr_bf0_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf0_ch3_reg_t;
-
-/** Type of in_dscr_bf1_ch3 register
- *  RX CH3 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last inlink descriptor's next address x-2.
-         */
-        uint32_t inlink_dscr_bf1_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf1_ch3_reg_t;
-
-/** Type of infifo_status_ch4 register
- *  RX CH4 INFIFO status register
- */
-typedef union {
-    struct {
-        /** infifo_full_l2_ch4 : RO; bitpos: [0]; default: 0;
-         *  Rx FIFO full signal for Rx channel.
-         */
-        uint32_t infifo_full_l2_ch4:1;
-        /** infifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1;
-         *  Rx FIFO empty signal for Rx channel.
-         */
-        uint32_t infifo_empty_l2_ch4:1;
-        /** infifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0;
-         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
-         */
-        uint32_t infifo_cnt_l2_ch4:4;
-        /** infifo_full_l1_ch4 : RO; bitpos: [6]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l1_ch4:1;
-        /** infifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l1_ch4:1;
-        /** infifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l1_ch4:5;
-        uint32_t reserved_13:3;
-        /** infifo_full_l3_ch4 : RO; bitpos: [16]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l3_ch4:1;
-        /** infifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l3_ch4:1;
-        /** infifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l3_ch4:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_dma_infifo_status_ch4_reg_t;
-
-/** Type of in_state_ch4 register
- *  RX CH4 state register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current inlink descriptor's address.
-         */
-        uint32_t inlink_dscr_addr_ch4:18;
-        /** in_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0;
-         *  This register stores the current descriptor state machine state.
-         */
-        uint32_t in_dscr_state_ch4:2;
-        /** in_state_ch4 : RO; bitpos: [22:20]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t in_state_ch4:3;
-        /** in_reset_avail_ch4 : RO; bitpos: [23]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t in_reset_avail_ch4:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_in_state_ch4_reg_t;
-
-/** Type of in_suc_eof_des_addr_ch4 register
- *  RX CH4 eof des addr register
- */
-typedef union {
-    struct {
-        /** in_suc_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t in_suc_eof_des_addr_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_in_suc_eof_des_addr_ch4_reg_t;
-
-/** Type of in_err_eof_des_addr_ch4 register
- *  RX CH4 err eof des addr register
- */
-typedef union {
-    struct {
-        /** in_err_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when there are some
-         *  errors in current receiving data.
-         */
-        uint32_t in_err_eof_des_addr_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_in_err_eof_des_addr_ch4_reg_t;
-
-/** Type of in_dscr_ch4 register
- *  RX CH4 next dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the next inlink descriptor address x.
-         */
-        uint32_t inlink_dscr_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_ch4_reg_t;
-
-/** Type of in_dscr_bf0_ch4 register
- *  RX CH4 last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last inlink descriptor's next address x-1.
-         */
-        uint32_t inlink_dscr_bf0_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf0_ch4_reg_t;
-
-/** Type of in_dscr_bf1_ch4 register
- *  RX CH4 second-to-last dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last inlink descriptor's next address x-2.
-         */
-        uint32_t inlink_dscr_bf1_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_in_dscr_bf1_ch4_reg_t;
-
-/** Type of infifo_status_ch5 register
- *  RX CH5 INFIFO status register
- */
-typedef union {
-    struct {
-        /** infifo_full_l1_ch5 : RO; bitpos: [0]; default: 0;
-         *  Tx FIFO full signal for Tx channel 1.
-         */
-        uint32_t infifo_full_l1_ch5:1;
-        /** infifo_empty_l1_ch5 : RO; bitpos: [1]; default: 1;
-         *  Tx FIFO empty signal for Tx channel 1.
-         */
-        uint32_t infifo_empty_l1_ch5:1;
-        /** infifo_cnt_l1_ch5 : RO; bitpos: [6:2]; default: 0;
-         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
-         */
-        uint32_t infifo_cnt_l1_ch5:5;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} h264_dma_infifo_status_ch5_reg_t;
-
-/** Type of in_state_ch5 register
- *  RX CH5 state register
- */
-typedef union {
-    struct {
-        /** in_state_ch5 : RO; bitpos: [2:0]; default: 0;
-         *  This register stores the current control module state machine state.
-         */
-        uint32_t in_state_ch5:3;
-        /** in_reset_avail_ch5 : RO; bitpos: [3]; default: 1;
-         *  This register indicate that if the channel reset is safety.
-         */
-        uint32_t in_reset_avail_ch5:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} h264_dma_in_state_ch5_reg_t;
-
-
-/** Group: out_link addr register */
-/** Type of out_link_addr_ch0 register
- *  TX CH0 out_link dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first outlink descriptor's address.
-         */
-        uint32_t outlink_addr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_out_link_addr_ch0_reg_t;
-
-
-/** Group: tx ch0 arb register */
-/** Type of out_arb_ch0 register
- *  TX CH0 arb register
- */
-typedef union {
-    struct {
-        /** out_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
-         */
-        uint32_t out_arb_token_num_ch0:4;
-        /** exter_out_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1;
-         *  Set the priority of channel
-         */
-        uint32_t exter_out_arb_priority_ch0:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} h264_dma_out_arb_ch0_reg_t;
-
-
-/** Group: TX CH0 test mode register */
-/** Type of out_mode_enable_ch0 register
- *  tx CH0 mode enable register
- */
-typedef union {
-    struct {
-        /** out_test_mode_enable_ch0 : R/W; bitpos: [0]; default: 0;
-         *  tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test
-         *  mode
-         */
-        uint32_t out_test_mode_enable_ch0:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} h264_dma_out_mode_enable_ch0_reg_t;
-
-/** Type of out_mode_yuv_ch0 register
- *  tx CH0 test mode yuv value register
- */
-typedef union {
-    struct {
-        /** out_test_y_value_ch0 : R/W; bitpos: [7:0]; default: 0;
-         *  tx CH0 test mode y value
-         */
-        uint32_t out_test_y_value_ch0:8;
-        /** out_test_u_value_ch0 : R/W; bitpos: [15:8]; default: 0;
-         *  tx CH0 test mode u value
-         */
-        uint32_t out_test_u_value_ch0:8;
-        /** out_test_v_value_ch0 : R/W; bitpos: [23:16]; default: 0;
-         *  tx CH0 test mode v value
-         */
-        uint32_t out_test_v_value_ch0:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_dma_out_mode_yuv_ch0_reg_t;
-
-
-/** Group: ETM config register */
-/** Type of out_etm_conf_ch0 register
- *  TX CH0 ETM config register
- */
-typedef union {
-    struct {
-        /** out_etm_en_ch0 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
-         */
-        uint32_t out_etm_en_ch0:1;
-        /** out_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
-         */
-        uint32_t out_etm_loop_en_ch0:1;
-        /** out_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
-         */
-        uint32_t out_dscr_task_mak_ch0:2;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} h264_dma_out_etm_conf_ch0_reg_t;
-
-
-/** Group: TX CH0 debug info */
-/** Type of out_buf_len_ch0 register
- *  tx CH0 buf len register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_buf_len_hb_ch0 : RO; bitpos: [12:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_buf_len_hb_ch0:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} h264_dma_out_buf_len_ch0_reg_t;
-
-/** Type of out_fifo_bcnt_ch0 register
- *  tx CH0 fifo byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_outfifo_bcnt_ch0 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_outfifo_bcnt_ch0:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_out_fifo_bcnt_ch0_reg_t;
-
-/** Type of out_push_bytecnt_ch0 register
- *  tx CH0 push byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_push_bytecnt_ch0 : RO; bitpos: [7:0]; default: 255;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_push_bytecnt_ch0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} h264_dma_out_push_bytecnt_ch0_reg_t;
-
-/** Type of out_xaddr_ch0 register
- *  tx CH0 xaddr register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_xaddr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_out_xaddr_ch0_reg_t;
-
-
-/** Group: TX CH1 config0 register */
-/** Type of out_conf0_ch1 register
- *  TX CH1 config0 register
- */
-typedef union {
-    struct {
-        /** out_auto_wrback_ch1 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
-         *  outlink descriptor has been received.
-         */
-        uint32_t out_auto_wrback_ch1:1;
-        /** out_eof_mode_ch1 : R/W; bitpos: [1]; default: 1;
-         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
-         *  generated when data need to read has been popped from FIFO in DMA
-         */
-        uint32_t out_eof_mode_ch1:1;
-        /** outdscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
-         *  descriptor when accessing internal SRAM.
-         */
-        uint32_t outdscr_burst_en_ch1:1;
-        /** out_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
-         */
-        uint32_t out_ecc_aes_en_ch1:1;
-        /** out_check_owner_ch1 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t out_check_owner_ch1:1;
-        uint32_t reserved_5:1;
-        /** out_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Tx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 64 bytes
-         */
-        uint32_t out_mem_burst_length_ch1:3;
-        uint32_t reserved_9:3;
-        /** out_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
-         *  define by mem_burst_length
-         */
-        uint32_t out_page_bound_en_ch1:1;
-        uint32_t reserved_13:11;
-        /** out_rst_ch1 : R/W; bitpos: [24]; default: 0;
-         *  Write 1 then write 0 to this bit to reset TX channel
-         */
-        uint32_t out_rst_ch1:1;
-        /** out_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0;
-         *  Write 1 before reset and write 0 after reset
-         */
-        uint32_t out_cmd_disable_ch1:1;
-        /** out_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
-         */
-        uint32_t out_arb_weight_opt_dis_ch1:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} h264_dma_out_conf0_ch1_reg_t;
-
-
-/** Group: TX CH1 out_link dscr addr register */
-/** Type of out_link_addr_ch1 register
- *  TX CH1 out_link dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first outlink descriptor's address.
-         */
-        uint32_t outlink_addr_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_out_link_addr_ch1_reg_t;
-
-
-/** Group: TX CH1 arb register */
-/** Type of out_arb_ch1 register
- *  TX CH1 arb register
- */
-typedef union {
-    struct {
-        /** out_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
-         */
-        uint32_t out_arb_token_num_ch1:4;
-        uint32_t reserved_4:2;
-        /** inter_out_arb_priority_ch1 : R/W; bitpos: [6]; default: 1;
-         *  Set the priority of channel
-         */
-        uint32_t inter_out_arb_priority_ch1:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} h264_dma_out_arb_ch1_reg_t;
-
-
-/** Group: TX CH1 ETM config register */
-/** Type of out_etm_conf_ch1 register
- *  TX CH1 ETM config register
- */
-typedef union {
-    struct {
-        /** out_etm_en_ch1 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
-         */
-        uint32_t out_etm_en_ch1:1;
-        /** out_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
-         */
-        uint32_t out_etm_loop_en_ch1:1;
-        /** out_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
-         */
-        uint32_t out_dscr_task_mak_ch1:2;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} h264_dma_out_etm_conf_ch1_reg_t;
-
-
-/** Group: TX CH1 debug info */
-/** Type of out_buf_len_ch1 register
- *  tx CH1 buf len register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_buf_len_hb_ch1 : RO; bitpos: [12:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_buf_len_hb_ch1:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} h264_dma_out_buf_len_ch1_reg_t;
-
-/** Type of out_fifo_bcnt_ch1 register
- *  tx CH1 fifo byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_outfifo_bcnt_ch1 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_outfifo_bcnt_ch1:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_out_fifo_bcnt_ch1_reg_t;
-
-/** Type of out_push_bytecnt_ch1 register
- *  tx CH1 push byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_push_bytecnt_ch1 : RO; bitpos: [7:0]; default: 255;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_push_bytecnt_ch1:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} h264_dma_out_push_bytecnt_ch1_reg_t;
-
-/** Type of out_xaddr_ch1 register
- *  tx CH1 xaddr register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_xaddr_ch1:32;
-    };
-    uint32_t val;
-} h264_dma_out_xaddr_ch1_reg_t;
-
-
-/** Group: TX CH2 config0 register */
-/** Type of out_conf0_ch2 register
- *  TX CH2 config0 register
- */
-typedef union {
-    struct {
-        /** out_auto_wrback_ch2 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
-         *  outlink descriptor has been received.
-         */
-        uint32_t out_auto_wrback_ch2:1;
-        /** out_eof_mode_ch2 : R/W; bitpos: [1]; default: 1;
-         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
-         *  generated when data need to read has been popped from FIFO in DMA
-         */
-        uint32_t out_eof_mode_ch2:1;
-        /** outdscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
-         *  descriptor when accessing internal SRAM.
-         */
-        uint32_t outdscr_burst_en_ch2:1;
-        /** out_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
-         */
-        uint32_t out_ecc_aes_en_ch2:1;
-        /** out_check_owner_ch2 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t out_check_owner_ch2:1;
-        uint32_t reserved_5:1;
-        /** out_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Tx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
-         */
-        uint32_t out_mem_burst_length_ch2:3;
-        uint32_t reserved_9:3;
-        /** out_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
-         *  define by mem_burst_length
-         */
-        uint32_t out_page_bound_en_ch2:1;
-        uint32_t reserved_13:11;
-        /** out_rst_ch2 : R/W; bitpos: [24]; default: 0;
-         *  Write 1 then write 0 to this bit to reset TX channel
-         */
-        uint32_t out_rst_ch2:1;
-        /** out_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0;
-         *  Write 1 before reset and write 0 after reset
-         */
-        uint32_t out_cmd_disable_ch2:1;
-        /** out_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
-         */
-        uint32_t out_arb_weight_opt_dis_ch2:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} h264_dma_out_conf0_ch2_reg_t;
-
-
-/** Group: TX CH2 out_link dscr addr register */
-/** Type of out_link_addr_ch2 register
- *  TX CH2 out_link dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first outlink descriptor's address.
-         */
-        uint32_t outlink_addr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_out_link_addr_ch2_reg_t;
-
-
-/** Group: TX CH2 arb register */
-/** Type of out_arb_ch2 register
- *  TX CH2 arb register
- */
-typedef union {
-    struct {
-        /** out_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
-         */
-        uint32_t out_arb_token_num_ch2:4;
-        uint32_t reserved_4:2;
-        /** inter_out_arb_priority_ch2 : R/W; bitpos: [6]; default: 1;
-         *  Set the priority of channel
-         */
-        uint32_t inter_out_arb_priority_ch2:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} h264_dma_out_arb_ch2_reg_t;
-
-
-/** Group: TX CH2 ETM config register */
-/** Type of out_etm_conf_ch2 register
- *  TX CH2 ETM config register
- */
-typedef union {
-    struct {
-        /** out_etm_en_ch2 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
-         */
-        uint32_t out_etm_en_ch2:1;
-        /** out_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
-         */
-        uint32_t out_etm_loop_en_ch2:1;
-        /** out_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
-         */
-        uint32_t out_dscr_task_mak_ch2:2;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} h264_dma_out_etm_conf_ch2_reg_t;
-
-
-/** Group: TX CH2 debug info */
-/** Type of out_buf_len_ch2 register
- *  tx CH2 buf len register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_buf_len_hb_ch2 : RO; bitpos: [12:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_buf_len_hb_ch2:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} h264_dma_out_buf_len_ch2_reg_t;
-
-/** Type of out_fifo_bcnt_ch2 register
- *  tx CH2 fifo byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_outfifo_bcnt_ch2 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_outfifo_bcnt_ch2:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_out_fifo_bcnt_ch2_reg_t;
-
-/** Type of out_push_bytecnt_ch2 register
- *  tx CH2 push byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_push_bytecnt_ch2 : RO; bitpos: [7:0]; default: 255;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_push_bytecnt_ch2:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} h264_dma_out_push_bytecnt_ch2_reg_t;
-
-/** Type of out_xaddr_ch2 register
- *  tx CH2 xaddr register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_xaddr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_out_xaddr_ch2_reg_t;
-
-
-/** Group: TX CH3 config0 register */
-/** Type of out_conf0_ch3 register
- *  TX CH3 config0 register
- */
-typedef union {
-    struct {
-        /** out_auto_wrback_ch3 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
-         *  outlink descriptor has been received.
-         */
-        uint32_t out_auto_wrback_ch3:1;
-        /** out_eof_mode_ch3 : R/W; bitpos: [1]; default: 1;
-         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
-         *  generated when data need to read has been popped from FIFO in DMA
-         */
-        uint32_t out_eof_mode_ch3:1;
-        /** outdscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
-         *  descriptor when accessing internal SRAM.
-         */
-        uint32_t outdscr_burst_en_ch3:1;
-        /** out_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
-         */
-        uint32_t out_ecc_aes_en_ch3:1;
-        /** out_check_owner_ch3 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t out_check_owner_ch3:1;
-        uint32_t reserved_5:1;
-        /** out_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Tx channel 3. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
-         */
-        uint32_t out_mem_burst_length_ch3:3;
-        uint32_t reserved_9:3;
-        /** out_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
-         *  define by mem_burst_length
-         */
-        uint32_t out_page_bound_en_ch3:1;
-        uint32_t reserved_13:13;
-        /** out_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
-         */
-        uint32_t out_arb_weight_opt_dis_ch3:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} h264_dma_out_conf0_ch3_reg_t;
-
-
-/** Group: TX CH3 out_link dscr addr register */
-/** Type of out_link_addr_ch3 register
- *  TX CH3 out_link dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first outlink descriptor's address.
-         */
-        uint32_t outlink_addr_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_out_link_addr_ch3_reg_t;
-
-
-/** Group: TX CH3 arb register */
-/** Type of out_arb_ch3 register
- *  TX CH3 arb register
- */
-typedef union {
-    struct {
-        /** out_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
-         */
-        uint32_t out_arb_token_num_ch3:4;
-        /** exter_out_arb_priority_ch3 : R/W; bitpos: [5:4]; default: 1;
-         *  Set the priority of channel
-         */
-        uint32_t exter_out_arb_priority_ch3:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} h264_dma_out_arb_ch3_reg_t;
-
-
-/** Group: TX CH3 ETM config register */
-/** Type of out_etm_conf_ch3 register
- *  TX CH3 ETM config register
- */
-typedef union {
-    struct {
-        /** out_etm_en_ch3 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
-         */
-        uint32_t out_etm_en_ch3:1;
-        /** out_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
-         */
-        uint32_t out_etm_loop_en_ch3:1;
-        /** out_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
-         */
-        uint32_t out_dscr_task_mak_ch3:2;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} h264_dma_out_etm_conf_ch3_reg_t;
-
-
-/** Group: TX CH3 debug info */
-/** Type of out_buf_len_ch3 register
- *  tx CH3 buf len register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_buf_len_hb_ch3 : RO; bitpos: [12:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_buf_len_hb_ch3:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} h264_dma_out_buf_len_ch3_reg_t;
-
-/** Type of out_fifo_bcnt_ch3 register
- *  tx CH3 fifo byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_outfifo_bcnt_ch3 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_outfifo_bcnt_ch3:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_out_fifo_bcnt_ch3_reg_t;
-
-/** Type of out_push_bytecnt_ch3 register
- *  tx CH3 push byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_push_bytecnt_ch3 : RO; bitpos: [7:0]; default: 63;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_push_bytecnt_ch3:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} h264_dma_out_push_bytecnt_ch3_reg_t;
-
-/** Type of out_xaddr_ch3 register
- *  tx CH3 xaddr register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_cmdfifo_xaddr_ch3:32;
-    };
-    uint32_t val;
-} h264_dma_out_xaddr_ch3_reg_t;
-
-/** Type of out_block_buf_len_ch3 register
- *  tx CH3 block buf len register
- */
-typedef union {
-    struct {
-        /** out_block_buf_len_ch3 : RO; bitpos: [27:0]; default: 0;
-         *  only for debug
-         */
-        uint32_t out_block_buf_len_ch3:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} h264_dma_out_block_buf_len_ch3_reg_t;
-
-
-/** Group: TX CH4 config0 register */
-/** Type of out_conf0_ch4 register
- *  TX CH4 config0 register
- */
-typedef union {
-    struct {
-        /** out_auto_wrback_ch4 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
-         *  outlink descriptor has been received.
-         */
-        uint32_t out_auto_wrback_ch4:1;
-        /** out_eof_mode_ch4 : R/W; bitpos: [1]; default: 1;
-         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
-         *  generated when data need to read has been popped from FIFO in DMA
-         */
-        uint32_t out_eof_mode_ch4:1;
-        /** outdscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
-         *  descriptor when accessing internal SRAM.
-         */
-        uint32_t outdscr_burst_en_ch4:1;
-        /** out_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0;
-         *  When access address space is ecc/aes area, this bit should be set to 1. In this
-         *  case, the start address of square should be 16-bit aligned. The width of square
-         *  multiply byte number of one pixel should be 16-bit aligned.
-         */
-        uint32_t out_ecc_aes_en_ch4:1;
-        /** out_check_owner_ch4 : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t out_check_owner_ch4:1;
-        uint32_t reserved_5:1;
-        /** out_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0;
-         *  Block size of Tx channel 4. 0: single      1: 16 bytes      2: 32 bytes    3: 64
-         *  bytes    4: 128 bytes
-         */
-        uint32_t out_mem_burst_length_ch4:3;
-        uint32_t reserved_9:3;
-        /** out_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
-         *  define by mem_burst_length
-         */
-        uint32_t out_page_bound_en_ch4:1;
-        uint32_t reserved_13:13;
-        /** out_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to 1 to disable arbiter optimum weight function.
-         */
-        uint32_t out_arb_weight_opt_dis_ch4:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} h264_dma_out_conf0_ch4_reg_t;
-
-
-/** Group: TX CH4 out_link dscr addr register */
-/** Type of out_link_addr_ch4 register
- *  TX CH4 out_link dscr addr register
- */
-typedef union {
-    struct {
-        /** outlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first outlink descriptor's address.
-         */
-        uint32_t outlink_addr_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_out_link_addr_ch4_reg_t;
-
+} h264_dma_in_int_st_ch5_reg_t;
 
-/** Group: TX CH4 arb register */
-/** Type of out_arb_ch4 register
- *  TX CH4 arb register
+/** Type of in_int_clr_ch5 register
+ *  RX CH5  interrupt clr register
  */
 typedef union {
     struct {
-        /** out_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
+        /** in_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
          */
-        uint32_t out_arb_token_num_ch4:4;
-        /** exter_out_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1;
-         *  Set the priority of channel
+        uint32_t in_done_int_clr:1;
+        /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
          */
-        uint32_t exter_out_arb_priority_ch4:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} h264_dma_out_arb_ch4_reg_t;
-
-
-/** Group: TX CH4 ETM config register */
-/** Type of out_etm_conf_ch4 register
- *  TX CH4 ETM config register
- */
-typedef union {
-    struct {
-        /** out_etm_en_ch4 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
+        uint32_t in_suc_eof_int_clr:1;
+        /** infifo_ovf_l1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
          */
-        uint32_t out_etm_en_ch4:1;
-        /** out_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
+        uint32_t infifo_ovf_l1_int_clr:1;
+        /** infifo_udf_l1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t out_etm_loop_en_ch4:1;
-        /** out_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
+        uint32_t infifo_udf_l1_int_clr:1;
+        /** fetch_mb_col_cnt_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
          */
-        uint32_t out_dscr_task_mak_ch4:2;
-        uint32_t reserved_4:28;
+        uint32_t fetch_mb_col_cnt_ovf_int_clr:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
-} h264_dma_out_etm_conf_ch4_reg_t;
+} h264_dma_in_int_clr_ch5_reg_t;
 
 
-/** Group: TX CH4 debug info */
-/** Type of out_buf_len_ch4 register
- *  tx CH4 buf len register
+/** Type of outfifo_status register
+ *  TX CHn outfifo status register
  */
 typedef union {
     struct {
-        /** out_cmdfifo_buf_len_hb_ch4 : RO; bitpos: [12:0]; default: 0;
-         *  only for debug
+        /** outfifo_full_l2 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
          */
-        uint32_t out_cmdfifo_buf_len_hb_ch4:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} h264_dma_out_buf_len_ch4_reg_t;
-
-/** Type of out_fifo_bcnt_ch4 register
- *  tx CH4 fifo byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_outfifo_bcnt_ch4 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
+        uint32_t outfifo_full_l2:1;
+        /** outfifo_empty_l2 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
          */
-        uint32_t out_cmdfifo_outfifo_bcnt_ch4:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_out_fifo_bcnt_ch4_reg_t;
-
-/** Type of out_push_bytecnt_ch4 register
- *  tx CH4 push byte cnt register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_push_bytecnt_ch4 : RO; bitpos: [7:0]; default: 63;
-         *  only for debug
+        uint32_t outfifo_empty_l2:1;
+        /** outfifo_cnt_l2 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
          */
-        uint32_t out_cmdfifo_push_bytecnt_ch4:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} h264_dma_out_push_bytecnt_ch4_reg_t;
-
-/** Type of out_xaddr_ch4 register
- *  tx CH4 xaddr register
- */
-typedef union {
-    struct {
-        /** out_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
+        uint32_t outfifo_cnt_l2:4;
+        /** outfifo_full_l1 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
          */
-        uint32_t out_cmdfifo_xaddr_ch4:32;
-    };
-    uint32_t val;
-} h264_dma_out_xaddr_ch4_reg_t;
-
-/** Type of out_block_buf_len_ch4 register
- *  tx CH4 block buf len register
- */
-typedef union {
-    struct {
-        /** out_block_buf_len_ch4 : RO; bitpos: [27:0]; default: 0;
-         *  only for debug
+        uint32_t outfifo_full_l1:1;
+        /** outfifo_empty_l1 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
          */
-        uint32_t out_block_buf_len_ch4:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} h264_dma_out_block_buf_len_ch4_reg_t;
-
-
-/** Group: RX CH0 in_link dscr addr register */
-/** Type of in_link_addr_ch0 register
- *  RX CH0 in_link dscr addr register
- */
-typedef union {
-    struct {
-        /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first inlink descriptor's address.
+        uint32_t outfifo_empty_l1:1;
+        /** outfifo_cnt_l1 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
          */
-        uint32_t inlink_addr_ch0:32;
-    };
-    uint32_t val;
-} h264_dma_in_link_addr_ch0_reg_t;
-
-
-/** Group: RX CH0 arb register */
-/** Type of in_arb_ch0 register
- *  RX CH0 arb register
- */
-typedef union {
-    struct {
-        /** in_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
+        uint32_t outfifo_cnt_l1:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
          */
-        uint32_t in_arb_token_num_ch0:4;
-        /** exter_in_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1;
-         *  Set the priority of channel
+        uint32_t outfifo_full_l3:1;
+        /** outfifo_empty_l3 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
          */
-        uint32_t exter_in_arb_priority_ch0:2;
-        /** inter_in_arb_priority_ch0 : R/W; bitpos: [8:6]; default: 1;
-         *  Set the priority of channel
+        uint32_t outfifo_empty_l3:1;
+        /** outfifo_cnt_l3 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
          */
-        uint32_t inter_in_arb_priority_ch0:3;
-        uint32_t reserved_9:23;
+        uint32_t outfifo_cnt_l3:2;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
-} h264_dma_in_arb_ch0_reg_t;
-
+} h264_dma_outfifo_status_reg_t;
 
-/** Group: RX CH0 ETM config register */
-/** Type of in_etm_conf_ch0 register
- *  RX CH0 ETM config register
+/** Type of out_state register
+ *  TX CHn state register
  */
 typedef union {
     struct {
-        /** in_etm_en_ch0 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
+        /** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
          */
-        uint32_t in_etm_en_ch0:1;
-        /** in_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
+        uint32_t outlink_dscr_addr:18;
+        /** out_dscr_state : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
          */
-        uint32_t in_etm_loop_en_ch0:1;
-        /** in_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
+        uint32_t out_dscr_state:2;
+        /** out_state : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
          */
-        uint32_t in_dscr_task_mak_ch0:2;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} h264_dma_in_etm_conf_ch0_reg_t;
-
-
-/** Group: RX CH0 debug info */
-/** Type of in_fifo_cnt_ch0 register
- *  rx CH0 fifo cnt register
- */
-typedef union {
-    struct {
-        /** in_cmdfifo_infifo_cnt_ch0 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
+        uint32_t out_state:4;
+        /** out_reset_avail : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
          */
-        uint32_t in_cmdfifo_infifo_cnt_ch0:10;
-        uint32_t reserved_10:22;
+        uint32_t out_reset_avail:1;
+        uint32_t reserved_25:7;
     };
     uint32_t val;
-} h264_dma_in_fifo_cnt_ch0_reg_t;
+} h264_dma_out_state_chn_reg_t;
 
-/** Type of in_pop_data_cnt_ch0 register
- *  rx CH0 pop data cnt register
+/** Type of out_eof_des_addr register
+ *  TX CHn eof des addr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_pop_data_cnt_ch0 : RO; bitpos: [7:0]; default: 7;
-         *  only for debug
+        /** out_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
          */
-        uint32_t in_cmdfifo_pop_data_cnt_ch0:8;
-        uint32_t reserved_8:24;
+        uint32_t out_eof_des_addr:32;
     };
     uint32_t val;
-} h264_dma_in_pop_data_cnt_ch0_reg_t;
+} h264_dma_out_eof_des_addr_chn_reg_t;
 
-/** Type of in_xaddr_ch0 register
- *  rx CH0 xaddr register
+/** Type of out_dscr register
+ *  TX CHn next dscr addr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
+        /** outlink_dscr : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
          */
-        uint32_t in_cmdfifo_xaddr_ch0:32;
+        uint32_t outlink_dscr:32;
     };
     uint32_t val;
-} h264_dma_in_xaddr_ch0_reg_t;
+} h264_dma_out_dscr_chn_reg_t;
 
-/** Type of in_buf_hb_rcv_ch0 register
- *  rx CH0 buf len hb rcv register
+/** Type of out_dscr_bf0 register
+ *  TX CHn last dscr addr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_buf_hb_rcv_ch0 : RO; bitpos: [28:0]; default: 0;
-         *  only for debug
+        /** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
          */
-        uint32_t in_cmdfifo_buf_hb_rcv_ch0:29;
-        uint32_t reserved_29:3;
+        uint32_t outlink_dscr_bf0:32;
     };
     uint32_t val;
-} h264_dma_in_buf_hb_rcv_ch0_reg_t;
+} h264_dma_out_dscr_bf0_chn_reg_t;
 
-
-/** Group: RX CH1 in_link dscr addr register */
-/** Type of in_link_addr_ch1 register
- *  RX CH1 in_link dscr addr register
+/** Type of out_dscr_bf1 register
+ *  TX CHn second-to-last dscr addr register
  */
 typedef union {
     struct {
-        /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first inlink descriptor's address.
+        /** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
          */
-        uint32_t inlink_addr_ch1:32;
+        uint32_t outlink_dscr_bf1:32;
     };
     uint32_t val;
-} h264_dma_in_link_addr_ch1_reg_t;
-
+} h264_dma_out_dscr_bf1_chn_reg_t;
 
-/** Group: RX CH1 arb register */
-/** Type of in_arb_ch1 register
- *  RX CH1 arb register
+/** Type of infifo_status register
+ *  RX CH0 INFIFO status register
  */
 typedef union {
     struct {
-        /** in_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
+        /** infifo_full_l2 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
          */
-        uint32_t in_arb_token_num_ch1:4;
-        /** exter_in_arb_priority_ch1 : R/W; bitpos: [5:4]; default: 1;
-         *  Set the priority of channel
+        uint32_t infifo_full_l2:1;
+        /** infifo_empty_l2 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
          */
-        uint32_t exter_in_arb_priority_ch1:2;
-        /** inter_in_arb_priority_ch1 : R/W; bitpos: [8:6]; default: 1;
-         *  Set the priority of channel
+        uint32_t infifo_empty_l2:1;
+        /** infifo_cnt_l2 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
          */
-        uint32_t inter_in_arb_priority_ch1:3;
-        uint32_t reserved_9:23;
+        uint32_t infifo_cnt_l2:4;
+        /** infifo_full_l1 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l1:1;
+        /** infifo_empty_l1 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l1:1;
+        /** infifo_cnt_l1 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l1:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l3:1;
+        /** infifo_empty_l3 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l3:1;
+        /** infifo_cnt_l3 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l3:2;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
-} h264_dma_in_arb_ch1_reg_t;
+} h264_dma_infifo_status_chn_reg_t;
 
-
-/** Group: RX CH1 ETM config register */
-/** Type of in_etm_conf_ch1 register
- *  RX CH1 ETM config register
+/** Type of in_state register
+ *  RX CH0 state register
  */
 typedef union {
     struct {
-        /** in_etm_en_ch1 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
+        /** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
          */
-        uint32_t in_etm_en_ch1:1;
-        /** in_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
+        uint32_t inlink_dscr_addr:18;
+        /** in_dscr_state : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
          */
-        uint32_t in_etm_loop_en_ch1:1;
-        /** in_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
+        uint32_t in_dscr_state:2;
+        /** in_state : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
          */
-        uint32_t in_dscr_task_mak_ch1:2;
-        uint32_t reserved_4:28;
+        uint32_t in_state:3;
+        /** in_reset_avail : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail:1;
+        uint32_t reserved_24:8;
     };
     uint32_t val;
-} h264_dma_in_etm_conf_ch1_reg_t;
+} h264_dma_in_state_chn_reg_t;
 
-
-/** Group: RX CH1 debug info */
-/** Type of in_fifo_cnt_ch1 register
- *  rx CH1 fifo cnt register
+/** Type of in_suc_eof_des_addr register
+ *  RX CH0 eof des addr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_infifo_cnt_ch1 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
+        /** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
          */
-        uint32_t in_cmdfifo_infifo_cnt_ch1:10;
-        uint32_t reserved_10:22;
+        uint32_t in_suc_eof_des_addr:32;
     };
     uint32_t val;
-} h264_dma_in_fifo_cnt_ch1_reg_t;
+} h264_dma_in_suc_eof_des_addr_chn_reg_t;
 
-/** Type of in_pop_data_cnt_ch1 register
- *  rx CH1 pop data cnt register
+/** Type of in_err_eof_des_addr register
+ *  RX CH0 err eof des addr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_pop_data_cnt_ch1 : RO; bitpos: [7:0]; default: 7;
-         *  only for debug
+        /** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
          */
-        uint32_t in_cmdfifo_pop_data_cnt_ch1:8;
-        uint32_t reserved_8:24;
+        uint32_t in_err_eof_des_addr:32;
     };
     uint32_t val;
-} h264_dma_in_pop_data_cnt_ch1_reg_t;
+} h264_dma_in_err_eof_des_addr_chn_reg_t;
 
-/** Type of in_xaddr_ch1 register
- *  rx CH1 xaddr register
+/** Type of in_dscr register
+ *  RX CH0 next dscr addr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
+        /** inlink_dscr : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
          */
-        uint32_t in_cmdfifo_xaddr_ch1:32;
+        uint32_t inlink_dscr:32;
     };
     uint32_t val;
-} h264_dma_in_xaddr_ch1_reg_t;
+} h264_dma_in_dscr_chn_reg_t;
 
-/** Type of in_buf_hb_rcv_ch1 register
- *  rx CH1 buf len hb rcv register
+/** Type of in_dscr_bf0 register
+ *  RX CH0 last dscr addr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_buf_hb_rcv_ch1 : RO; bitpos: [28:0]; default: 0;
-         *  only for debug
+        /** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
          */
-        uint32_t in_cmdfifo_buf_hb_rcv_ch1:29;
-        uint32_t reserved_29:3;
+        uint32_t inlink_dscr_bf0:32;
     };
     uint32_t val;
-} h264_dma_in_buf_hb_rcv_ch1_reg_t;
+} h264_dma_in_dscr_bf0_chn_reg_t;
 
-
-/** Group: RX CH2 in_link dscr addr register */
-/** Type of in_link_addr_ch2 register
- *  RX CH2 in_link dscr addr register
+/** Type of in_dscr_bf1 register
+ *  RX CH0 second-to-last dscr addr register
  */
 typedef union {
     struct {
-        /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first inlink descriptor's address.
+        /** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
          */
-        uint32_t inlink_addr_ch2:32;
+        uint32_t inlink_dscr_bf1:32;
     };
     uint32_t val;
-} h264_dma_in_link_addr_ch2_reg_t;
+} h264_dma_in_dscr_bf1_chn_reg_t;
 
 
-/** Group: RX CH2 arb register */
-/** Type of in_arb_ch2 register
- *  RX CH2 arb register
+/** Type of infifo_status_ch5 register
+ *  RX CH5 INFIFO status register
  */
 typedef union {
     struct {
-        /** in_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1;
-         *  Set the max number of token count of arbiter
+        /** infifo_full_l1 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
          */
-        uint32_t in_arb_token_num_ch2:4;
-        uint32_t reserved_4:2;
-        /** inter_in_arb_priority_ch2 : R/W; bitpos: [8:6]; default: 1;
-         *  Set the priority of channel
+        uint32_t infifo_full_l1:1;
+        /** infifo_empty_l1 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
          */
-        uint32_t inter_in_arb_priority_ch2:3;
-        uint32_t reserved_9:23;
+        uint32_t infifo_empty_l1:1;
+        /** infifo_cnt_l1 : RO; bitpos: [6:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1:5;
+        uint32_t reserved_7:25;
     };
     uint32_t val;
-} h264_dma_in_arb_ch2_reg_t;
-
+} h264_dma_infifo_status_ch5_reg_t;
 
-/** Group: RX CH2 ETM config register */
-/** Type of in_etm_conf_ch2 register
- *  RX CH2 ETM config register
+/** Type of in_state_ch5 register
+ *  RX CH5 state register
  */
 typedef union {
     struct {
-        /** in_etm_en_ch2 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to 1 to enable ETM task function
-         */
-        uint32_t in_etm_en_ch2:1;
-        /** in_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0;
-         *  when this bit is 1, dscr can be processed after receiving a task
+        /** in_state : RO; bitpos: [2:0]; default: 0;
+         *  This register stores the current control module state machine state.
          */
-        uint32_t in_etm_loop_en_ch2:1;
-        /** in_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1;
-         *  ETM dscr_ready maximum cache numbers
+        uint32_t in_state:3;
+        /** in_reset_avail : RO; bitpos: [3]; default: 1;
+         *  This register indicate that if the channel reset is safety.
          */
-        uint32_t in_dscr_task_mak_ch2:2;
+        uint32_t in_reset_avail:1;
         uint32_t reserved_4:28;
     };
     uint32_t val;
-} h264_dma_in_etm_conf_ch2_reg_t;
-
+} h264_dma_in_state_ch5_reg_t;
 
-/** Group: RX CH2 debug info */
-/** Type of in_fifo_cnt_ch2 register
- *  rx CH2 fifo cnt register
+/** Group: TX CHn config0 register */
+/** Type of out_conf0 register
+ *  TX CHn config0 register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_infifo_cnt_ch2 : RO; bitpos: [9:0]; default: 0;
-         *  only for debug
+        /** out_auto_wrback : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
          */
-        uint32_t in_cmdfifo_infifo_cnt_ch2:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} h264_dma_in_fifo_cnt_ch2_reg_t;
-
-/** Type of in_pop_data_cnt_ch2 register
- *  rx CH2 pop data cnt register
- */
-typedef union {
-    struct {
-        /** in_cmdfifo_pop_data_cnt_ch2 : RO; bitpos: [7:0]; default: 7;
-         *  only for debug
+        uint32_t out_auto_wrback:1;
+        /** out_eof_mode : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
          */
-        uint32_t in_cmdfifo_pop_data_cnt_ch2:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} h264_dma_in_pop_data_cnt_ch2_reg_t;
-
-/** Type of in_xaddr_ch2 register
- *  rx CH2 xaddr register
- */
-typedef union {
-    struct {
-        /** in_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0;
-         *  only for debug
+        uint32_t out_eof_mode:1;
+        /** outdscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
          */
-        uint32_t in_cmdfifo_xaddr_ch2:32;
-    };
-    uint32_t val;
-} h264_dma_in_xaddr_ch2_reg_t;
-
-/** Type of in_buf_hb_rcv_ch2 register
- *  rx CH2 buf len hb rcv register
- */
-typedef union {
-    struct {
-        /** in_cmdfifo_buf_hb_rcv_ch2 : RO; bitpos: [28:0]; default: 0;
-         *  only for debug
+        uint32_t outdscr_burst_en_ch3:1;
+        /** out_ecc_aes_en : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
          */
-        uint32_t in_cmdfifo_buf_hb_rcv_ch2:29;
-        uint32_t reserved_29:3;
+        uint32_t out_ecc_aes_en:1;
+        /** out_check_owner : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 3. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en:1;
+        uint32_t reserved_17:7;
+        /** out_rst : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst:1;
+        /** out_cmd_disable : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable:1;
+        /** out_arb_weight_opt_dis : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis:1;
+        uint32_t reserved_27:5;
     };
     uint32_t val;
-} h264_dma_in_buf_hb_rcv_ch2_reg_t;
+} h264_dma_out_conf0_chn_reg_t;
 
 
-/** Group: RX CH3 in_link dscr addr register */
-/** Type of in_link_addr_ch3 register
- *  RX CH3 in_link dscr addr register
+/** Group: TX CHn out_link dscr addr register */
+/** Type of out_link_addr register
+ *  TX CHn out_link dscr addr register
  */
 typedef union {
     struct {
-        /** inlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0;
-         *  This register stores the first inlink descriptor's address.
+        /** outlink_addr : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
          */
-        uint32_t inlink_addr_ch3:32;
+        uint32_t outlink_addr:32;
     };
     uint32_t val;
-} h264_dma_in_link_addr_ch3_reg_t;
+} h264_dma_out_link_addr_chn_reg_t;
 
 
-/** Group: RX CH3 arb register */
-/** Type of in_arb_ch3 register
- *  RX CH3 arb register
+/** Group: TX CHn arb register */
+/** Type of out_arb register
+ *  TX CHn arb register
  */
 typedef union {
     struct {
-        /** in_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1;
+        /** out_arb_token_num : R/W; bitpos: [3:0]; default: 1;
          *  Set the max number of token count of arbiter
          */
-        uint32_t in_arb_token_num_ch3:4;
-        uint32_t reserved_4:2;
-        /** inter_in_arb_priority_ch3 : R/W; bitpos: [8:6]; default: 1;
+        uint32_t out_arb_token_num:4;
+        /** exter_out_arb_priority : R/W; bitpos: [5:4]; default: 1;
          *  Set the priority of channel
          */
-        uint32_t inter_in_arb_priority_ch3:3;
-        uint32_t reserved_9:23;
+        uint32_t exter_out_arb_priority:2;
+        uint32_t reserved_6:26;
     };
     uint32_t val;
-} h264_dma_in_arb_ch3_reg_t;
+} h264_dma_out_arb_chn_reg_t;
 
 
-/** Group: RX CH3 ETM config register */
-/** Type of in_etm_conf_ch3 register
- *  RX CH3 ETM config register
+/** Group: TX CHn ETM config register */
+/** Type of out_etm_conf register
+ *  TX CHn ETM config register
  */
 typedef union {
     struct {
-        /** in_etm_en_ch3 : R/W; bitpos: [0]; default: 0;
+        /** out_etm_en : R/W; bitpos: [0]; default: 0;
          *  Set this bit to 1 to enable ETM task function
          */
-        uint32_t in_etm_en_ch3:1;
-        /** in_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0;
+        uint32_t out_etm_en:1;
+        /** out_etm_loop_en : R/W; bitpos: [1]; default: 0;
          *  when this bit is 1, dscr can be processed after receiving a task
          */
-        uint32_t in_etm_loop_en_ch3:1;
-        /** in_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1;
+        uint32_t out_etm_loop_en:1;
+        /** out_dscr_task_mak : R/W; bitpos: [3:2]; default: 1;
          *  ETM dscr_ready maximum cache numbers
          */
-        uint32_t in_dscr_task_mak_ch3:2;
+        uint32_t out_dscr_task_mak:2;
         uint32_t reserved_4:28;
     };
     uint32_t val;
-} h264_dma_in_etm_conf_ch3_reg_t;
+} h264_dma_out_etm_conf_chn_reg_t;
 
 
-/** Group: RX CH3 debug info */
-/** Type of in_fifo_cnt_ch3 register
- *  rx CH3 fifo cnt register
+/** Group: TX CHn debug info */
+/** Type of out_buf_len register
+ *  tx CHn buf len register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_infifo_cnt_ch3 : RO; bitpos: [9:0]; default: 0;
+        /** out_cmdfifo_buf_len_hb : RO; bitpos: [12:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_infifo_cnt_ch3:10;
+        uint32_t out_cmdfifo_buf_len_hb:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_chn_reg_t;
+
+/** Type of out_fifo_bcnt register
+ *  tx CHn fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt:10;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} h264_dma_in_fifo_cnt_ch3_reg_t;
+} h264_dma_out_fifo_bcnt_chn_reg_t;
 
-/** Type of in_pop_data_cnt_ch3 register
- *  rx CH3 pop data cnt register
+/** Type of out_push_bytecnt register
+ *  tx CHn push byte cnt register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_pop_data_cnt_ch3 : RO; bitpos: [7:0]; default: 7;
+        /** out_cmdfifo_push_bytecnt : RO; bitpos: [7:0]; default: 63;
          *  only for debug
          */
-        uint32_t in_cmdfifo_pop_data_cnt_ch3:8;
+        uint32_t out_cmdfifo_push_bytecnt:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} h264_dma_in_pop_data_cnt_ch3_reg_t;
+} h264_dma_out_push_bytecnt_chn_reg_t;
 
-/** Type of in_xaddr_ch3 register
- *  rx CH3 xaddr register
+/** Type of out_xaddr register
+ *  tx CHn xaddr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0;
+        /** out_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_xaddr_ch3:32;
+        uint32_t out_cmdfifo_xaddr:32;
     };
     uint32_t val;
-} h264_dma_in_xaddr_ch3_reg_t;
+} h264_dma_out_xaddr_chn_reg_t;
 
-/** Type of in_buf_hb_rcv_ch3 register
- *  rx CH3 buf len hb rcv register
+/** Type of out_block_buf_len register
+ *  tx CHn block buf len register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_buf_hb_rcv_ch3 : RO; bitpos: [28:0]; default: 0;
+        /** out_block_buf_len : RO; bitpos: [27:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_buf_hb_rcv_ch3:29;
-        uint32_t reserved_29:3;
+        uint32_t out_block_buf_len:28;
+        uint32_t reserved_28:4;
     };
     uint32_t val;
-} h264_dma_in_buf_hb_rcv_ch3_reg_t;
+} h264_dma_out_block_buf_len_chn_reg_t;
 
 
-/** Group: RX CH4 in_link dscr addr register */
-/** Type of in_link_addr_ch4 register
- *  RX CH4 in_link dscr addr register
+/** Group: RX CH0 in_link dscr addr register */
+/** Type of in_link_addr register
+ *  RX CH0 in_link dscr addr register
  */
 typedef union {
     struct {
-        /** inlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0;
+        /** inlink_addr : R/W; bitpos: [31:0]; default: 0;
          *  This register stores the first inlink descriptor's address.
          */
-        uint32_t inlink_addr_ch4:32;
+        uint32_t inlink_addr:32;
     };
     uint32_t val;
-} h264_dma_in_link_addr_ch4_reg_t;
+} h264_dma_in_link_addr_chn_reg_t;
 
 
-/** Group: RX CH4 arb register */
-/** Type of in_arb_ch4 register
- *  RX CH4 arb register
+/** Group: RX CH0 arb register */
+/** Type of in_arb register
+ *  RX CH0 arb register
  */
 typedef union {
     struct {
-        /** in_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1;
+        /** in_arb_token_num : R/W; bitpos: [3:0]; default: 1;
          *  Set the max number of token count of arbiter
          */
-        uint32_t in_arb_token_num_ch4:4;
-        /** exter_in_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1;
+        uint32_t in_arb_token_num:4;
+        /** exter_in_arb_priority : R/W; bitpos: [5:4]; default: 1;
          *  Set the priority of channel
          */
-        uint32_t exter_in_arb_priority_ch4:2;
-        /** inter_in_arb_priority_ch4 : R/W; bitpos: [8:6]; default: 1;
+        uint32_t exter_in_arb_priority:2;
+        /** inter_in_arb_priority : R/W; bitpos: [8:6]; default: 1;
          *  Set the priority of channel
          */
-        uint32_t inter_in_arb_priority_ch4:3;
+        uint32_t inter_in_arb_priority:3;
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} h264_dma_in_arb_ch4_reg_t;
+} h264_dma_in_arb_chn_reg_t;
 
 
-/** Group: RX CH4 ETM config register */
-/** Type of in_etm_conf_ch4 register
- *  RX CH4 ETM config register
+/** Group: RX CH0 ETM config register */
+/** Type of in_etm_conf register
+ *  RX CH0 ETM config register
  */
 typedef union {
     struct {
-        /** in_etm_en_ch4 : R/W; bitpos: [0]; default: 0;
+        /** in_etm_en : R/W; bitpos: [0]; default: 0;
          *  Set this bit to 1 to enable ETM task function
          */
-        uint32_t in_etm_en_ch4:1;
-        /** in_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0;
+        uint32_t in_etm_en:1;
+        /** in_etm_loop_en : R/W; bitpos: [1]; default: 0;
          *  when this bit is 1, dscr can be processed after receiving a task
          */
-        uint32_t in_etm_loop_en_ch4:1;
-        /** in_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1;
+        uint32_t in_etm_loop_en:1;
+        /** in_dscr_task_mak : R/W; bitpos: [3:2]; default: 1;
          *  ETM dscr_ready maximum cache numbers
          */
-        uint32_t in_dscr_task_mak_ch4:2;
+        uint32_t in_dscr_task_mak:2;
         uint32_t reserved_4:28;
     };
     uint32_t val;
-} h264_dma_in_etm_conf_ch4_reg_t;
+} h264_dma_in_etm_conf_chn_reg_t;
 
 
-/** Group: RX CH4 debug info */
-/** Type of in_fifo_cnt_ch4 register
- *  rx CH4 fifo cnt register
+/** Group: RX CH0 debug info */
+/** Type of in_fifo_cnt register
+ *  rx CH0 fifo cnt register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_infifo_cnt_ch4 : RO; bitpos: [9:0]; default: 0;
+        /** in_cmdfifo_infifo_cnt : RO; bitpos: [9:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_infifo_cnt_ch4:10;
+        uint32_t in_cmdfifo_infifo_cnt:10;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} h264_dma_in_fifo_cnt_ch4_reg_t;
+} h264_dma_in_fifo_cnt_chn_reg_t;
 
-/** Type of in_pop_data_cnt_ch4 register
- *  rx CH4 pop data cnt register
+/** Type of in_pop_data_cnt register
+ *  rx CH0 pop data cnt register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_pop_data_cnt_ch4 : RO; bitpos: [7:0]; default: 7;
+        /** in_cmdfifo_pop_data_cnt : RO; bitpos: [7:0]; default: 7;
          *  only for debug
          */
-        uint32_t in_cmdfifo_pop_data_cnt_ch4:8;
+        uint32_t in_cmdfifo_pop_data_cnt:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} h264_dma_in_pop_data_cnt_ch4_reg_t;
+} h264_dma_in_pop_data_cnt_chn_reg_t;
 
-/** Type of in_xaddr_ch4 register
- *  rx CH4 xaddr register
+/** Type of in_xaddr register
+ *  rx CH0 xaddr register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0;
+        /** in_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_xaddr_ch4:32;
+        uint32_t in_cmdfifo_xaddr:32;
     };
     uint32_t val;
-} h264_dma_in_xaddr_ch4_reg_t;
+} h264_dma_in_xaddr_chn_reg_t;
 
-/** Type of in_buf_hb_rcv_ch4 register
- *  rx CH4 buf len hb rcv register
+/** Type of in_buf_hb_rcv register
+ *  rx CH0 buf len hb rcv register
  */
 typedef union {
     struct {
-        /** in_cmdfifo_buf_hb_rcv_ch4 : RO; bitpos: [28:0]; default: 0;
+        /** in_cmdfifo_buf_hb_rcv : RO; bitpos: [28:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_buf_hb_rcv_ch4:29;
+        uint32_t in_cmdfifo_buf_hb_rcv:29;
         uint32_t reserved_29:3;
     };
     uint32_t val;
-} h264_dma_in_buf_hb_rcv_ch4_reg_t;
-
+} h264_dma_in_buf_hb_rcv_chn_reg_t;
 
 /** Group: RX CH5 config1 register */
 /** Type of in_conf1_ch5 register
@@ -5926,10 +1414,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** block_start_addr_ch5 : R/W; bitpos: [31:0]; default: 0;
+        /** block_start_addr : R/W; bitpos: [31:0]; default: 0;
          *  RX Channel 5 destination start address
          */
-        uint32_t block_start_addr_ch5:32;
+        uint32_t block_start_addr:32;
     };
     uint32_t val;
 } h264_dma_in_conf1_ch5_reg_t;
@@ -5941,14 +1429,14 @@ typedef union {
  */
 typedef union {
     struct {
-        /** block_row_length_12line_ch5 : R/W; bitpos: [15:0]; default: 30720;
+        /** block_row_length_12line : R/W; bitpos: [15:0]; default: 30720;
          *  The number of bytes contained in a row block 12line in RX channel 5
          */
-        uint32_t block_row_length_12line_ch5:16;
-        /** block_row_length_4line_ch5 : R/W; bitpos: [31:16]; default: 15360;
+        uint32_t block_row_length_12line:16;
+        /** block_row_length_4line : R/W; bitpos: [31:16]; default: 15360;
          *  The number of bytes contained in a row block 4line in RX channel 5
          */
-        uint32_t block_row_length_4line_ch5:16;
+        uint32_t block_row_length_4line:16;
     };
     uint32_t val;
 } h264_dma_in_conf2_ch5_reg_t;
@@ -5960,14 +1448,14 @@ typedef union {
  */
 typedef union {
     struct {
-        /** block_length_12line_ch5 : R/W; bitpos: [13:0]; default: 256;
+        /** block_length_12line : R/W; bitpos: [13:0]; default: 256;
          *  The number of bytes contained in a block 12line
          */
-        uint32_t block_length_12line_ch5:14;
-        /** block_length_4line_ch5 : R/W; bitpos: [27:14]; default: 128;
+        uint32_t block_length_12line:14;
+        /** block_length_4line : R/W; bitpos: [27:14]; default: 128;
          *  The number of bytes contained in a block 4line
          */
-        uint32_t block_length_4line_ch5:14;
+        uint32_t block_length_4line:14;
         uint32_t reserved_28:4;
     };
     uint32_t val;
@@ -5980,15 +1468,15 @@ typedef union {
  */
 typedef union {
     struct {
-        /** in_arb_token_num_ch5 : R/W; bitpos: [3:0]; default: 1;
+        /** in_arb_token_num : R/W; bitpos: [3:0]; default: 1;
          *  Set the max number of token count of arbiter
          */
-        uint32_t in_arb_token_num_ch5:4;
+        uint32_t in_arb_token_num:4;
         uint32_t reserved_4:2;
-        /** inter_in_arb_priority_ch5 : R/W; bitpos: [8:6]; default: 1;
+        /** inter_in_arb_priority : R/W; bitpos: [8:6]; default: 1;
          *  Set the priority of channel
          */
-        uint32_t inter_in_arb_priority_ch5:3;
+        uint32_t inter_in_arb_priority:3;
         uint32_t reserved_9:23;
     };
     uint32_t val;
@@ -6001,10 +1489,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** in_cmdfifo_infifo_cnt_ch5 : RO; bitpos: [9:0]; default: 0;
+        /** in_cmdfifo_infifo_cnt : RO; bitpos: [9:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_infifo_cnt_ch5:10;
+        uint32_t in_cmdfifo_infifo_cnt:10;
         uint32_t reserved_10:22;
     };
     uint32_t val;
@@ -6015,10 +1503,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** in_cmdfifo_pop_data_cnt_ch5 : RO; bitpos: [7:0]; default: 255;
+        /** in_cmdfifo_pop_data_cnt : RO; bitpos: [7:0]; default: 255;
          *  only for debug
          */
-        uint32_t in_cmdfifo_pop_data_cnt_ch5:8;
+        uint32_t in_cmdfifo_pop_data_cnt:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -6029,10 +1517,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** in_cmdfifo_xaddr_ch5 : RO; bitpos: [31:0]; default: 0;
+        /** in_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_xaddr_ch5:32;
+        uint32_t in_cmdfifo_xaddr:32;
     };
     uint32_t val;
 } h264_dma_in_xaddr_ch5_reg_t;
@@ -6042,10 +1530,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** in_cmdfifo_buf_hb_rcv_ch5 : RO; bitpos: [28:0]; default: 0;
+        /** in_cmdfifo_buf_hb_rcv : RO; bitpos: [28:0]; default: 0;
          *  only for debug
          */
-        uint32_t in_cmdfifo_buf_hb_rcv_ch5:29;
+        uint32_t in_cmdfifo_buf_hb_rcv:29;
         uint32_t reserved_29:3;
     };
     uint32_t val;
@@ -6133,153 +1621,51 @@ typedef union {
 
 
 /** Group: dscr addr range register */
-/** Type of inter_mem_start_addr0 register
- *  Start address of inter memory range0 register
- */
-typedef union {
-    struct {
-        /** access_inter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944;
-         *  The start address of accessible address space.
-         */
-        uint32_t access_inter_mem_start_addr0:32;
-    };
-    uint32_t val;
-} h264_dma_inter_mem_start_addr0_reg_t;
-
-/** Type of inter_mem_end_addr0 register
- *  end address of inter memory range0 register
- */
-typedef union {
-    struct {
-        /** access_inter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103;
-         *  The end address of accessible address space. The access address beyond this range
-         *  would lead to descriptor error.
-         */
-        uint32_t access_inter_mem_end_addr0:32;
-    };
-    uint32_t val;
-} h264_dma_inter_mem_end_addr0_reg_t;
-
-/** Type of inter_mem_start_addr1 register
- *  Start address of inter memory range1 register
- */
-typedef union {
-    struct {
-        /** access_inter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944;
-         *  The start address of accessible address space.
-         */
-        uint32_t access_inter_mem_start_addr1:32;
-    };
-    uint32_t val;
-} h264_dma_inter_mem_start_addr1_reg_t;
-
-/** Type of inter_mem_end_addr1 register
- *  end address of inter memory range1 register
- */
-typedef union {
-    struct {
-        /** access_inter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103;
-         *  The end address of accessible address space. The access address beyond this range
-         *  would lead to descriptor error.
-         */
-        uint32_t access_inter_mem_end_addr1:32;
-    };
-    uint32_t val;
-} h264_dma_inter_mem_end_addr1_reg_t;
-
-/** Type of exter_mem_start_addr0 register
- *  Start address of exter memory range0 register
- */
-typedef union {
-    struct {
-        /** access_exter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944;
-         *  The start address of accessible address space.
-         */
-        uint32_t access_exter_mem_start_addr0:32;
-    };
-    uint32_t val;
-} h264_dma_exter_mem_start_addr0_reg_t;
-
-/** Type of exter_mem_end_addr0 register
- *  end address of exter memory range0 register
- */
-typedef union {
-    struct {
-        /** access_exter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103;
-         *  The end address of accessible address space. The access address beyond this range
-         *  would lead to descriptor error.
-         */
-        uint32_t access_exter_mem_end_addr0:32;
-    };
-    uint32_t val;
-} h264_dma_exter_mem_end_addr0_reg_t;
-
-/** Type of exter_mem_start_addr1 register
- *  Start address of exter memory range1 register
+/** Type of mem_start_addr register
+ *  Start address of inter memory range register
  */
 typedef union {
     struct {
-        /** access_exter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944;
+        /** access_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
          *  The start address of accessible address space.
          */
-        uint32_t access_exter_mem_start_addr1:32;
+        uint32_t access_mem_start_addr:32;
     };
     uint32_t val;
-} h264_dma_exter_mem_start_addr1_reg_t;
+} h264_dma_mem_start_addr_reg_t;
 
-/** Type of exter_mem_end_addr1 register
- *  end address of exter memory range1 register
+/** Type of mem_end_addr register
+ *  end address of inter memory range register
  */
 typedef union {
     struct {
-        /** access_exter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103;
+        /** access_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
          *  The end address of accessible address space. The access address beyond this range
          *  would lead to descriptor error.
          */
-        uint32_t access_exter_mem_end_addr1:32;
-    };
-    uint32_t val;
-} h264_dma_exter_mem_end_addr1_reg_t;
-
-
-/** Group: out arb config register */
-/** Type of out_arb_config register
- *  reserved
- */
-typedef union {
-    struct {
-        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
-         *  Set the max number of timeout count of arbiter
-         */
-        uint32_t out_arb_timeout_num:16;
-        /** out_weight_en : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t out_weight_en:1;
-        uint32_t reserved_17:15;
+        uint32_t access_mem_end_addr:32;
     };
     uint32_t val;
-} h264_dma_out_arb_config_reg_t;
-
+} h264_dma_mem_end_addr_reg_t;
 
-/** Group: in arb config register */
-/** Type of in_arb_config register
+/** Group: arb config register */
+/** Type of arb_config register
  *  reserved
  */
 typedef union {
     struct {
-        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+        /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
          *  Set the max number of timeout count of arbiter
          */
-        uint32_t in_arb_timeout_num:16;
-        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+        uint32_t arb_timeout_num:16;
+        /** weight_en : R/W; bitpos: [16]; default: 0;
          *  reserved
          */
-        uint32_t in_weight_en:1;
+        uint32_t weight_en:1;
         uint32_t reserved_17:15;
     };
     uint32_t val;
-} h264_dma_in_arb_config_reg_t;
+} h264_dma_arb_config_reg_t;
 
 
 /** Group: date register */
@@ -6384,293 +1770,102 @@ typedef union {
 
 
 typedef struct {
-    volatile h264_dma_out_conf0_ch0_reg_t out_conf0_ch0;
-    volatile h264_dma_out_int_raw_ch0_reg_t out_int_raw_ch0;
-    volatile h264_dma_out_int_ena_ch0_reg_t out_int_ena_ch0;
-    volatile h264_dma_out_int_st_ch0_reg_t out_int_st_ch0;
-    volatile h264_dma_out_int_clr_ch0_reg_t out_int_clr_ch0;
-    volatile h264_dma_outfifo_status_ch0_reg_t outfifo_status_ch0;
-    volatile h264_dma_out_push_ch0_reg_t out_push_ch0;
-    volatile h264_dma_out_link_conf_ch0_reg_t out_link_conf_ch0;
-    volatile h264_dma_out_link_addr_ch0_reg_t out_link_addr_ch0;
-    volatile h264_dma_out_state_ch0_reg_t out_state_ch0;
-    volatile h264_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0;
-    volatile h264_dma_out_dscr_ch0_reg_t out_dscr_ch0;
-    volatile h264_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0;
-    volatile h264_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0;
-    uint32_t reserved_038;
-    volatile h264_dma_out_arb_ch0_reg_t out_arb_ch0;
-    volatile h264_dma_out_ro_status_ch0_reg_t out_ro_status_ch0;
-    volatile h264_dma_out_ro_pd_conf_ch0_reg_t out_ro_pd_conf_ch0;
-    uint32_t reserved_048[2];
-    volatile h264_dma_out_mode_enable_ch0_reg_t out_mode_enable_ch0;
-    volatile h264_dma_out_mode_yuv_ch0_reg_t out_mode_yuv_ch0;
-    uint32_t reserved_058[4];
-    volatile h264_dma_out_etm_conf_ch0_reg_t out_etm_conf_ch0;
-    uint32_t reserved_06c;
-    volatile h264_dma_out_buf_len_ch0_reg_t out_buf_len_ch0;
-    volatile h264_dma_out_fifo_bcnt_ch0_reg_t out_fifo_bcnt_ch0;
-    volatile h264_dma_out_push_bytecnt_ch0_reg_t out_push_bytecnt_ch0;
-    volatile h264_dma_out_xaddr_ch0_reg_t out_xaddr_ch0;
-    uint32_t reserved_080[32];
-    volatile h264_dma_out_conf0_ch1_reg_t out_conf0_ch1;
-    volatile h264_dma_out_int_raw_ch1_reg_t out_int_raw_ch1;
-    volatile h264_dma_out_int_ena_ch1_reg_t out_int_ena_ch1;
-    volatile h264_dma_out_int_st_ch1_reg_t out_int_st_ch1;
-    volatile h264_dma_out_int_clr_ch1_reg_t out_int_clr_ch1;
-    volatile h264_dma_outfifo_status_ch1_reg_t outfifo_status_ch1;
-    volatile h264_dma_out_push_ch1_reg_t out_push_ch1;
-    volatile h264_dma_out_link_conf_ch1_reg_t out_link_conf_ch1;
-    volatile h264_dma_out_link_addr_ch1_reg_t out_link_addr_ch1;
-    volatile h264_dma_out_state_ch1_reg_t out_state_ch1;
-    volatile h264_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1;
-    volatile h264_dma_out_dscr_ch1_reg_t out_dscr_ch1;
-    volatile h264_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1;
-    volatile h264_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1;
-    uint32_t reserved_138;
-    volatile h264_dma_out_arb_ch1_reg_t out_arb_ch1;
-    uint32_t reserved_140[10];
-    volatile h264_dma_out_etm_conf_ch1_reg_t out_etm_conf_ch1;
-    uint32_t reserved_16c;
-    volatile h264_dma_out_buf_len_ch1_reg_t out_buf_len_ch1;
-    volatile h264_dma_out_fifo_bcnt_ch1_reg_t out_fifo_bcnt_ch1;
-    volatile h264_dma_out_push_bytecnt_ch1_reg_t out_push_bytecnt_ch1;
-    volatile h264_dma_out_xaddr_ch1_reg_t out_xaddr_ch1;
-    uint32_t reserved_180[32];
-    volatile h264_dma_out_conf0_ch2_reg_t out_conf0_ch2;
-    volatile h264_dma_out_int_raw_ch2_reg_t out_int_raw_ch2;
-    volatile h264_dma_out_int_ena_ch2_reg_t out_int_ena_ch2;
-    volatile h264_dma_out_int_st_ch2_reg_t out_int_st_ch2;
-    volatile h264_dma_out_int_clr_ch2_reg_t out_int_clr_ch2;
-    volatile h264_dma_outfifo_status_ch2_reg_t outfifo_status_ch2;
-    volatile h264_dma_out_push_ch2_reg_t out_push_ch2;
-    volatile h264_dma_out_link_conf_ch2_reg_t out_link_conf_ch2;
-    volatile h264_dma_out_link_addr_ch2_reg_t out_link_addr_ch2;
-    volatile h264_dma_out_state_ch2_reg_t out_state_ch2;
-    volatile h264_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2;
-    volatile h264_dma_out_dscr_ch2_reg_t out_dscr_ch2;
-    volatile h264_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2;
-    volatile h264_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2;
-    uint32_t reserved_238;
-    volatile h264_dma_out_arb_ch2_reg_t out_arb_ch2;
-    uint32_t reserved_240[10];
-    volatile h264_dma_out_etm_conf_ch2_reg_t out_etm_conf_ch2;
-    uint32_t reserved_26c;
-    volatile h264_dma_out_buf_len_ch2_reg_t out_buf_len_ch2;
-    volatile h264_dma_out_fifo_bcnt_ch2_reg_t out_fifo_bcnt_ch2;
-    volatile h264_dma_out_push_bytecnt_ch2_reg_t out_push_bytecnt_ch2;
-    volatile h264_dma_out_xaddr_ch2_reg_t out_xaddr_ch2;
-    uint32_t reserved_280[32];
-    volatile h264_dma_out_conf0_ch3_reg_t out_conf0_ch3;
-    volatile h264_dma_out_int_raw_ch3_reg_t out_int_raw_ch3;
-    volatile h264_dma_out_int_ena_ch3_reg_t out_int_ena_ch3;
-    volatile h264_dma_out_int_st_ch3_reg_t out_int_st_ch3;
-    volatile h264_dma_out_int_clr_ch3_reg_t out_int_clr_ch3;
-    volatile h264_dma_outfifo_status_ch3_reg_t outfifo_status_ch3;
-    volatile h264_dma_out_push_ch3_reg_t out_push_ch3;
-    volatile h264_dma_out_link_conf_ch3_reg_t out_link_conf_ch3;
-    volatile h264_dma_out_link_addr_ch3_reg_t out_link_addr_ch3;
-    volatile h264_dma_out_state_ch3_reg_t out_state_ch3;
-    volatile h264_dma_out_eof_des_addr_ch3_reg_t out_eof_des_addr_ch3;
-    volatile h264_dma_out_dscr_ch3_reg_t out_dscr_ch3;
-    volatile h264_dma_out_dscr_bf0_ch3_reg_t out_dscr_bf0_ch3;
-    volatile h264_dma_out_dscr_bf1_ch3_reg_t out_dscr_bf1_ch3;
+    volatile h264_dma_out_conf0_chn_reg_t conf0;
+    volatile h264_dma_out_int_raw_chn_reg_t int_raw;
+    volatile h264_dma_out_int_ena_chn_reg_t int_ena;
+    volatile h264_dma_out_int_st_chn_reg_t int_st;
+    volatile h264_dma_out_int_clr_chn_reg_t int_clr;
+    volatile h264_dma_outfifo_status_reg_t outfifo_status;
+    volatile h264_dma_out_push_chn_reg_t push;
+    volatile h264_dma_out_link_conf_chn_reg_t link_conf;
+    volatile h264_dma_out_link_addr_chn_reg_t link_addr;
+    volatile h264_dma_out_state_chn_reg_t state;
+    volatile h264_dma_out_eof_des_addr_chn_reg_t eof_des_addr;
+    volatile h264_dma_out_dscr_chn_reg_t dscr;
+    volatile h264_dma_out_dscr_bf0_chn_reg_t dscr_bf0;
+    volatile h264_dma_out_dscr_bf1_chn_reg_t dscr_bf1;
     uint32_t reserved_338;
-    volatile h264_dma_out_arb_ch3_reg_t out_arb_ch3;
+    volatile h264_dma_out_arb_chn_reg_t arb;
     uint32_t reserved_340[10];
-    volatile h264_dma_out_etm_conf_ch3_reg_t out_etm_conf_ch3;
+    volatile h264_dma_out_etm_conf_chn_reg_t etm_conf;
     uint32_t reserved_36c;
-    volatile h264_dma_out_buf_len_ch3_reg_t out_buf_len_ch3;
-    volatile h264_dma_out_fifo_bcnt_ch3_reg_t out_fifo_bcnt_ch3;
-    volatile h264_dma_out_push_bytecnt_ch3_reg_t out_push_bytecnt_ch3;
-    volatile h264_dma_out_xaddr_ch3_reg_t out_xaddr_ch3;
-    volatile h264_dma_out_block_buf_len_ch3_reg_t out_block_buf_len_ch3;
+    volatile h264_dma_out_buf_len_chn_reg_t buf_len;
+    volatile h264_dma_out_fifo_bcnt_chn_reg_t fifo_bcnt;
+    volatile h264_dma_out_push_bytecnt_chn_reg_t push_bytecnt;
+    volatile h264_dma_out_xaddr_chn_reg_t xaddr;
+    volatile h264_dma_out_block_buf_len_chn_reg_t block_buf_len;    // Please note that this reg only exists on out[3] and out[4]
     uint32_t reserved_384[31];
-    volatile h264_dma_out_conf0_ch4_reg_t out_conf0_ch4;
-    volatile h264_dma_out_int_raw_ch4_reg_t out_int_raw_ch4;
-    volatile h264_dma_out_int_ena_ch4_reg_t out_int_ena_ch4;
-    volatile h264_dma_out_int_st_ch4_reg_t out_int_st_ch4;
-    volatile h264_dma_out_int_clr_ch4_reg_t out_int_clr_ch4;
-    volatile h264_dma_outfifo_status_ch4_reg_t outfifo_status_ch4;
-    volatile h264_dma_out_push_ch4_reg_t out_push_ch4;
-    volatile h264_dma_out_link_conf_ch4_reg_t out_link_conf_ch4;
-    volatile h264_dma_out_link_addr_ch4_reg_t out_link_addr_ch4;
-    volatile h264_dma_out_state_ch4_reg_t out_state_ch4;
-    volatile h264_dma_out_eof_des_addr_ch4_reg_t out_eof_des_addr_ch4;
-    volatile h264_dma_out_dscr_ch4_reg_t out_dscr_ch4;
-    volatile h264_dma_out_dscr_bf0_ch4_reg_t out_dscr_bf0_ch4;
-    volatile h264_dma_out_dscr_bf1_ch4_reg_t out_dscr_bf1_ch4;
-    uint32_t reserved_438;
-    volatile h264_dma_out_arb_ch4_reg_t out_arb_ch4;
-    uint32_t reserved_440[10];
-    volatile h264_dma_out_etm_conf_ch4_reg_t out_etm_conf_ch4;
-    uint32_t reserved_46c;
-    volatile h264_dma_out_buf_len_ch4_reg_t out_buf_len_ch4;
-    volatile h264_dma_out_fifo_bcnt_ch4_reg_t out_fifo_bcnt_ch4;
-    volatile h264_dma_out_push_bytecnt_ch4_reg_t out_push_bytecnt_ch4;
-    volatile h264_dma_out_xaddr_ch4_reg_t out_xaddr_ch4;
-    volatile h264_dma_out_block_buf_len_ch4_reg_t out_block_buf_len_ch4;
-    uint32_t reserved_484[31];
-    volatile h264_dma_in_conf0_ch0_reg_t in_conf0_ch0;
-    volatile h264_dma_in_int_raw_ch0_reg_t in_int_raw_ch0;
-    volatile h264_dma_in_int_ena_ch0_reg_t in_int_ena_ch0;
-    volatile h264_dma_in_int_st_ch0_reg_t in_int_st_ch0;
-    volatile h264_dma_in_int_clr_ch0_reg_t in_int_clr_ch0;
-    volatile h264_dma_infifo_status_ch0_reg_t infifo_status_ch0;
-    volatile h264_dma_in_pop_ch0_reg_t in_pop_ch0;
-    volatile h264_dma_in_link_conf_ch0_reg_t in_link_conf_ch0;
-    volatile h264_dma_in_link_addr_ch0_reg_t in_link_addr_ch0;
-    volatile h264_dma_in_state_ch0_reg_t in_state_ch0;
-    volatile h264_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0;
-    volatile h264_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0;
-    volatile h264_dma_in_dscr_ch0_reg_t in_dscr_ch0;
-    volatile h264_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0;
-    volatile h264_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0;
+} h264_dma_out_chn_regs_t;
+
+typedef struct {
+    volatile h264_dma_in_conf0_chn_reg_t conf0;
+    volatile h264_dma_in_int_raw_chn_reg_t int_raw;
+    volatile h264_dma_in_int_ena_chn_reg_t int_ena;
+    volatile h264_dma_in_int_st_chn_reg_t int_st;
+    volatile h264_dma_in_int_clr_chn_reg_t int_clr;
+    volatile h264_dma_infifo_status_chn_reg_t infifo_status;
+    volatile h264_dma_in_pop_chn_reg_t pop;
+    volatile h264_dma_in_link_conf_chn_reg_t link_conf;
+    volatile h264_dma_in_link_addr_chn_reg_t link_addr;
+    volatile h264_dma_in_state_chn_reg_t state;
+    volatile h264_dma_in_suc_eof_des_addr_chn_reg_t suc_eof_des_addr;
+    volatile h264_dma_in_err_eof_des_addr_chn_reg_t err_eof_des_addr;
+    volatile h264_dma_in_dscr_chn_reg_t dscr;
+    volatile h264_dma_in_dscr_bf0_chn_reg_t dscr_bf0;
+    volatile h264_dma_in_dscr_bf1_chn_reg_t dscr_bf1;
     uint32_t reserved_53c;
-    volatile h264_dma_in_arb_ch0_reg_t in_arb_ch0;
+    volatile h264_dma_in_arb_chn_reg_t arb;
     uint32_t reserved_544;
-    volatile h264_dma_in_ro_pd_conf_ch0_reg_t in_ro_pd_conf_ch0;
+    volatile h264_dma_in_ro_pd_conf_chn_reg_t ro_pd_conf;
     uint32_t reserved_54c[8];
-    volatile h264_dma_in_etm_conf_ch0_reg_t in_etm_conf_ch0;
+    volatile h264_dma_in_etm_conf_chn_reg_t etm_conf;
     uint32_t reserved_570[4];
-    volatile h264_dma_in_fifo_cnt_ch0_reg_t in_fifo_cnt_ch0;
-    volatile h264_dma_in_pop_data_cnt_ch0_reg_t in_pop_data_cnt_ch0;
-    volatile h264_dma_in_xaddr_ch0_reg_t in_xaddr_ch0;
-    volatile h264_dma_in_buf_hb_rcv_ch0_reg_t in_buf_hb_rcv_ch0;
+    volatile h264_dma_in_fifo_cnt_chn_reg_t fifo_cnt;
+    volatile h264_dma_in_pop_data_cnt_chn_reg_t pop_data_cnt;
+    volatile h264_dma_in_xaddr_chn_reg_t xaddr;
+    volatile h264_dma_in_buf_hb_rcv_chn_reg_t buf_hb_rcv;
     uint32_t reserved_590[28];
-    volatile h264_dma_in_conf0_ch1_reg_t in_conf0_ch1;
-    volatile h264_dma_in_int_raw_ch1_reg_t in_int_raw_ch1;
-    volatile h264_dma_in_int_ena_ch1_reg_t in_int_ena_ch1;
-    volatile h264_dma_in_int_st_ch1_reg_t in_int_st_ch1;
-    volatile h264_dma_in_int_clr_ch1_reg_t in_int_clr_ch1;
-    volatile h264_dma_infifo_status_ch1_reg_t infifo_status_ch1;
-    volatile h264_dma_in_pop_ch1_reg_t in_pop_ch1;
-    volatile h264_dma_in_link_conf_ch1_reg_t in_link_conf_ch1;
-    volatile h264_dma_in_link_addr_ch1_reg_t in_link_addr_ch1;
-    volatile h264_dma_in_state_ch1_reg_t in_state_ch1;
-    volatile h264_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1;
-    volatile h264_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1;
-    volatile h264_dma_in_dscr_ch1_reg_t in_dscr_ch1;
-    volatile h264_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1;
-    volatile h264_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1;
-    uint32_t reserved_63c;
-    volatile h264_dma_in_arb_ch1_reg_t in_arb_ch1;
-    uint32_t reserved_644;
-    volatile h264_dma_in_etm_conf_ch1_reg_t in_etm_conf_ch1;
-    uint32_t reserved_64c[13];
-    volatile h264_dma_in_fifo_cnt_ch1_reg_t in_fifo_cnt_ch1;
-    volatile h264_dma_in_pop_data_cnt_ch1_reg_t in_pop_data_cnt_ch1;
-    volatile h264_dma_in_xaddr_ch1_reg_t in_xaddr_ch1;
-    volatile h264_dma_in_buf_hb_rcv_ch1_reg_t in_buf_hb_rcv_ch1;
-    uint32_t reserved_690[28];
-    volatile h264_dma_in_conf0_ch2_reg_t in_conf0_ch2;
-    volatile h264_dma_in_int_raw_ch2_reg_t in_int_raw_ch2;
-    volatile h264_dma_in_int_ena_ch2_reg_t in_int_ena_ch2;
-    volatile h264_dma_in_int_st_ch2_reg_t in_int_st_ch2;
-    volatile h264_dma_in_int_clr_ch2_reg_t in_int_clr_ch2;
-    volatile h264_dma_infifo_status_ch2_reg_t infifo_status_ch2;
-    volatile h264_dma_in_pop_ch2_reg_t in_pop_ch2;
-    volatile h264_dma_in_link_conf_ch2_reg_t in_link_conf_ch2;
-    volatile h264_dma_in_link_addr_ch2_reg_t in_link_addr_ch2;
-    volatile h264_dma_in_state_ch2_reg_t in_state_ch2;
-    volatile h264_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2;
-    volatile h264_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2;
-    volatile h264_dma_in_dscr_ch2_reg_t in_dscr_ch2;
-    volatile h264_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2;
-    volatile h264_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2;
-    uint32_t reserved_73c;
-    volatile h264_dma_in_arb_ch2_reg_t in_arb_ch2;
-    uint32_t reserved_744;
-    volatile h264_dma_in_etm_conf_ch2_reg_t in_etm_conf_ch2;
-    uint32_t reserved_74c[13];
-    volatile h264_dma_in_fifo_cnt_ch2_reg_t in_fifo_cnt_ch2;
-    volatile h264_dma_in_pop_data_cnt_ch2_reg_t in_pop_data_cnt_ch2;
-    volatile h264_dma_in_xaddr_ch2_reg_t in_xaddr_ch2;
-    volatile h264_dma_in_buf_hb_rcv_ch2_reg_t in_buf_hb_rcv_ch2;
-    uint32_t reserved_790[28];
-    volatile h264_dma_in_conf0_ch3_reg_t in_conf0_ch3;
-    volatile h264_dma_in_int_raw_ch3_reg_t in_int_raw_ch3;
-    volatile h264_dma_in_int_ena_ch3_reg_t in_int_ena_ch3;
-    volatile h264_dma_in_int_st_ch3_reg_t in_int_st_ch3;
-    volatile h264_dma_in_int_clr_ch3_reg_t in_int_clr_ch3;
-    volatile h264_dma_infifo_status_ch3_reg_t infifo_status_ch3;
-    volatile h264_dma_in_pop_ch3_reg_t in_pop_ch3;
-    volatile h264_dma_in_link_conf_ch3_reg_t in_link_conf_ch3;
-    volatile h264_dma_in_link_addr_ch3_reg_t in_link_addr_ch3;
-    volatile h264_dma_in_state_ch3_reg_t in_state_ch3;
-    volatile h264_dma_in_suc_eof_des_addr_ch3_reg_t in_suc_eof_des_addr_ch3;
-    volatile h264_dma_in_err_eof_des_addr_ch3_reg_t in_err_eof_des_addr_ch3;
-    volatile h264_dma_in_dscr_ch3_reg_t in_dscr_ch3;
-    volatile h264_dma_in_dscr_bf0_ch3_reg_t in_dscr_bf0_ch3;
-    volatile h264_dma_in_dscr_bf1_ch3_reg_t in_dscr_bf1_ch3;
-    uint32_t reserved_83c;
-    volatile h264_dma_in_arb_ch3_reg_t in_arb_ch3;
-    uint32_t reserved_844;
-    volatile h264_dma_in_etm_conf_ch3_reg_t in_etm_conf_ch3;
-    uint32_t reserved_84c[13];
-    volatile h264_dma_in_fifo_cnt_ch3_reg_t in_fifo_cnt_ch3;
-    volatile h264_dma_in_pop_data_cnt_ch3_reg_t in_pop_data_cnt_ch3;
-    volatile h264_dma_in_xaddr_ch3_reg_t in_xaddr_ch3;
-    volatile h264_dma_in_buf_hb_rcv_ch3_reg_t in_buf_hb_rcv_ch3;
-    uint32_t reserved_890[28];
-    volatile h264_dma_in_conf0_ch4_reg_t in_conf0_ch4;
-    volatile h264_dma_in_int_raw_ch4_reg_t in_int_raw_ch4;
-    volatile h264_dma_in_int_ena_ch4_reg_t in_int_ena_ch4;
-    volatile h264_dma_in_int_st_ch4_reg_t in_int_st_ch4;
-    volatile h264_dma_in_int_clr_ch4_reg_t in_int_clr_ch4;
-    volatile h264_dma_infifo_status_ch4_reg_t infifo_status_ch4;
-    volatile h264_dma_in_pop_ch4_reg_t in_pop_ch4;
-    volatile h264_dma_in_link_conf_ch4_reg_t in_link_conf_ch4;
-    volatile h264_dma_in_link_addr_ch4_reg_t in_link_addr_ch4;
-    volatile h264_dma_in_state_ch4_reg_t in_state_ch4;
-    volatile h264_dma_in_suc_eof_des_addr_ch4_reg_t in_suc_eof_des_addr_ch4;
-    volatile h264_dma_in_err_eof_des_addr_ch4_reg_t in_err_eof_des_addr_ch4;
-    volatile h264_dma_in_dscr_ch4_reg_t in_dscr_ch4;
-    volatile h264_dma_in_dscr_bf0_ch4_reg_t in_dscr_bf0_ch4;
-    volatile h264_dma_in_dscr_bf1_ch4_reg_t in_dscr_bf1_ch4;
-    uint32_t reserved_93c;
-    volatile h264_dma_in_arb_ch4_reg_t in_arb_ch4;
-    uint32_t reserved_944;
-    volatile h264_dma_in_etm_conf_ch4_reg_t in_etm_conf_ch4;
-    uint32_t reserved_94c[13];
-    volatile h264_dma_in_fifo_cnt_ch4_reg_t in_fifo_cnt_ch4;
-    volatile h264_dma_in_pop_data_cnt_ch4_reg_t in_pop_data_cnt_ch4;
-    volatile h264_dma_in_xaddr_ch4_reg_t in_xaddr_ch4;
-    volatile h264_dma_in_buf_hb_rcv_ch4_reg_t in_buf_hb_rcv_ch4;
-    uint32_t reserved_990[28];
-    volatile h264_dma_in_conf0_ch5_reg_t in_conf0_ch5;
-    volatile h264_dma_in_conf1_ch5_reg_t in_conf1_ch5;
-    volatile h264_dma_in_conf2_ch5_reg_t in_conf2_ch5;
-    volatile h264_dma_in_conf3_ch5_reg_t in_conf3_ch5;
-    volatile h264_dma_in_int_raw_ch5_reg_t in_int_raw_ch5;
-    volatile h264_dma_in_int_ena_ch5_reg_t in_int_ena_ch5;
-    volatile h264_dma_in_int_st_ch5_reg_t in_int_st_ch5;
-    volatile h264_dma_in_int_clr_ch5_reg_t in_int_clr_ch5;
-    volatile h264_dma_infifo_status_ch5_reg_t infifo_status_ch5;
-    volatile h264_dma_in_pop_ch5_reg_t in_pop_ch5;
-    volatile h264_dma_in_state_ch5_reg_t in_state_ch5;
+} h264_dma_in_chn_regs_t;
+
+typedef struct {
+    volatile h264_dma_in_conf0_ch5_reg_t conf0;
+    volatile h264_dma_in_conf1_ch5_reg_t conf1;
+    volatile h264_dma_in_conf2_ch5_reg_t conf2;
+    volatile h264_dma_in_conf3_ch5_reg_t conf3;
+    volatile h264_dma_in_int_raw_ch5_reg_t int_raw;
+    volatile h264_dma_in_int_ena_ch5_reg_t int_ena;
+    volatile h264_dma_in_int_st_ch5_reg_t int_st;
+    volatile h264_dma_in_int_clr_ch5_reg_t int_clr;
+    volatile h264_dma_infifo_status_ch5_reg_t infifo_status;
+    volatile h264_dma_in_pop_ch5_reg_t pop;
+    volatile h264_dma_in_state_ch5_reg_t state;
     uint32_t reserved_a2c[5];
-    volatile h264_dma_in_arb_ch5_reg_t in_arb_ch5;
+    volatile h264_dma_in_arb_ch5_reg_t arb;
     uint32_t reserved_a44[15];
-    volatile h264_dma_in_fifo_cnt_ch5_reg_t in_fifo_cnt_ch5;
-    volatile h264_dma_in_pop_data_cnt_ch5_reg_t in_pop_data_cnt_ch5;
-    volatile h264_dma_in_xaddr_ch5_reg_t in_xaddr_ch5;
-    volatile h264_dma_in_buf_hb_rcv_ch5_reg_t in_buf_hb_rcv_ch5;
+    volatile h264_dma_in_fifo_cnt_ch5_reg_t fifo_cnt;
+    volatile h264_dma_in_pop_data_cnt_ch5_reg_t pop_data_cnt;
+    volatile h264_dma_in_xaddr_ch5_reg_t xaddr;
+    volatile h264_dma_in_buf_hb_rcv_ch5_reg_t buf_hb_rcv;
     uint32_t reserved_a90[28];
+} h264_dma_in_ch5_regs_t;
+
+typedef struct {
+    volatile h264_dma_mem_start_addr_reg_t start;
+    volatile h264_dma_mem_end_addr_reg_t end;
+} h264_dma_mem_addr_reg_t;
+
+typedef struct {
+    volatile h264_dma_out_chn_regs_t dma_out_ch[5];
+    volatile h264_dma_in_chn_regs_t dma_in_ch[5];
+    volatile h264_dma_in_ch5_regs_t dma_in_ch5;
     volatile h264_dma_inter_axi_err_reg_t inter_axi_err;
     volatile h264_dma_exter_axi_err_reg_t exter_axi_err;
     volatile h264_dma_rst_conf_reg_t rst_conf;
-    volatile h264_dma_inter_mem_start_addr0_reg_t inter_mem_start_addr0;
-    volatile h264_dma_inter_mem_end_addr0_reg_t inter_mem_end_addr0;
-    volatile h264_dma_inter_mem_start_addr1_reg_t inter_mem_start_addr1;
-    volatile h264_dma_inter_mem_end_addr1_reg_t inter_mem_end_addr1;
+    volatile h264_dma_mem_addr_reg_t inter_mem_addr[2];
     uint32_t reserved_b1c;
-    volatile h264_dma_exter_mem_start_addr0_reg_t exter_mem_start_addr0;
-    volatile h264_dma_exter_mem_end_addr0_reg_t exter_mem_end_addr0;
-    volatile h264_dma_exter_mem_start_addr1_reg_t exter_mem_start_addr1;
-    volatile h264_dma_exter_mem_end_addr1_reg_t exter_mem_end_addr1;
-    volatile h264_dma_out_arb_config_reg_t out_arb_config;
-    volatile h264_dma_in_arb_config_reg_t in_arb_config;
+    volatile h264_dma_mem_addr_reg_t exter_mem_addr[2];
+    volatile h264_dma_arb_config_reg_t out_arb_config;
+    volatile h264_dma_arb_config_reg_t in_arb_config;
     uint32_t reserved_b38;
     volatile h264_dma_date_reg_t date;
     uint32_t reserved_b40[4];
diff --git a/components/soc/esp32p4/include/soc/h264_struct.h b/components/soc/esp32p4/include/soc/h264_struct.h
index c21ac4ef224..f45ebac7848 100644
--- a/components/soc/esp32p4/include/soc/h264_struct.h
+++ b/components/soc/esp32p4/include/soc/h264_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -63,1029 +63,286 @@ typedef union {
     uint32_t val;
 } h264_gop_conf_reg_t;
 
-/** Type of a_sys_mb_res register
+/** Type of sys_mb_res register
  *  Video A horizontal and vertical MB resolution register.
  */
 typedef union {
     struct {
-        /** a_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0;
+        /** sys_total_mb_y : R/W; bitpos: [6:0]; default: 0;
          *  Configures video A vertical MB resolution.
          */
-        uint32_t a_sys_total_mb_y:7;
-        /** a_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0;
+        uint32_t sys_total_mb_y:7;
+        /** sys_total_mb_x : R/W; bitpos: [13:7]; default: 0;
          *  Configures video A horizontal MB resolution.
          */
-        uint32_t a_sys_total_mb_x:7;
+        uint32_t sys_total_mb_x:7;
         uint32_t reserved_14:18;
     };
     uint32_t val;
-} h264_a_sys_mb_res_reg_t;
+} h264_sys_mb_res_reg_t;
 
-/** Type of a_sys_conf register
+/** Type of sys_conf register
  *  Video A system level configuration register.
  */
 typedef union {
     struct {
-        /** a_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3;
+        /** db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3;
          *  Configures when to trigger  video A H264_DB_TMP_READY_INT. When the (MB number of
          *  written db temp+1) is greater than this filed in first MB line, trigger
          *  H264_DB_TMP_READY_INT. Min is 3.
          */
-        uint32_t a_db_tmp_ready_trigger_mb_num:7;
-        /** a_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4;
+        uint32_t db_tmp_ready_trigger_mb_num:7;
+        /** rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4;
          *  Configures when to trigger  video A H264_REC_READY_INT. When the MB line number of
          *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
          *  Min is 4.
          */
-        uint32_t a_rec_ready_trigger_mb_lines:7;
-        /** a_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0;
+        uint32_t rec_ready_trigger_mb_lines:7;
+        /** intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0;
          *  Configures video A intra cost offset when I MB compared with P MB.
          */
-        uint32_t a_intra_cost_cmp_offset:16;
+        uint32_t intra_cost_cmp_offset:16;
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} h264_a_sys_conf_reg_t;
+} h264_sys_conf_reg_t;
 
-/** Type of a_deci_score register
+/** Type of deci_score register
  *  Video A luma and chroma MB decimate score Register.
  */
 typedef union {
     struct {
-        /** a_c_deci_score : R/W; bitpos: [9:0]; default: 0;
+        /** c_deci_score : R/W; bitpos: [9:0]; default: 0;
          *  Configures video A chroma MB decimate score. When chroma score is smaller than it,
          *  chroma decimate will be enable.
          */
-        uint32_t a_c_deci_score:10;
-        /** a_l_deci_score : R/W; bitpos: [19:10]; default: 0;
+        uint32_t c_deci_score:10;
+        /** l_deci_score : R/W; bitpos: [19:10]; default: 0;
          *  Configures video A luma MB decimate score. When luma score is smaller than it, luma
          *  decimate will be enable.
          */
-        uint32_t a_l_deci_score:10;
+        uint32_t l_deci_score:10;
         uint32_t reserved_20:12;
     };
     uint32_t val;
-} h264_a_deci_score_reg_t;
+} h264_deci_score_reg_t;
 
-/** Type of a_deci_score_offset register
+/** Type of deci_score_offset register
  *  Video A luma and chroma MB decimate score offset Register.
  */
 typedef union {
     struct {
-        /** a_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0;
+        /** i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0;
          *  Configures video A i16x16 MB decimate score offset. This offset will be added to
          *  i16x16 MB score.
          */
-        uint32_t a_i16x16_deci_score_offset:6;
-        /** a_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0;
+        uint32_t i16x16_deci_score_offset:6;
+        /** i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0;
          *  Configures video A I chroma MB decimate score offset. This offset will be added to
          *  I chroma MB score.
          */
-        uint32_t a_i_chroma_deci_score_offset:6;
-        /** a_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0;
+        uint32_t i_chroma_deci_score_offset:6;
+        /** p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0;
          *  Configures video A p16x16 MB decimate score offset. This offset will be added to
          *  p16x16 MB score.
          */
-        uint32_t a_p16x16_deci_score_offset:6;
-        /** a_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0;
+        uint32_t p16x16_deci_score_offset:6;
+        /** p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0;
          *  Configures video A p chroma MB decimate score offset. This offset will be added to
          *  p chroma MB score.
          */
-        uint32_t a_p_chroma_deci_score_offset:6;
+        uint32_t p_chroma_deci_score_offset:6;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} h264_a_deci_score_offset_reg_t;
+} h264_deci_score_offset_reg_t;
 
-/** Type of a_rc_conf0 register
+/** Type of rc_conf0 register
  *  Video A rate control configuration register0.
  */
 typedef union {
     struct {
-        /** a_qp : R/W; bitpos: [5:0]; default: 0;
+        /** qp : R/W; bitpos: [5:0]; default: 0;
          *  Configures video A frame level initial luma QP value.
          */
-        uint32_t a_qp:6;
-        /** a_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0;
+        uint32_t qp:6;
+        /** rate_ctrl_u : R/W; bitpos: [21:6]; default: 0;
          *  Configures video A parameter U value. U = int((float) u << 8).
          */
-        uint32_t a_rate_ctrl_u:16;
-        /** a_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0;
+        uint32_t rate_ctrl_u:16;
+        /** mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0;
          *  Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro
          *  block rate ctrl\\1:Close the macro block rate ctrl.
          */
-        uint32_t a_mb_rate_ctrl_en:1;
+        uint32_t mb_rate_ctrl_en:1;
         uint32_t reserved_23:9;
     };
     uint32_t val;
-} h264_a_rc_conf0_reg_t;
+} h264_rc_conf0_reg_t;
 
-/** Type of a_rc_conf1 register
+/** Type of rc_conf1 register
  *  Video A rate control configuration register1.
  */
 typedef union {
     struct {
-        /** a_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0;
+        /** chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0;
          *  Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
          *  QP(after map) + reg_chroma_dc_qp_delta.
          */
-        uint32_t a_chroma_dc_qp_delta:3;
-        /** a_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0;
+        uint32_t chroma_dc_qp_delta:3;
+        /** chroma_qp_delta : R/W; bitpos: [6:3]; default: 0;
          *  Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma
          *  QP + reg_chroma_qp_delta.
          */
-        uint32_t a_chroma_qp_delta:4;
-        /** a_qp_min : R/W; bitpos: [12:7]; default: 0;
+        uint32_t chroma_qp_delta:4;
+        /** qp_min : R/W; bitpos: [12:7]; default: 0;
          *  Configures video A allowed luma QP min value.
          */
-        uint32_t a_qp_min:6;
-        /** a_qp_max : R/W; bitpos: [18:13]; default: 0;
+        uint32_t qp_min:6;
+        /** qp_max : R/W; bitpos: [18:13]; default: 0;
          *  Configures video A allowed luma QP max value.
          */
-        uint32_t a_qp_max:6;
-        /** a_mad_frame_pred : R/W; bitpos: [30:19]; default: 0;
+        uint32_t qp_max:6;
+        /** mad_frame_pred : R/W; bitpos: [30:19]; default: 0;
          *  Configures vdieo A frame level predicted MB MAD value.
          */
-        uint32_t a_mad_frame_pred:12;
+        uint32_t mad_frame_pred:12;
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} h264_a_rc_conf1_reg_t;
+} h264_rc_conf1_reg_t;
 
-/** Type of a_db_bypass register
+/** Type of db_bypass register
  *  Video A Deblocking bypass register
  */
 typedef union {
     struct {
-        /** a_bypass_db_filter : R/W; bitpos: [0]; default: 0;
+        /** bypass_db_filter : R/W; bitpos: [0]; default: 0;
          *  Configures whether or not to bypass video A deblcoking filter. \\0: Open the
          *  deblock filter\\1: Close the deblock filter
          */
-        uint32_t a_bypass_db_filter:1;
+        uint32_t bypass_db_filter:1;
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} h264_a_db_bypass_reg_t;
+} h264_db_bypass_reg_t;
 
-/** Type of a_roi_region0 register
- *  Video A H264 ROI region0 range configure register.
+/** Type of roi_region register
+ *  Video A H264 ROI region range configure register.
  */
 typedef union {
     struct {
-        /** a_roi_region0_x : R/W; bitpos: [6:0]; default: 0;
+        /** roi_region_x : R/W; bitpos: [6:0]; default: 0;
          *  Configures the horizontal start macroblocks of region 0 in Video A.
          */
-        uint32_t a_roi_region0_x:7;
-        /** a_roi_region0_y : R/W; bitpos: [13:7]; default: 0;
+        uint32_t roi_region_x:7;
+        /** roi_region_y : R/W; bitpos: [13:7]; default: 0;
          *  Configures the  vertical start macroblocks of region 0 in Video A.
          */
-        uint32_t a_roi_region0_y:7;
-        /** a_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0;
+        uint32_t roi_region_y:7;
+        /** roi_region_x_len : R/W; bitpos: [20:14]; default: 0;
          *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
          *  Video A.
          */
-        uint32_t a_roi_region0_x_len:7;
-        /** a_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0;
+        uint32_t roi_region_x_len:7;
+        /** roi_region_y_len : R/W; bitpos: [27:21]; default: 0;
          *  Configures the number of  macroblocks in vertical direction of  the region 0 in
          *  Video A.
          */
-        uint32_t a_roi_region0_y_len:7;
-        /** a_roi_region0_en : R/W; bitpos: [28]; default: 0;
+        uint32_t roi_region_y_len:7;
+        /** roi_region_en : R/W; bitpos: [28]; default: 0;
          *  Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open
          *  ROI.
          */
-        uint32_t a_roi_region0_en:1;
+        uint32_t roi_region_en:1;
         uint32_t reserved_29:3;
     };
     uint32_t val;
-} h264_a_roi_region0_reg_t;
+} h264_roi_region_reg_t;
 
-/** Type of a_roi_region1 register
- *  Video A H264 ROI region1 range configure register.
- */
-typedef union {
-    struct {
-        /** a_roi_region1_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 1 in Video A.
-         */
-        uint32_t a_roi_region1_x:7;
-        /** a_roi_region1_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 1 in Video A.
-         */
-        uint32_t a_roi_region1_y:7;
-        /** a_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
-         *  Video A.
-         */
-        uint32_t a_roi_region1_x_len:7;
-        /** a_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 1 in
-         *  Video A.
-         */
-        uint32_t a_roi_region1_y_len:7;
-        /** a_roi_region1_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t a_roi_region1_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_a_roi_region1_reg_t;
-
-/** Type of a_roi_region2 register
- *  Video A H264 ROI region2 range configure register.
- */
-typedef union {
-    struct {
-        /** a_roi_region2_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 2 in Video A.
-         */
-        uint32_t a_roi_region2_x:7;
-        /** a_roi_region2_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 2 in Video A.
-         */
-        uint32_t a_roi_region2_y:7;
-        /** a_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
-         *  Video A.
-         */
-        uint32_t a_roi_region2_x_len:7;
-        /** a_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 2 in
-         *  Video A.
-         */
-        uint32_t a_roi_region2_y_len:7;
-        /** a_roi_region2_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t a_roi_region2_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_a_roi_region2_reg_t;
-
-/** Type of a_roi_region3 register
- *  Video A H264 ROI region3 range configure register.
- */
-typedef union {
-    struct {
-        /** a_roi_region3_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 3 in Video A.
-         */
-        uint32_t a_roi_region3_x:7;
-        /** a_roi_region3_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 3 in Video A.
-         */
-        uint32_t a_roi_region3_y:7;
-        /** a_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
-         *  video A.
-         */
-        uint32_t a_roi_region3_x_len:7;
-        /** a_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 3 in
-         *  video A.
-         */
-        uint32_t a_roi_region3_y_len:7;
-        /** a_roi_region3_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t a_roi_region3_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_a_roi_region3_reg_t;
-
-/** Type of a_roi_region4 register
- *  Video A H264 ROI region4 range configure register.
- */
-typedef union {
-    struct {
-        /** a_roi_region4_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 4 in Video A.
-         */
-        uint32_t a_roi_region4_x:7;
-        /** a_roi_region4_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 4 in Video A.
-         */
-        uint32_t a_roi_region4_y:7;
-        /** a_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
-         *  video A.
-         */
-        uint32_t a_roi_region4_x_len:7;
-        /** a_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 4 in
-         *  video A.
-         */
-        uint32_t a_roi_region4_y_len:7;
-        /** a_roi_region4_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t a_roi_region4_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_a_roi_region4_reg_t;
-
-/** Type of a_roi_region5 register
- *  Video A H264 ROI region5 range configure register.
- */
-typedef union {
-    struct {
-        /** a_roi_region5_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontial start macroblocks of region 5 video A.
-         */
-        uint32_t a_roi_region5_x:7;
-        /** a_roi_region5_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 5 video A.
-         */
-        uint32_t a_roi_region5_y:7;
-        /** a_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 5
-         *  video A.
-         */
-        uint32_t a_roi_region5_x_len:7;
-        /** a_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 5 in
-         *  video A.
-         */
-        uint32_t a_roi_region5_y_len:7;
-        /** a_roi_region5_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t a_roi_region5_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_a_roi_region5_reg_t;
-
-/** Type of a_roi_region6 register
- *  Video A H264 ROI region6 range configure register.
- */
-typedef union {
-    struct {
-        /** a_roi_region6_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontial start macroblocks of region 6 video A.
-         */
-        uint32_t a_roi_region6_x:7;
-        /** a_roi_region6_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 6 in video A.
-         */
-        uint32_t a_roi_region6_y:7;
-        /** a_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
-         *  video A.
-         */
-        uint32_t a_roi_region6_x_len:7;
-        /** a_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 6 in
-         *  video A.
-         */
-        uint32_t a_roi_region6_y_len:7;
-        /** a_roi_region6_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t a_roi_region6_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_a_roi_region6_reg_t;
-
-/** Type of a_roi_region7 register
- *  Video A H264 ROI region7 range configure register.
- */
-typedef union {
-    struct {
-        /** a_roi_region7_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 7 in video A.
-         */
-        uint32_t a_roi_region7_x:7;
-        /** a_roi_region7_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 7 in video A.
-         */
-        uint32_t a_roi_region7_y:7;
-        /** a_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
-         *  video A.
-         */
-        uint32_t a_roi_region7_x_len:7;
-        /** a_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 7 in
-         *  video A.
-         */
-        uint32_t a_roi_region7_y_len:7;
-        /** a_roi_region7_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t a_roi_region7_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_a_roi_region7_reg_t;
-
-/** Type of a_roi_region0_3_qp register
+/** Type of roi_region0_3_qp register
  *  Video A H264 ROI region0, region1,region2,region3 QP register.
  */
 typedef union {
     struct {
-        /** a_roi_region0_qp : R/W; bitpos: [6:0]; default: 0;
+        /** roi_region0_qp : R/W; bitpos: [6:0]; default: 0;
          *  Configure H264 ROI region0 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region0_qp:7;
-        /** a_roi_region1_qp : R/W; bitpos: [13:7]; default: 0;
+        uint32_t roi_region0_qp:7;
+        /** roi_region1_qp : R/W; bitpos: [13:7]; default: 0;
          *  Configure H264 ROI region1 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region1_qp:7;
-        /** a_roi_region2_qp : R/W; bitpos: [20:14]; default: 0;
+        uint32_t roi_region1_qp:7;
+        /** roi_region2_qp : R/W; bitpos: [20:14]; default: 0;
          *  Configure H264 ROI region2 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region2_qp:7;
-        /** a_roi_region3_qp : R/W; bitpos: [27:21]; default: 0;
+        uint32_t roi_region2_qp:7;
+        /** roi_region3_qp : R/W; bitpos: [27:21]; default: 0;
          *  Configure H264 ROI region3 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region3_qp:7;
+        uint32_t roi_region3_qp:7;
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} h264_a_roi_region0_3_qp_reg_t;
+} h264_roi_region0_3_qp_reg_t;
 
-/** Type of a_roi_region4_7_qp register
+/** Type of roi_region4_7_qp register
  *  Video A H264 ROI region4, region5,region6,region7 QP register.
  */
 typedef union {
     struct {
-        /** a_roi_region4_qp : R/W; bitpos: [6:0]; default: 0;
+        /** roi_region4_qp : R/W; bitpos: [6:0]; default: 0;
          *  Configure H264 ROI region4 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region4_qp:7;
-        /** a_roi_region5_qp : R/W; bitpos: [13:7]; default: 0;
+        uint32_t roi_region4_qp:7;
+        /** roi_region5_qp : R/W; bitpos: [13:7]; default: 0;
          *  Configure H264 ROI region5 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region5_qp:7;
-        /** a_roi_region6_qp : R/W; bitpos: [20:14]; default: 0;
+        uint32_t roi_region5_qp:7;
+        /** roi_region6_qp : R/W; bitpos: [20:14]; default: 0;
          *  Configure H264 ROI region6 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region6_qp:7;
-        /** a_roi_region7_qp : R/W; bitpos: [27:21]; default: 0;
+        uint32_t roi_region6_qp:7;
+        /** roi_region7_qp : R/W; bitpos: [27:21]; default: 0;
          *  Configure H264 ROI region7 qp in video A,fixed qp or delta qp.
          */
-        uint32_t a_roi_region7_qp:7;
+        uint32_t roi_region7_qp:7;
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} h264_a_roi_region4_7_qp_reg_t;
+} h264_roi_region4_7_qp_reg_t;
 
-/** Type of a_no_roi_region_qp_offset register
+/** Type of no_roi_region_qp_offset register
  *  Video A H264 no roi region QP register.
  */
 typedef union {
     struct {
-        /** a_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0;
+        /** no_roi_region_qp : R/W; bitpos: [6:0]; default: 0;
          *  Configure H264 no region qp in video A, delta qp.
          */
-        uint32_t a_no_roi_region_qp:7;
+        uint32_t no_roi_region_qp:7;
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} h264_a_no_roi_region_qp_offset_reg_t;
+} h264_no_roi_region_qp_offset_reg_t;
 
-/** Type of a_roi_config register
+/** Type of roi_config register
  *  Video A H264 ROI configure register.
  */
 typedef union {
     struct {
-        /** a_roi_en : R/W; bitpos: [0]; default: 0;
+        /** roi_en : R/W; bitpos: [0]; default: 0;
          *  Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI.
          */
-        uint32_t a_roi_en:1;
-        /** a_roi_mode : R/W; bitpos: [1]; default: 0;
+        uint32_t roi_en:1;
+        /** roi_mode : R/W; bitpos: [1]; default: 0;
          *  Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp.
          */
-        uint32_t a_roi_mode:1;
+        uint32_t roi_mode:1;
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} h264_a_roi_config_reg_t;
-
-/** Type of b_sys_mb_res register
- *  Video B horizontal and vertical MB resolution register.
- */
-typedef union {
-    struct {
-        /** b_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0;
-         *  Configures video B vertical MB resolution.
-         */
-        uint32_t b_sys_total_mb_y:7;
-        /** b_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0;
-         *  Configures video B horizontal MB resolution.
-         */
-        uint32_t b_sys_total_mb_x:7;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} h264_b_sys_mb_res_reg_t;
-
-/** Type of b_sys_conf register
- *  Video B system level configuration register.
- */
-typedef union {
-    struct {
-        /** b_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3;
-         *  Configures when to trigger  video B H264_DB_TMP_READY_INT. When the (MB number of
-         *  written db temp+1) is greater than this filed in first MB line, trigger
-         *  H264_DB_TMP_READY_INT. Min is 3.
-         */
-        uint32_t b_db_tmp_ready_trigger_mb_num:7;
-        /** b_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4;
-         *  Configures when to trigger  video B H264_REC_READY_INT. When the MB line number of
-         *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
-         *  Min is 4.
-         */
-        uint32_t b_rec_ready_trigger_mb_lines:7;
-        /** b_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0;
-         *  Configures video B intra cost offset when I MB compared with P MB.
-         */
-        uint32_t b_intra_cost_cmp_offset:16;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} h264_b_sys_conf_reg_t;
-
-/** Type of b_deci_score register
- *  Video B luma and chroma MB decimate score Register.
- */
-typedef union {
-    struct {
-        /** b_c_deci_score : R/W; bitpos: [9:0]; default: 0;
-         *  Configures video B chroma MB decimate score. When chroma score is smaller than it,
-         *  chroma decimate will be enable.
-         */
-        uint32_t b_c_deci_score:10;
-        /** b_l_deci_score : R/W; bitpos: [19:10]; default: 0;
-         *  Configures video B luma MB decimate score. When luma score is smaller than it, luma
-         *  decimate will be enable.
-         */
-        uint32_t b_l_deci_score:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} h264_b_deci_score_reg_t;
-
-/** Type of b_deci_score_offset register
- *  Video B luma and chroma MB decimate score offset Register.
- */
-typedef union {
-    struct {
-        /** b_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0;
-         *  Configures video B i16x16 MB decimate score offset. This offset will be added to
-         *  i16x16 MB score.
-         */
-        uint32_t b_i16x16_deci_score_offset:6;
-        /** b_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0;
-         *  Configures video B I chroma MB decimate score offset. This offset will be added to
-         *  I chroma MB score.
-         */
-        uint32_t b_i_chroma_deci_score_offset:6;
-        /** b_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0;
-         *  Configures video B p16x16 MB decimate score offset. This offset will be added to
-         *  p16x16 MB score.
-         */
-        uint32_t b_p16x16_deci_score_offset:6;
-        /** b_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0;
-         *  Configures video B p chroma MB decimate score offset. This offset will be added to
-         *  p chroma MB score.
-         */
-        uint32_t b_p_chroma_deci_score_offset:6;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} h264_b_deci_score_offset_reg_t;
-
-/** Type of b_rc_conf0 register
- *  Video B rate control configuration register0.
- */
-typedef union {
-    struct {
-        /** b_qp : R/W; bitpos: [5:0]; default: 0;
-         *  Configures video B frame level initial luma QP value.
-         */
-        uint32_t b_qp:6;
-        /** b_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0;
-         *  Configures video B parameter U value. U = int((float) u << 8).
-         */
-        uint32_t b_rate_ctrl_u:16;
-        /** b_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0;
-         *  Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro
-         *  block rate ctrl\\1:Close the macro block rate ctrl.
-         */
-        uint32_t b_mb_rate_ctrl_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} h264_b_rc_conf0_reg_t;
-
-/** Type of b_rc_conf1 register
- *  Video B rate control configuration register1.
- */
-typedef union {
-    struct {
-        /** b_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0;
-         *  Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
-         *  QP(after map) + reg_chroma_dc_qp_delta.
-         */
-        uint32_t b_chroma_dc_qp_delta:3;
-        /** b_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0;
-         *  Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma
-         *  QP + reg_chroma_qp_delta.
-         */
-        uint32_t b_chroma_qp_delta:4;
-        /** b_qp_min : R/W; bitpos: [12:7]; default: 0;
-         *  Configures video B allowed luma QP min value.
-         */
-        uint32_t b_qp_min:6;
-        /** b_qp_max : R/W; bitpos: [18:13]; default: 0;
-         *  Configures video B allowed luma QP max value.
-         */
-        uint32_t b_qp_max:6;
-        /** b_mad_frame_pred : R/W; bitpos: [30:19]; default: 0;
-         *  Configures vdieo B frame level predicted MB MAD value.
-         */
-        uint32_t b_mad_frame_pred:12;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} h264_b_rc_conf1_reg_t;
-
-/** Type of b_db_bypass register
- *  Video B Deblocking bypass register
- */
-typedef union {
-    struct {
-        /** b_bypass_db_filter : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to bypass video B deblcoking filter. \\0: Open the
-         *  deblock filter\\1: Close the deblock filter
-         */
-        uint32_t b_bypass_db_filter:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} h264_b_db_bypass_reg_t;
-
-/** Type of b_roi_region0 register
- *  Video B H264 ROI region0 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region0_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 0 in Video B.
-         */
-        uint32_t b_roi_region0_x:7;
-        /** b_roi_region0_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 0 in Video B.
-         */
-        uint32_t b_roi_region0_y:7;
-        /** b_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
-         *  Video B.
-         */
-        uint32_t b_roi_region0_x_len:7;
-        /** b_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 0 in
-         *  Video B.
-         */
-        uint32_t b_roi_region0_y_len:7;
-        /** b_roi_region0_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region0_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region0_reg_t;
-
-/** Type of b_roi_region1 register
- *  Video B H264 ROI region1 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region1_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 1 in Video B.
-         */
-        uint32_t b_roi_region1_x:7;
-        /** b_roi_region1_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 1 in Video B.
-         */
-        uint32_t b_roi_region1_y:7;
-        /** b_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
-         *  Video B.
-         */
-        uint32_t b_roi_region1_x_len:7;
-        /** b_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 1 in
-         *  Video B.
-         */
-        uint32_t b_roi_region1_y_len:7;
-        /** b_roi_region1_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region1_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region1_reg_t;
-
-/** Type of b_roi_region2 register
- *  Video B H264 ROI region2 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region2_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 2 in Video B.
-         */
-        uint32_t b_roi_region2_x:7;
-        /** b_roi_region2_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 2 in Video B.
-         */
-        uint32_t b_roi_region2_y:7;
-        /** b_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
-         *  Video B.
-         */
-        uint32_t b_roi_region2_x_len:7;
-        /** b_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 2 in
-         *  Video B.
-         */
-        uint32_t b_roi_region2_y_len:7;
-        /** b_roi_region2_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region2_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region2_reg_t;
-
-/** Type of b_roi_region3 register
- *  Video B H264 ROI region3 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region3_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 3 in Video B.
-         */
-        uint32_t b_roi_region3_x:7;
-        /** b_roi_region3_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 3 in Video B.
-         */
-        uint32_t b_roi_region3_y:7;
-        /** b_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
-         *  video B.
-         */
-        uint32_t b_roi_region3_x_len:7;
-        /** b_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 3 in
-         *  video B.
-         */
-        uint32_t b_roi_region3_y_len:7;
-        /** b_roi_region3_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region3_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region3_reg_t;
-
-/** Type of b_roi_region4 register
- *  Video B H264 ROI region4 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region4_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 4 in Video B.
-         */
-        uint32_t b_roi_region4_x:7;
-        /** b_roi_region4_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 4 in Video B.
-         */
-        uint32_t b_roi_region4_y:7;
-        /** b_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
-         *  video B.
-         */
-        uint32_t b_roi_region4_x_len:7;
-        /** b_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 4 in
-         *  video B.
-         */
-        uint32_t b_roi_region4_y_len:7;
-        /** b_roi_region4_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region4_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region4_reg_t;
-
-/** Type of b_roi_region5 register
- *  Video B H264 ROI region5 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region5_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontial start macroblocks of region 5 video B.
-         */
-        uint32_t b_roi_region5_x:7;
-        /** b_roi_region5_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 5 video B.
-         */
-        uint32_t b_roi_region5_y:7;
-        /** b_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 5
-         *  video B.
-         */
-        uint32_t b_roi_region5_x_len:7;
-        /** b_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 5 in
-         *  video B.
-         */
-        uint32_t b_roi_region5_y_len:7;
-        /** b_roi_region5_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region5_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region5_reg_t;
-
-/** Type of b_roi_region6 register
- *  Video B H264 ROI region6 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region6_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontial start macroblocks of region 6 video B.
-         */
-        uint32_t b_roi_region6_x:7;
-        /** b_roi_region6_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 6 in video B.
-         */
-        uint32_t b_roi_region6_y:7;
-        /** b_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
-         *  video B.
-         */
-        uint32_t b_roi_region6_x_len:7;
-        /** b_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 6 in
-         *  video B.
-         */
-        uint32_t b_roi_region6_y_len:7;
-        /** b_roi_region6_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region6_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region6_reg_t;
-
-/** Type of b_roi_region7 register
- *  Video B H264 ROI region7 range configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_region7_x : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the horizontal start macroblocks of region 7 in video B.
-         */
-        uint32_t b_roi_region7_x:7;
-        /** b_roi_region7_y : R/W; bitpos: [13:7]; default: 0;
-         *  Configures the  vertical start macroblocks of region 7 in video B.
-         */
-        uint32_t b_roi_region7_y:7;
-        /** b_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0;
-         *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
-         *  video B.
-         */
-        uint32_t b_roi_region7_x_len:7;
-        /** b_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0;
-         *  Configures the number of  macroblocks in vertical direction of  the region 7 in
-         *  video B.
-         */
-        uint32_t b_roi_region7_y_len:7;
-        /** b_roi_region7_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open
-         *  ROI.
-         */
-        uint32_t b_roi_region7_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} h264_b_roi_region7_reg_t;
-
-/** Type of b_roi_region0_3_qp register
- *  Video B H264 ROI region0, region1,region2,region3 QP register.
- */
-typedef union {
-    struct {
-        /** b_roi_region0_qp : R/W; bitpos: [6:0]; default: 0;
-         *  Configure H264 ROI region0 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region0_qp:7;
-        /** b_roi_region1_qp : R/W; bitpos: [13:7]; default: 0;
-         *  Configure H264 ROI region1 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region1_qp:7;
-        /** b_roi_region2_qp : R/W; bitpos: [20:14]; default: 0;
-         *  Configure H264 ROI region2 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region2_qp:7;
-        /** b_roi_region3_qp : R/W; bitpos: [27:21]; default: 0;
-         *  Configure H264 ROI region3 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region3_qp:7;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} h264_b_roi_region0_3_qp_reg_t;
-
-/** Type of b_roi_region4_7_qp register
- *  Video B H264 ROI region4, region5,region6,region7 QP register.
- */
-typedef union {
-    struct {
-        /** b_roi_region4_qp : R/W; bitpos: [6:0]; default: 0;
-         *  Configure H264 ROI region4 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region4_qp:7;
-        /** b_roi_region5_qp : R/W; bitpos: [13:7]; default: 0;
-         *  Configure H264 ROI region5 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region5_qp:7;
-        /** b_roi_region6_qp : R/W; bitpos: [20:14]; default: 0;
-         *  Configure H264 ROI region6 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region6_qp:7;
-        /** b_roi_region7_qp : R/W; bitpos: [27:21]; default: 0;
-         *  Configure H264 ROI region7 qp in video B,fixed qp or delta qp.
-         */
-        uint32_t b_roi_region7_qp:7;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} h264_b_roi_region4_7_qp_reg_t;
-
-/** Type of b_no_roi_region_qp_offset register
- *  Video B H264 no roi region QP register.
- */
-typedef union {
-    struct {
-        /** b_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0;
-         *  Configure H264 no region qp in video B, delta qp.
-         */
-        uint32_t b_no_roi_region_qp:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} h264_b_no_roi_region_qp_offset_reg_t;
-
-/** Type of b_roi_config register
- *  Video B H264 ROI configure register.
- */
-typedef union {
-    struct {
-        /** b_roi_en : R/W; bitpos: [0]; default: 0;
-         *  Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI.
-         */
-        uint32_t b_roi_en:1;
-        /** b_roi_mode : R/W; bitpos: [1]; default: 0;
-         *  Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp.
-         */
-        uint32_t b_roi_mode:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} h264_b_roi_config_reg_t;
+} h264_roi_config_reg_t;
 
 /** Type of slice_header_remain register
  *  Frame Slice Header remain bit register.
@@ -1134,31 +391,18 @@ typedef union {
     uint32_t val;
 } h264_bs_threshold_reg_t;
 
-/** Type of slice_header_byte0 register
- *  Frame Slice Header byte low 32 bit  register.
+/** Type of slice_header_byte register
+ *  Frame Slice Header byte 32 bit register.
  */
 typedef union {
     struct {
-        /** slice_byte_lsb : R/W; bitpos: [31:0]; default: 0;
-         *  Configures Slice Header low 32 bit
+        /** byte : R/W; bitpos: [31:0]; default: 0;
+         *  Configures Slice Header 32 bit
          */
-        uint32_t slice_byte_lsb:32;
+        uint32_t byte:32;
     };
     uint32_t val;
-} h264_slice_header_byte0_reg_t;
-
-/** Type of slice_header_byte1 register
- *  Frame Slice Header byte high 32 bit  register.
- */
-typedef union {
-    struct {
-        /** slice_byte_msb : R/W; bitpos: [31:0]; default: 0;
-         *  Configures Slice Header high 32 bit
-         */
-        uint32_t slice_byte_msb:32;
-    };
-    uint32_t val;
-} h264_slice_header_byte1_reg_t;
+} h264_slice_header_reg_t;
 
 /** Type of conf register
  *  General configuration register.
@@ -1742,55 +986,32 @@ typedef union {
 } h264_date_reg_t;
 
 
+typedef struct {
+    volatile h264_sys_mb_res_reg_t sys_mb_res;
+    volatile h264_sys_conf_reg_t sys_conf;
+    volatile h264_deci_score_reg_t deci_score;
+    volatile h264_deci_score_offset_reg_t deci_score_offset;
+    volatile h264_rc_conf0_reg_t rc_conf0;
+    volatile h264_rc_conf1_reg_t rc_conf1;
+    volatile h264_db_bypass_reg_t db_bypass;
+    volatile h264_roi_region_reg_t roi_region[8];
+    volatile h264_roi_region0_3_qp_reg_t roi_region0_3_qp;
+    volatile h264_roi_region4_7_qp_reg_t roi_region4_7_qp;
+    volatile h264_no_roi_region_qp_offset_reg_t no_roi_region_qp_offset;
+    volatile h264_roi_config_reg_t roi_config;
+} h264_ctrl_regs_t;
+
 typedef struct {
     volatile h264_sys_ctrl_reg_t sys_ctrl;
     volatile h264_gop_conf_reg_t gop_conf;
-    volatile h264_a_sys_mb_res_reg_t a_sys_mb_res;
-    volatile h264_a_sys_conf_reg_t a_sys_conf;
-    volatile h264_a_deci_score_reg_t a_deci_score;
-    volatile h264_a_deci_score_offset_reg_t a_deci_score_offset;
-    volatile h264_a_rc_conf0_reg_t a_rc_conf0;
-    volatile h264_a_rc_conf1_reg_t a_rc_conf1;
-    volatile h264_a_db_bypass_reg_t a_db_bypass;
-    volatile h264_a_roi_region0_reg_t a_roi_region0;
-    volatile h264_a_roi_region1_reg_t a_roi_region1;
-    volatile h264_a_roi_region2_reg_t a_roi_region2;
-    volatile h264_a_roi_region3_reg_t a_roi_region3;
-    volatile h264_a_roi_region4_reg_t a_roi_region4;
-    volatile h264_a_roi_region5_reg_t a_roi_region5;
-    volatile h264_a_roi_region6_reg_t a_roi_region6;
-    volatile h264_a_roi_region7_reg_t a_roi_region7;
-    volatile h264_a_roi_region0_3_qp_reg_t a_roi_region0_3_qp;
-    volatile h264_a_roi_region4_7_qp_reg_t a_roi_region4_7_qp;
-    volatile h264_a_no_roi_region_qp_offset_reg_t a_no_roi_region_qp_offset;
-    volatile h264_a_roi_config_reg_t a_roi_config;
-    volatile h264_b_sys_mb_res_reg_t b_sys_mb_res;
-    volatile h264_b_sys_conf_reg_t b_sys_conf;
-    volatile h264_b_deci_score_reg_t b_deci_score;
-    volatile h264_b_deci_score_offset_reg_t b_deci_score_offset;
-    volatile h264_b_rc_conf0_reg_t b_rc_conf0;
-    volatile h264_b_rc_conf1_reg_t b_rc_conf1;
-    volatile h264_b_db_bypass_reg_t b_db_bypass;
-    volatile h264_b_roi_region0_reg_t b_roi_region0;
-    volatile h264_b_roi_region1_reg_t b_roi_region1;
-    volatile h264_b_roi_region2_reg_t b_roi_region2;
-    volatile h264_b_roi_region3_reg_t b_roi_region3;
-    volatile h264_b_roi_region4_reg_t b_roi_region4;
-    volatile h264_b_roi_region5_reg_t b_roi_region5;
-    volatile h264_b_roi_region6_reg_t b_roi_region6;
-    volatile h264_b_roi_region7_reg_t b_roi_region7;
-    volatile h264_b_roi_region0_3_qp_reg_t b_roi_region0_3_qp;
-    volatile h264_b_roi_region4_7_qp_reg_t b_roi_region4_7_qp;
-    volatile h264_b_no_roi_region_qp_offset_reg_t b_no_roi_region_qp_offset;
-    volatile h264_b_roi_config_reg_t b_roi_config;
+    volatile h264_ctrl_regs_t ctrl[2];
     volatile h264_rc_status0_reg_t rc_status0;
     volatile h264_rc_status1_reg_t rc_status1;
     volatile h264_rc_status2_reg_t rc_status2;
     volatile h264_slice_header_remain_reg_t slice_header_remain;
     volatile h264_slice_header_byte_length_reg_t slice_header_byte_length;
     volatile h264_bs_threshold_reg_t bs_threshold;
-    volatile h264_slice_header_byte0_reg_t slice_header_byte0;
-    volatile h264_slice_header_byte1_reg_t slice_header_byte1;
+    volatile h264_slice_header_reg_t slice_header[2];
     volatile h264_int_raw_reg_t int_raw;
     volatile h264_int_st_reg_t int_st;
     volatile h264_int_ena_reg_t int_ena;
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index 6db49e7d849..f4391a63242 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -577,6 +577,7 @@
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT                (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                  (1)
+#define SOC_TEMPERATURE_SENSOR_IS_INDEPENDENT_FROM_ADC       (1)  /*!< Temperature sensor is a separate module, not share regs with ADC */
 
 /*-------------------------- Memory CAPS --------------------------*/
 #define SOC_MEM_TCM_SUPPORTED    (1)
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
index 09829c5cdc0..e3bfc692140 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
+++ b/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
index 3d002460034..b78578c0825 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
+++ b/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -393,10 +393,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0;
+        /** usr_mosi_bit_len : R/W; bitpos: [9:0]; default: 0;
          *  The length in bits of write-data. The register value shall be (bit_num-1).
          */
-        uint32_t usr_mosi_dbitlen:10;
+        uint32_t usr_mosi_bit_len:10;
         uint32_t reserved_10:22;
     };
     uint32_t val;
@@ -407,10 +407,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0;
+        /** usr_miso_bit_len : R/W; bitpos: [9:0]; default: 0;
          *  The length in bits of  read-data. The register value shall be (bit_num-1).
          */
-        uint32_t usr_miso_dbitlen:10;
+        uint32_t usr_miso_bit_len:10;
         uint32_t reserved_10:22;
     };
     uint32_t val;
@@ -807,217 +807,6 @@ typedef union {
     uint32_t val;
 } spi1_mem_c_tx_crc_reg_t;
 
-
-/** Group: Memory data buffer register */
-/** Type of w0 register
- *  SPI1 memory data buffer0
- */
-typedef union {
-    struct {
-        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf0:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w0_reg_t;
-
-/** Type of w1 register
- *  SPI1 memory data buffer1
- */
-typedef union {
-    struct {
-        /** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf1:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w1_reg_t;
-
-/** Type of w2 register
- *  SPI1 memory data buffer2
- */
-typedef union {
-    struct {
-        /** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf2:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w2_reg_t;
-
-/** Type of w3 register
- *  SPI1 memory data buffer3
- */
-typedef union {
-    struct {
-        /** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf3:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w3_reg_t;
-
-/** Type of w4 register
- *  SPI1 memory data buffer4
- */
-typedef union {
-    struct {
-        /** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf4:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w4_reg_t;
-
-/** Type of w5 register
- *  SPI1 memory data buffer5
- */
-typedef union {
-    struct {
-        /** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf5:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w5_reg_t;
-
-/** Type of w6 register
- *  SPI1 memory data buffer6
- */
-typedef union {
-    struct {
-        /** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf6:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w6_reg_t;
-
-/** Type of w7 register
- *  SPI1 memory data buffer7
- */
-typedef union {
-    struct {
-        /** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf7:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w7_reg_t;
-
-/** Type of w8 register
- *  SPI1 memory data buffer8
- */
-typedef union {
-    struct {
-        /** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf8:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w8_reg_t;
-
-/** Type of w9 register
- *  SPI1 memory data buffer9
- */
-typedef union {
-    struct {
-        /** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf9:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w9_reg_t;
-
-/** Type of w10 register
- *  SPI1 memory data buffer10
- */
-typedef union {
-    struct {
-        /** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf10:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w10_reg_t;
-
-/** Type of w11 register
- *  SPI1 memory data buffer11
- */
-typedef union {
-    struct {
-        /** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf11:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w11_reg_t;
-
-/** Type of w12 register
- *  SPI1 memory data buffer12
- */
-typedef union {
-    struct {
-        /** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf12:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w12_reg_t;
-
-/** Type of w13 register
- *  SPI1 memory data buffer13
- */
-typedef union {
-    struct {
-        /** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf13:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w13_reg_t;
-
-/** Type of w14 register
- *  SPI1 memory data buffer14
- */
-typedef union {
-    struct {
-        /** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf14:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w14_reg_t;
-
-/** Type of w15 register
- *  SPI1 memory data buffer15
- */
-typedef union {
-    struct {
-        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf15:32;
-    };
-    uint32_t val;
-} spi1_mem_c_w15_reg_t;
-
-
 /** Group: Interrupt registers */
 /** Type of int_ena register
  *  SPI1 interrupt enable register
@@ -1208,7 +997,7 @@ typedef union {
 
 typedef struct spi1_mem_c_dev_s {
     volatile spi1_mem_c_cmd_reg_t cmd;
-    volatile spi1_mem_c_addr_reg_t addr;
+    volatile uint32_t addr;
     volatile spi1_mem_c_ctrl_reg_t ctrl;
     volatile spi1_mem_c_ctrl1_reg_t ctrl1;
     volatile spi1_mem_c_ctrl2_reg_t ctrl2;
@@ -1224,22 +1013,7 @@ typedef struct spi1_mem_c_dev_s {
     volatile spi1_mem_c_tx_crc_reg_t tx_crc;
     volatile spi1_mem_c_cache_fctrl_reg_t cache_fctrl;
     uint32_t reserved_040[6];
-    volatile spi1_mem_c_w0_reg_t w0;
-    volatile spi1_mem_c_w1_reg_t w1;
-    volatile spi1_mem_c_w2_reg_t w2;
-    volatile spi1_mem_c_w3_reg_t w3;
-    volatile spi1_mem_c_w4_reg_t w4;
-    volatile spi1_mem_c_w5_reg_t w5;
-    volatile spi1_mem_c_w6_reg_t w6;
-    volatile spi1_mem_c_w7_reg_t w7;
-    volatile spi1_mem_c_w8_reg_t w8;
-    volatile spi1_mem_c_w9_reg_t w9;
-    volatile spi1_mem_c_w10_reg_t w10;
-    volatile spi1_mem_c_w11_reg_t w11;
-    volatile spi1_mem_c_w12_reg_t w12;
-    volatile spi1_mem_c_w13_reg_t w13;
-    volatile spi1_mem_c_w14_reg_t w14;
-    volatile spi1_mem_c_w15_reg_t w15;
+    volatile uint32_t data_buf[16];
     volatile spi1_mem_c_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
     volatile spi1_mem_c_flash_sus_ctrl_reg_t flash_sus_ctrl;
     volatile spi1_mem_c_flash_sus_cmd_reg_t flash_sus_cmd;
@@ -1259,7 +1033,6 @@ typedef struct spi1_mem_c_dev_s {
     volatile spi1_mem_c_date_reg_t date;
 } spi1_mem_c_dev_t;
 
-
 #ifndef __cplusplus
 _Static_assert(sizeof(spi1_mem_c_dev_t) == 0x400, "Invalid size of spi1_mem_c_dev_t structure");
 #endif
diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h b/components/soc/esp32p4/include/soc/spi_mem_c_struct.h
index 208d6dde4df..c694be7e0a3 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_c_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -11,46 +11,46 @@ extern "C" {
 #endif
 
 /** Group: Status and state control register */
-/** Type of mem_cmd register
+/** Type of cmd register
  *  SPI0 FSM status register
  */
 typedef union {
     struct {
-        /** mem_mst_st : RO; bitpos: [3:0]; default: 0;
+        /** mst_st : RO; bitpos: [3:0]; default: 0;
          *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
          *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
          *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
          */
-        uint32_t mem_mst_st:4;
-        /** mem_slv_st : RO; bitpos: [7:4]; default: 0;
+        uint32_t mst_st:4;
+        /** slv_st : RO; bitpos: [7:4]; default: 0;
          *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
          *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
          *  6:write data state, 7: done state, 8: read data end state.
          */
-        uint32_t mem_slv_st:4;
+        uint32_t slv_st:4;
         uint32_t reserved_8:10;
-        /** mem_usr : HRO; bitpos: [18]; default: 0;
+        /** usr : HRO; bitpos: [18]; default: 0;
          *  SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared.  An operation
          *  will be triggered when the bit is set. The bit will be cleared once the operation
          *  done.1: enable 0: disable.
          */
-        uint32_t mem_usr:1;
+        uint32_t usr:1;
         uint32_t reserved_19:13;
     };
     uint32_t val;
 } spi_mem_c_cmd_reg_t;
 
-/** Type of mem_axi_err_addr register
+/** Type of axi_err_addr register
  *  SPI0 AXI request error address.
  */
 typedef union {
     struct {
-        /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
+        /** axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first AXI write/read invalid error or AXI write flash error
          *  address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR,
          *  spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set.
          */
-        uint32_t mem_axi_err_addr:27;
+        uint32_t axi_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
@@ -58,118 +58,118 @@ typedef union {
 
 
 /** Group: Flash Control and configuration registers */
-/** Type of mem_ctrl register
+/** Type of ctrl register
  *  SPI0 control register.
  */
 typedef union {
     struct {
-        /** mem_wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0;
+        /** wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0;
          *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
          *  of SPI_DQS is output by the MSPI controller.
          */
-        uint32_t mem_wdummy_dqs_always_out:1;
-        /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0;
+        uint32_t wdummy_dqs_always_out:1;
+        /** wdummy_always_out : R/W; bitpos: [1]; default: 0;
          *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
          *  of SPI_IO[7:0] is output by the MSPI controller.
          */
-        uint32_t mem_wdummy_always_out:1;
-        /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1;
+        uint32_t wdummy_always_out:1;
+        /** fdummy_rin : R/W; bitpos: [2]; default: 1;
          *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
          *  output by the MSPI controller in the first half part of dummy phase. It is used to
          *  mask invalid SPI_DQS in the half part of dummy phase.
          */
-        uint32_t mem_fdummy_rin:1;
-        /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1;
+        uint32_t fdummy_rin:1;
+        /** fdummy_wout : R/W; bitpos: [3]; default: 1;
          *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
          *  output by the MSPI controller in the second half part of dummy phase. It is used to
          *  pre-drive flash.
          */
-        uint32_t mem_fdummy_wout:1;
-        /** mem_fdout_oct : HRO; bitpos: [4]; default: 0;
+        uint32_t fdummy_wout:1;
+        /** fdout_oct : HRO; bitpos: [4]; default: 0;
          *  Apply 8 signals during write-data phase 1:enable 0: disable
          */
-        uint32_t mem_fdout_oct:1;
-        /** mem_fdin_oct : HRO; bitpos: [5]; default: 0;
+        uint32_t fdout_oct:1;
+        /** fdin_oct : HRO; bitpos: [5]; default: 0;
          *  Apply 8 signals during read-data phase 1:enable 0: disable
          */
-        uint32_t mem_fdin_oct:1;
-        /** mem_faddr_oct : HRO; bitpos: [6]; default: 0;
+        uint32_t fdin_oct:1;
+        /** faddr_oct : HRO; bitpos: [6]; default: 0;
          *  Apply 8 signals during address phase 1:enable 0: disable
          */
-        uint32_t mem_faddr_oct:1;
+        uint32_t faddr_oct:1;
         uint32_t reserved_7:1;
-        /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0;
+        /** fcmd_quad : R/W; bitpos: [8]; default: 0;
          *  Apply 4 signals during command phase 1:enable 0: disable
          */
-        uint32_t mem_fcmd_quad:1;
-        /** mem_fcmd_oct : HRO; bitpos: [9]; default: 0;
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : HRO; bitpos: [9]; default: 0;
          *  Apply 8 signals during command phase 1:enable 0: disable
          */
-        uint32_t mem_fcmd_oct:1;
+        uint32_t fcmd_oct:1;
         uint32_t reserved_10:3;
-        /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1;
+        /** fastrd_mode : R/W; bitpos: [13]; default: 1;
          *  This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT
          *  and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable.
          */
-        uint32_t mem_fastrd_mode:1;
-        /** mem_fread_dual : R/W; bitpos: [14]; default: 0;
+        uint32_t fastrd_mode:1;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
          *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
          */
-        uint32_t mem_fread_dual:1;
+        uint32_t fread_dual:1;
         uint32_t reserved_15:3;
-        /** mem_q_pol : R/W; bitpos: [18]; default: 1;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
          *  The bit is used to set MISO line polarity, 1: high 0, low
          */
-        uint32_t mem_q_pol:1;
-        /** mem_d_pol : R/W; bitpos: [19]; default: 1;
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
          *  The bit is used to set MOSI line polarity, 1: high 0, low
          */
-        uint32_t mem_d_pol:1;
-        /** mem_fread_quad : R/W; bitpos: [20]; default: 0;
+        uint32_t d_pol:1;
+        /** fread_quad : R/W; bitpos: [20]; default: 0;
          *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
          */
-        uint32_t mem_fread_quad:1;
-        /** mem_wp_reg : R/W; bitpos: [21]; default: 1;
+        uint32_t fread_quad:1;
+        /** wp_reg : R/W; bitpos: [21]; default: 1;
          *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
          */
-        uint32_t mem_wp_reg:1;
+        uint32_t wp_reg:1;
         uint32_t reserved_22:1;
-        /** mem_fread_dio : R/W; bitpos: [23]; default: 0;
+        /** fread_dio : R/W; bitpos: [23]; default: 0;
          *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
          *  0: disable.
          */
-        uint32_t mem_fread_dio:1;
-        /** mem_fread_qio : R/W; bitpos: [24]; default: 0;
+        uint32_t fread_dio:1;
+        /** fread_qio : R/W; bitpos: [24]; default: 0;
          *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
          *  0: disable.
          */
-        uint32_t mem_fread_qio:1;
+        uint32_t fread_qio:1;
         uint32_t reserved_25:5;
-        /** mem_dqs_ie_always_on : HRO; bitpos: [30]; default: 0;
+        /** dqs_ie_always_on : HRO; bitpos: [30]; default: 0;
          *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
          *  1. 0: Others.
          */
-        uint32_t mem_dqs_ie_always_on:1;
-        /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1;
+        uint32_t dqs_ie_always_on:1;
+        /** data_ie_always_on : R/W; bitpos: [31]; default: 1;
          *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
          *  always 1. 0: Others.
          */
-        uint32_t mem_data_ie_always_on:1;
+        uint32_t data_ie_always_on:1;
     };
     uint32_t val;
 } spi_mem_c_ctrl_reg_t;
 
-/** Type of mem_ctrl1 register
+/** Type of ctrl1 register
  *  SPI0 control1 register.
  */
 typedef union {
     struct {
-        /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0;
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
          *  SPI clock is alwasy on.
          */
-        uint32_t mem_clk_mode:2;
+        uint32_t clk_mode:2;
         uint32_t reserved_2:19;
         /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1;
          *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
@@ -185,131 +185,131 @@ typedef union {
          *  Reply AXI read data to AXI bus when all the read data is available.
          */
         uint32_t axi_rdata_back_fast:1;
-        /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
+        /** rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
          *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
          *  when there is a ECC error in AXI read data. The ECC error information is recorded
          *  in spi_mem_c_C_ECC_ERR_ADDR_REG.
          */
-        uint32_t mem_rresp_ecc_err_en:1;
-        /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0;
+        uint32_t rresp_ecc_err_en:1;
+        /** ar_splice_en : HRO; bitpos: [25]; default: 0;
          *  Set this bit to enable AXI Read Splice-transfer.
          */
-        uint32_t mem_ar_splice_en:1;
-        /** mem_aw_splice_en : HRO; bitpos: [26]; default: 0;
+        uint32_t ar_splice_en:1;
+        /** aw_splice_en : HRO; bitpos: [26]; default: 0;
          *  Set this bit to enable AXI Write Splice-transfer.
          */
-        uint32_t mem_aw_splice_en:1;
-        /** mem_ram0_en : HRO; bitpos: [27]; default: 1;
+        uint32_t aw_splice_en:1;
+        /** ram0_en : HRO; bitpos: [27]; default: 1;
          *  When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be
          *  accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1
          *  will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
          *  accessed at the same time.
          */
-        uint32_t mem_ram0_en:1;
-        /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0;
+        uint32_t ram0_en:1;
+        /** dual_ram_en : HRO; bitpos: [28]; default: 0;
          *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
          *  same time.
          */
-        uint32_t mem_dual_ram_en:1;
-        /** mem_fast_write_en : R/W; bitpos: [29]; default: 1;
+        uint32_t dual_ram_en:1;
+        /** fast_write_en : R/W; bitpos: [29]; default: 1;
          *  Set this bit to write data faster, do not wait write data has been stored in
          *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
          *  in  tx_bus_fifo_l2.
          */
-        uint32_t mem_fast_write_en:1;
-        /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0;
+        uint32_t fast_write_en:1;
+        /** rxfifo_rst : WT; bitpos: [30]; default: 0;
          *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
          *  receive signals from AXI.  Set this bit to reset these FIFO.
          */
-        uint32_t mem_rxfifo_rst:1;
-        /** mem_txfifo_rst : WT; bitpos: [31]; default: 0;
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : WT; bitpos: [31]; default: 0;
          *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
          *  send signals to AXI. Set this bit to reset these FIFO.
          */
-        uint32_t mem_txfifo_rst:1;
+        uint32_t txfifo_rst:1;
     };
     uint32_t val;
 } spi_mem_c_ctrl1_reg_t;
 
-/** Type of mem_ctrl2 register
+/** Type of ctrl2 register
  *  SPI0 control2 register.
  */
 typedef union {
     struct {
-        /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1;
+        /** cs_setup_time : R/W; bitpos: [4:0]; default: 1;
          *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
          *  spi_mem_c_C_CS_SETUP bit.
          */
-        uint32_t mem_cs_setup_time:5;
-        /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1;
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [9:5]; default: 1;
          *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
          *  spi_mem_c_C_CS_HOLD bit.
          */
-        uint32_t mem_cs_hold_time:5;
-        /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3;
+        uint32_t cs_hold_time:5;
+        /** ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3;
          *  spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
          *  mode when accessed flash.
          */
-        uint32_t mem_ecc_cs_hold_time:3;
-        /** mem_ecc_skip_page_corner : HRO; bitpos: [13]; default: 1;
+        uint32_t ecc_cs_hold_time:3;
+        /** ecc_skip_page_corner : HRO; bitpos: [13]; default: 1;
          *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
          *  accesses flash.
          */
-        uint32_t mem_ecc_skip_page_corner:1;
-        /** mem_ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0;
+        uint32_t ecc_skip_page_corner:1;
+        /** ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0;
          *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
          *  accesses flash.
          */
-        uint32_t mem_ecc_16to18_byte_en:1;
+        uint32_t ecc_16to18_byte_en:1;
         uint32_t reserved_15:9;
-        /** mem_split_trans_en : R/W; bitpos: [24]; default: 1;
+        /** split_trans_en : R/W; bitpos: [24]; default: 1;
          *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
          *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
          *  matter whether there is an ECC region or not.
          */
-        uint32_t mem_split_trans_en:1;
-        /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
+        uint32_t split_trans_en:1;
+        /** cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
          *  These bits are used to set the minimum CS high time tSHSL between SPI burst
          *  transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI
          *  core clock cycles.
          */
-        uint32_t mem_cs_hold_delay:6;
-        /** mem_sync_reset : WT; bitpos: [31]; default: 0;
+        uint32_t cs_hold_delay:6;
+        /** sync_reset : WT; bitpos: [31]; default: 0;
          *  The spi0_mst_st and spi0_slv_st will be reset.
          */
-        uint32_t mem_sync_reset:1;
+        uint32_t sync_reset:1;
     };
     uint32_t val;
 } spi_mem_c_ctrl2_reg_t;
 
-/** Type of mem_misc register
+/** Type of misc register
  *  SPI0 misc register
  */
 typedef union {
     struct {
         uint32_t reserved_0:7;
-        /** mem_fsub_pin : HRO; bitpos: [7]; default: 0;
+        /** fsub_pin : HRO; bitpos: [7]; default: 0;
          *  For SPI0,  flash is connected to SUBPINs.
          */
-        uint32_t mem_fsub_pin:1;
-        /** mem_ssub_pin : HRO; bitpos: [8]; default: 0;
+        uint32_t fsub_pin:1;
+        /** ssub_pin : HRO; bitpos: [8]; default: 0;
          *  For SPI0,  sram is connected to SUBPINs.
          */
-        uint32_t mem_ssub_pin:1;
-        /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0;
+        uint32_t ssub_pin:1;
+        /** ck_idle_edge : R/W; bitpos: [9]; default: 0;
          *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
          */
-        uint32_t mem_ck_idle_edge:1;
-        /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0;
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [10]; default: 0;
          *  SPI_CS line keep low when the bit is set.
          */
-        uint32_t mem_cs_keep_active:1;
+        uint32_t cs_keep_active:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
 } spi_mem_c_misc_reg_t;
 
-/** Type of mem_cache_fctrl register
+/** Type of cache_fctrl register
  *  SPI0 bit mode control register.
  */
 typedef union {
@@ -328,7 +328,7 @@ typedef union {
     uint32_t val;
 } spi_mem_c_cache_fctrl_reg_t;
 
-/** Type of mem_ddr register
+/** Type of ddr register
  *  SPI0 flash DDR mode control register
  */
 typedef union {
@@ -414,35 +414,35 @@ typedef union {
 
 
 /** Group: Clock control and configuration registers */
-/** Type of mem_clock register
+/** Type of clock register
  *  SPI clock division control register.
  */
 typedef union {
     struct {
-        /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3;
+        /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
          *  In the master mode it must be equal to spi_mem_c_clkcnt_N.
          */
-        uint32_t mem_clkcnt_l:8;
-        /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1;
+        uint32_t clkcnt_l:8;
+        /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
          *  In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1).
          */
-        uint32_t mem_clkcnt_h:8;
-        /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3;
+        uint32_t clkcnt_h:8;
+        /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
          *  In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is
          *  system/(spi_mem_c_clkcnt_N+1)
          */
-        uint32_t mem_clkcnt_n:8;
+        uint32_t clkcnt_n:8;
         uint32_t reserved_24:7;
-        /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0;
          *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
          *  clock.
          */
-        uint32_t mem_clk_equ_sysclk:1;
+        uint32_t clk_equ_sysclk:1;
     };
     uint32_t val;
 } spi_mem_c_clock_reg_t;
 
-/** Type of mem_clock_gate register
+/** Type of clock_gate register
  *  SPI0 clock gate register
  */
 typedef union {
@@ -458,84 +458,84 @@ typedef union {
 
 
 /** Group: Flash User-defined control registers */
-/** Type of mem_user register
+/** Type of user register
  *  SPI0 user register.
  */
 typedef union {
     struct {
         uint32_t reserved_0:6;
-        /** mem_cs_hold : R/W; bitpos: [6]; default: 0;
+        /** cs_hold : R/W; bitpos: [6]; default: 0;
          *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
          */
-        uint32_t mem_cs_hold:1;
-        /** mem_cs_setup : R/W; bitpos: [7]; default: 0;
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 0;
          *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
          */
-        uint32_t mem_cs_setup:1;
+        uint32_t cs_setup:1;
         uint32_t reserved_8:1;
-        /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
          *  The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
          */
-        uint32_t mem_ck_out_edge:1;
+        uint32_t ck_out_edge:1;
         uint32_t reserved_10:16;
-        /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
          *  spi clock is disable in dummy phase when the bit is enable.
          */
-        uint32_t mem_usr_dummy_idle:1;
+        uint32_t usr_dummy_idle:1;
         uint32_t reserved_27:2;
-        /** mem_usr_dummy : R/W; bitpos: [29]; default: 0;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
          *  This bit enable the dummy phase of an operation.
          */
-        uint32_t mem_usr_dummy:1;
+        uint32_t usr_dummy:1;
         uint32_t reserved_30:2;
     };
     uint32_t val;
 } spi_mem_c_user_reg_t;
 
-/** Type of mem_user1 register
+/** Type of user1 register
  *  SPI0 user1 register.
  */
 typedef union {
     struct {
-        /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
+        /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
          *  The length in spi_mem_c_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
-        uint32_t mem_usr_dummy_cyclelen:6;
-        /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1;
+        uint32_t usr_dummy_cyclelen:6;
+        /** usr_dbytelen : HRO; bitpos: [8:6]; default: 1;
          *  SPI0 USR_CMD read or write data byte length -1
          */
-        uint32_t mem_usr_dbytelen:3;
+        uint32_t usr_dbytelen:3;
         uint32_t reserved_9:17;
-        /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23;
+        /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23;
          *  The length in bits of address phase. The register value shall be (bit_num-1).
          */
-        uint32_t mem_usr_addr_bitlen:6;
+        uint32_t usr_addr_bitlen:6;
     };
     uint32_t val;
 } spi_mem_c_user1_reg_t;
 
-/** Type of mem_user2 register
+/** Type of user2 register
  *  SPI0 user2 register.
  */
 typedef union {
     struct {
-        /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0;
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
          *  The value of  command.
          */
-        uint32_t mem_usr_command_value:16;
+        uint32_t usr_command_value:16;
         uint32_t reserved_16:12;
-        /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
          *  The length in bits of command phase. The register value shall be (bit_num-1)
          */
-        uint32_t mem_usr_command_bitlen:4;
+        uint32_t usr_command_bitlen:4;
     };
     uint32_t val;
 } spi_mem_c_user2_reg_t;
 
 
 /** Group: External RAM Control and configuration registers */
-/** Type of mem_sram_cmd register
+/** Type of sram_cmd register
  *  SPI0 external RAM mode control register
  */
 typedef union {
@@ -709,16 +709,16 @@ typedef union {
 
 
 /** Group: State control register */
-/** Type of mem_fsm register
+/** Type of fsm register
  *  SPI0 FSM status register
  */
 typedef union {
     struct {
         uint32_t reserved_0:7;
-        /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4;
+        /** lock_delay_time : R/W; bitpos: [11:7]; default: 4;
          *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
          */
-        uint32_t mem_lock_delay_time:5;
+        uint32_t lock_delay_time:5;
         uint32_t reserved_12:20;
     };
     uint32_t val;
@@ -726,102 +726,102 @@ typedef union {
 
 
 /** Group: Interrupt registers */
-/** Type of mem_int_ena register
+/** Type of int_ena register
  *  SPI0 interrupt enable register
  */
 typedef union {
     struct {
         uint32_t reserved_0:3;
-        /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
+        /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
          *  The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
-        uint32_t mem_slv_st_end_int_ena:1;
-        /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
+        uint32_t slv_st_end_int_ena:1;
+        /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
          *  The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
-        uint32_t mem_mst_st_end_int_ena:1;
-        /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0;
+        uint32_t mst_st_end_int_ena:1;
+        /** ecc_err_int_ena : HRO; bitpos: [5]; default: 0;
          *  The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
-        uint32_t mem_ecc_err_int_ena:1;
-        /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
+        uint32_t ecc_err_int_ena:1;
+        /** pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
          *  The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
-        uint32_t mem_pms_reject_int_ena:1;
-        /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
+        uint32_t pms_reject_int_ena:1;
+        /** axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
          *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
-        uint32_t mem_axi_raddr_err_int_ena:1;
-        /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0;
+        uint32_t axi_raddr_err_int_ena:1;
+        /** axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0;
          *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
-        uint32_t mem_axi_wr_flash_err_int_ena:1;
-        /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0;
+        uint32_t axi_wr_flash_err_int_ena:1;
+        /** axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0;
          *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
-        uint32_t mem_axi_waddr_err_int__ena:1;
+        uint32_t axi_waddr_err_int__ena:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
 } spi_mem_c_int_ena_reg_t;
 
-/** Type of mem_int_clr register
+/** Type of int_clr register
  *  SPI0 interrupt clear register
  */
 typedef union {
     struct {
         uint32_t reserved_0:3;
-        /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
+        /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
          *  The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
-        uint32_t mem_slv_st_end_int_clr:1;
-        /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
+        uint32_t slv_st_end_int_clr:1;
+        /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
          *  The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
-        uint32_t mem_mst_st_end_int_clr:1;
-        /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0;
+        uint32_t mst_st_end_int_clr:1;
+        /** ecc_err_int_clr : HRO; bitpos: [5]; default: 0;
          *  The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
-        uint32_t mem_ecc_err_int_clr:1;
-        /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0;
+        uint32_t ecc_err_int_clr:1;
+        /** pms_reject_int_clr : WT; bitpos: [6]; default: 0;
          *  The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
-        uint32_t mem_pms_reject_int_clr:1;
-        /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
+        uint32_t pms_reject_int_clr:1;
+        /** axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
          *  The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
-        uint32_t mem_axi_raddr_err_int_clr:1;
-        /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0;
+        uint32_t axi_raddr_err_int_clr:1;
+        /** axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0;
          *  The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
-        uint32_t mem_axi_wr_flash_err_int_clr:1;
-        /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0;
+        uint32_t axi_wr_flash_err_int_clr:1;
+        /** axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0;
          *  The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
-        uint32_t mem_axi_waddr_err_int_clr:1;
+        uint32_t axi_waddr_err_int_clr:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
 } spi_mem_c_int_clr_reg_t;
 
-/** Type of mem_int_raw register
+/** Type of int_raw register
  *  SPI0 interrupt raw register
  */
 typedef union {
     struct {
         uint32_t reserved_0:3;
-        /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+        /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
          *  The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
-        uint32_t mem_slv_st_end_int_raw:1;
-        /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+        uint32_t slv_st_end_int_raw:1;
+        /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
          *  The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
-        uint32_t mem_mst_st_end_int_raw:1;
-        /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0;
+        uint32_t mst_st_end_int_raw:1;
+        /** ecc_err_int_raw : HRO; bitpos: [5]; default: 0;
          *  The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set
          *  and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
          *  of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When
@@ -833,66 +833,66 @@ typedef union {
          *  spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN
          *  are cleared, this bit will not be triggered.
          */
-        uint32_t mem_ecc_err_int_raw:1;
-        /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+        uint32_t ecc_err_int_raw:1;
+        /** pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
          *  The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
          *  rejected. 0: Others.
          */
-        uint32_t mem_pms_reject_int_raw:1;
-        /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+        uint32_t pms_reject_int_raw:1;
+        /** axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
          *  The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
-        uint32_t mem_axi_raddr_err_int_raw:1;
-        /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0;
+        uint32_t axi_raddr_err_int_raw:1;
+        /** axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0;
          *  The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
          *  flash request is received. 0: Others.
          */
-        uint32_t mem_axi_wr_flash_err_int_raw:1;
-        /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0;
+        uint32_t axi_wr_flash_err_int_raw:1;
+        /** axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0;
          *  The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
-        uint32_t mem_axi_waddr_err_int_raw:1;
+        uint32_t axi_waddr_err_int_raw:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
 } spi_mem_c_int_raw_reg_t;
 
-/** Type of mem_int_st register
+/** Type of int_st register
  *  SPI0 interrupt status register
  */
 typedef union {
     struct {
         uint32_t reserved_0:3;
-        /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0;
+        /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
          *  The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
-        uint32_t mem_slv_st_end_int_st:1;
-        /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0;
+        uint32_t slv_st_end_int_st:1;
+        /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
          *  The status bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
-        uint32_t mem_mst_st_end_int_st:1;
-        /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0;
+        uint32_t mst_st_end_int_st:1;
+        /** ecc_err_int_st : HRO; bitpos: [5]; default: 0;
          *  The status bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
-        uint32_t mem_ecc_err_int_st:1;
-        /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0;
+        uint32_t ecc_err_int_st:1;
+        /** pms_reject_int_st : RO; bitpos: [6]; default: 0;
          *  The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
-        uint32_t mem_pms_reject_int_st:1;
-        /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
+        uint32_t pms_reject_int_st:1;
+        /** axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
          *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
-        uint32_t mem_axi_raddr_err_int_st:1;
-        /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0;
+        uint32_t axi_raddr_err_int_st:1;
+        /** axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0;
          *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
-        uint32_t mem_axi_wr_flash_err_int_st:1;
-        /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0;
+        uint32_t axi_wr_flash_err_int_st:1;
+        /** axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0;
          *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
-        uint32_t mem_axi_waddr_err_int_st:1;
+        uint32_t axi_waddr_err_int_st:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
@@ -1006,57 +1006,57 @@ typedef union {
     uint32_t val;
 } spi_mem_c_smem_pmsn_size_reg_t;
 
-/** Type of mem_pms_reject register
+/** Type of pms_reject register
  *  SPI1 access reject register
  */
 typedef union {
     struct {
-        /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
+        /** reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first SPI1 access error address. It is cleared by when
          *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
-        uint32_t mem_reject_addr:27;
-        /** mem_pm_en : R/W; bitpos: [27]; default: 0;
+        uint32_t reject_addr:27;
+        /** pm_en : R/W; bitpos: [27]; default: 0;
          *  Set this bit to enable SPI0/1 transfer permission control function.
          */
-        uint32_t mem_pm_en:1;
-        /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
+        uint32_t pm_en:1;
+        /** pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
          *  1: SPI1 write access error. 0: No write access error. It is cleared by when
          *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
-        uint32_t mem_pms_ld:1;
-        /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0;
+        uint32_t pms_ld:1;
+        /** pms_st : R/SS/WTC; bitpos: [29]; default: 0;
          *  1: SPI1 read access error. 0: No read access error. It is cleared by when
          *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
-        uint32_t mem_pms_st:1;
-        /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
+        uint32_t pms_st:1;
+        /** pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
          *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
          *  cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
-        uint32_t mem_pms_multi_hit:1;
-        /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
+        uint32_t pms_multi_hit:1;
+        /** pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
          *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
          *  error. It is cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
-        uint32_t mem_pms_ivd:1;
+        uint32_t pms_ivd:1;
     };
     uint32_t val;
 } spi_mem_c_pms_reject_reg_t;
 
 
 /** Group: MSPI ECC registers */
-/** Type of mem_ecc_ctrl register
+/** Type of ecc_ctrl register
  *  MSPI ECC control register
  */
 typedef union {
     struct {
         uint32_t reserved_0:5;
-        /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0;
+        /** ecc_err_cnt : HRO; bitpos: [10:5]; default: 0;
          *  This bits show the error times of MSPI ECC read. It is cleared by when
          *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
          */
-        uint32_t mem_ecc_err_cnt:6;
+        uint32_t ecc_err_cnt:6;
         /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10;
          *  Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt.
          */
@@ -1076,36 +1076,36 @@ typedef union {
          *  should be 0. Otherwise, this bit should be 1.
          */
         uint32_t fmem_ecc_addr_en:1;
-        /** mem_usr_ecc_addr_en : HRO; bitpos: [21]; default: 0;
+        /** usr_ecc_addr_en : HRO; bitpos: [21]; default: 0;
          *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
          */
-        uint32_t mem_usr_ecc_addr_en:1;
+        uint32_t usr_ecc_addr_en:1;
         uint32_t reserved_22:2;
-        /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1;
+        /** ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1;
          *  1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is
          *  updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and
          *  spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information.
          */
-        uint32_t mem_ecc_continue_record_err_en:1;
-        /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0;
+        uint32_t ecc_continue_record_err_en:1;
+        /** ecc_err_bits : HRO; bitpos: [31:25]; default: 0;
          *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
          *  byte 0 bit 0 to byte 15 bit 7)
          */
-        uint32_t mem_ecc_err_bits:7;
+        uint32_t ecc_err_bits:7;
     };
     uint32_t val;
 } spi_mem_c_ecc_ctrl_reg_t;
 
-/** Type of mem_ecc_err_addr register
+/** Type of ecc_err_addr register
  *  MSPI ECC error address register
  */
 typedef union {
     struct {
-        /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0;
+        /** ecc_err_addr : HRO; bitpos: [26:0]; default: 0;
          *  This bits show the first MSPI ECC error address. It is cleared by when
          *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
          */
-        uint32_t mem_ecc_err_addr:27;
+        uint32_t ecc_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
@@ -1146,11 +1146,11 @@ typedef union {
 typedef union {
     struct {
         uint32_t reserved_0:26;
-        /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1;
+        /** all_fifo_empty : RO; bitpos: [26]; default: 1;
          *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
          *  and SPI0 transfers are done. 0: Others.
          */
-        uint32_t mem_all_fifo_empty:1;
+        uint32_t all_fifo_empty:1;
         /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1;
          *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
          */
@@ -1176,60 +1176,60 @@ typedef union {
     uint32_t val;
 } spi_mem_c_smem_axi_addr_ctrl_reg_t;
 
-/** Type of mem_axi_err_resp_en register
+/** Type of axi_err_resp_en register
  *  SPI0 AXI error response enable register
  */
 typedef union {
     struct {
-        /** mem_aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0;
+        /** aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0;
          *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
          */
-        uint32_t mem_aw_resp_en_mmu_vld:1;
-        /** mem_aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0;
+        uint32_t aw_resp_en_mmu_vld:1;
+        /** aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0;
          *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
          */
-        uint32_t mem_aw_resp_en_mmu_gid:1;
-        /** mem_aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0;
+        uint32_t aw_resp_en_mmu_gid:1;
+        /** aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0;
          *  Set this bit  to enable AXI response function for axi size err in axi write trans.
          */
-        uint32_t mem_aw_resp_en_axi_size:1;
-        /** mem_aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0;
+        uint32_t aw_resp_en_axi_size:1;
+        /** aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0;
          *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
          */
-        uint32_t mem_aw_resp_en_axi_flash:1;
-        /** mem_aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0;
+        uint32_t aw_resp_en_axi_flash:1;
+        /** aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0;
          *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
          */
-        uint32_t mem_aw_resp_en_mmu_ecc:1;
-        /** mem_aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0;
+        uint32_t aw_resp_en_mmu_ecc:1;
+        /** aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0;
          *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
          */
-        uint32_t mem_aw_resp_en_mmu_sens:1;
-        /** mem_aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0;
+        uint32_t aw_resp_en_mmu_sens:1;
+        /** aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0;
          *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
          */
-        uint32_t mem_aw_resp_en_axi_wstrb:1;
-        /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0;
+        uint32_t aw_resp_en_axi_wstrb:1;
+        /** ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0;
          *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
          */
-        uint32_t mem_ar_resp_en_mmu_vld:1;
-        /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0;
+        uint32_t ar_resp_en_mmu_vld:1;
+        /** ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0;
          *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
          */
-        uint32_t mem_ar_resp_en_mmu_gid:1;
-        /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0;
+        uint32_t ar_resp_en_mmu_gid:1;
+        /** ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0;
          *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
          */
-        uint32_t mem_ar_resp_en_mmu_ecc:1;
-        /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0;
+        uint32_t ar_resp_en_mmu_ecc:1;
+        /** ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0;
          *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
          *  trans.
          */
-        uint32_t mem_ar_resp_en_mmu_sens:1;
-        /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0;
+        uint32_t ar_resp_en_mmu_sens:1;
+        /** ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0;
          *  Set this bit  to enable AXI response function for axi size err in axi read trans.
          */
-        uint32_t mem_ar_resp_en_axi_size:1;
+        uint32_t ar_resp_en_axi_size:1;
         uint32_t reserved_12:20;
     };
     uint32_t val;
@@ -1237,223 +1237,223 @@ typedef union {
 
 
 /** Group: Flash timing registers */
-/** Type of mem_timing_cali register
+/** Type of timing_cali register
  *  SPI0 flash timing calibration register
  */
 typedef union {
     struct {
-        /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1;
+        /** timing_clk_ena : R/W; bitpos: [0]; default: 1;
          *  The bit is used to enable timing adjust clock for all reading operations.
          */
-        uint32_t mem_timing_clk_ena:1;
-        /** mem_timing_cali : R/W; bitpos: [1]; default: 0;
+        uint32_t timing_clk_ena:1;
+        /** timing_cali : R/W; bitpos: [1]; default: 0;
          *  The bit is used to enable timing auto-calibration for all reading operations.
          */
-        uint32_t mem_timing_cali:1;
-        /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
+        uint32_t timing_cali:1;
+        /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
          *  add extra dummy spi clock cycle length for spi clock calibration.
          */
-        uint32_t mem_extra_dummy_cyclelen:3;
-        /** mem_dll_timing_cali : HRO; bitpos: [5]; default: 0;
+        uint32_t extra_dummy_cyclelen:3;
+        /** dll_timing_cali : HRO; bitpos: [5]; default: 0;
          *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
          *  flash.
          */
-        uint32_t mem_dll_timing_cali:1;
-        /** mem_timing_cali_update : WT; bitpos: [6]; default: 0;
+        uint32_t dll_timing_cali:1;
+        /** timing_cali_update : WT; bitpos: [6]; default: 0;
          *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
          */
-        uint32_t mem_timing_cali_update:1;
+        uint32_t timing_cali_update:1;
         uint32_t reserved_7:25;
     };
     uint32_t val;
 } spi_mem_c_timing_cali_reg_t;
 
-/** Type of mem_din_mode register
+/** Type of din_mode register
  *  MSPI flash input timing delay mode control register
  */
 typedef union {
     struct {
-        /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0;
+        /** din0_mode : R/W; bitpos: [2:0]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
          *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
          *  spi_clk high edge,  6: input with the spi_clk low edge
          */
-        uint32_t mem_din0_mode:3;
-        /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0;
+        uint32_t din0_mode:3;
+        /** din1_mode : R/W; bitpos: [5:3]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
          *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
          *  spi_clk high edge,  6: input with the spi_clk low edge
          */
-        uint32_t mem_din1_mode:3;
-        /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0;
+        uint32_t din1_mode:3;
+        /** din2_mode : R/W; bitpos: [8:6]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
          *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
          *  spi_clk high edge,  6: input with the spi_clk low edge
          */
-        uint32_t mem_din2_mode:3;
-        /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0;
+        uint32_t din2_mode:3;
+        /** din3_mode : R/W; bitpos: [11:9]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
          *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
          *  spi_clk high edge,  6: input with the spi_clk low edge
          */
-        uint32_t mem_din3_mode:3;
-        /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0;
+        uint32_t din3_mode:3;
+        /** din4_mode : R/W; bitpos: [14:12]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
          *  with the spi_clk
          */
-        uint32_t mem_din4_mode:3;
-        /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0;
+        uint32_t din4_mode:3;
+        /** din5_mode : R/W; bitpos: [17:15]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
          *  with the spi_clk
          */
-        uint32_t mem_din5_mode:3;
-        /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0;
+        uint32_t din5_mode:3;
+        /** din6_mode : R/W; bitpos: [20:18]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
          *  with the spi_clk
          */
-        uint32_t mem_din6_mode:3;
-        /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0;
+        uint32_t din6_mode:3;
+        /** din7_mode : R/W; bitpos: [23:21]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
          *  with the spi_clk
          */
-        uint32_t mem_din7_mode:3;
-        /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0;
+        uint32_t din7_mode:3;
+        /** dins_mode : R/W; bitpos: [26:24]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
          *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
          *  with the spi_clk
          */
-        uint32_t mem_dins_mode:3;
+        uint32_t dins_mode:3;
         uint32_t reserved_27:5;
     };
     uint32_t val;
 } spi_mem_c_din_mode_reg_t;
 
-/** Type of mem_din_num register
+/** Type of din_num register
  *  MSPI flash input timing delay number control register
  */
 typedef union {
     struct {
-        /** mem_din0_num : R/W; bitpos: [1:0]; default: 0;
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din0_num:2;
-        /** mem_din1_num : R/W; bitpos: [3:2]; default: 0;
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din1_num:2;
-        /** mem_din2_num : R/W; bitpos: [5:4]; default: 0;
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din2_num:2;
-        /** mem_din3_num : R/W; bitpos: [7:6]; default: 0;
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din3_num:2;
-        /** mem_din4_num : R/W; bitpos: [9:8]; default: 0;
+        uint32_t din3_num:2;
+        /** din4_num : R/W; bitpos: [9:8]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din4_num:2;
-        /** mem_din5_num : R/W; bitpos: [11:10]; default: 0;
+        uint32_t din4_num:2;
+        /** din5_num : R/W; bitpos: [11:10]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din5_num:2;
-        /** mem_din6_num : R/W; bitpos: [13:12]; default: 0;
+        uint32_t din5_num:2;
+        /** din6_num : R/W; bitpos: [13:12]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din6_num:2;
-        /** mem_din7_num : R/W; bitpos: [15:14]; default: 0;
+        uint32_t din6_num:2;
+        /** din7_num : R/W; bitpos: [15:14]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_din7_num:2;
-        /** mem_dins_num : R/W; bitpos: [17:16]; default: 0;
+        uint32_t din7_num:2;
+        /** dins_num : R/W; bitpos: [17:16]; default: 0;
          *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
          *  delayed by 2 cycles,...
          */
-        uint32_t mem_dins_num:2;
+        uint32_t dins_num:2;
         uint32_t reserved_18:14;
     };
     uint32_t val;
 } spi_mem_c_din_num_reg_t;
 
-/** Type of mem_dout_mode register
+/** Type of dout_mode register
  *  MSPI flash output timing adjustment control register
  */
 typedef union {
     struct {
-        /** mem_dout0_mode : R/W; bitpos: [0]; default: 0;
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
          *  with the spi_clk high edge ,6: output with the spi_clk low edge
          */
-        uint32_t mem_dout0_mode:1;
-        /** mem_dout1_mode : R/W; bitpos: [1]; default: 0;
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
          *  with the spi_clk high edge ,6: output with the spi_clk low edge
          */
-        uint32_t mem_dout1_mode:1;
-        /** mem_dout2_mode : R/W; bitpos: [2]; default: 0;
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
          *  with the spi_clk high edge ,6: output with the spi_clk low edge
          */
-        uint32_t mem_dout2_mode:1;
-        /** mem_dout3_mode : R/W; bitpos: [3]; default: 0;
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
          *  with the spi_clk high edge ,6: output with the spi_clk low edge
          */
-        uint32_t mem_dout3_mode:1;
-        /** mem_dout4_mode : R/W; bitpos: [4]; default: 0;
+        uint32_t dout3_mode:1;
+        /** dout4_mode : R/W; bitpos: [4]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the spi_clk
          */
-        uint32_t mem_dout4_mode:1;
-        /** mem_dout5_mode : R/W; bitpos: [5]; default: 0;
+        uint32_t dout4_mode:1;
+        /** dout5_mode : R/W; bitpos: [5]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the spi_clk
          */
-        uint32_t mem_dout5_mode:1;
-        /** mem_dout6_mode : R/W; bitpos: [6]; default: 0;
+        uint32_t dout5_mode:1;
+        /** dout6_mode : R/W; bitpos: [6]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the spi_clk
          */
-        uint32_t mem_dout6_mode:1;
-        /** mem_dout7_mode : R/W; bitpos: [7]; default: 0;
+        uint32_t dout6_mode:1;
+        /** dout7_mode : R/W; bitpos: [7]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the spi_clk
          */
-        uint32_t mem_dout7_mode:1;
-        /** mem_douts_mode : R/W; bitpos: [8]; default: 0;
+        uint32_t dout7_mode:1;
+        /** douts_mode : R/W; bitpos: [8]; default: 0;
          *  the output signals are delayed by system clock cycles, 0: output without delayed,
          *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
          *  output with the spi_clk
          */
-        uint32_t mem_douts_mode:1;
+        uint32_t douts_mode:1;
         uint32_t reserved_9:23;
     };
     uint32_t val;
@@ -1692,7 +1692,7 @@ typedef union {
 
 
 /** Group: Manual Encryption plaintext Memory */
-/** Type of mem_xts_plain_base register
+/** Type of xts_plain_base register
  *  The base address of the memory that stores plaintext in Manual Encryption
  */
 typedef union {
@@ -1708,7 +1708,7 @@ typedef union {
 
 
 /** Group: Manual Encryption configuration registers */
-/** Type of mem_xts_linesize register
+/** Type of xts_linesize register
  *  Manual Encryption Line-Size register
  */
 typedef union {
@@ -1724,7 +1724,7 @@ typedef union {
     uint32_t val;
 } spi_mem_c_xts_linesize_reg_t;
 
-/** Type of mem_xts_destination register
+/** Type of xts_destination register
  *  Manual Encryption destination register
  */
 typedef union {
@@ -1739,7 +1739,7 @@ typedef union {
     uint32_t val;
 } spi_mem_c_xts_destination_reg_t;
 
-/** Type of mem_xts_physical_address register
+/** Type of xts_physical_address register
  *  Manual Encryption physical address register
  */
 typedef union {
@@ -1757,7 +1757,7 @@ typedef union {
 
 
 /** Group: Manual Encryption control and status registers */
-/** Type of mem_xts_trigger register
+/** Type of xts_trigger register
  *  Manual Encryption physical address register
  */
 typedef union {
@@ -1774,7 +1774,7 @@ typedef union {
     uint32_t val;
 } spi_mem_c_xts_trigger_reg_t;
 
-/** Type of mem_xts_release register
+/** Type of xts_release register
  *  Manual Encryption physical address register
  */
 typedef union {
@@ -1790,7 +1790,7 @@ typedef union {
     uint32_t val;
 } spi_mem_c_xts_release_reg_t;
 
-/** Type of mem_xts_destroy register
+/** Type of xts_destroy register
  *  Manual Encryption physical address register
  */
 typedef union {
@@ -1806,7 +1806,7 @@ typedef union {
     uint32_t val;
 } spi_mem_c_xts_destroy_reg_t;
 
-/** Type of mem_xts_state register
+/** Type of xts_state register
  *  Manual Encryption physical address register
  */
 typedef union {
@@ -1824,7 +1824,7 @@ typedef union {
 
 
 /** Group: Manual Encryption version control register */
-/** Type of mem_xts_date register
+/** Type of xts_date register
  *  Manual Encryption version register
  */
 typedef union {
@@ -1840,7 +1840,7 @@ typedef union {
 
 
 /** Group: MMU access registers */
-/** Type of mem_mmu_item_content register
+/** Type of mmu_item_content register
  *  MSPI-MMU item content register
  */
 typedef union {
@@ -1853,7 +1853,7 @@ typedef union {
     uint32_t val;
 } spi_mem_c_mmu_item_content_reg_t;
 
-/** Type of mem_mmu_item_index register
+/** Type of mmu_item_index register
  *  MSPI-MMU item index register
  */
 typedef union {
@@ -1868,7 +1868,7 @@ typedef union {
 
 
 /** Group: MMU power control and configuration registers */
-/** Type of mem_mmu_power_ctrl register
+/** Type of mmu_power_ctrl register
  *  MSPI MMU power control register
  */
 typedef union {
@@ -1891,10 +1891,10 @@ typedef union {
          */
         uint32_t mmu_page_size:2;
         uint32_t reserved_5:11;
-        /** mem_aux_ctrl : HRO; bitpos: [29:16]; default: 4896;
+        /** aux_ctrl : HRO; bitpos: [29:16]; default: 4896;
          *  MMU PSRAM aux control register
          */
-        uint32_t mem_aux_ctrl:14;
+        uint32_t aux_ctrl:14;
         uint32_t reserved_30:2;
     };
     uint32_t val;
@@ -1902,7 +1902,7 @@ typedef union {
 
 
 /** Group: External mem cryption DPA registers */
-/** Type of mem_dpa_ctrl register
+/** Type of dpa_ctrl register
  *  SPI memory cryption DPA register
  */
 typedef union {
@@ -1931,15 +1931,15 @@ typedef union {
 
 
 /** Group: Version control register */
-/** Type of mem_date register
+/** Type of date register
  *  SPI0 version control register
  */
 typedef union {
     struct {
-        /** mem_date : R/W; bitpos: [27:0]; default: 36712560;
+        /** date : R/W; bitpos: [27:0]; default: 36712560;
          *  SPI0 register version.
          */
-        uint32_t mem_date:28;
+        uint32_t date:28;
         uint32_t reserved_28:4;
     };
     uint32_t val;
@@ -1947,30 +1947,30 @@ typedef union {
 
 
 typedef struct spi_mem_c_dev_s {
-    volatile spi_mem_c_cmd_reg_t mem_cmd;
+    volatile spi_mem_c_cmd_reg_t cmd;
     uint32_t reserved_004;
-    volatile spi_mem_c_ctrl_reg_t mem_ctrl;
-    volatile spi_mem_c_ctrl1_reg_t mem_ctrl1;
-    volatile spi_mem_c_ctrl2_reg_t mem_ctrl2;
-    volatile spi_mem_c_clock_reg_t mem_clock;
-    volatile spi_mem_c_user_reg_t mem_user;
-    volatile spi_mem_c_user1_reg_t mem_user1;
-    volatile spi_mem_c_user2_reg_t mem_user2;
+    volatile spi_mem_c_ctrl_reg_t ctrl;
+    volatile spi_mem_c_ctrl1_reg_t ctrl1;
+    volatile spi_mem_c_ctrl2_reg_t ctrl2;
+    volatile spi_mem_c_clock_reg_t clock;
+    volatile spi_mem_c_user_reg_t user;
+    volatile spi_mem_c_user1_reg_t user1;
+    volatile spi_mem_c_user2_reg_t user2;
     uint32_t reserved_024[4];
-    volatile spi_mem_c_misc_reg_t mem_misc;
+    volatile spi_mem_c_misc_reg_t misc;
     uint32_t reserved_038;
-    volatile spi_mem_c_cache_fctrl_reg_t mem_cache_fctrl;
+    volatile spi_mem_c_cache_fctrl_reg_t cache_fctrl;
     uint32_t reserved_040;
-    volatile spi_mem_c_sram_cmd_reg_t mem_sram_cmd;
+    volatile spi_mem_c_sram_cmd_reg_t sram_cmd;
     uint32_t reserved_048[3];
-    volatile spi_mem_c_fsm_reg_t mem_fsm;
+    volatile spi_mem_c_fsm_reg_t fsm;
     uint32_t reserved_058[26];
-    volatile spi_mem_c_int_ena_reg_t mem_int_ena;
-    volatile spi_mem_c_int_clr_reg_t mem_int_clr;
-    volatile spi_mem_c_int_raw_reg_t mem_int_raw;
-    volatile spi_mem_c_int_st_reg_t mem_int_st;
+    volatile spi_mem_c_int_ena_reg_t int_ena;
+    volatile spi_mem_c_int_clr_reg_t int_clr;
+    volatile spi_mem_c_int_raw_reg_t int_raw;
+    volatile spi_mem_c_int_st_reg_t int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_c_ddr_reg_t mem_ddr;
+    volatile spi_mem_c_ddr_reg_t ddr;
     volatile spi_mem_c_smem_ddr_reg_t smem_ddr;
     uint32_t reserved_0dc[9];
     volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
@@ -1980,42 +1980,42 @@ typedef struct spi_mem_c_dev_s {
     volatile spi_mem_c_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
     volatile spi_mem_c_smem_pmsn_size_reg_t smem_pmsn_size[4];
     uint32_t reserved_160;
-    volatile spi_mem_c_pms_reject_reg_t mem_pms_reject;
-    volatile spi_mem_c_ecc_ctrl_reg_t mem_ecc_ctrl;
-    volatile spi_mem_c_ecc_err_addr_reg_t mem_ecc_err_addr;
-    volatile spi_mem_c_axi_err_addr_reg_t mem_axi_err_addr;
+    volatile spi_mem_c_pms_reject_reg_t pms_reject;
+    volatile spi_mem_c_ecc_ctrl_reg_t ecc_ctrl;
+    volatile spi_mem_c_ecc_err_addr_reg_t ecc_err_addr;
+    volatile spi_mem_c_axi_err_addr_reg_t axi_err_addr;
     volatile spi_mem_c_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
     volatile spi_mem_c_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
-    volatile spi_mem_c_axi_err_resp_en_reg_t mem_axi_err_resp_en;
-    volatile spi_mem_c_timing_cali_reg_t mem_timing_cali;
-    volatile spi_mem_c_din_mode_reg_t mem_din_mode;
-    volatile spi_mem_c_din_num_reg_t mem_din_num;
-    volatile spi_mem_c_dout_mode_reg_t mem_dout_mode;
+    volatile spi_mem_c_axi_err_resp_en_reg_t axi_err_resp_en;
+    volatile spi_mem_c_timing_cali_reg_t timing_cali;
+    volatile spi_mem_c_din_mode_reg_t din_mode;
+    volatile spi_mem_c_din_num_reg_t din_num;
+    volatile spi_mem_c_dout_mode_reg_t dout_mode;
     volatile spi_mem_c_smem_timing_cali_reg_t smem_timing_cali;
     volatile spi_mem_c_smem_din_mode_reg_t smem_din_mode;
     volatile spi_mem_c_smem_din_num_reg_t smem_din_num;
     volatile spi_mem_c_smem_dout_mode_reg_t smem_dout_mode;
     volatile spi_mem_c_smem_ac_reg_t smem_ac;
     uint32_t reserved_1a4[23];
-    volatile spi_mem_c_clock_gate_reg_t mem_clock_gate;
+    volatile spi_mem_c_clock_gate_reg_t clock_gate;
     uint32_t reserved_204[63];
-    volatile spi_mem_c_xts_plain_base_reg_t mem_xts_plain_base;
+    volatile spi_mem_c_xts_plain_base_reg_t xts_plain_base;
     uint32_t reserved_304[15];
-    volatile spi_mem_c_xts_linesize_reg_t mem_xts_linesize;
-    volatile spi_mem_c_xts_destination_reg_t mem_xts_destination;
-    volatile spi_mem_c_xts_physical_address_reg_t mem_xts_physical_address;
-    volatile spi_mem_c_xts_trigger_reg_t mem_xts_trigger;
-    volatile spi_mem_c_xts_release_reg_t mem_xts_release;
-    volatile spi_mem_c_xts_destroy_reg_t mem_xts_destroy;
-    volatile spi_mem_c_xts_state_reg_t mem_xts_state;
-    volatile spi_mem_c_xts_date_reg_t mem_xts_date;
+    volatile spi_mem_c_xts_linesize_reg_t xts_linesize;
+    volatile spi_mem_c_xts_destination_reg_t xts_destination;
+    volatile spi_mem_c_xts_physical_address_reg_t xts_physical_address;
+    volatile spi_mem_c_xts_trigger_reg_t xts_trigger;
+    volatile spi_mem_c_xts_release_reg_t xts_release;
+    volatile spi_mem_c_xts_destroy_reg_t xts_destroy;
+    volatile spi_mem_c_xts_state_reg_t xts_state;
+    volatile spi_mem_c_xts_date_reg_t xts_date;
     uint32_t reserved_360[7];
-    volatile spi_mem_c_mmu_item_content_reg_t mem_mmu_item_content;
-    volatile spi_mem_c_mmu_item_index_reg_t mem_mmu_item_index;
-    volatile spi_mem_c_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
-    volatile spi_mem_c_dpa_ctrl_reg_t mem_dpa_ctrl;
+    volatile spi_mem_c_mmu_item_content_reg_t mmu_item_content;
+    volatile spi_mem_c_mmu_item_index_reg_t mmu_item_index;
+    volatile spi_mem_c_mmu_power_ctrl_reg_t mmu_power_ctrl;
+    volatile spi_mem_c_dpa_ctrl_reg_t dpa_ctrl;
     uint32_t reserved_38c[28];
-    volatile spi_mem_c_date_reg_t mem_date;
+    volatile spi_mem_c_date_reg_t date;
 } spi_mem_c_dev_t;
 
 
diff --git a/components/soc/esp32p4/include/soc/spi_mem_reg.h b/components/soc/esp32p4/include/soc/spi_mem_reg.h
index 1a559cf575b..75a585fb6e8 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_reg.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_reg.h
@@ -1,3444 +1,9 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
-#include <stdint.h>
-#include "soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
-/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (BIT(31))
-#define SPI_MEM_FLASH_READ_V  0x1
-#define SPI_MEM_FLASH_READ_S  31
-/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
-bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (BIT(30))
-#define SPI_MEM_FLASH_WREN_V  0x1
-#define SPI_MEM_FLASH_WREN_S  30
-/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Write flash disable. Write disable command will be sent when the bit is set. The
- bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
-#define SPI_MEM_FLASH_WRDI_V  0x1
-#define SPI_MEM_FLASH_WRDI_S  29
-/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
-e cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (BIT(28))
-#define SPI_MEM_FLASH_RDID_V  0x1
-#define SPI_MEM_FLASH_RDID_S  28
-/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Read status register-1.  Read status operation will be triggered when the bit is
- set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
-#define SPI_MEM_FLASH_RDSR_V  0x1
-#define SPI_MEM_FLASH_RDSR_S  27
-/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write status register enable.   Write status operation  will be triggered when t
-he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
-ble..*/
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
-#define SPI_MEM_FLASH_WRSR_V  0x1
-#define SPI_MEM_FLASH_WRSR_S  26
-/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
-tion  will be triggered when the bit is set. The bit will be cleared once the op
-eration done .1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (BIT(25))
-#define SPI_MEM_FLASH_PP_V  0x1
-#define SPI_MEM_FLASH_PP_S  25
-/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
-is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (BIT(24))
-#define SPI_MEM_FLASH_SE_V  0x1
-#define SPI_MEM_FLASH_SE_S  24
-/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
- is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (BIT(23))
-#define SPI_MEM_FLASH_BE_V  0x1
-#define SPI_MEM_FLASH_BE_S  23
-/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (BIT(22))
-#define SPI_MEM_FLASH_CE_V  0x1
-#define SPI_MEM_FLASH_CE_S  22
-/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
-. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (BIT(21))
-#define SPI_MEM_FLASH_DP_V  0x1
-#define SPI_MEM_FLASH_DP_S  21
-/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
-e or high performance mode and obtains the devices ID. The bit will be cleared o
-nce the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (BIT(20))
-#define SPI_MEM_FLASH_RES_V  0x1
-#define SPI_MEM_FLASH_RES_S  20
-/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
-ion done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (BIT(19))
-#define SPI_MEM_FLASH_HPM_V  0x1
-#define SPI_MEM_FLASH_HPM_S  19
-/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
-ion will be triggered when the bit is set. The bit will be cleared once the oper
-ation done.1: enable 0: disable..*/
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (BIT(18))
-#define SPI_MEM_USR_V  0x1
-#define SPI_MEM_USR_S  18
-/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
-/*description: In user mode, it is set to indicate that program/erase operation will be trigger
-ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
-peration done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (BIT(17))
-#define SPI_MEM_FLASH_PE_V  0x1
-#define SPI_MEM_FLASH_PE_S  17
-/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
-#define SPI_MEM_SLV_ST    0x0000000F
-#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
-#define SPI_MEM_SLV_ST_V  0xF
-#define SPI_MEM_SLV_ST_S  4
-/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
-, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
-nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
-#define SPI_MEM_MST_ST    0x0000000F
-#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
-#define SPI_MEM_MST_ST_V  0xF
-#define SPI_MEM_MST_ST_S  0
-
-#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
-/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
-address, the bit24-bit31 are the byte length of a transfer..*/
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_S  0
-
-#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
-/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
-lways 1. 0: Others..*/
-#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
-/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
-s 1. 0: Others..*/
-#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (BIT(24))
-#define SPI_MEM_FREAD_QIO_V  0x1
-#define SPI_MEM_FREAD_QIO_S  24
-/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (BIT(23))
-#define SPI_MEM_FREAD_DIO_V  0x1
-#define SPI_MEM_FREAD_DIO_S  23
-/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
-isable..*/
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (BIT(22))
-#define SPI_MEM_WRSR_2B_V  0x1
-#define SPI_MEM_WRSR_2B_S  22
-/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (BIT(21))
-#define SPI_MEM_WP_REG_V  0x1
-#define SPI_MEM_WP_REG_S  21
-/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define SPI_MEM_FREAD_QUAD_V  0x1
-#define SPI_MEM_FREAD_QUAD_S  20
-/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (BIT(19))
-#define SPI_MEM_D_POL_V  0x1
-#define SPI_MEM_D_POL_S  19
-/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (BIT(18))
-#define SPI_MEM_Q_POL_V  0x1
-#define SPI_MEM_Q_POL_S  18
-/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-spi_mem_flash_res bit. 1: enable 0: disable..*/
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (BIT(15))
-#define SPI_MEM_RESANDRES_V  0x1
-#define SPI_MEM_RESANDRES_S  15
-/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define SPI_MEM_FREAD_DUAL_V  0x1
-#define SPI_MEM_FREAD_DUAL_S  14
-/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
-UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define SPI_MEM_FASTRD_MODE_V  0x1
-#define SPI_MEM_FASTRD_MODE_S  13
-/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
-e.*/
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
-#define SPI_MEM_TX_CRC_EN_V  0x1
-#define SPI_MEM_TX_CRC_EN_S  11
-/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
-e low..*/
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_V  0x1
-#define SPI_MEM_FCS_CRC_EN_S  10
-/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (BIT(9))
-#define SPI_MEM_FCMD_OCT_V  0x1
-#define SPI_MEM_FCMD_OCT_S  9
-/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define SPI_MEM_FCMD_QUAD_V  0x1
-#define SPI_MEM_FCMD_QUAD_S  8
-/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (BIT(6))
-#define SPI_MEM_FADDR_OCT_V  0x1
-#define SPI_MEM_FADDR_OCT_S  6
-/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (BIT(5))
-#define SPI_MEM_FDIN_OCT_V  0x1
-#define SPI_MEM_FDIN_OCT_S  5
-/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
-#define SPI_MEM_FDOUT_OCT_V  0x1
-#define SPI_MEM_FDOUT_OCT_S  4
-/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
-is output by the MSPI controller in the second half part of dummy phase. It is u
-sed to pre-drive flash..*/
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_V  0x1
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
-s output by the MSPI controller in the first half part of dummy phase. It is use
-d to mask invalid SPI_DQS in the half part of dummy phase..*/
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_V  0x1
-#define SPI_MEM_FDUMMY_RIN_S  2
-/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_IO[7:0] is output by the MSPI controller..*/
-#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_DQS is output by the MSPI controller..*/
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-
-#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
-/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
- send signals to AXI. Set this bit to reset these FIFO..*/
-#define SPI_MEM_TXFIFO_RST    (BIT(31))
-#define SPI_MEM_TXFIFO_RST_M  (BIT(31))
-#define SPI_MEM_TXFIFO_RST_V  0x1
-#define SPI_MEM_TXFIFO_RST_S  31
-/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
- receive signals from AXI.  Set this bit to reset these FIFO..*/
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define SPI_MEM_RXFIFO_RST_V  0x1
-#define SPI_MEM_RXFIFO_RST_S  30
-/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
-bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
-in  tx_bus_fifo_l2..*/
-#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_M  (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_V  0x1
-#define SPI_MEM_FAST_WRITE_EN_S  29
-/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
-the same time..*/
-#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_M  (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_V  0x1
-#define SPI_MEM_DUAL_RAM_EN_S  28
-/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
-cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
-ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
-cessed at the same time..*/
-#define SPI_MEM_RAM0_EN    (BIT(27))
-#define SPI_MEM_RAM0_EN_M  (BIT(27))
-#define SPI_MEM_RAM0_EN_V  0x1
-#define SPI_MEM_RAM0_EN_S  27
-/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Write Splice-transfer..*/
-#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_M  (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_V  0x1
-#define SPI_MEM_AW_SPLICE_EN_S  26
-/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Read Splice-transfer..*/
-#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_M  (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_V  0x1
-#define SPI_MEM_AR_SPLICE_EN_S  25
-/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
- when there is a ECC error in AXI read data. The ECC error information is record
-ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
-#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x1
-#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
-/* SPI_MEM_SPI_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */
-/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
-eply AXI read data to AXI bus when all the read data is available..*/
-#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST    (BIT(23))
-#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_M  (BIT(23))
-#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_V  0x1
-#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_S  23
-/* SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
-#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
-#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V  0x1
-#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S  22
-/* SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
-y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
-#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
-#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V  0x1
-#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S  21
-/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
-/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
-12) SPI_CLK cycles..*/
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
-#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
-/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
-#define SPI_MEM_CLK_MODE    0x00000003
-#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
-#define SPI_MEM_CLK_MODE_V  0x3
-#define SPI_MEM_CLK_MODE_S  0
-
-#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
-/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (BIT(31))
-#define SPI_MEM_SYNC_RESET_V  0x1
-#define SPI_MEM_SYNC_RESET_S  31
-/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
- clock cycles..*/
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
-fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
-whether there is an ECC region or not..*/
-#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_V  0x1
-#define SPI_MEM_SPLIT_TRANS_EN_S  24
-/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses flash..*/
-#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */
-/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
-hen accesses flash..*/
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
- mode when accessed flash..*/
-#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
-/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
-th SPI_MEM_CS_HOLD bit..*/
-#define SPI_MEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
-#define SPI_MEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
-M_CS_SETUP bit..*/
-#define SPI_MEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
-#define SPI_MEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_CS_SETUP_TIME_S  0
-
-#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
-/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
- clock..*/
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
-/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- system/(spi_mem_clkcnt_N+1).*/
-#define SPI_MEM_CLKCNT_N    0x000000FF
-#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
-#define SPI_MEM_CLKCNT_N_V  0xFF
-#define SPI_MEM_CLKCNT_N_S  16
-/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define SPI_MEM_CLKCNT_H    0x000000FF
-#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
-#define SPI_MEM_CLKCNT_H_V  0xFF
-#define SPI_MEM_CLKCNT_H_S  8
-/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
-#define SPI_MEM_CLKCNT_L    0x000000FF
-#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
-#define SPI_MEM_CLKCNT_L_V  0xFF
-#define SPI_MEM_CLKCNT_L_S  0
-
-#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
-/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation..*/
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (BIT(31))
-#define SPI_MEM_USR_COMMAND_V  0x1
-#define SPI_MEM_USR_COMMAND_S  31
-/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation..*/
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (BIT(30))
-#define SPI_MEM_USR_ADDR_V  0x1
-#define SPI_MEM_USR_ADDR_S  30
-/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation..*/
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (BIT(29))
-#define SPI_MEM_USR_DUMMY_V  0x1
-#define SPI_MEM_USR_DUMMY_S  29
-/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation..*/
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (BIT(28))
-#define SPI_MEM_USR_MISO_V  0x1
-#define SPI_MEM_USR_MISO_S  28
-/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation..*/
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (BIT(27))
-#define SPI_MEM_USR_MOSI_V  0x1
-#define SPI_MEM_USR_MOSI_S  27
-/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable..*/
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-1: enable 0: disable..*/
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
-: enable 0: disable..*/
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 4 signals..*/
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
-#define SPI_MEM_FWRITE_QIO_V  0x1
-#define SPI_MEM_FWRITE_QIO_S  15
-/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 2 signals..*/
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
-#define SPI_MEM_FWRITE_DIO_V  0x1
-#define SPI_MEM_FWRITE_DIO_S  14
-/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals.*/
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_V  0x1
-#define SPI_MEM_FWRITE_QUAD_S  13
-/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals.*/
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_V  0x1
-#define SPI_MEM_FWRITE_DUAL_S  12
-/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_V  0x1
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (BIT(7))
-#define SPI_MEM_CS_SETUP_V  0x1
-#define SPI_MEM_CS_SETUP_S  7
-/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (BIT(6))
-#define SPI_MEM_CS_HOLD_V  0x1
-#define SPI_MEM_CS_HOLD_S  6
-
-#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
-/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
-/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
-/*description: SPI0 USR_CMD read or write data byte length -1.*/
-#define SPI_MEM_USR_DBYTELEN    0x00000007
-#define SPI_MEM_USR_DBYTELEN_M  ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S))
-#define SPI_MEM_USR_DBYTELEN_V  0x7
-#define SPI_MEM_USR_DBYTELEN_S  6
-/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
-cle_num-1)..*/
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
-/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
-/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command..*/
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
-#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
-/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
-
-#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
-/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
-
-#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
-/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
-it..*/
-#define SPI_MEM_WB_MODE    0x000000FF
-#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
-#define SPI_MEM_WB_MODE_V  0xFF
-#define SPI_MEM_WB_MODE_S  16
-/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
-#define SPI_MEM_STATUS    0x0000FFFF
-#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
-#define SPI_MEM_STATUS_V  0xFFFF
-#define SPI_MEM_STATUS_S  0
-
-#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
-/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: SPI_CS line keep low when the bit is set..*/
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
-/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_V  0x1
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0,  sram is connected to SUBPINs..*/
-#define SPI_MEM_SSUB_PIN    (BIT(8))
-#define SPI_MEM_SSUB_PIN_M  (BIT(8))
-#define SPI_MEM_SSUB_PIN_V  0x1
-#define SPI_MEM_SSUB_PIN_S  8
-/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0,  flash is connected to SUBPINs..*/
-#define SPI_MEM_FSUB_PIN    (BIT(7))
-#define SPI_MEM_FSUB_PIN_M  (BIT(7))
-#define SPI_MEM_FSUB_PIN_V  0x1
-#define SPI_MEM_FSUB_PIN_S  7
-/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (BIT(1))
-#define SPI_MEM_CS1_DIS_V  0x1
-#define SPI_MEM_CS1_DIS_S  1
-/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (BIT(0))
-#define SPI_MEM_CS0_DIS_V  0x1
-#define SPI_MEM_CS0_DIS_S  0
-
-#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
-/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: For SPI1, the value of crc32..*/
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_S  0
-
-#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
-/* SPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
-_ERR will be replied to BRESP/RRESP..*/
-#define SPI_MEM_SPI_CLOSE_AXI_INF_EN    (BIT(31))
-#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_M  (BIT(31))
-#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_V  0x1
-#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_S  31
-/* SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: Set this bit to check AXI read/write the same address region..*/
-#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
-#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x1
-#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
-/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_qio..*/
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define SPI_MEM_FADDR_QUAD_V  0x1
-#define SPI_MEM_FADDR_QUAD_S  8
-/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
-e same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_V  0x1
-#define SPI_MEM_FDOUT_QUAD_S  7
-/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
- same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define SPI_MEM_FDIN_QUAD_V  0x1
-#define SPI_MEM_FDIN_QUAD_S  6
-/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_dio..*/
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define SPI_MEM_FADDR_DUAL_V  0x1
-#define SPI_MEM_FADDR_DUAL_S  5
-/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
- same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_V  0x1
-#define SPI_MEM_FDOUT_DUAL_S  4
-/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define SPI_MEM_FDIN_DUAL_V  0x1
-#define SPI_MEM_FDIN_DUAL_S  3
-/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
-#define SPI_MEM_AXI_REQ_EN    (BIT(0))
-#define SPI_MEM_AXI_REQ_EN_M  (BIT(0))
-#define SPI_MEM_AXI_REQ_EN_V  0x1
-#define SPI_MEM_AXI_REQ_EN_S  0
-
-#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
-/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
-e. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
-/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: reserved.*/
-#define SPI_MEM_SRAM_OCT    (BIT(21))
-#define SPI_MEM_SRAM_OCT_M  (BIT(21))
-#define SPI_MEM_SRAM_OCT_V  0x1
-#define SPI_MEM_SRAM_OCT_S  21
-/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
-#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
-/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
-he register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
-#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
-/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
-. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
-/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
-nd..*/
-#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
-/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
- operations..*/
-#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
-/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
-e operations..*/
-#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
-/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
-le.*/
-#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_V  0x1
-#define SPI_MEM_USR_SRAM_QIO_S  2
-/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
-le.*/
-#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_V  0x1
-#define SPI_MEM_USR_SRAM_DIO_S  1
-/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
-able, 0:disable..*/
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
-
-#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
-/* SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
-] are always 1. 0: Others..*/
-#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_S  31
-/* SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
-e always 1. 0: Others..*/
-#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_S  30
-/* SPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDOUT_HEX    (BIT(27))
-#define SPI_MEM_SDOUT_HEX_M  (BIT(27))
-#define SPI_MEM_SDOUT_HEX_V  0x1
-#define SPI_MEM_SDOUT_HEX_S  27
-/* SPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDIN_HEX    (BIT(26))
-#define SPI_MEM_SDIN_HEX_M  (BIT(26))
-#define SPI_MEM_SDIN_HEX_V  0x1
-#define SPI_MEM_SDIN_HEX_S  26
-/* SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_IO[7:0] is output by the MSPI controller..*/
-#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
-#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/* SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_DQS is output by the MSPI controller..*/
-#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
-#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
-the signal level of SPI bus is output by the MSPI controller..*/
-#define SPI_MEM_SDUMMY_WOUT    (BIT(23))
-#define SPI_MEM_SDUMMY_WOUT_M  (BIT(23))
-#define SPI_MEM_SDUMMY_WOUT_V  0x1
-#define SPI_MEM_SDUMMY_WOUT_S  23
-/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
-he signal level of SPI bus is output by the MSPI controller..*/
-#define SPI_MEM_SDUMMY_RIN    (BIT(22))
-#define SPI_MEM_SDUMMY_RIN_M  (BIT(22))
-#define SPI_MEM_SDUMMY_RIN_V  0x1
-#define SPI_MEM_SDUMMY_RIN_S  22
-/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SCMD_OCT    (BIT(21))
-#define SPI_MEM_SCMD_OCT_M  (BIT(21))
-#define SPI_MEM_SCMD_OCT_V  0x1
-#define SPI_MEM_SCMD_OCT_S  21
-/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SADDR_OCT    (BIT(20))
-#define SPI_MEM_SADDR_OCT_M  (BIT(20))
-#define SPI_MEM_SADDR_OCT_V  0x1
-#define SPI_MEM_SADDR_OCT_S  20
-/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDOUT_OCT    (BIT(19))
-#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
-#define SPI_MEM_SDOUT_OCT_V  0x1
-#define SPI_MEM_SDOUT_OCT_S  19
-/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDIN_OCT    (BIT(18))
-#define SPI_MEM_SDIN_OCT_M  (BIT(18))
-#define SPI_MEM_SDIN_OCT_V  0x1
-#define SPI_MEM_SDIN_OCT_S  18
-/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SCMD_QUAD    (BIT(17))
-#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
-#define SPI_MEM_SCMD_QUAD_V  0x1
-#define SPI_MEM_SCMD_QUAD_S  17
-/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SADDR_QUAD    (BIT(16))
-#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
-#define SPI_MEM_SADDR_QUAD_V  0x1
-#define SPI_MEM_SADDR_QUAD_S  16
-/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SDOUT_QUAD    (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_V  0x1
-#define SPI_MEM_SDOUT_QUAD_S  15
-/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SDIN_QUAD    (BIT(14))
-#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
-#define SPI_MEM_SDIN_QUAD_V  0x1
-#define SPI_MEM_SDIN_QUAD_S  14
-/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SADDR_DUAL    (BIT(12))
-#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
-#define SPI_MEM_SADDR_DUAL_V  0x1
-#define SPI_MEM_SADDR_DUAL_S  12
-/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SDOUT_DUAL    (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_V  0x1
-#define SPI_MEM_SDOUT_DUAL_S  11
-/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SDIN_DUAL    (BIT(10))
-#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
-#define SPI_MEM_SDIN_DUAL_V  0x1
-#define SPI_MEM_SDIN_DUAL_S  10
-/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */
-/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
-_mode bit..*/
-#define SPI_MEM_SWB_MODE    0x000000FF
-#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
-#define SPI_MEM_SWB_MODE_V  0xFF
-#define SPI_MEM_SWB_MODE_S  2
-/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is always on..*/
-#define SPI_MEM_SCLK_MODE    0x00000003
-#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
-#define SPI_MEM_SCLK_MODE_V  0x3
-#define SPI_MEM_SCLK_MODE_S  0
-
-#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
- sram. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the read command value of command phase
- for sram..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
- The register value shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the write command value of command phas
-e for sram..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
-/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
-lk is divided from system clock..*/
-#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
-/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
-lk frequency is system/(spi_mem_clkcnt_N+1).*/
-#define SPI_MEM_SCLKCNT_N    0x000000FF
-#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
-#define SPI_MEM_SCLKCNT_N_V  0xFF
-#define SPI_MEM_SCLKCNT_N_S  16
-/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define SPI_MEM_SCLKCNT_H    0x000000FF
-#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
-#define SPI_MEM_SCLKCNT_H_V  0xFF
-#define SPI_MEM_SCLKCNT_H_S  8
-/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
-#define SPI_MEM_SCLKCNT_L    0x000000FF
-#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
-#define SPI_MEM_SCLKCNT_L_V  0xFF
-#define SPI_MEM_SCLKCNT_L_S  0
-
-#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
-/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
-/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
-#define SPI_MEM_LOCK_DELAY_TIME    0x0000001F
-#define SPI_MEM_LOCK_DELAY_TIME_M  ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S))
-#define SPI_MEM_LOCK_DELAY_TIME_V  0x1F
-#define SPI_MEM_LOCK_DELAY_TIME_S  7
-
-#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
-/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF0    0xFFFFFFFF
-#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
-#define SPI_MEM_BUF0_V  0xFFFFFFFF
-#define SPI_MEM_BUF0_S  0
-
-#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
-/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF1    0xFFFFFFFF
-#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
-#define SPI_MEM_BUF1_V  0xFFFFFFFF
-#define SPI_MEM_BUF1_S  0
-
-#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
-/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF2    0xFFFFFFFF
-#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
-#define SPI_MEM_BUF2_V  0xFFFFFFFF
-#define SPI_MEM_BUF2_S  0
-
-#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
-/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF3    0xFFFFFFFF
-#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
-#define SPI_MEM_BUF3_V  0xFFFFFFFF
-#define SPI_MEM_BUF3_S  0
-
-#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
-/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF4    0xFFFFFFFF
-#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
-#define SPI_MEM_BUF4_V  0xFFFFFFFF
-#define SPI_MEM_BUF4_S  0
-
-#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
-/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF5    0xFFFFFFFF
-#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
-#define SPI_MEM_BUF5_V  0xFFFFFFFF
-#define SPI_MEM_BUF5_S  0
-
-#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
-/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF6    0xFFFFFFFF
-#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
-#define SPI_MEM_BUF6_V  0xFFFFFFFF
-#define SPI_MEM_BUF6_S  0
-
-#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
-/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF7    0xFFFFFFFF
-#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
-#define SPI_MEM_BUF7_V  0xFFFFFFFF
-#define SPI_MEM_BUF7_S  0
-
-#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
-/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF8    0xFFFFFFFF
-#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
-#define SPI_MEM_BUF8_V  0xFFFFFFFF
-#define SPI_MEM_BUF8_S  0
-
-#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
-/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF9    0xFFFFFFFF
-#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
-#define SPI_MEM_BUF9_V  0xFFFFFFFF
-#define SPI_MEM_BUF9_S  0
-
-#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
-/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF10    0xFFFFFFFF
-#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
-#define SPI_MEM_BUF10_V  0xFFFFFFFF
-#define SPI_MEM_BUF10_S  0
-
-#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
-/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF11    0xFFFFFFFF
-#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
-#define SPI_MEM_BUF11_V  0xFFFFFFFF
-#define SPI_MEM_BUF11_S  0
-
-#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
-/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF12    0xFFFFFFFF
-#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
-#define SPI_MEM_BUF12_V  0xFFFFFFFF
-#define SPI_MEM_BUF12_S  0
-
-#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
-/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF13    0xFFFFFFFF
-#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
-#define SPI_MEM_BUF13_V  0xFFFFFFFF
-#define SPI_MEM_BUF13_S  0
-
-#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
-/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF14    0xFFFFFFFF
-#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
-#define SPI_MEM_BUF14_V  0xFFFFFFFF
-#define SPI_MEM_BUF14_S  0
-
-#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
-/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF15    0xFFFFFFFF
-#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
-#define SPI_MEM_BUF15_V  0xFFFFFFFF
-#define SPI_MEM_BUF15_S  0
-
-#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
-/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: The command value to wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_CMD    0x0000FFFF
-#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
-#define SPI_MEM_WAITI_CMD_V  0xFFFF
-#define SPI_MEM_WAITI_CMD_S  16
-/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: The dummy cycle length when wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is
- 8..*/
-#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_M  (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_V  0x1
-#define SPI_MEM_WAITI_CMD_2B_S  9
-/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI
-_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
-SPI_MEM_WAITI_ADDR_EN is cleared..*/
-#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S))
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x3
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
-/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out ad
-dress in RDSR or read SUS command transfer..*/
-#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_M  (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_V  0x1
-#define SPI_MEM_WAITI_ADDR_EN_S  2
-/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The dummy phase enable when wait flash idle (RDSR).*/
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_V  0x1
-#define SPI_MEM_WAITI_DUMMY_S  1
-/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
- Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
-Suspend/Resume are not supported..*/
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (BIT(0))
-#define SPI_MEM_WAITI_EN_V  0x1
-#define SPI_MEM_WAITI_EN_S  0
-
-#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
-/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
-/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
- it will be treated as check pass..*/
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
-/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
-s of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (BIT(24))
-#define SPI_MEM_PES_END_EN_V  0x1
-#define SPI_MEM_PES_END_EN_S  24
-/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
- of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (BIT(23))
-#define SPI_MEM_PER_END_EN_V  0x1
-#define SPI_MEM_PER_END_EN_S  23
-/* SPI_MEM_SPI_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
-hen check flash SUS/SUS1/SUS2 status bit.*/
-#define SPI_MEM_SPI_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_SPI_FMEM_RD_SUS_2B_M  (BIT(22))
-#define SPI_MEM_SPI_FMEM_RD_SUS_2B_V  0x1
-#define SPI_MEM_SPI_FMEM_RD_SUS_2B_S  22
-/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
-/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
-status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
-out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
-2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
-#define SPI_MEM_PESR_END_MSK    0x0000FFFF
-#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
-#define SPI_MEM_PESR_END_MSK_V  0xFFFF
-#define SPI_MEM_PESR_END_MSK_S  6
-/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable Auto-suspending function..*/
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_V  0x1
-#define SPI_MEM_FLASH_PES_EN_S  5
-/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
-pplication should send PER after PES is done..*/
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (BIT(4))
-#define SPI_MEM_PES_PER_EN_V  0x1
-#define SPI_MEM_PES_PER_EN_S  4
-/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase suspend command is sent. 0: SPI1 does not wait after program erase
- suspend command is sent..*/
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase resume command is sent. 0: SPI1 does not wait after program erase
-resume command is sent..*/
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit, program erase suspend operation will be triggered whe
-n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
-isable..*/
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (BIT(1))
-#define SPI_MEM_FLASH_PES_V  0x1
-#define SPI_MEM_FLASH_PES_S  1
-/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: program erase resume bit, program erase suspend operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: di
-sable..*/
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (BIT(0))
-#define SPI_MEM_FLASH_PER_V  0x1
-#define SPI_MEM_FLASH_PER_S  0
-
-#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
-/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
-/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
-..*/
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
-/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */
-/*description: Program/Erase suspend command..*/
-#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFF
-#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
-#define SPI_MEM_FLASH_PES_COMMAND_V  0xFFFF
-#define SPI_MEM_FLASH_PES_COMMAND_S  0
-
-#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
-/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */
-/*description: Program/Erase resume command..*/
-#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFF
-#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
-#define SPI_MEM_FLASH_PER_COMMAND_V  0xFFFF
-#define SPI_MEM_FLASH_PER_COMMAND_S  16
-/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng
-th of Program/Erase Suspend/Resume command is 8..*/
-#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_M  (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x1
-#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
-/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_V  0x1
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
-mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-after DP command is sent..*/
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after RES command is sent..*/
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after HPM command is sent..*/
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The status of flash suspend, only used in SPI1..*/
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (BIT(0))
-#define SPI_MEM_FLASH_SUS_V  0x1
-#define SPI_MEM_FLASH_SUS_S  0
-
-#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
-/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_ENA    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
-/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ENA_S  5
-/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_V  0x1
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_V  0x1
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_V  0x1
-#define SPI_MEM_PER_END_INT_ENA_S  0
-
-#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
-/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
-/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
-#define SPI_MEM_ECC_ERR_INT_CLR_S  5
-/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_V  0x1
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_V  0x1
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_V  0x1
-#define SPI_MEM_PER_END_INT_CLR_S  0
-
-#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
-/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-chip is loosing power and RTC module sends out brown out close flash request to
-SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
- and MSPI returns to idle state. 0: Others..*/
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
- address is invalid by compared to MMU configuration. 0: Others..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
-ite flash request is received. 0: Others..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
-address is invalid by compared to MMU configuration. 0: Others..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
-is rejected. 0: Others..*/
-#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
-/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
-et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
- times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
-. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
-his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
-ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
-I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
-of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
-d, this bit will not be triggered..*/
-#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
-#define SPI_MEM_ECC_ERR_INT_RAW_S  5
-/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
-is changed from non idle state to idle state. 0: Others..*/
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
-is changed from non idle state to idle state. It means that SPI_CS raises high.
-0: Others.*/
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
-E is sent and flash is already idle. 0: Others..*/
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_V  0x1
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
-mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_V  0x1
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
-mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_V  0x1
-#define SPI_MEM_PER_END_INT_RAW_S  0
-
-#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
-/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ST_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_ST_S  6
-/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ST_S  5
-/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_V  0x1
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_V  0x1
-#define SPI_MEM_PES_END_INT_ST_S  1
-/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_V  0x1
-#define SPI_MEM_PER_END_INT_ST_S  0
-
-#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
-/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
-..*/
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_SPI_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S  26
-/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to flash..*/
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to flash..*/
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the panda device..*/
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_SPI_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S  1
-/* SPI_MEM_SPI_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define SPI_MEM_SPI_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_SPI_FMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_SPI_FMEM_DDR_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_EN_S  0
-
-#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD8)
-/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
-]}..*/
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
-, 1'b0}..*/
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_SPI_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S  26
-/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to external RAM..*/
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to external RAM..*/
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the DDR psram..*/
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_SPI_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S  1
-/* SPI_MEM_SPI_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define SPI_MEM_SPI_SMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_SPI_SMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_DDR_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_EN_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x100)
-/* SPI_MEM_SPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_FMEM_PMS0_ECC    (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS0_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS0_ECC_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS0_ECC_S  2
-/* SPI_MEM_SPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_S  1
-/* SPI_MEM_SPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x104)
-/* SPI_MEM_SPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_FMEM_PMS1_ECC    (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS1_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS1_ECC_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS1_ECC_S  2
-/* SPI_MEM_SPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_S  1
-/* SPI_MEM_SPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x108)
-/* SPI_MEM_SPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_FMEM_PMS2_ECC    (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS2_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS2_ECC_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS2_ECC_S  2
-/* SPI_MEM_SPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_S  1
-/* SPI_MEM_SPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10C)
-/* SPI_MEM_SPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_FMEM_PMS3_ECC    (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS3_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_FMEM_PMS3_ECC_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS3_ECC_S  2
-/* SPI_MEM_SPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_S  1
-/* SPI_MEM_SPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x110)
-/* SPI_MEM_SPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S))
-#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x114)
-/* SPI_MEM_SPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S))
-#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x118)
-/* SPI_MEM_SPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S))
-#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x11C)
-/* SPI_MEM_SPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_M  ((SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S))
-#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x120)
-/* SPI_MEM_SPI_FMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_FMEM_PMS0_SIZE    0x00007FFF
-#define SPI_MEM_SPI_FMEM_PMS0_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS0_SIZE_S))
-#define SPI_MEM_SPI_FMEM_PMS0_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_FMEM_PMS0_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x124)
-/* SPI_MEM_SPI_FMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_FMEM_PMS1_SIZE    0x00007FFF
-#define SPI_MEM_SPI_FMEM_PMS1_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS1_SIZE_S))
-#define SPI_MEM_SPI_FMEM_PMS1_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_FMEM_PMS1_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x128)
-/* SPI_MEM_SPI_FMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_FMEM_PMS2_SIZE    0x00007FFF
-#define SPI_MEM_SPI_FMEM_PMS2_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS2_SIZE_S))
-#define SPI_MEM_SPI_FMEM_PMS2_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_FMEM_PMS2_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x12C)
-/* SPI_MEM_SPI_FMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_FMEM_PMS3_SIZE    0x00007FFF
-#define SPI_MEM_SPI_FMEM_PMS3_SIZE_M  ((SPI_MEM_SPI_FMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS3_SIZE_S))
-#define SPI_MEM_SPI_FMEM_PMS3_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_FMEM_PMS3_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x130)
-/* SPI_MEM_SPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_SMEM_PMS0_ECC    (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS0_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS0_ECC_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS0_ECC_S  2
-/* SPI_MEM_SPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_S  1
-/* SPI_MEM_SPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x134)
-/* SPI_MEM_SPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_SMEM_PMS1_ECC    (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS1_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS1_ECC_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS1_ECC_S  2
-/* SPI_MEM_SPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_S  1
-/* SPI_MEM_SPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x138)
-/* SPI_MEM_SPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_SMEM_PMS2_ECC    (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS2_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS2_ECC_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS2_ECC_S  2
-/* SPI_MEM_SPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_S  1
-/* SPI_MEM_SPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x13C)
-/* SPI_MEM_SPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SPI_SMEM_PMS3_ECC    (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS3_ECC_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_PMS3_ECC_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS3_ECC_S  2
-/* SPI_MEM_SPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_S  1
-/* SPI_MEM_SPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_V  0x1
-#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x140)
-/* SPI_MEM_SPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S))
-#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x144)
-/* SPI_MEM_SPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S))
-#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x148)
-/* SPI_MEM_SPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S))
-#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14C)
-/* SPI_MEM_SPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S    0x07FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_M  ((SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S))
-#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V  0x7FFFFFF
-#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x150)
-/* SPI_MEM_SPI_SMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_SMEM_PMS0_SIZE    0x00007FFF
-#define SPI_MEM_SPI_SMEM_PMS0_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS0_SIZE_S))
-#define SPI_MEM_SPI_SMEM_PMS0_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_SMEM_PMS0_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x154)
-/* SPI_MEM_SPI_SMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_SMEM_PMS1_SIZE    0x00007FFF
-#define SPI_MEM_SPI_SMEM_PMS1_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS1_SIZE_S))
-#define SPI_MEM_SPI_SMEM_PMS1_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_SMEM_PMS1_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x158)
-/* SPI_MEM_SPI_SMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_SMEM_PMS2_SIZE    0x00007FFF
-#define SPI_MEM_SPI_SMEM_PMS2_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS2_SIZE_S))
-#define SPI_MEM_SPI_SMEM_PMS2_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_SMEM_PMS2_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x15C)
-/* SPI_MEM_SPI_SMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SPI_SMEM_PMS3_SIZE    0x00007FFF
-#define SPI_MEM_SPI_SMEM_PMS3_SIZE_M  ((SPI_MEM_SPI_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS3_SIZE_S))
-#define SPI_MEM_SPI_SMEM_PMS3_SIZE_V  0x7FFF
-#define SPI_MEM_SPI_SMEM_PMS3_SIZE_S  0
-
-#define SPI_MEM_PMS_REJECT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x164)
-/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
-/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_IVD    (BIT(31))
-#define SPI_MEM_PMS_IVD_M  (BIT(31))
-#define SPI_MEM_PMS_IVD_V  0x1
-#define SPI_MEM_PMS_IVD_S  31
-/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
- is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_V  0x1
-#define SPI_MEM_PMS_MULTI_HIT_S  30
-/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_ST    (BIT(29))
-#define SPI_MEM_PMS_ST_M  (BIT(29))
-#define SPI_MEM_PMS_ST_V  0x1
-#define SPI_MEM_PMS_ST_S  29
-/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
-_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_LD    (BIT(28))
-#define SPI_MEM_PMS_LD_M  (BIT(28))
-#define SPI_MEM_PMS_LD_V  0x1
-#define SPI_MEM_PMS_LD_S  28
-/* SPI_MEM_PM_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
-#define SPI_MEM_PM_EN    (BIT(27))
-#define SPI_MEM_PM_EN_M  (BIT(27))
-#define SPI_MEM_PM_EN_V  0x1
-#define SPI_MEM_PM_EN_S  27
-/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_REJECT_ADDR    0x07FFFFFF
-#define SPI_MEM_REJECT_ADDR_M  ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S))
-#define SPI_MEM_REJECT_ADDR_V  0x7FFFFFF
-#define SPI_MEM_REJECT_ADDR_S  0
-
-#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x168)
-/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */
-/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
- to byte 0 bit 0 to byte 15 bit 7).*/
-#define SPI_MEM_ECC_ERR_BITS    0x0000007F
-#define SPI_MEM_ECC_ERR_BITS_M  ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S))
-#define SPI_MEM_ECC_ERR_BITS_V  0x7F
-#define SPI_MEM_ECC_ERR_BITS_S  25
-/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */
-/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
-ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
-R record the first ECC error information..*/
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */
-/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
-#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_USR_ECC_ADDR_EN_S  21
-/* SPI_MEM_SPI_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
-is bit should be 0. Otherwise, this bit should be 1..*/
-#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_M  (BIT(20))
-#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_S  20
-/* SPI_MEM_SPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
-1024 bytes. 3: 2048 bytes..*/
-#define SPI_MEM_SPI_FMEM_PAGE_SIZE    0x00000003
-#define SPI_MEM_SPI_FMEM_PAGE_SIZE_M  ((SPI_MEM_SPI_FMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_FMEM_PAGE_SIZE_S))
-#define SPI_MEM_SPI_FMEM_PAGE_SIZE_V  0x3
-#define SPI_MEM_SPI_FMEM_PAGE_SIZE_S  18
-/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
-h..*/
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S  17
-/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */
-/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
-upt..*/
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM    0x0000003F
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S))
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V  0x3F
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S  11
-/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[10:5] ;default: 6'd0 ; */
-/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define SPI_MEM_ECC_ERR_CNT    0x0000003F
-#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
-#define SPI_MEM_ECC_ERR_CNT_V  0x3F
-#define SPI_MEM_ECC_ERR_CNT_S  5
-
-#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x16C)
-/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define SPI_MEM_ECC_ERR_ADDR    0x07FFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
-#define SPI_MEM_ECC_ERR_ADDR_V  0x7FFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_S  0
-
-#define SPI_MEM_AXI_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x170)
-/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
-H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
-#define SPI_MEM_AXI_ERR_ADDR    0x07FFFFFF
-#define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
-#define SPI_MEM_AXI_ERR_ADDR_V  0x7FFFFFF
-#define SPI_MEM_AXI_ERR_ADDR_S  0
-
-#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x174)
-/* SPI_MEM_SPI_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
-ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
-#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_M  (BIT(20))
-#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_S  20
-/* SPI_MEM_SPI_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */
-/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
-es. 2: 1024 bytes. 3: 2048 bytes..*/
-#define SPI_MEM_SPI_SMEM_PAGE_SIZE    0x00000003
-#define SPI_MEM_SPI_SMEM_PAGE_SIZE_M  ((SPI_MEM_SPI_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_SMEM_PAGE_SIZE_S))
-#define SPI_MEM_SPI_SMEM_PAGE_SIZE_V  0x3
-#define SPI_MEM_SPI_SMEM_PAGE_SIZE_S  18
-/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
-rnal RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S  17
-
-#define SPI_MEM_SPI_SMEM_AXI_ADDR_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x178)
-/* SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
-and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
-#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
-#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
-#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
-/* SPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M  (BIT(30))
-#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S  30
-/* SPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY    (BIT(29))
-#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_M  (BIT(29))
-#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_S  29
-/* SPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
-/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY    (BIT(28))
-#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_M  (BIT(28))
-#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_S  28
-/* SPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY    (BIT(27))
-#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_M  (BIT(27))
-#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_S  27
-/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
-/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
- and SPI0 transfers are done. 0: Others..*/
-#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
-#define SPI_MEM_ALL_FIFO_EMPTY_S  26
-
-#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x180)
-/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
-#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_V  0x1
-#define SPI_MEM_TIMING_CALI_UPDATE_S  6
-/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
-lash..*/
-#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_V  0x1
-#define SPI_MEM_DLL_TIMING_CALI_S  5
-/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_TIMING_CALI_V  0x1
-#define SPI_MEM_TIMING_CALI_S  1
-/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable timing adjust clock for all reading operations..*/
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x184)
-/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DINS_MODE    0x00000007
-#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
-#define SPI_MEM_DINS_MODE_V  0x7
-#define SPI_MEM_DINS_MODE_S  24
-/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN7_MODE    0x00000007
-#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
-#define SPI_MEM_DIN7_MODE_V  0x7
-#define SPI_MEM_DIN7_MODE_S  21
-/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN6_MODE    0x00000007
-#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
-#define SPI_MEM_DIN6_MODE_V  0x7
-#define SPI_MEM_DIN6_MODE_S  18
-/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN5_MODE    0x00000007
-#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
-#define SPI_MEM_DIN5_MODE_V  0x7
-#define SPI_MEM_DIN5_MODE_S  15
-/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN4_MODE    0x00000007
-#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
-#define SPI_MEM_DIN4_MODE_V  0x7
-#define SPI_MEM_DIN4_MODE_S  12
-/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN3_MODE    0x00000007
-#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
-#define SPI_MEM_DIN3_MODE_V  0x7
-#define SPI_MEM_DIN3_MODE_S  9
-/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN2_MODE    0x00000007
-#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
-#define SPI_MEM_DIN2_MODE_V  0x7
-#define SPI_MEM_DIN2_MODE_S  6
-/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN1_MODE    0x00000007
-#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
-#define SPI_MEM_DIN1_MODE_V  0x7
-#define SPI_MEM_DIN1_MODE_S  3
-/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN0_MODE    0x00000007
-#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
-#define SPI_MEM_DIN0_MODE_V  0x7
-#define SPI_MEM_DIN0_MODE_S  0
-
-#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x188)
-/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DINS_NUM    0x00000003
-#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
-#define SPI_MEM_DINS_NUM_V  0x3
-#define SPI_MEM_DINS_NUM_S  16
-/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN7_NUM    0x00000003
-#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
-#define SPI_MEM_DIN7_NUM_V  0x3
-#define SPI_MEM_DIN7_NUM_S  14
-/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN6_NUM    0x00000003
-#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
-#define SPI_MEM_DIN6_NUM_V  0x3
-#define SPI_MEM_DIN6_NUM_S  12
-/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN5_NUM    0x00000003
-#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
-#define SPI_MEM_DIN5_NUM_V  0x3
-#define SPI_MEM_DIN5_NUM_S  10
-/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN4_NUM    0x00000003
-#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
-#define SPI_MEM_DIN4_NUM_V  0x3
-#define SPI_MEM_DIN4_NUM_S  8
-/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN3_NUM    0x00000003
-#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
-#define SPI_MEM_DIN3_NUM_V  0x3
-#define SPI_MEM_DIN3_NUM_S  6
-/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN2_NUM    0x00000003
-#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
-#define SPI_MEM_DIN2_NUM_V  0x3
-#define SPI_MEM_DIN2_NUM_S  4
-/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN1_NUM    0x00000003
-#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
-#define SPI_MEM_DIN1_NUM_V  0x3
-#define SPI_MEM_DIN1_NUM_S  2
-/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN0_NUM    0x00000003
-#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
-#define SPI_MEM_DIN0_NUM_V  0x3
-#define SPI_MEM_DIN0_NUM_S  0
-
-#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18C)
-/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_DOUTS_MODE_S  8
-/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_DOUT7_MODE_S  7
-/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_DOUT6_MODE_S  6
-/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_DOUT5_MODE_S  5
-/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_DOUT4_MODE_S  4
-/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_DOUT3_MODE_S  3
-/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_DOUT2_MODE_S  2
-/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_DOUT1_MODE_S  1
-/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x190)
-/* SPI_MEM_SPI_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
-XT_RAM..*/
-#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_M  (BIT(5))
-#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_V  0x1
-#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_S  5
-/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_SPI_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
-ations..*/
-#define SPI_MEM_SPI_SMEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_V  0x1
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_S  1
-/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
-ns..*/
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x194)
-/* SPI_MEM_SPI_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DINS_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DINS_MODE_M  ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S))
-#define SPI_MEM_SPI_SMEM_DINS_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DINS_MODE_S  24
-/* SPI_MEM_SPI_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN7_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN7_MODE_M  ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN7_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN7_MODE_S  21
-/* SPI_MEM_SPI_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN6_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN6_MODE_M  ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN6_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN6_MODE_S  18
-/* SPI_MEM_SPI_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN5_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN5_MODE_M  ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN5_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN5_MODE_S  15
-/* SPI_MEM_SPI_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN4_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN4_MODE_M  ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN4_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN4_MODE_S  12
-/* SPI_MEM_SPI_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN3_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN3_MODE_M  ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN3_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN3_MODE_S  9
-/* SPI_MEM_SPI_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN2_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN2_MODE_M  ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN2_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN2_MODE_S  6
-/* SPI_MEM_SPI_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN1_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN1_MODE_M  ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN1_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN1_MODE_S  3
-/* SPI_MEM_SPI_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN0_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN0_MODE_M  ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN0_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x198)
-/* SPI_MEM_SPI_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DINS_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DINS_NUM_M  ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S))
-#define SPI_MEM_SPI_SMEM_DINS_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DINS_NUM_S  16
-/* SPI_MEM_SPI_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN7_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN7_NUM_M  ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN7_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN7_NUM_S  14
-/* SPI_MEM_SPI_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN6_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN6_NUM_M  ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN6_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN6_NUM_S  12
-/* SPI_MEM_SPI_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN5_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN5_NUM_M  ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN5_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN5_NUM_S  10
-/* SPI_MEM_SPI_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN4_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN4_NUM_M  ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN4_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN4_NUM_S  8
-/* SPI_MEM_SPI_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN3_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN3_NUM_M  ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN3_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN3_NUM_S  6
-/* SPI_MEM_SPI_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN2_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN2_NUM_M  ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN2_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN2_NUM_S  4
-/* SPI_MEM_SPI_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN1_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN1_NUM_M  ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN1_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN1_NUM_S  2
-/* SPI_MEM_SPI_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN0_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN0_NUM_M  ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN0_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN0_NUM_S  0
-
-#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x19C)
-/* SPI_MEM_SPI_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S  8
-/* SPI_MEM_SPI_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S  7
-/* SPI_MEM_SPI_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S  6
-/* SPI_MEM_SPI_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S  5
-/* SPI_MEM_SPI_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S  4
-/* SPI_MEM_SPI_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S  3
-/* SPI_MEM_SPI_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S  2
-/* SPI_MEM_SPI_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S  1
-/* SPI_MEM_SPI_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A0)
-/* SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
- transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
-er whether there is an ECC region or not..*/
-#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
-#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_S  31
-/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
-SPI core clock cycles..*/
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses external RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
-/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
-en accesses external RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
-ycles in ECC mode when accessed external RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S  12
-/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */
-/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
-re combined with spi_mem_cs_hold bit..*/
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S  7
-/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
-/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
-pi_mem_cs_setup bit..*/
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S))
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S  2
-/* SPI_MEM_SPI_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
-le..*/
-#define SPI_MEM_SPI_SMEM_CS_HOLD    (BIT(1))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_V  0x1
-#define SPI_MEM_SPI_SMEM_CS_HOLD_S  1
-/* SPI_MEM_SPI_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
-isable..*/
-#define SPI_MEM_SPI_SMEM_CS_SETUP    (BIT(0))
-#define SPI_MEM_SPI_SMEM_CS_SETUP_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_CS_SETUP_V  0x1
-#define SPI_MEM_SPI_SMEM_CS_SETUP_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_HEX_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A4)
-/* SPI_MEM_SPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_M  ((SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S))
-#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S  24
-/* SPI_MEM_SPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN15_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN15_MODE_M  ((SPI_MEM_SPI_SMEM_DIN15_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN15_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN15_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN15_MODE_S  21
-/* SPI_MEM_SPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN14_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN14_MODE_M  ((SPI_MEM_SPI_SMEM_DIN14_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN14_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN14_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN14_MODE_S  18
-/* SPI_MEM_SPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN13_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN13_MODE_M  ((SPI_MEM_SPI_SMEM_DIN13_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN13_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN13_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN13_MODE_S  15
-/* SPI_MEM_SPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN12_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN12_MODE_M  ((SPI_MEM_SPI_SMEM_DIN12_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN12_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN12_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN12_MODE_S  12
-/* SPI_MEM_SPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN11_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN11_MODE_M  ((SPI_MEM_SPI_SMEM_DIN11_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN11_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN11_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN11_MODE_S  9
-/* SPI_MEM_SPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN10_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN10_MODE_M  ((SPI_MEM_SPI_SMEM_DIN10_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN10_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN10_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN10_MODE_S  6
-/* SPI_MEM_SPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN09_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN09_MODE_M  ((SPI_MEM_SPI_SMEM_DIN09_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN09_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN09_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN09_MODE_S  3
-/* SPI_MEM_SPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DIN08_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN08_MODE_M  ((SPI_MEM_SPI_SMEM_DIN08_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN08_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN08_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN08_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_HEX_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A8)
-/* SPI_MEM_SPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_M  ((SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S))
-#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S  16
-/* SPI_MEM_SPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN15_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN15_NUM_M  ((SPI_MEM_SPI_SMEM_DIN15_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN15_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN15_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN15_NUM_S  14
-/* SPI_MEM_SPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN14_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN14_NUM_M  ((SPI_MEM_SPI_SMEM_DIN14_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN14_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN14_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN14_NUM_S  12
-/* SPI_MEM_SPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN13_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN13_NUM_M  ((SPI_MEM_SPI_SMEM_DIN13_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN13_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN13_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN13_NUM_S  10
-/* SPI_MEM_SPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN12_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN12_NUM_M  ((SPI_MEM_SPI_SMEM_DIN12_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN12_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN12_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN12_NUM_S  8
-/* SPI_MEM_SPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN11_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN11_NUM_M  ((SPI_MEM_SPI_SMEM_DIN11_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN11_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN11_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN11_NUM_S  6
-/* SPI_MEM_SPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN10_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN10_NUM_M  ((SPI_MEM_SPI_SMEM_DIN10_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN10_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN10_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN10_NUM_S  4
-/* SPI_MEM_SPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN09_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN09_NUM_M  ((SPI_MEM_SPI_SMEM_DIN09_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN09_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN09_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN09_NUM_S  2
-/* SPI_MEM_SPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SPI_SMEM_DIN08_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN08_NUM_M  ((SPI_MEM_SPI_SMEM_DIN08_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN08_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN08_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN08_NUM_S  0
-
-#define SPI_MEM_SPI_SMEM_DOUT_HEX_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1AC)
-/* SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE    (BIT(8))
-#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_M  (BIT(8))
-#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_S  8
-/* SPI_MEM_SPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT15_MODE    (BIT(7))
-#define SPI_MEM_SPI_SMEM_DOUT15_MODE_M  (BIT(7))
-#define SPI_MEM_SPI_SMEM_DOUT15_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT15_MODE_S  7
-/* SPI_MEM_SPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT14_MODE    (BIT(6))
-#define SPI_MEM_SPI_SMEM_DOUT14_MODE_M  (BIT(6))
-#define SPI_MEM_SPI_SMEM_DOUT14_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT14_MODE_S  6
-/* SPI_MEM_SPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT13_MODE    (BIT(5))
-#define SPI_MEM_SPI_SMEM_DOUT13_MODE_M  (BIT(5))
-#define SPI_MEM_SPI_SMEM_DOUT13_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT13_MODE_S  5
-/* SPI_MEM_SPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT12_MODE    (BIT(4))
-#define SPI_MEM_SPI_SMEM_DOUT12_MODE_M  (BIT(4))
-#define SPI_MEM_SPI_SMEM_DOUT12_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT12_MODE_S  4
-/* SPI_MEM_SPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT11_MODE    (BIT(3))
-#define SPI_MEM_SPI_SMEM_DOUT11_MODE_M  (BIT(3))
-#define SPI_MEM_SPI_SMEM_DOUT11_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT11_MODE_S  3
-/* SPI_MEM_SPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT10_MODE    (BIT(2))
-#define SPI_MEM_SPI_SMEM_DOUT10_MODE_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_DOUT10_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT10_MODE_S  2
-/* SPI_MEM_SPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT09_MODE    (BIT(1))
-#define SPI_MEM_SPI_SMEM_DOUT09_MODE_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_DOUT09_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT09_MODE_S  1
-/* SPI_MEM_SPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SPI_SMEM_DOUT08_MODE    (BIT(0))
-#define SPI_MEM_SPI_SMEM_DOUT08_MODE_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_DOUT08_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT08_MODE_S  0
-
-#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x200)
-/* SPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
-#define SPI_MEM_SPI_CLK_EN    (BIT(0))
-#define SPI_MEM_SPI_CLK_EN_M  (BIT(0))
-#define SPI_MEM_SPI_CLK_EN_V  0x1
-#define SPI_MEM_SPI_CLK_EN_S  0
-
-#define SPI_MEM_XTS_PLAIN_BASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x300)
-/* SPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field is only used to generate include file in c case. This field is useles
-s. Please do not use this field..*/
-#define SPI_MEM_SPI_XTS_PLAIN    0xFFFFFFFF
-#define SPI_MEM_SPI_XTS_PLAIN_M  ((SPI_MEM_SPI_XTS_PLAIN_V)<<(SPI_MEM_SPI_XTS_PLAIN_S))
-#define SPI_MEM_SPI_XTS_PLAIN_V  0xFFFFFFFF
-#define SPI_MEM_SPI_XTS_PLAIN_S  0
-
-#define SPI_MEM_XTS_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
-/* SPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the line-size parameter which will be used in manual encryption
- calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
- 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
-#define SPI_MEM_SPI_XTS_LINESIZE    0x00000003
-#define SPI_MEM_SPI_XTS_LINESIZE_M  ((SPI_MEM_SPI_XTS_LINESIZE_V)<<(SPI_MEM_SPI_XTS_LINESIZE_S))
-#define SPI_MEM_SPI_XTS_LINESIZE_V  0x3
-#define SPI_MEM_SPI_XTS_LINESIZE_S  0
-
-#define SPI_MEM_XTS_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
-/* SPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
-n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
-used..*/
-#define SPI_MEM_SPI_XTS_DESTINATION    (BIT(0))
-#define SPI_MEM_SPI_XTS_DESTINATION_M  (BIT(0))
-#define SPI_MEM_SPI_XTS_DESTINATION_V  0x1
-#define SPI_MEM_SPI_XTS_DESTINATION_S  0
-
-#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
-/* SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits stores the physical-address parameter which will be used in manual enc
-ryption calculation. This value should aligned with byte number decided by line-
-size parameter..*/
-#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFF
-#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M  ((SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S))
-#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V  0x3FFFFFF
-#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S  0
-
-#define SPI_MEM_XTS_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
-/* SPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to trigger the process of manual encryption calculation. This actio
-n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
-n status becomes 2..*/
-#define SPI_MEM_SPI_XTS_TRIGGER    (BIT(0))
-#define SPI_MEM_SPI_XTS_TRIGGER_M  (BIT(0))
-#define SPI_MEM_SPI_XTS_TRIGGER_V  0x1
-#define SPI_MEM_SPI_XTS_TRIGGER_S  0
-
-#define SPI_MEM_XTS_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
-/* SPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to release encrypted result to mspi. This action should only be ass
-erted when manual encryption status is 2. After this action, manual encryption s
-tatus will become 3..*/
-#define SPI_MEM_SPI_XTS_RELEASE    (BIT(0))
-#define SPI_MEM_SPI_XTS_RELEASE_M  (BIT(0))
-#define SPI_MEM_SPI_XTS_RELEASE_V  0x1
-#define SPI_MEM_SPI_XTS_RELEASE_S  0
-
-#define SPI_MEM_XTS_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
-/* SPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
-en manual encryption status is 3. After this action, manual encryption status wi
-ll become 0..*/
-#define SPI_MEM_SPI_XTS_DESTROY    (BIT(0))
-#define SPI_MEM_SPI_XTS_DESTROY_M  (BIT(0))
-#define SPI_MEM_SPI_XTS_DESTROY_V  0x1
-#define SPI_MEM_SPI_XTS_DESTROY_S  0
-
-#define SPI_MEM_XTS_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
-/* SPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
- calculation, 2: encryption calculation is done but the encrypted result is invi
-sible to mspi, 3: the encrypted result is visible to mspi..*/
-#define SPI_MEM_SPI_XTS_STATE    0x00000003
-#define SPI_MEM_SPI_XTS_STATE_M  ((SPI_MEM_SPI_XTS_STATE_V)<<(SPI_MEM_SPI_XTS_STATE_S))
-#define SPI_MEM_SPI_XTS_STATE_V  0x3
-#define SPI_MEM_SPI_XTS_STATE_S  0
-
-#define SPI_MEM_XTS_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
-/* SPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
-/*description: This bits stores the last modified-time of manual encryption feature..*/
-#define SPI_MEM_SPI_XTS_DATE    0x3FFFFFFF
-#define SPI_MEM_SPI_XTS_DATE_M  ((SPI_MEM_SPI_XTS_DATE_V)<<(SPI_MEM_SPI_XTS_DATE_S))
-#define SPI_MEM_SPI_XTS_DATE_V  0x3FFFFFFF
-#define SPI_MEM_SPI_XTS_DATE_S  0
-
-#define SPI_MEM_MMU_ITEM_CONTENT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x37C)
-/* SPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: MSPI-MMU item content.*/
-#define SPI_MEM_SPI_MMU_ITEM_CONTENT    0xFFFFFFFF
-#define SPI_MEM_SPI_MMU_ITEM_CONTENT_M  ((SPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(SPI_MEM_SPI_MMU_ITEM_CONTENT_S))
-#define SPI_MEM_SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFF
-#define SPI_MEM_SPI_MMU_ITEM_CONTENT_S  0
-
-#define SPI_MEM_MMU_ITEM_INDEX_REG(i)          (REG_SPI_MEM_BASE(i) + 0x380)
-/* SPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: MSPI-MMU item index.*/
-#define SPI_MEM_SPI_MMU_ITEM_INDEX    0xFFFFFFFF
-#define SPI_MEM_SPI_MMU_ITEM_INDEX_M  ((SPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(SPI_MEM_SPI_MMU_ITEM_INDEX_S))
-#define SPI_MEM_SPI_MMU_ITEM_INDEX_V  0xFFFFFFFF
-#define SPI_MEM_SPI_MMU_ITEM_INDEX_S  0
-
-#define SPI_MEM_MMU_POWER_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x384)
-/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
-#define SPI_MEM_RDN_RESULT    (BIT(31))
-#define SPI_MEM_RDN_RESULT_M  (BIT(31))
-#define SPI_MEM_RDN_RESULT_V  0x1
-#define SPI_MEM_RDN_RESULT_S  31
-/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: ECO register enable bit.*/
-#define SPI_MEM_RDN_ENA    (BIT(30))
-#define SPI_MEM_RDN_ENA_M  (BIT(30))
-#define SPI_MEM_RDN_ENA_V  0x1
-#define SPI_MEM_RDN_ENA_S  30
-/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */
-/*description: MMU PSRAM aux control register.*/
-#define SPI_MEM_AUX_CTRL    0x00003FFF
-#define SPI_MEM_AUX_CTRL_M  ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S))
-#define SPI_MEM_AUX_CTRL_V  0x3FFF
-#define SPI_MEM_AUX_CTRL_S  16
-/* SPI_MEM_SPI_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
-/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/
-#define SPI_MEM_SPI_MMU_PAGE_SIZE    0x00000003
-#define SPI_MEM_SPI_MMU_PAGE_SIZE_M  ((SPI_MEM_SPI_MMU_PAGE_SIZE_V)<<(SPI_MEM_SPI_MMU_PAGE_SIZE_S))
-#define SPI_MEM_SPI_MMU_PAGE_SIZE_V  0x3
-#define SPI_MEM_SPI_MMU_PAGE_SIZE_S  3
-/* SPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
- controlled by rtc..*/
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PU    (BIT(2))
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_M  (BIT(2))
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_V  0x1
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_S  2
-/* SPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to force mmu-memory powerdown.*/
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PD    (BIT(1))
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_M  (BIT(1))
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_V  0x1
-#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_S  1
-/* SPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable mmu-memory clock force on.*/
-#define SPI_MEM_SPI_MMU_MEM_FORCE_ON    (BIT(0))
-#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_M  (BIT(0))
-#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_V  0x1
-#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_S  0
-
-#define SPI_MEM_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
-/* SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
-T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
-#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
-#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V  0x1
-#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S  4
-/* SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
-ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
-ing key 1..*/
-#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
-#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V  0x1
-#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S  3
-/* SPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
-7: The bigger the number is, the more secure the cryption is. (Note that the per
-formance of cryption will decrease together with this number increasing).*/
-#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL    0x00000007
-#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M  ((SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S))
-#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V  0x7
-#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S  0
-
-#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F0)
-/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO high register.*/
-#define SPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_HIGH_M  ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
-#define SPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_HIGH_S  0
-
-#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F4)
-/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO low register.*/
-#define SPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_LOW_M  ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S))
-#define SPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_LOW_S  0
-
-#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
-/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2212091 ; */
-/*description: SPI0 register version..*/
-#define SPI_MEM_DATE    0x0FFFFFFF
-#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
-#define SPI_MEM_DATE_V  0xFFFFFFF
-#define SPI_MEM_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
+#include "soc/spi_mem_c_reg.h"
+#include "soc/spi1_mem_c_reg.h"
diff --git a/components/soc/esp32p4/include/soc/spi_mem_struct.h b/components/soc/esp32p4/include/soc/spi_mem_struct.h
index 73af7d2536d..13568f66a09 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32p4/include/soc/spi_mem_struct.h
@@ -1,1138 +1,20 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
-#include <stdint.h>
+#include "soc/spi_mem_c_struct.h"
+#include "soc/spi1_mem_c_struct.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct spi_mem_dev_s {
-    union {
-        struct {
-            uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
-            uint32_t slv_st                        :    4;  /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
-            uint32_t reserved8                     :    9;  /*reserved*/
-            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t usr                           :    1;  /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
-            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t fdummy_rin                    :    1;  /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/
-            uint32_t fdummy_wout                   :    1;  /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/
-            uint32_t fdout_oct                     :    1;  /*Apply 8 signals during write-data phase 1:enable 0: disable*/
-            uint32_t fdin_oct                      :    1;  /*Apply 8 signals during read-data phase 1:enable 0: disable*/
-            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during address phase 1:enable 0: disable*/
-            uint32_t reserved7                     :    1;  /*reserved*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
-            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable*/
-            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
-            uint32_t reserved12                    :    1;  /*reserved*/
-            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
-            uint32_t reserved16                    :    2;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
-            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
-            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t reserved25                    :    5;  /*reserved*/
-            uint32_t dqs_ie_always_on              :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t data_ie_always_on             :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
-            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
-            uint32_t reserved2                     :    9;  /*reserved*/
-            uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_aw_size0_1_support_en     :    1;  /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_axi_rdata_back_fast       :    1;  /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/
-            uint32_t rresp_ecc_err_en              :    1;  /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/
-            uint32_t ar_splice_en                  :    1;  /*Set this bit to enable AXI Read Splice-transfer.*/
-            uint32_t aw_splice_en                  :    1;  /*Set this bit to enable AXI Write Splice-transfer.*/
-            uint32_t ram0_en                       :    1;  /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t dual_ram_en                   :    1;  /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t fast_write_en                 :    1;  /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.*/
-            uint32_t rxfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.*/
-            uint32_t txfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/
-            uint32_t cs_hold_time                  :    5;  /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/
-            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/
-            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
-            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
-            uint32_t reserved15                    :    9;  /*reserved*/
-            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t sync_reset                    :    1;  /*The spi0_mst_st and spi0_slv_st will be reset.*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
-            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
-            uint32_t clk_equ_sysclk                :    1;  /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
-            uint32_t reserved8                     :    1;  /*reserved*/
-            uint32_t ck_out_edge                   :    1;  /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
-            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
-            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
-            uint32_t reserved16                    :    8;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
-            uint32_t usr_dbytelen                  :    3;  /*SPI0 USR_CMD read or write data byte length -1*/
-            uint32_t reserved9                     :    17;  /*reserved*/
-            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    union {
-        struct {
-            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } rd_status;
-    uint32_t reserved_30;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t reserved0                     :    5;  /*reserved*/
-            uint32_t fsub_pin                      :    1;  /*For SPI0,  flash is connected to SUBPINs.*/
-            uint32_t ssub_pin                      :    1;  /*For SPI0,  sram is connected to SUBPINs.*/
-            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle     0: spi clk line is low when idle */
-            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } misc;
-    uint32_t tx_crc;
-    union {
-        struct {
-            uint32_t axi_req_en                    :    1;  /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
-            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
-            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
-            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t reserved9                     :    21;  /*reserved*/
-            uint32_t reg_same_aw_ar_addr_chk_en    :    1;  /*Set this bit to check AXI read/write the same address region.*/
-            uint32_t reg_close_axi_inf_en          :    1;  /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    union {
-        struct {
-            uint32_t usr_saddr_4byte               :    1;  /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
-            uint32_t usr_sram_dio                  :    1;  /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_sram_qio                  :    1;  /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_wr_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
-            uint32_t usr_rd_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
-            uint32_t sram_usr_rcmd                 :    1;  /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
-            uint32_t sram_rdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved12                    :    2;  /*reserved*/
-            uint32_t sram_addr_bitlen              :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
-            uint32_t sram_usr_wcmd                 :    1;  /*For SPI0, In the external RAM mode cache write sram for user define command*/
-            uint32_t sram_oct                      :    1;  /*reserved*/
-            uint32_t sram_wdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_sctrl;
-    union {
-        struct {
-            uint32_t sclk_mode                     :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
-            uint32_t swb_mode                      :    8;  /*Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t sdin_dual                     :    1;  /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t sdout_dual                    :    1;  /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t saddr_dual                    :    1;  /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t reserved13                    :    1;  /*reserved*/
-            uint32_t sdin_quad                     :    1;  /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdout_quad                    :    1;  /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t saddr_quad                    :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t scmd_quad                     :    1;  /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdin_oct                      :    1;  /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdout_oct                     :    1;  /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t saddr_oct                     :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t scmd_oct                      :    1;  /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdummy_rin                    :    1;  /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t sdummy_wout                   :    1;  /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t sdin_hex                      :    1;  /*For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. */
-            uint32_t sdout_hex                     :    1;  /*For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. */
-            uint32_t reserved28                    :    2;  /*reserved*/
-            uint32_t dqs_ie_always_on              :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t data_ie_always_on             :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } sram_cmd;
-    union {
-        struct {
-            uint32_t sram_usr_rd_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t sram_usr_rd_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_drd_cmd;
-    union {
-        struct {
-            uint32_t usr_wr_cmd_value              :    16;  /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_wr_cmd_bitlen             :    4;  /*For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_dwr_cmd;
-    union {
-        struct {
-            uint32_t cnt_l                         :    8;  /*For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.*/
-            uint32_t cnt_h                         :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t cnt_n                         :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t equ_sysclk                    :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
-        };
-        uint32_t val;
-    } sram_clk;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;  /*reserved*/
-            uint32_t lock_delay_time               :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } fsm;
-    uint32_t data_buf[16];
-    union {
-        struct {
-            uint32_t waiti_en                      :    1;  /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/
-            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
-            uint32_t waiti_addr_en                 :    1;  /*1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/
-            uint32_t waiti_addr_cyclelen           :    2;  /*When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/
-            uint32_t reserved5                     :    4;  /*reserved*/
-            uint32_t waiti_cmd_2b                  :    1;  /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/
-            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
-            uint32_t waiti_cmd                     :    16;  /*The command value to wait flash idle(RDSR).*/
-        };
-        uint32_t val;
-    } flash_waiti_ctrl;
-    union {
-        struct {
-            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
-            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
-            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
-            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
-            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
-            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
-            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
-        };
-        uint32_t val;
-    } flash_sus_ctrl;
-    union {
-        struct {
-            uint32_t flash_pes_command             :    16;  /*Program/Erase suspend command.*/
-            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
-        };
-        uint32_t val;
-    } flash_sus_cmd;
-    union {
-        struct {
-            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
-            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
-            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
-            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
-            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
-            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
-            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
-            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
-            uint32_t reserved8                     :    7;  /*reserved*/
-            uint32_t flash_pesr_cmd_2b             :    1;  /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/
-            uint32_t flash_per_command             :    16;  /*Program/Erase resume command.*/
-        };
-        uint32_t val;
-    } sus_status;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    union {
-        struct {
-            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject_en                 :    1;  /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err_en           :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved10                    :    17;  /*reserved*/
-            uint32_t dqs0_afifo_ovf_en             :    1;  /*The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/
-            uint32_t dqs1_afifo_ovf_en             :    1;  /*The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/
-            uint32_t bus_fifo1_udf_en              :    1;  /*The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/
-            uint32_t bus_fifo0_udf_en              :    1;  /*The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved10                    :    17;  /*reserved*/
-            uint32_t dqs0_afifo_ovf                :    1;  /*The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/
-            uint32_t dqs1_afifo_ovf                :    1;  /*The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/
-            uint32_t bus_fifo1_udf                 :    1;  /*The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/
-            uint32_t bus_fifo0_udf                 :    1;  /*The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
-            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
-            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
-            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
-            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/
-            uint32_t ecc_err                       :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
-            uint32_t pms_reject                    :    1;  /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/
-            uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
-            uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
-            uint32_t reserved10                    :    17;  /*reserved*/
-            uint32_t dqs0_afifo_ovf                :    1;  /*The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow.*/
-            uint32_t dqs1_afifo_ovf                :    1;  /*The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow.*/
-            uint32_t bus_fifo1_udf                 :    1;  /*The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow.*/
-            uint32_t bus_fifo0_udf                 :    1;  /*The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow.*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved10                    :    17;  /*reserved*/
-            uint32_t dqs0_afifo_ovf                :    1;  /*The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/
-            uint32_t dqs1_afifo_ovf                :    1;  /*The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/
-            uint32_t bus_fifo1_udf                 :    1;  /*The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/
-            uint32_t bus_fifo0_udf                 :    1;  /*The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/
-        };
-        uint32_t val;
-    } int_st;
-    uint32_t reserved_d0;
-    union {
-        struct {
-            uint32_t fmem_ddr_en                   :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t fmem_var_dummy                :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t fmem_ddr_rdat_swp             :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t fmem_ddr_wdat_swp             :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t fmem_ddr_cmd_dis              :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t fmem_outminbytelen            :    7;  /*It is the minimum output data length in the panda device.*/
-            uint32_t fmem_tx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
-            uint32_t fmem_rx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/
-            uint32_t fmem_usr_ddr_dqs_thd          :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t fmem_ddr_dqs_loop             :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t fmem_clk_diff_en              :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t fmem_dqs_ca_in                :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t fmem_hyperbus_dummy_2x        :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t fmem_clk_diff_inv             :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
-            uint32_t fmem_octa_ram_addr            :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t fmem_hyperbus_ca              :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } ddr;
-    union {
-        struct {
-            uint32_t ddr_en                        :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t var_dummy                     :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t ddr_rdat_swp                  :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t ddr_wdat_swp                  :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t ddr_cmd_dis                   :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t outminbytelen                 :    7;  /*It is the minimum output data length in the DDR psram.*/
-            uint32_t tx_ddr_msk_en                 :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/
-            uint32_t rx_ddr_msk_en                 :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/
-            uint32_t usr_ddr_dqs_thd               :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t ddr_dqs_loop                  :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t clk_diff_en                   :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t dqs_ca_in                     :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t hyperbus_dummy_2x             :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t clk_diff_inv                  :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
-            uint32_t octa_ram_addr                 :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t hyperbus_ca                   :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ddr;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    union {
-        struct {
-            uint32_t fmem_pms0_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t fmem_pms0_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t fmem_pms0_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_attr;
-    union {
-        struct {
-            uint32_t fmem_pms1_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t fmem_pms1_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t fmem_pms1_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_attr;
-    union {
-        struct {
-            uint32_t fmem_pms2_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t fmem_pms2_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t fmem_pms2_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_attr;
-    union {
-        struct {
-            uint32_t fmem_pms3_rd_attr             :    1;  /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t fmem_pms3_wr_attr             :    1;  /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t fmem_pms3_ecc                 :    1;  /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_attr;
-    union {
-        struct {
-            uint32_t fmem_pms0_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_addr;
-    union {
-        struct {
-            uint32_t fmem_pms1_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_addr;
-    union {
-        struct {
-            uint32_t fmem_pms2_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_addr;
-    union {
-        struct {
-            uint32_t fmem_pms3_addr_s              :    26;  /*SPI1 flash PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_addr;
-    union {
-        struct {
-            uint32_t fmem_pms0_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_size;
-    union {
-        struct {
-            uint32_t fmem_pms1_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_size;
-    union {
-        struct {
-            uint32_t fmem_pms2_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_size;
-    union {
-        struct {
-            uint32_t fmem_pms3_size                :    14;  /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_size;
-    union {
-        struct {
-            uint32_t pms0_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t pms0_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t pms0_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_attr;
-    union {
-        struct {
-            uint32_t pms1_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t pms1_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t pms1_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_attr;
-    union {
-        struct {
-            uint32_t pms2_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t pms2_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t pms2_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_attr;
-    union {
-        struct {
-            uint32_t pms3_rd_attr                  :    1;  /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/
-            uint32_t pms3_wr_attr                  :    1;  /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/
-            uint32_t pms3_ecc                      :    1;  /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_attr;
-    union {
-        struct {
-            uint32_t pms0_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_addr;
-    union {
-        struct {
-            uint32_t pms1_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_addr;
-    union {
-        struct {
-            uint32_t pms2_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_addr;
-    union {
-        struct {
-            uint32_t pms3_addr_s                   :    26;  /*SPI1 external RAM PMS section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_addr;
-    union {
-        struct {
-            uint32_t pms0_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_size;
-    union {
-        struct {
-            uint32_t pms1_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_size;
-    union {
-        struct {
-            uint32_t pms2_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_size;
-    union {
-        struct {
-            uint32_t pms3_size                     :    14;  /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_size;
-    uint32_t reserved_160;
-    union {
-        struct {
-            uint32_t reject_addr                   :    26;  /*This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pm_en                         :    1;  /*Set this bit to enable SPI0/1 transfer permission control function.*/
-            uint32_t reserved27                    :    1;  /*reserved*/
-            uint32_t pms_ld                        :    1;  /*1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_st                        :    1;  /*1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_multi_hit                 :    1;  /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_ivd                       :    1;  /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } pms_reject;
-    union {
-        struct {
-            uint32_t reserved0                     :    11;  /*reserved*/
-            uint32_t ecc_err_int_num               :    6;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t fmem_ecc_err_int_en           :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
-            uint32_t fmem_page_size                :    2;  /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t fmem_ecc_addr_en              :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t usr_ecc_addr_en               :    1;  /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t ecc_continue_record_err_en    :    1;  /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/
-            uint32_t ecc_err_bits                  :    7;  /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/
-        };
-        uint32_t val;
-    } ecc_ctrl;
-    union {
-        struct {
-            uint32_t ecc_err_addr                  :    26;  /*This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-            uint32_t ecc_err_cnt                   :    6;  /*This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } ecc_err_addr;
-    union {
-        struct {
-            uint32_t axi_err_addr                  :    26;  /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
-            uint32_t all_fifo_empty                :    1;  /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
-            uint32_t reg_rdata_afifo_rempty        :    1;  /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_raddr_afifo_rempty        :    1;  /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_wdata_afifo_rempty        :    1;  /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_wblen_afifo_rempty        :    1;  /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_all_axi_trans_afifo_empty :    1;  /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/
-        };
-        uint32_t val;
-    } axi_err_addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    17;  /*reserved*/
-            uint32_t ecc_err_int_en                :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
-            uint32_t page_size                     :    2;  /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t ecc_addr_en                   :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ecc_ctrl;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    union {
-        struct {
-            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/
-            uint32_t timing_cali_update            :    1;  /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/
-            uint32_t reserved7                     :    25;  /*reserved*/
-        };
-        uint32_t val;
-    } timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    union {
-        struct {
-            uint32_t timing_clk_ena                :    1;  /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali                   :    1;  /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen          :    3;  /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_dout_mode;
-    union {
-        struct {
-            uint32_t cs_setup                      :    1;  /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
-            uint32_t cs_hold                       :    1;  /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
-            uint32_t cs_setup_time                 :    5;  /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
-            uint32_t cs_hold_time                  :    5;  /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
-            uint32_t ecc_cs_hold_time              :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/
-            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
-            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
-            uint32_t reserved17                    :    8;  /*reserved*/
-            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-        };
-        uint32_t val;
-    } spi_smem_ac;
-    union {
-        struct {
-            uint32_t din08_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din09_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din10_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din11_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din12_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din13_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din14_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din15_mode                    :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t dins_hex_mode                 :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_hex_mode;
-    union {
-        struct {
-            uint32_t din08_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din09_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din10_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din11_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din12_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din13_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din14_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din15_num                     :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t dins_hex_num                  :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_hex_num;
-    union {
-        struct {
-            uint32_t dout08_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout09_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout10_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout11_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout12_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout13_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout14_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout15_mode                   :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t douts_hex_mode                :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_dout_hex_mode;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t xts_plain_base;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    union {
-        struct {
-            uint32_t reg_xts_linesize              :    2;  /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_linesize;
-    union {
-        struct {
-            uint32_t reg_xts_destination           :    1;  /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destination;
-    union {
-        struct {
-            uint32_t reg_xts_physical_address      :    26;  /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_physical_address;
-    union {
-        struct {
-            uint32_t reg_xts_trigger               :    1;  /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_trigger;
-    union {
-        struct {
-            uint32_t reg_xts_release               :    1;  /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_release;
-    union {
-        struct {
-            uint32_t reg_xts_destroy               :    1;  /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destroy;
-    union {
-        struct {
-            uint32_t reg_xts_state                 :    2;  /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_state;
-    union {
-        struct {
-            uint32_t reg_xts_date                  :    30;  /*This bits stores the last modified-time of manual encryption feature.*/
-            uint32_t reserved30                    :    2;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_date;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t mmu_item_content;
-    uint32_t mmu_item_index;
-    union {
-        struct {
-            uint32_t mem_force_on                  :    1;  /*Set this bit to enable mmu-memory clock force on*/
-            uint32_t mem_force_pd                  :    1;  /*Set this bit to force mmu-memory powerdown*/
-            uint32_t mem_force_pu                  :    1;  /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/
-            uint32_t reserved3                     :    13;  /*reserved*/
-            uint32_t aux_ctrl                      :    14;  /*MMU PSRAM aux control register*/
-            uint32_t rdn_ena                       :    1;  /*ECO register enable bit*/
-            uint32_t rdn_result                    :    1;  /*MSPI module clock domain and AXI clock domain ECO register result register*/
-        };
-        uint32_t val;
-    } mmu_power_ctrl;
-    union {
-        struct {
-            uint32_t crtyp_security_level          :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
-            uint32_t crtyp_calc_d_dpa_en           :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
-            uint32_t crtyp_dpa_selectister         :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } dpa_ctrl;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t registeredrnd_eco_high;
-    uint32_t registeredrnd_eco_low;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI0 register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_mem_dev_t;
-extern spi_mem_dev_t SPIMEM0;
+typedef struct spi1_mem_c_dev_s spi_mem_dev_t;
 extern spi_mem_dev_t SPIMEM1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
-#endif
+extern spi_mem_c_dev_t SPIMEM0;
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/include/soc/spi_periph.h b/components/soc/include/soc/spi_periph.h
index f127fa26876..28a4f049e53 100644
--- a/components/soc/include/soc/spi_periph.h
+++ b/components/soc/include/soc/spi_periph.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index 9c145f1ee7f..862e57e5b55 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -402,12 +402,17 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void)
 
 IRAM_ATTR void esp_config_data_cache_mode(void)
 {
+#define CACHE_SIZE_0KB  99  //If Cache set to 0 KB, cache is bypassed, the cache size doesn't take into effect. Set this macro to a unique value for log
+
     cache_size_t cache_size;
     cache_ways_t cache_ways;
     cache_line_size_t cache_line_size;
 
 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
-#if CONFIG_ESP32S2_DATA_CACHE_8KB
+#if CONFIG_ESP32S2_DATA_CACHE_0KB
+    Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
+    cache_size = CACHE_SIZE_0KB;
+#elif CONFIG_ESP32S2_DATA_CACHE_8KB
     Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
     cache_size = CACHE_SIZE_8KB;
 #else
@@ -415,7 +420,10 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
     cache_size = CACHE_SIZE_16KB;
 #endif
 #else
-#if CONFIG_ESP32S2_DATA_CACHE_8KB
+#if CONFIG_ESP32S2_DATA_CACHE_0KB
+    Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
+    cache_size = CACHE_SIZE_0KB;
+#elif CONFIG_ESP32S2_DATA_CACHE_8KB
     Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
     cache_size = CACHE_SIZE_8KB;
 #else
@@ -430,7 +438,7 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
 #else
     cache_line_size = CACHE_LINE_SIZE_32B;
 #endif
-    ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32);
+    ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", (cache_size == CACHE_SIZE_0KB) ? 0 : ((cache_size == CACHE_SIZE_8KB) ? 8 : 16), 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32);
     Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
     Cache_Invalidate_DCache_All();
 }
diff --git a/components/spi_flash/spi_flash_wrap.c b/components/spi_flash/spi_flash_wrap.c
index 3a514d435f5..e43f8d31b7a 100644
--- a/components/spi_flash/spi_flash_wrap.c
+++ b/components/spi_flash/spi_flash_wrap.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "spi_flash_defs.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
+#include "rom/spi_flash.h"
 #include "spi_flash_override.h"
 #include "esp_private/spi_flash_os.h"
 
@@ -87,9 +88,9 @@ esp_err_t spi_flash_wrap_enable_77(spi_flash_wrap_size_t wrap_size)
 {
     uint8_t wrap_code = (uint8_t) (((__builtin_ctz(wrap_size) - 3) * 2) << 4);
     // According to the special format, we need enable QIO_FWRITE for command 77h and clear it after this command is done.
-    REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
+    REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
     bootloader_flash_execute_command_common(CMD_WRAP, 0, 0, 6, 8, wrap_code, 0);
-    REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
+    REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
     return ESP_OK;
 }
 
@@ -110,9 +111,9 @@ esp_err_t spi_flash_wrap_clear_c0(void)
 esp_err_t spi_flash_wrap_clear_77(void)
 {
     // According to the special format, we need enable QIO_FWRITE for command 77h and clear it after this command is done.
-    REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
+    REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
     bootloader_flash_execute_command_common(CMD_WRAP, 0, 0, 6, 8, 0x10, 0);
-    REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
+    REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
     return ESP_OK;
 }
 
@@ -153,7 +154,7 @@ esp_err_t spi_flash_wrap_disable(void)
 bool spi_flash_support_wrap_size(uint32_t wrap_size)
 {
     // Only QIO mode supports wrap.
-    if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO)) {
+    if (!REG_GET_BIT(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO)) {
         ESP_EARLY_LOGE(FLASH_WRAP_TAG, "flash wrap is only supported in QIO mode");
         abort();
     }
diff --git a/components/spi_flash/test_apps/.build-test-rules.yml b/components/spi_flash/test_apps/.build-test-rules.yml
index 6011e396609..ea0839892e8 100644
--- a/components/spi_flash/test_apps/.build-test-rules.yml
+++ b/components/spi_flash/test_apps/.build-test-rules.yml
@@ -1,10 +1,6 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
 components/spi_flash/test_apps/esp_flash:
-  disable:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: target esp32p4 is not supported yet # TODO: IDF-7499
   depends_filepatterns:
     - components/bootloader_support/bootloader_flash/**/*
   depends_components:
@@ -28,9 +24,6 @@ components/spi_flash/test_apps/flash_encryption:
 components/spi_flash/test_apps/flash_suspend:
   disable:
     - if: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND != 1
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: target esp32p4 is not supported yet # TODO: IDF-7499
   disable_test:
     - if: IDF_TARGET != "esp32c3"
       temporary: true
diff --git a/components/spi_flash/test_apps/esp_flash/README.md b/components/spi_flash/test_apps/esp_flash/README.md
index a8b7833fa30..bf47d80ec64 100644
--- a/components/spi_flash/test_apps/esp_flash/README.md
+++ b/components/spi_flash/test_apps/esp_flash/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
index 5761165ed24..766ea621d08 100644
--- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
+++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -97,6 +97,24 @@
 #define FSPI_PIN_NUM_WP     5
 #define FSPI_PIN_NUM_CS     17
 
+// Just use the same pins for HSPI
+#define HSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
+#define HSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
+#define HSPI_PIN_NUM_CLK    FSPI_PIN_NUM_CLK
+#define HSPI_PIN_NUM_HD     FSPI_PIN_NUM_HD
+#define HSPI_PIN_NUM_WP     FSPI_PIN_NUM_WP
+#define HSPI_PIN_NUM_CS     FSPI_PIN_NUM_CS
+
+#elif CONFIG_IDF_TARGET_ESP32P4
+
+// Normal IOMUX pins
+#define FSPI_PIN_NUM_MOSI   8
+#define FSPI_PIN_NUM_MISO   10
+#define FSPI_PIN_NUM_CLK    9
+#define FSPI_PIN_NUM_HD     6
+#define FSPI_PIN_NUM_WP     11
+#define FSPI_PIN_NUM_CS     7
+
 // Just use the same pins for HSPI
 #define HSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
 #define HSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
diff --git a/components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c b/components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c
index b8759919656..aefc037d8b0 100644
--- a/components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c
+++ b/components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c
@@ -122,7 +122,7 @@ TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_fla
 }
 
 //  TODO: This test is disabled on S3 with legacy impl - IDF-3505
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4)
 
 #if portNUM_PROCESSORS > 1
 TEST_CASE("spi_flash deadlock with high priority busy-waiting task", "[spi_flash][esp_flash]")
diff --git a/components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py b/components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py
index 53d206d9f3d..8eeed76f5cc 100644
--- a/components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py
+++ b/components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py
@@ -6,7 +6,6 @@
 
 
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD')  # TODO: IDF-8984
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/components/vfs/CMakeLists.txt b/components/vfs/CMakeLists.txt
index 1a090fa1e90..96f9c886303 100644
--- a/components/vfs/CMakeLists.txt
+++ b/components/vfs/CMakeLists.txt
@@ -10,10 +10,9 @@ list(APPEND sources "vfs.c"
                     "vfs_console.c"
                     )
 
-list(APPEND pr driver
-               esp_timer
+list(APPEND pr esp_timer
                # for backwards compatibility (TODO: IDF-8799)
-               esp_driver_uart
+               esp_driver_uart esp_driver_usb_serial_jtag
                )
 
 idf_component_register(SRCS ${sources}
@@ -26,10 +25,6 @@ if(CONFIG_ESP_CONSOLE_USB_CDC)
     target_sources(${COMPONENT_LIB} PRIVATE "vfs_cdcacm.c")
 endif()
 
-if(CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG OR CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG)
-    target_sources(${COMPONENT_LIB} PRIVATE "vfs_usb_serial_jtag.c")
-endif()
-
 # Some newlib syscalls are implemented in vfs.c, make sure these are always
 # seen by the linker
 target_link_libraries(${COMPONENT_LIB} INTERFACE "-u vfs_include_syscalls_impl")
diff --git a/components/vfs/include/esp_vfs_dev.h b/components/vfs/include/esp_vfs_dev.h
index a6513ca27f9..b3df3254ba3 100644
--- a/components/vfs/include/esp_vfs_dev.h
+++ b/components/vfs/include/esp_vfs_dev.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -60,14 +60,14 @@ void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) __attribute__
  * @note application must configure USB-SERIAL-JTAG driver before calling these functions
  * With these functions, read and write are blocking and interrupt-driven.
  */
-void esp_vfs_usb_serial_jtag_use_driver(void);
+void esp_vfs_usb_serial_jtag_use_driver(void) __attribute__((deprecated("Please use usb_serial_jtag_vfs_use_driver() instead")));
 
 /**
  * @brief set VFS to use simple functions for reading and writing UART
  * Read is non-blocking, write is busy waiting until TX FIFO has enough space.
  * These functions are used by default.
  */
-void esp_vfs_usb_serial_jtag_use_nonblocking(void);
+void esp_vfs_usb_serial_jtag_use_nonblocking(void) __attribute__((deprecated("Please use usb_serial_jtag_vfs_use_nonblocking() instead")));
 
 #ifdef __cplusplus
 }
diff --git a/components/vfs/include/esp_vfs_usb_serial_jtag.h b/components/vfs/include/esp_vfs_usb_serial_jtag.h
index c53a671be89..8350f960326 100644
--- a/components/vfs/include/esp_vfs_usb_serial_jtag.h
+++ b/components/vfs/include/esp_vfs_usb_serial_jtag.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,44 +14,11 @@
 extern "C" {
 #endif
 
-/**
- * @brief add /dev/usbserjtag virtual filesystem driver
- *
- * This function is called from startup code to enable console output
- */
-esp_err_t esp_vfs_dev_usb_serial_jtag_register(void);
+esp_err_t esp_vfs_dev_usb_serial_jtag_register(void) __attribute__((deprecated("Please use usb_serial_jtag_vfs_register instead")));
 
-/**
- * @brief Set the line endings expected to be received
- *
- * This specifies the conversion between line endings received and
- * newlines ('\n', LF) passed into stdin:
- *
- * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF
- * - ESP_LINE_ENDINGS_CR: convert CR to LF
- * - ESP_LINE_ENDINGS_LF: no modification
- *
- * @note this function is not thread safe w.r.t. reading
- *
- * @param mode line endings expected
- */
-void esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(esp_line_endings_t mode);
+void esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(esp_line_endings_t mode) __attribute__((deprecated("Please use usb_serial_jtag_vfs_set_rx_line_endings instead")));
 
-/**
- * @brief Set the line endings to sent
- *
- * This specifies the conversion between newlines ('\n', LF) on stdout and line
- * endings sent:
- *
- * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF
- * - ESP_LINE_ENDINGS_CR: convert LF to CR
- * - ESP_LINE_ENDINGS_LF: no modification
- *
- * @note this function is not thread safe w.r.t. writing
- *
- * @param mode line endings to send
- */
-void esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(esp_line_endings_t mode);
+void esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(esp_line_endings_t mode) __attribute__((deprecated("Please use usb_serial_jtag_vfs_set_tx_line_endings instead")));
 
 #ifdef __cplusplus
 }
diff --git a/components/vfs/vfs_console.c b/components/vfs/vfs_console.c
index 336feed706f..37d2c420982 100644
--- a/components/vfs/vfs_console.c
+++ b/components/vfs/vfs_console.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,7 +8,6 @@
 #include "esp_rom_sys.h"
 #include "esp_vfs_cdcacm.h"
 #include "esp_vfs_private.h"
-#include "esp_vfs_usb_serial_jtag.h"
 #include "esp_private/usb_console.h"
 #include "esp_vfs_console.h"
 #include "esp_private/esp_vfs_console.h"
@@ -59,7 +58,7 @@ int console_open(const char * path, int flags, int mode)
 #if CONFIG_ESP_CONSOLE_UART
     vfs_console.fd_primary = get_vfs_for_path(primary_path)->vfs.open("/"STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM), flags, mode);
 #elif CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
-    vfs_console.fd_primary = esp_vfs_usb_serial_jtag_get_vfs()->open("/", flags, mode);
+    vfs_console.fd_primary = get_vfs_for_path(primary_path)->vfs.open("/", flags, mode);
 #elif CONFIG_ESP_CONSOLE_USB_CDC
     vfs_console.fd_primary = esp_vfs_cdcacm_get_vfs()->open("/", flags, mode);
 #endif
@@ -199,7 +198,7 @@ esp_err_t esp_vfs_console_register(void)
 {
     esp_err_t err = ESP_OK;
 // Primary register part.
-#ifdef CONFIG_ESP_CONSOLE_UART
+#if CONFIG_ESP_CONSOLE_UART || CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
     assert(primary_vfs);
 #elif CONFIG_ESP_CONSOLE_USB_CDC
     primary_vfs = esp_vfs_cdcacm_get_vfs();
@@ -207,9 +206,7 @@ esp_err_t esp_vfs_console_register(void)
     if (err != ESP_OK) {
         return err;
     }
-#elif CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
-    primary_vfs = esp_vfs_usb_serial_jtag_get_vfs();
-#endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
+#endif
     err = esp_vfs_register_common(primary_path, strlen(primary_path), primary_vfs, NULL, &primary_vfs_index);
     if (err != ESP_OK) {
         return err;
@@ -217,7 +214,7 @@ esp_err_t esp_vfs_console_register(void)
 
 // Secondary register part.
 #if CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
-    secondary_vfs = esp_vfs_usb_serial_jtag_get_vfs();
+    assert(secondary_vfs);
     err = esp_vfs_register_common(secondary_path, strlen(secondary_path), secondary_vfs, NULL, &secondary_vfs_index);
     if(err != ESP_OK) {
         return err;
diff --git a/docs/en/api-guides/performance/size.rst b/docs/en/api-guides/performance/size.rst
index d14ec93d1eb..14d2dfdd2a3 100644
--- a/docs/en/api-guides/performance/size.rst
+++ b/docs/en/api-guides/performance/size.rst
@@ -441,7 +441,7 @@ lwIP IPv6
 
   .. note::
 
-      IPv6 is required by some components such as ``coap`` and :doc:`/api-reference/protocols/asio`. These components will not be available if IPV6 is disabled.
+      IPv6 is required by some components such as :doc:`/api-reference/protocols/asio`. These components will not be available if IPV6 is disabled.
 
 lwIP IPv4
 @@@@@@@@@
diff --git a/docs/en/api-reference/peripherals/sdmmc_host.rst b/docs/en/api-reference/peripherals/sdmmc_host.rst
index 5b8f231447b..b8517de4ba2 100644
--- a/docs/en/api-reference/peripherals/sdmmc_host.rst
+++ b/docs/en/api-reference/peripherals/sdmmc_host.rst
@@ -76,6 +76,7 @@ Overview
     - :c:macro:`SDMMC_HOST_SLOT_1` is routed via GPIO Matrix. This means that any GPIO may be used for each of the SD card signals. It is for non UHS-I usage.
     - :c:macro:`SDMMC_HOST_SLOT_0` is dedicated to UHS-I mode, which is not yet supported in the driver.
 
+    Currently SDMMC host driver is using the on-chip LDO 4 as the default power supply. SDMMC power control driver is not supported yet. If you buy the ESP32P4 chip itself and plan to use SDMMC peripheral, make sure the VDDPST_5 pin is connected to the on-chip LDO 4 or correct external power supply.
 
 Supported Speed Modes
 ---------------------
diff --git a/docs/en/migration-guides/release-5.x/5.3/peripherals.rst b/docs/en/migration-guides/release-5.x/5.3/peripherals.rst
index 483139b7664..2a13c56cc76 100644
--- a/docs/en/migration-guides/release-5.x/5.3/peripherals.rst
+++ b/docs/en/migration-guides/release-5.x/5.3/peripherals.rst
@@ -26,6 +26,7 @@ In order to control the dependence of other components on drivers at a smaller g
 - `esp_driver_uart` - Driver for UART
 - `esp_driver_ledc` - Driver for LEDC
 - `esp_driver_parlio` - Driver for Parallel IO
+- `esp_driver_usb_serial_jtag` - Driver for USB_SERIAL_JTAG
 
 For compatibility, the original `driver`` component is still treated as an all-in-one component by registering these `esp_driver_xyz`` components as its public dependencies. In other words, you do not need to modify the CMake file of an existing project, but you now have a way to specify the specific peripheral driver that your project depends on.
 
diff --git a/docs/zh_CN/api-guides/performance/size.rst b/docs/zh_CN/api-guides/performance/size.rst
index db8e43870fa..86eec89b68a 100644
--- a/docs/zh_CN/api-guides/performance/size.rst
+++ b/docs/zh_CN/api-guides/performance/size.rst
@@ -441,7 +441,7 @@ lwIP IPv6
 
   .. note::
 
-      如果禁用 IPv6， ``coap`` 和 :doc:`/api-reference/protocols/asio` 等组件将无法使用。
+      如果禁用 IPv6，:doc:`/api-reference/protocols/asio` 等组件将无法使用。
 
 lwIP IPv4
 @@@@@@@@@
diff --git a/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst b/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst
index 743db13cf86..5d49cd7ad55 100644
--- a/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst
+++ b/docs/zh_CN/migration-guides/release-5.x/5.3/peripherals.rst
@@ -26,6 +26,7 @@
 - `esp_driver_uart` - UART 驱动
 - `esp_driver_ledc` - LEDC 驱动
 - `esp_driver_parlio` - 并行 IO 驱动
+- `esp_driver_usb_serial_jtag` - USB_SERIAL_JTAG 驱动
 
 为了兼容性，原来的 `driver` 组件仍然存在，并作为一个 “all-in-one" 的组件，将以上这些 `esp_driver_xyz` 组件注册成自己的公共依赖。换句话说，你无需修改既有项目的 CMake 文件，但是你现在多了一个途径去指定你项目依赖的具体的外设驱动。
 
diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml
index e8c91f93cf8..1941ae6f5a3 100644
--- a/examples/peripherals/.build-test-rules.yml
+++ b/examples/peripherals/.build-test-rules.yml
@@ -453,3 +453,5 @@ examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo:
     - if: IDF_TARGET not in ["esp32c6"]
       temporary: true
       reason: lack of runners. Hardware is similar, test on one target is enough currently.
+  depends_components:
+    - esp_driver_usb_serial_jtag
diff --git a/examples/protocols/esp_http_client/main/esp_http_client_example.c b/examples/protocols/esp_http_client/main/esp_http_client_example.c
index b0bafef2e04..07b70feedcf 100644
--- a/examples/protocols/esp_http_client/main/esp_http_client_example.c
+++ b/examples/protocols/esp_http_client/main/esp_http_client_example.c
@@ -651,6 +651,31 @@ static void https_async(void)
         ESP_LOGE(TAG, "Error perform http request %s", esp_err_to_name(err));
     }
     esp_http_client_cleanup(client);
+
+    // Test HTTP_METHOD_HEAD with is_async enabled
+    config.url = "https://"CONFIG_EXAMPLE_HTTP_ENDPOINT"/get";
+    config.event_handler = _http_event_handler;
+    config.crt_bundle_attach = esp_crt_bundle_attach;
+    config.is_async = true;
+    config.timeout_ms = 5000;
+
+    client = esp_http_client_init(&config);
+    esp_http_client_set_method(client, HTTP_METHOD_HEAD);
+
+    while (1) {
+        err = esp_http_client_perform(client);
+        if (err != ESP_ERR_HTTP_EAGAIN) {
+            break;
+        }
+    }
+    if (err == ESP_OK) {
+        ESP_LOGI(TAG, "HTTPS Status = %d, content_length = %"PRId64,
+                esp_http_client_get_status_code(client),
+                esp_http_client_get_content_length(client));
+    } else {
+        ESP_LOGE(TAG, "Error perform http request %s", esp_err_to_name(err));
+    }
+    esp_http_client_cleanup(client);
 }
 
 static void https_with_invalid_url(void)
diff --git a/examples/protocols/esp_http_client/pytest_esp_http_client.py b/examples/protocols/esp_http_client/pytest_esp_http_client.py
index 853d7f8a4ed..dc229272010 100644
--- a/examples/protocols/esp_http_client/pytest_esp_http_client.py
+++ b/examples/protocols/esp_http_client/pytest_esp_http_client.py
@@ -46,6 +46,7 @@ def test_examples_protocol_esp_http_client(dut: Dut) -> None:
     # content-len for chunked encoding is typically -1, could be a positive length in some cases
     dut.expect(r'HTTP Stream reader Status = 200, content_length = (\d)')
     dut.expect(r'HTTPS Status = 200, content_length = (\d)')
+    dut.expect(r'HTTPS Status = 200, content_length = (\d)')
     dut.expect(r'Last esp error code: 0x8001')
     dut.expect(r'HTTP GET Status = 200, content_length = (\d)')
     dut.expect(r'HTTP POST Status = 200, content_length = (\d)')
@@ -92,6 +93,7 @@ def test_examples_protocol_esp_http_client_dynamic_buffer(dut: Dut) -> None:
     # content-len for chunked encoding is typically -1, could be a positive length in some cases
     dut.expect(r'HTTP Stream reader Status = 200, content_length = (\d)')
     dut.expect(r'HTTPS Status = 200, content_length = (\d)')
+    dut.expect(r'HTTPS Status = 200, content_length = (\d)')
     dut.expect(r'Last esp error code: 0x8001')
     dut.expect(r'HTTP GET Status = 200, content_length = (\d)')
     dut.expect(r'HTTP POST Status = 200, content_length = (\d)')
diff --git a/examples/protocols/http_server/advanced_tests/main/tests.c b/examples/protocols/http_server/advanced_tests/main/tests.c
index 3780670a539..916f7470b3a 100644
--- a/examples/protocols/http_server/advanced_tests/main/tests.c
+++ b/examples/protocols/http_server/advanced_tests/main/tests.c
@@ -4,6 +4,7 @@
 #include <esp_log.h>
 #include <esp_system.h>
 #include <esp_http_server.h>
+#include "esp_check.h"
 
 #include "tests.h"
 
@@ -221,6 +222,7 @@ static esp_err_t adder_post_handler(httpd_req_t *req)
     if (! req->sess_ctx) {
         ESP_LOGI(TAG, "/adder allocating new session");
         req->sess_ctx = malloc(sizeof(int));
+        ESP_RETURN_ON_FALSE(req->sess_ctx, ESP_ERR_NO_MEM, TAG, "Failed to allocate sess_ctx");
         req->free_ctx = adder_free_func;
         *(int *)req->sess_ctx = 0;
     }
@@ -286,6 +288,7 @@ static esp_err_t async_get_handler(httpd_req_t *req)
      * socket again
      */
     struct async_resp_arg *resp_arg = malloc(sizeof(struct async_resp_arg));
+    ESP_RETURN_ON_FALSE(resp_arg, ESP_ERR_NO_MEM, TAG, "Failed to allocate resp_arg");
     resp_arg->hd = req->handle;
     resp_arg->fd = httpd_req_to_sockfd(req);
     if (resp_arg->fd < 0) {
diff --git a/examples/protocols/http_server/persistent_sockets/main/main.c b/examples/protocols/http_server/persistent_sockets/main/main.c
index 92be4422a12..56eb0f749f8 100644
--- a/examples/protocols/http_server/persistent_sockets/main/main.c
+++ b/examples/protocols/http_server/persistent_sockets/main/main.c
@@ -15,6 +15,7 @@
 #include "esp_netif.h"
 #include "esp_eth.h"
 #include "protocol_examples_common.h"
+#include "esp_check.h"
 
 #include <esp_http_server.h>
 
@@ -61,6 +62,7 @@ static esp_err_t adder_post_handler(httpd_req_t *req)
     if (! req->sess_ctx) {
         ESP_LOGI(TAG, "/adder allocating new session");
         req->sess_ctx = malloc(sizeof(int));
+        ESP_RETURN_ON_FALSE(req->sess_ctx, ESP_ERR_NO_MEM, TAG, "Failed to allocate sess_ctx");
         req->free_ctx = adder_free_func;
         *(int *)req->sess_ctx = 0;
     }
@@ -88,6 +90,7 @@ static esp_err_t adder_get_handler(httpd_req_t *req)
     if (! req->sess_ctx) {
         ESP_LOGI(TAG, "/adder GET allocating new session");
         req->sess_ctx = malloc(sizeof(int));
+        ESP_RETURN_ON_FALSE(req->sess_ctx, ESP_ERR_NO_MEM, TAG, "Failed to allocate sess_ctx");
         req->free_ctx = adder_free_func;
         *(int *)req->sess_ctx = 0;
     }
@@ -168,6 +171,7 @@ static esp_err_t adder_put_handler(httpd_req_t *req)
     if (! req->sess_ctx) {
         ESP_LOGI(TAG, "/adder PUT allocating new session");
         req->sess_ctx = malloc(sizeof(int));
+        ESP_RETURN_ON_FALSE(req->sess_ctx, ESP_ERR_NO_MEM, TAG, "Failed to allocate sess_ctx");
         req->free_ctx = adder_free_func;
     }
     *(int *)req->sess_ctx = val;
diff --git a/examples/protocols/http_server/simple/main/main.c b/examples/protocols/http_server/simple/main/main.c
index 4a0678a39c3..d23969c591f 100644
--- a/examples/protocols/http_server/simple/main/main.c
+++ b/examples/protocols/http_server/simple/main/main.c
@@ -21,6 +21,7 @@
 #include "esp_event.h"
 #include "esp_netif.h"
 #include "esp_tls.h"
+#include "esp_check.h"
 
 #if !CONFIG_IDF_TARGET_LINUX
 #include <esp_wifi.h>
@@ -177,6 +178,7 @@ static esp_err_t hello_get_handler(httpd_req_t *req)
     buf_len = httpd_req_get_hdr_value_len(req, "Host") + 1;
     if (buf_len > 1) {
         buf = malloc(buf_len);
+        ESP_RETURN_ON_FALSE(buf, ESP_ERR_NO_MEM, TAG, "buffer alloc failed");
         /* Copy null terminated value string into buffer */
         if (httpd_req_get_hdr_value_str(req, "Host", buf, buf_len) == ESP_OK) {
             ESP_LOGI(TAG, "Found header => Host: %s", buf);
@@ -187,6 +189,7 @@ static esp_err_t hello_get_handler(httpd_req_t *req)
     buf_len = httpd_req_get_hdr_value_len(req, "Test-Header-2") + 1;
     if (buf_len > 1) {
         buf = malloc(buf_len);
+        ESP_RETURN_ON_FALSE(buf, ESP_ERR_NO_MEM, TAG, "buffer alloc failed");
         if (httpd_req_get_hdr_value_str(req, "Test-Header-2", buf, buf_len) == ESP_OK) {
             ESP_LOGI(TAG, "Found header => Test-Header-2: %s", buf);
         }
@@ -196,6 +199,7 @@ static esp_err_t hello_get_handler(httpd_req_t *req)
     buf_len = httpd_req_get_hdr_value_len(req, "Test-Header-1") + 1;
     if (buf_len > 1) {
         buf = malloc(buf_len);
+        ESP_RETURN_ON_FALSE(buf, ESP_ERR_NO_MEM, TAG, "buffer alloc failed");
         if (httpd_req_get_hdr_value_str(req, "Test-Header-1", buf, buf_len) == ESP_OK) {
             ESP_LOGI(TAG, "Found header => Test-Header-1: %s", buf);
         }
@@ -207,6 +211,7 @@ static esp_err_t hello_get_handler(httpd_req_t *req)
     buf_len = httpd_req_get_url_query_len(req) + 1;
     if (buf_len > 1) {
         buf = malloc(buf_len);
+        ESP_RETURN_ON_FALSE(buf, ESP_ERR_NO_MEM, TAG, "buffer alloc failed");
         if (httpd_req_get_url_query_str(req, buf, buf_len) == ESP_OK) {
             ESP_LOGI(TAG, "Found URL query => %s", buf);
             char param[EXAMPLE_HTTP_QUERY_KEY_MAX_LEN], dec_param[EXAMPLE_HTTP_QUERY_KEY_MAX_LEN] = {0};
diff --git a/examples/protocols/https_server/wss_server/main/wss_server_example.c b/examples/protocols/https_server/wss_server/main/wss_server_example.c
index 8b045d20d2f..cc27539f8a5 100644
--- a/examples/protocols/https_server/wss_server/main/wss_server_example.c
+++ b/examples/protocols/https_server/wss_server/main/wss_server_example.c
@@ -167,6 +167,7 @@ bool check_client_alive_cb(wss_keep_alive_t h, int fd)
 {
     ESP_LOGD(TAG, "Checking if client (fd=%d) is alive", fd);
     struct async_resp_arg *resp_arg = malloc(sizeof(struct async_resp_arg));
+    assert(resp_arg != NULL);
     resp_arg->hd = wss_keep_alive_get_user_ctx(h);
     resp_arg->fd = fd;
 
@@ -269,6 +270,7 @@ static void wss_server_send_messages(httpd_handle_t* server)
                 if (httpd_ws_get_fd_info(*server, sock) == HTTPD_WS_CLIENT_WEBSOCKET) {
                     ESP_LOGI(TAG, "Active client (fd=%d) -> sending async message", sock);
                     struct async_resp_arg *resp_arg = malloc(sizeof(struct async_resp_arg));
+                    assert(resp_arg != NULL);
                     resp_arg->hd = *server;
                     resp_arg->fd = sock;
                     if (httpd_queue_work(resp_arg->hd, send_hello, resp_arg) != ESP_OK) {
diff --git a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c
index d1731af3c07..ef891439630 100644
--- a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c
+++ b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c
@@ -45,7 +45,7 @@
 #include "esp_spiffs.h"
 #include "esp_vfs_eventfd.h"
 #include "esp_vfs_dev.h"
-#include "esp_vfs_usb_serial_jtag.h"
+#include "driver/usb_serial_jtag_vfs.h"
 #include "driver/uart_vfs.h"
 #include "esp_wifi.h"
 #include "nvs_flash.h"
@@ -67,9 +67,9 @@ esp_err_t esp_zb_gateway_console_init(void)
     setvbuf(stdin, NULL, _IONBF, 0);
 
     /* Minicom, screen, idf_monitor send CR when ENTER key is pressed */
-    esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
+    usb_serial_jtag_vfs_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
     /* Move the caret to the beginning of the next line on '\n' */
-    esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
+    usb_serial_jtag_vfs_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
 
     /* Enable non-blocking mode on stdin and stdout */
     fcntl(fileno(stdout), F_SETFL, O_NONBLOCK);
@@ -77,7 +77,7 @@ esp_err_t esp_zb_gateway_console_init(void)
 
     usb_serial_jtag_driver_config_t usb_serial_jtag_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT();
     ret = usb_serial_jtag_driver_install(&usb_serial_jtag_config);
-    esp_vfs_usb_serial_jtag_use_driver();
+    usb_serial_jtag_vfs_use_driver();
     uart_vfs_dev_register();
     return ret;
 }
diff --git a/tools/ci/check_kconfigs.py b/tools/ci/check_kconfigs.py
index ac3adf2cded..08b086ebfb1 100755
--- a/tools/ci/check_kconfigs.py
+++ b/tools/ci/check_kconfigs.py
@@ -61,7 +61,7 @@ def valid_directory(path:str) -> str:
 if args.exclude_submodules:
     ignore_dirs = ignore_dirs + tuple(get_submodule_dirs(full_path=True))
 
-files_to_check: list = []
+files_to_check: list = args.files
 
 # if the deprecated argument '--includes' is used all valid paths are checked for KConfigs
 # except IGNORE_DIRS and submodules (if exclude is given)
diff --git a/tools/ci/idf_pytest/constants.py b/tools/ci/idf_pytest/constants.py
index a56cedc2dd7..f5bb8743aec 100644
--- a/tools/ci/idf_pytest/constants.py
+++ b/tools/ci/idf_pytest/constants.py
@@ -108,7 +108,8 @@
     'twai_network': 'multiple runners form a TWAI network.',
     'sdio_master_slave': 'Test sdio multi board, esp32+esp32',
     'sdio_multidev_32_c6': 'Test sdio multi board, esp32+esp32c6',
-    'usj_device': 'Test usb_serial_jtag and usb_serial_jtag is used as serial only (not console)'
+    'usj_device': 'Test usb_serial_jtag and usb_serial_jtag is used as serial only (not console)',
+    'twai_std': 'twai runner with all twai supported targets connect to usb-can adapter'
 }
 
 
diff --git a/tools/idf_py_actions/debug_ext.py b/tools/idf_py_actions/debug_ext.py
index 5e4974beb70..dd4cacc1b41 100644
--- a/tools/idf_py_actions/debug_ext.py
+++ b/tools/idf_py_actions/debug_ext.py
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 import json
 import os
@@ -405,15 +405,21 @@ def gdbui(action: str, ctx: Context, args: PropertyDict, gdbgui_port: Optional[s
         gdb = project_desc['monitor_toolprefix'] + 'gdb'
         generate_gdbinit_files(gdb, gdbinit, project_desc)
 
-        # this is a workaround for gdbgui
-        # gdbgui is using shlex.split for the --gdb-args option. When the input is:
-        # - '"-x=foo -x=bar"', would return ['foo bar']
-        # - '-x=foo', would return ['-x', 'foo'] and mess up the former option '--gdb-args'
-        # so for one item, use extra double quotes. for more items, use no extra double quotes.
         gdb_args_list = get_gdb_args(project_desc)
-        gdb_args = '"{}"'.format(' '.join(gdb_args_list)) if len(gdb_args_list) == 1 else ' '.join(gdb_args_list)
-        args = ['gdbgui', '-g', gdb, '--gdb-args', gdb_args]
-        print(args)
+        if sys.version_info[:2] >= (3, 11):
+            # If we use Python 3.11+ then the only compatible gdbgui doesn't support the --gdb-args argument. This
+            # check is easier than checking gdbgui version or re-running the process in case of gdb-args-related
+            # failure.
+            gdb_args = ' '.join(gdb_args_list)
+            args = ['gdbgui', '-g', ' '.join((gdb, gdb_args))]
+        else:
+            # this is a workaround for gdbgui
+            # gdbgui is using shlex.split for the --gdb-args option. When the input is:
+            # - '"-x=foo -x=bar"', would return ['foo bar']
+            # - '-x=foo', would return ['-x', 'foo'] and mess up the former option '--gdb-args'
+            # so for one item, use extra double quotes. for more items, use no extra double quotes.
+            gdb_args = '"{}"'.format(' '.join(gdb_args_list)) if len(gdb_args_list) == 1 else ' '.join(gdb_args_list)
+            args = ['gdbgui', '-g', gdb, '--gdb-args', gdb_args]
 
         if gdbgui_port is not None:
             args += ['--port', gdbgui_port]
@@ -425,10 +431,11 @@ def gdbui(action: str, ctx: Context, args: PropertyDict, gdbgui_port: Optional[s
         # pygdbmi).
         env['PURE_PYTHON'] = '1'
         try:
+            print('Running: ', args)
             process = subprocess.Popen(args, stdout=gdbgui_out, stderr=subprocess.STDOUT, bufsize=1, env=env)
         except (OSError, subprocess.CalledProcessError) as e:
             print(e)
-            if sys.version_info[:2] >= (3, 11):
+            if sys.version_info[:2] >= (3, 11) and sys.platform == 'win32':
                 raise SystemExit('Unfortunately, gdbgui is supported only with Python 3.10 or older. '
                                  'See: https://github.com/espressif/esp-idf/issues/10116. '
                                  'Please use "idf.py gdb" or debug in Eclipse/Vscode instead.')
diff --git a/tools/mocks/driver/CMakeLists.txt b/tools/mocks/driver/CMakeLists.txt
index 0a5490f7436..f8647eda7c9 100644
--- a/tools/mocks/driver/CMakeLists.txt
+++ b/tools/mocks/driver/CMakeLists.txt
@@ -12,9 +12,9 @@ set(include_dirs
     "${IDF_PATH}/components/esp_driver_rmt/include/driver"
     "${IDF_PATH}/components/esp_driver_rmt/include"
     "${original_driver_dir}/i2c/include/driver"
-    "${original_driver_dir}/usb_serial_jtag/include/driver"
+    "${IDF_PATH}/components/esp_driver_usb_serial_jtag/include/driver"
     "${original_driver_dir}/i2c/include"
-    "${original_driver_dir}/usb_serial_jtag/include")
+    "${IDF_PATH}/components/esp_driver_usb_serial_jtag/include")
 
 # Note: "hal" and "soc" are only required for corresponding header files and their definitions
 # here, they don't provide functionality when built for running on the host.
@@ -29,4 +29,4 @@ idf_component_mock(INCLUDE_DIRS ${include_dirs}
     ${IDF_PATH}/components/esp_driver_rmt/include/driver/rmt_common.h
     ${IDF_PATH}/components/esp_driver_rmt/include/driver/rmt_encoder.h
     ${original_driver_dir}/i2c/include/driver/i2c.h
-    ${original_driver_dir}/usb_serial_jtag/include/driver/usb_serial_jtag.h)
+    ${IDF_PATH}/components/esp_driver_usb_serial_jtag/include/driver/usb_serial_jtag.h)
diff --git a/tools/requirements/requirements.gdbgui.txt b/tools/requirements/requirements.gdbgui.txt
index 0e78495afbb..a00523d1e4d 100644
--- a/tools/requirements/requirements.gdbgui.txt
+++ b/tools/requirements/requirements.gdbgui.txt
@@ -1,5 +1,7 @@
 # Python package requirements for gdbgui support ESP-IDF.
 # This feature can be enabled by running "install.{sh,bat,ps1,fish} --enable-gdbgui"
 
-# gdbgui is not supported on Python 3.11. See https://github.com/cs01/gdbgui/issues/447
-gdbgui; python_version < "3.11"
+# gdbgui Python 3.11 issue https://github.com/cs01/gdbgui/issues/447 was fixed in 0.15.2.0. Windows users need an
+# older Python to use since new gdbgui versions don't support Windows anymore.
+gdbgui; sys_platform != 'win32'
+gdbgui; sys_platform == 'win32' and python_version < "3.11"