From 69d4893e8519cdf27197e5c639014a05bc47f2c4 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Thu, 29 Feb 2024 16:51:31 +0800 Subject: [PATCH 01/15] docs(spi_master): fixed timing comments that only apply for ESP32 --- components/esp_driver_spi/include/driver/spi_common.h | 3 ++- components/esp_driver_spi/include/driver/spi_master.h | 9 +++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/components/esp_driver_spi/include/driver/spi_common.h b/components/esp_driver_spi/include/driver/spi_common.h index 23f5299ea09..15672131eec 100644 --- a/components/esp_driver_spi/include/driver/spi_common.h +++ b/components/esp_driver_spi/include/driver/spi_common.h @@ -89,7 +89,8 @@ typedef spi_common_dma_t spi_dma_chan_t; * * You can use this structure to specify the GPIO pins of the bus. Normally, the driver will use the * GPIO matrix to route the signals. An exception is made when all signals either can be routed through - * the IO_MUX or are -1. In that case, the IO_MUX is used, allowing for >40MHz speeds. + * the IO_MUX or are -1. In that case, the IO_MUX is used. On ESP32, using GPIO matrix will bring about 25ns of input + * delay, which may cause incorrect read for >40MHz speeds. * * @note Be advised that the slave driver does not use the quadwp/quadhd lines and fields in spi_bus_config_t refering to these lines will be ignored and can thus safely be left uninitialized. */ diff --git a/components/esp_driver_spi/include/driver/spi_master.h b/components/esp_driver_spi/include/driver/spi_master.h index 0fb098954ce..660f46283fb 100644 --- a/components/esp_driver_spi/include/driver/spi_master.h +++ b/components/esp_driver_spi/include/driver/spi_master.h @@ -165,8 +165,13 @@ typedef struct spi_device_t *spi_device_handle_t; ///< Handle for a device on a * peripheral and routes it to the indicated GPIO. All SPI master devices have three CS pins and can thus control * up to three devices. * - * @note While in general, speeds up to 80MHz on the dedicated SPI pins and 40MHz on GPIO-matrix-routed pins are - * supported, full-duplex transfers routed over the GPIO matrix only support speeds up to 26MHz. + * @note On ESP32, due to the delay of GPIO matrix, the maximum frequency SPI Master can correctly samples the slave's + * output is lower than the case using IOMUX. Typical maximum frequency communicating with an ideal slave + * without data output delay: 80MHz (IOMUX pins) and 26MHz (GPIO matrix pins). With the help of extra dummy + * cycles in half-duplex mode, the delay can be compensated by setting `input_delay_ns` in `dev_config` structure + * correctly. + * + * There's no notable delay on chips other than ESP32. * * @param host_id SPI peripheral to allocate device on * @param dev_config SPI interface protocol config for the device From 87b47b461dc38b32cea6af4f2673323e5d327510 Mon Sep 17 00:00:00 2001 From: Roshan Bangar Date: Mon, 4 Mar 2024 14:53:20 +0530 Subject: [PATCH 02/15] docs(nimble): Improved documentation for uart host only example --- .../tutorial/bleprph_host_only_walkthrough.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/examples/bluetooth/nimble/bleprph_host_only/tutorial/bleprph_host_only_walkthrough.md b/examples/bluetooth/nimble/bleprph_host_only/tutorial/bleprph_host_only_walkthrough.md index 4bfba23bc44..89bcc3e0da3 100644 --- a/examples/bluetooth/nimble/bleprph_host_only/tutorial/bleprph_host_only_walkthrough.md +++ b/examples/bluetooth/nimble/bleprph_host_only/tutorial/bleprph_host_only_walkthrough.md @@ -7,11 +7,18 @@ The tutorial is focused on how to implement the custom transport in the applicat Note: This walkthrough only covers the transport used by the application, for detailed explanation see the [bleprph_walkthrough](../../bleprph/tutorial/bleprph_walkthrough.md) ## Hardware Setup -This example uses esp32 chip to run the example `bleprph_host_only` that runs the nimble-host and sends and receives the commands and events using uart. The another chip used is esp32c6 that runs the esp-hosted `esp-hosted/esp_hosted_fg/esp/esp_driver/network_adapter` example that runs the controller and receives commands and sends events using UART. Below is the setup of esp32 and esp32c6. +This example uses esp32 chip to run the example `bleprph_host_only` that runs the nimble-host and sends and receives the commands and events using uart. The another chip used is esp32c6 that runs the controller `esp-idf/examples/bluetooth/nimble/hci` example that runs the controller and receives commands and sends events using UART. Below is the setup of esp32 and esp32c6. ![Hardware Setup](hardware_setup.png) -Note that the esp32s gpio pins tx=4 and rx=5 are defined in [uart_driver.c](../main/uart_driver.c) file. The tx pin of one chip connectes to the rx pin of the other and vice versa. +Note that the esp32 gpio pins tx=4 and rx=5 are configurable using idf.py menuconfig -> example config -> Uart Configuration. The tx pin of one chip connectes to the rx pin of the other and vice versa. + +Below is the pin connection chart for Esp32 and esp32c6. + +| Esp32 (Signal) | Esp32 (GPIO Pin) | C6 (Signal) | C6 (GPIO Pin) | +|----------------|-------------------|-------------|---------------| +| Rx | 5 | Tx | 5 | +| Tx | 4 | Rx | 12 | ```c #define UART_TX_PIN (4) From 2b6f12ba51d14337ac9f85825755e92adb26d8ea Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Tue, 5 Mar 2024 15:06:39 +0530 Subject: [PATCH 03/15] fix(hal/crypto): Do not reset parent crypto clk when resetting a crypto peripheral --- components/hal/esp32p4/include/hal/clk_gate_ll.h | 16 ++++++++-------- components/hal/esp32p4/include/hal/ds_ll.h | 2 -- components/hal/esp32p4/include/hal/ecc_ll.h | 2 -- components/hal/esp32p4/include/hal/ecdsa_ll.h | 2 -- components/hal/esp32p4/include/hal/hmac_ll.h | 2 -- components/hal/esp32p4/include/hal/key_mgr_ll.h | 2 -- components/hal/esp32p4/include/hal/mpi_ll.h | 2 -- 7 files changed, 8 insertions(+), 20 deletions(-) diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index 012b45cd0c8..caf46ad96e0 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -67,40 +67,40 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en case PERIPH_SARADC_MODULE: return HP_SYS_CLKRST_REG_RST_EN_ADC; case PERIPH_AES_MODULE: - ret = HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_AES; + ret = HP_SYS_CLKRST_REG_RST_EN_AES; if (enable == true) { // Clear reset on digital signature, otherwise AES unit is held in reset ret |= HP_SYS_CLKRST_REG_RST_EN_DS; } return ret; case PERIPH_DS_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_DS; + return HP_SYS_CLKRST_REG_RST_EN_DS; case PERIPH_ECC_MODULE: - ret = HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_ECC; + ret = HP_SYS_CLKRST_REG_RST_EN_ECC; if (enable == true) { ret |= HP_SYS_CLKRST_REG_RST_EN_ECDSA; } return ret; case PERIPH_HMAC_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_HMAC; + return HP_SYS_CLKRST_REG_RST_EN_HMAC; case PERIPH_RSA_MODULE: - ret = HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_RSA; + ret = HP_SYS_CLKRST_REG_RST_EN_RSA; if (enable == true) { // Clear reset on digital signature, and ECDSA, otherwise RSA is held in reset ret |= HP_SYS_CLKRST_REG_RST_EN_DS | HP_SYS_CLKRST_REG_RST_EN_ECDSA; } return ret; case PERIPH_SEC_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_SEC; + return HP_SYS_CLKRST_REG_RST_EN_SEC; case PERIPH_SHA_MODULE: - ret = HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_SHA; + ret = HP_SYS_CLKRST_REG_RST_EN_SHA; if (enable == true) { // Clear reset on digital signature, HMAC and ECDSA, otherwise SHA is held in reset ret |= (HP_SYS_CLKRST_REG_RST_EN_HMAC | HP_SYS_CLKRST_REG_RST_EN_DS | HP_SYS_CLKRST_REG_RST_EN_ECDSA); } return ret; case PERIPH_ECDSA_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_CRYPTO | HP_SYS_CLKRST_REG_RST_EN_ECDSA; + return HP_SYS_CLKRST_REG_RST_EN_ECDSA; case PERIPH_EMAC_MODULE: return LP_CLKRST_RST_EN_EMAC; default: diff --git a/components/hal/esp32p4/include/hal/ds_ll.h b/components/hal/esp32p4/include/hal/ds_ll.h index 64d556e0409..3873a9311e4 100644 --- a/components/hal/esp32p4/include/hal/ds_ll.h +++ b/components/hal/esp32p4/include/hal/ds_ll.h @@ -46,8 +46,6 @@ static inline void ds_ll_reset_register(void) { HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ds = 1; HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ds = 0; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 1; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 0; } /// use a macro to wrap the function, force the caller to use it in a critical section diff --git a/components/hal/esp32p4/include/hal/ecc_ll.h b/components/hal/esp32p4/include/hal/ecc_ll.h index be25321fe45..7320b4123cd 100644 --- a/components/hal/esp32p4/include/hal/ecc_ll.h +++ b/components/hal/esp32p4/include/hal/ecc_ll.h @@ -46,8 +46,6 @@ static inline void ecc_ll_reset_register(void) { HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecc = 1; HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecc = 0; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 1; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 0; // Clear reset on ECDSA, otherwise ECC is held in reset HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecdsa = 0; diff --git a/components/hal/esp32p4/include/hal/ecdsa_ll.h b/components/hal/esp32p4/include/hal/ecdsa_ll.h index b30b078b410..fe4123b9fce 100644 --- a/components/hal/esp32p4/include/hal/ecdsa_ll.h +++ b/components/hal/esp32p4/include/hal/ecdsa_ll.h @@ -91,8 +91,6 @@ static inline void ecdsa_ll_reset_register(void) { HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecdsa = 1; HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecdsa = 0; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 1; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 0; } /** diff --git a/components/hal/esp32p4/include/hal/hmac_ll.h b/components/hal/esp32p4/include/hal/hmac_ll.h index 8772385259d..b2bc080045a 100644 --- a/components/hal/esp32p4/include/hal/hmac_ll.h +++ b/components/hal/esp32p4/include/hal/hmac_ll.h @@ -53,8 +53,6 @@ static inline void hmac_ll_reset_register(void) { HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_hmac = 1; HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_hmac = 0; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 1; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 0; } /// use a macro to wrap the function, force the caller to use it in a critical section diff --git a/components/hal/esp32p4/include/hal/key_mgr_ll.h b/components/hal/esp32p4/include/hal/key_mgr_ll.h index bcf68a199f7..04acb90c1e0 100644 --- a/components/hal/esp32p4/include/hal/key_mgr_ll.h +++ b/components/hal/esp32p4/include/hal/key_mgr_ll.h @@ -59,8 +59,6 @@ static inline void key_mgr_ll_reset_register(void) { HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_km = 1; HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_km = 0; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 1; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 0; } /// use a macro to wrap the function, force the caller to use it in a critical section diff --git a/components/hal/esp32p4/include/hal/mpi_ll.h b/components/hal/esp32p4/include/hal/mpi_ll.h index 00360a8ddcd..ebe4b558589 100644 --- a/components/hal/esp32p4/include/hal/mpi_ll.h +++ b/components/hal/esp32p4/include/hal/mpi_ll.h @@ -39,8 +39,6 @@ static inline void mpi_ll_reset_register(void) { HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_rsa = 1; HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_rsa = 0; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 1; - HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 0; // Clear reset on digital signature and ECDSA, otherwise RSA is held in reset HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ds = 0; From 82c2602afacb902832e0ffa52d98883023f2726b Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Wed, 28 Feb 2024 19:13:55 +0800 Subject: [PATCH 04/15] fix(ble/bluedroid): Fixed BLE crash when repeatedly initialize and deinitialize host --- components/bt/host/bluedroid/bta/dm/bta_dm_act.c | 5 +++++ components/bt/host/bluedroid/bta/dm/bta_dm_api.c | 1 - components/bt/host/bluedroid/stack/btm/btm_ble_multi_adv.c | 7 +++++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c index a4e580728bb..2e8a3563d72 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c @@ -615,6 +615,11 @@ void bta_dm_disable (tBTA_DM_MSG *p_data) btm_ble_resolving_list_cleanup (); //by TH, because cmn_ble_vsc_cb.max_filter has something mistake as btm_ble_adv_filter_cleanup #endif +#if BLE_INCLUDED == TRUE + // btm_ble_multi_adv_init is called when the host is enabled, so btm_ble_multi_adv_cleanup is called when the host is disabled. + btm_ble_multi_adv_cleanup(); +#endif + } /******************************************************************************* diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c index ed8b7d1e3fa..06d748937dd 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c @@ -2921,7 +2921,6 @@ void BTA_VendorCleanup (void) } #endif - btm_ble_multi_adv_cleanup(); } #if (BLE_50_FEATURE_SUPPORT == TRUE) void BTA_DmBleGapReadPHY(BD_ADDR addr) diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_multi_adv.c b/components/bt/host/bluedroid/stack/btm/btm_ble_multi_adv.c index 443dd64edfa..bc300b02358 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_multi_adv.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_multi_adv.c @@ -824,6 +824,13 @@ void btm_ble_multi_adv_init(void) *******************************************************************************/ void btm_ble_multi_adv_cleanup(void) { +#if BTM_DYNAMIC_MEMORY == TRUE + if (btm_multi_adv_cb_ptr == NULL) + { + BTM_TRACE_WARNING("%s memory has been freed", __func__); + return; + } +#endif if (btm_multi_adv_cb.p_adv_inst) { osi_free(btm_multi_adv_cb.p_adv_inst); btm_multi_adv_cb.p_adv_inst = NULL; From 2c3d9ae5dedae13add8ad539e13681220a81e782 Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Wed, 6 Mar 2024 18:08:51 +0800 Subject: [PATCH 05/15] fix(ble/bluedroid): Fixed BLE BLE periodic advertising parameter check --- components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c index 1b474ae2705..78711b589c1 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c @@ -798,8 +798,13 @@ tBTM_STATUS BTM_BlePeriodicAdvCreateSync(tBTM_BLE_Periodic_Sync_Params *params) || (params->reports_disabled > 0x01) || (params->filter_duplicates > 0x01) #endif - || (params->addr_type > 0x01) || - (params->sid > 0xf) || (params->skip > 0x01F3)) { + /*If the Periodic Advertiser List is not used, + the Advertising_SID, Advertiser Address_Type, and Advertiser Address + parameters specify the periodic advertising device to listen to; otherwise they + shall be ignored.*/ + || (params->filter_policy == 0 && params->addr_type > 0x01) + || (params->filter_policy == 0 && params->sid > 0xf) + || (params->skip > 0x01F3)) { status = BTM_ILLEGAL_VALUE; BTM_TRACE_ERROR("%s, The sync parameters is invalid.", __func__); goto end; From 5136081cf3e942ba10d0f5de8d2cc6699b5f84a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adam=20M=C3=BAdry?= Date: Thu, 7 Mar 2024 01:25:52 +0100 Subject: [PATCH 06/15] feat: LittleFS bump version to 1.14.2 --- examples/storage/littlefs/main/idf_component.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/storage/littlefs/main/idf_component.yml b/examples/storage/littlefs/main/idf_component.yml index 68f4b1b88b1..427e1c36bde 100644 --- a/examples/storage/littlefs/main/idf_component.yml +++ b/examples/storage/littlefs/main/idf_component.yml @@ -1,3 +1,3 @@ ## IDF Component Manager Manifest File dependencies: - joltwallet/littlefs: "~=1.13.0" + joltwallet/littlefs: "~=1.14.2" From 20ba589f1c7b5f569fc6821754ea766c810b5ade Mon Sep 17 00:00:00 2001 From: Abhinav Kudnar Date: Thu, 7 Mar 2024 14:35:43 +0530 Subject: [PATCH 07/15] fix(nimble): Revise the help section for the Kconfig macro BLE_RPA_TIMEOUT. --- components/bt/host/nimble/Kconfig.in | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index 1163d4d7974..a89888400d3 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -388,8 +388,7 @@ config BT_NIMBLE_RPA_TIMEOUT depends on BT_NIMBLE_ENABLED default 900 help - Time interval between RPA address change. This is applicable in case of - Host based RPA + Time interval between RPA address change. menuconfig BT_NIMBLE_MESH bool "Enable BLE mesh functionality" From 0cf11e5b873b9ff797a185a328d43181946fea2b Mon Sep 17 00:00:00 2001 From: wanlei Date: Tue, 20 Feb 2024 20:40:19 +0800 Subject: [PATCH 08/15] feat(spi): add esp32c5 spi support --- .../esp_driver_spi/src/gpspi/spi_common.c | 21 +- components/hal/esp32c5/include/hal/spi_ll.h | 1044 ++++++++--------- components/hal/esp32c6/include/hal/spi_ll.h | 10 +- components/idf_test/include/esp32c5/.gitkeep | 0 .../include/esp32c5/idf_performance_target.h | 6 + components/soc/esp32c2/spi_periph.c | 2 +- components/soc/esp32c3/spi_periph.c | 2 +- .../beta3/include/soc/Kconfig.soc_caps.in | 40 + .../esp32c5/beta3/include/soc/clk_tree_defs.h | 8 +- .../soc/esp32c5/beta3/include/soc/soc_caps.h | 22 +- .../soc/esp32c5/beta3/include/soc/spi_pins.h | 15 +- .../esp32c5/beta3/include/soc/spi_struct.h | 199 +--- components/soc/esp32c5/beta3/spi_periph.c | 64 + components/soc/esp32c6/spi_periph.c | 2 +- components/soc/esp32h2/spi_periph.c | 2 +- components/soc/esp32p4/spi_periph.c | 2 +- components/soc/esp32s2/spi_periph.c | 2 +- components/soc/esp32s3/spi_periph.c | 2 +- .../api-reference/peripherals/spi_master.rst | 20 +- .../api-reference/peripherals/spi_master.rst | 20 +- 20 files changed, 634 insertions(+), 849 deletions(-) delete mode 100644 components/idf_test/include/esp32c5/.gitkeep create mode 100644 components/soc/esp32c5/beta3/spi_periph.c diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index b10c9a9b8e8..f78559f925e 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,8 +15,9 @@ #include "esp_heap_caps.h" #include "soc/spi_periph.h" #include "soc/ext_mem_defs.h" -#include "driver/gpio.h" #include "driver/spi_master.h" +#include "driver/gpio.h" +#include "esp_private/gpio.h" #include "esp_private/periph_ctrl.h" #include "esp_private/spi_common_internal.h" #include "esp_private/spi_share_hw_ctrl.h" @@ -645,7 +646,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->mosi_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->mosi_io_num, FUNC_GPIO); } if (bus_config->miso_io_num >= 0) { if (miso_need_output || (temp_flag & SPICOMMON_BUSFLAG_DUAL)) { @@ -658,7 +659,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->miso_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->miso_io_num, FUNC_GPIO); } if (bus_config->quadwp_io_num >= 0) { gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT); @@ -667,7 +668,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->quadwp_io_num, FUNC_GPIO); } if (bus_config->quadhd_io_num >= 0) { gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT); @@ -676,7 +677,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->quadhd_io_num, FUNC_GPIO); } if (bus_config->sclk_io_num >= 0) { if (sclk_need_output) { @@ -689,7 +690,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->sclk_io_num]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO); + gpio_func_sel(bus_config->sclk_io_num, FUNC_GPIO); } #if SOC_SPI_SUPPORT_OCT if ((flags & SPICOMMON_BUSFLAG_OCTAL) == SPICOMMON_BUSFLAG_OCTAL) { @@ -707,7 +708,7 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf #if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_nums[i]]); #endif - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_nums[i]], FUNC_GPIO); + gpio_func_sel(io_nums[i], FUNC_GPIO); } } } @@ -755,8 +756,10 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, if (cs_num == 0) { esp_rom_gpio_connect_in_signal(cs_io_num, spi_periph_signal[host].spics_in, false); } +#if CONFIG_IDF_TARGET_ESP32S2 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[cs_io_num]); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO); +#endif + gpio_func_sel(cs_io_num, FUNC_GPIO); } } diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h index bb045677056..3187bc1144d 100644 --- a/components/hal/esp32c5/include/hal/spi_ll.h +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,11 +16,11 @@ #include //for abs() #include -#include "esp_attr.h" #include "esp_types.h" #include "soc/spi_periph.h" #include "soc/spi_struct.h" #include "soc/lldesc.h" +#include "soc/clk_tree_defs.h" #include "hal/assert.h" #include "hal/misc.h" #include "hal/spi_types.h" @@ -42,6 +42,8 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized +#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral +#define SPI_LL_CLK_SRC_PRE_DIV_MAX 256//div1(8bit) /** * The data structure holding calculated clock configuration. Since the @@ -97,20 +99,15 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) -{ - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // switch (host_id) - // { - // case SPI1_HOST: - // PCR.mspi_conf.mspi_clk_en = enable; - // break; - // case SPI2_HOST: - // PCR.spi2_conf.spi2_clk_en = enable; - // break; - // default: HAL_ASSERT(false); - // } - abort(); +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { + switch (host_id) + { + case SPI2_HOST: + PCR.spi2_conf.spi2_clk_en = enable; + break; + default: + HAL_ASSERT(false); + } } /** @@ -118,22 +115,16 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) -{ - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // switch (host_id) - // { - // case SPI1_HOST: - // PCR.mspi_conf.mspi_rst_en = 1; - // PCR.mspi_conf.mspi_rst_en = 0; - // break; - // case SPI2_HOST: - // PCR.spi2_conf.spi2_rst_en = 1; - // PCR.spi2_conf.spi2_rst_en = 0; - // break; - // default: HAL_ASSERT(false); - // } - abort(); +static inline void spi_ll_reset_register(spi_host_device_t host_id) { + switch (host_id) + { + case SPI2_HOST: + PCR.spi2_conf.spi2_rst_en = 1; + PCR.spi2_conf.spi2_rst_en = 0; + break; + default: + HAL_ASSERT(false); + } } /** @@ -144,10 +135,7 @@ static inline void spi_ll_reset_register(spi_host_device_t host_id) */ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // (void) host_id; - // PCR.spi2_clkm_conf.spi2_clkm_en = enable; - abort(); + PCR.spi2_clkm_conf.spi2_clkm_en = enable; } /** @@ -159,20 +147,40 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) __attribute__((always_inline)) static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // switch (clk_source) - // { - // case SPI_CLK_SRC_RC_FAST: - // PCR.spi2_clkm_conf.spi2_clkm_sel = 2; - // break; - // case SPI_CLK_SRC_XTAL: - // PCR.spi2_clkm_conf.spi2_clkm_sel = 0; - // break; - // default: - // PCR.spi2_clkm_conf.spi2_clkm_sel = 1; - // break; - // } - abort(); + uint32_t clk_id = 0; + switch (clk_source) { + case SOC_MOD_CLK_PLL_F160M: + clk_id = 1; + break; + case SOC_MOD_CLK_RC_FAST: + clk_id = 2; + break; + case SOC_MOD_CLK_XTAL: + clk_id = 0; + break; + default: + HAL_ASSERT(false); + } + + PCR.spi2_clkm_conf.spi2_clkm_sel = clk_id; +} + +/** + * Config clock source integrate pre_div before it enter GPSPI peripheral + * + * @note 1. For timing turning(e.g. input_delay) feature available, should be (mst_div >= 2) + * 2. From peripheral limitation: (sour_freq/hs_div <= 160M) and (sour_freq/hs_div/mst_div <= 80M) + * + * @param hw Beginning address of the peripheral registers. + * @param hs_div Timing turning clock divider: (hs_clk_o = sour_freq/hs_div) + * @param mst_div Functional output clock divider: (mst_clk_o = sour_freq/hs_div/mst_div) + */ +__attribute__((always_inline)) +static inline void spi_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div) +{ + // In IDF master driver 'mst_div' will be const 2 and 'hs_div' is actually pre_div temporally + (void) hs_div; + PCR.spi2_clkm_conf.spi2_clkm_div_num = mst_div - 1; } /** @@ -182,22 +190,22 @@ static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_s */ static inline void spi_ll_master_init(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //Reset timing - // hw->user1.cs_setup_time = 0; - // hw->user1.cs_hold_time = 0; - // // //use all 64 bytes of the buffer - // hw->user.usr_miso_highpart = 0; - // hw->user.usr_mosi_highpart = 0; - // // //Disable unneeded ints - // hw->slave.val = 0; - // hw->user.val = 0; - // // PCR.spi2_clkm_conf.spi2_clkm_sel = 1; - // // hw->dma_conf.val = 0; - // hw->dma_conf.slv_tx_seg_trans_clr_en = 1; - // hw->dma_conf.slv_rx_seg_trans_clr_en = 1; - // hw->dma_conf.dma_slv_seg_trans_en = 0; - abort(); + //Reset timing + hw->user1.cs_setup_time = 0; + hw->user1.cs_hold_time = 0; + + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + //Disable unneeded ints + hw->slave.val = 0; + hw->user.val = 0; + + hw->dma_conf.val = 0; + hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -207,25 +215,25 @@ static inline void spi_ll_master_init(spi_dev_t *hw) */ static inline void spi_ll_slave_init(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //Configure slave - // hw->clock.val = 0; - // hw->user.val = 0; - // hw->ctrl.val = 0; - // hw->user.doutdin = 1; //we only support full duplex - // hw->user.sio = 0; - // hw->slave.slave_mode = 1; - // hw->slave.soft_reset = 1; - // hw->slave.soft_reset = 0; - // //use all 64 bytes of the buffer - // hw->user.usr_miso_highpart = 0; - // hw->user.usr_mosi_highpart = 0; - // // // Configure DMA In-Link to not be terminated when transaction bit counter exceeds - // hw->dma_conf.rx_eof_en = 0; - // hw->dma_conf.dma_slv_seg_trans_en = 0; - // // //Disable unneeded ints - // hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; - abort(); + //Configure slave + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 1; //we only support full duplex + hw->user.sio = 0; + hw->slave.slave_mode = 1; + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + // Configure DMA In-Link to not be terminated when transaction bit counter exceeds + hw->dma_conf.rx_eof_en = 0; + hw->dma_conf.dma_slv_seg_trans_en = 0; + + //Disable unneeded ints + hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; } /** @@ -235,28 +243,27 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) */ static inline void spi_ll_slave_hd_init(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->clock.val = 0; - // hw->user.val = 0; - // hw->ctrl.val = 0; - // hw->user.doutdin = 0; - // hw->user.sio = 0; - // // hw->slave.soft_reset = 1; - // hw->slave.soft_reset = 0; - // hw->slave.slave_mode = 1; - abort(); + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 0; + hw->user.sio = 0; + + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + hw->slave.slave_mode = 1; } /** - * Determine and unify the default level of mosi line when bus free + * Check whether user-defined transaction is done. * * @param hw Beginning address of the peripheral registers. + * + * @return True if transaction is done, otherwise false. */ -static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level) +static inline bool spi_ll_usr_is_done(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state - abort(); + return hw->dma_int_raw.trans_done_int_raw; } /** @@ -266,25 +273,8 @@ static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level) */ static inline void spi_ll_apply_config(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->cmd.update = 1; - // while (hw->cmd.update); //waiting config applied - abort(); -} - -/** - * Check whether user-defined transaction is done. - * - * @param hw Beginning address of the peripheral registers. - * - * @return True if transaction is done, otherwise false. - */ -static inline bool spi_ll_usr_is_done(spi_dev_t *hw) -{ - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->dma_int_raw.trans_done; - abort(); - return (bool)0; + hw->cmd.update = 1; + while (hw->cmd.update); //waiting config applied } /** @@ -294,9 +284,7 @@ static inline bool spi_ll_usr_is_done(spi_dev_t *hw) */ static inline void spi_ll_user_start(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->cmd.usr = 1; - abort(); + hw->cmd.usr = 1; } /** @@ -308,10 +296,7 @@ static inline void spi_ll_user_start(spi_dev_t *hw) */ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->cmd.val; - abort(); - return (uint32_t)0; + return hw->cmd.usr; } /** @@ -321,40 +306,34 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) */ static inline void spi_ll_slave_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->slave.soft_reset = 1; - // hw->slave.soft_reset = 0; - abort(); + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; } /** * Reset SPI CPU TX FIFO * - * On ESP32C3, this function is not seperated + * On esp32c5, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.buf_afifo_rst = 1; - // hw->dma_conf.buf_afifo_rst = 0; - abort(); + hw->dma_conf.buf_afifo_rst = 1; + hw->dma_conf.buf_afifo_rst = 0; } /** * Reset SPI CPU RX FIFO * - * On ESP32C3, this function is not seperated + * On esp32c5, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.rx_afifo_rst = 1; - // hw->dma_conf.rx_afifo_rst = 0; - abort(); + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; } /** @@ -364,10 +343,8 @@ static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_afifo_rst = 1; - // hw->dma_conf.dma_afifo_rst = 0; - abort(); + hw->dma_conf.dma_afifo_rst = 1; + hw->dma_conf.dma_afifo_rst = 0; } /** @@ -377,10 +354,8 @@ static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.rx_afifo_rst = 1; - // hw->dma_conf.rx_afifo_rst = 0; - abort(); + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; } /** @@ -390,9 +365,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_clr.dma_infifo_full_err = 1; - abort(); + hw->dma_int_clr.dma_infifo_full_err_int_clr = 1; } /** @@ -402,9 +375,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) */ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_clr.dma_outfifo_empty_err = 1; - abort(); + hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1; } /*------------------------------------------------------------------------------ @@ -418,9 +389,7 @@ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) */ static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_rx_ena = enable; - abort(); + hw->dma_conf.dma_rx_ena = enable; } /** @@ -431,9 +400,7 @@ static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) */ static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_tx_ena = enable; - abort(); + hw->dma_conf.dma_tx_ena = enable; } /** @@ -444,9 +411,7 @@ static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) */ static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.rx_eof_en = enable; - abort(); + hw->dma_conf.rx_eof_en = enable; } /*------------------------------------------------------------------------------ @@ -461,14 +426,12 @@ static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) */ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // for (int x = 0; x < bitlen; x += 32) { - // //Use memcpy to get around alignment issues for txdata - // uint32_t word; - // memcpy(&word, &buffer_to_send[x / 8], 4); - // hw->data_buf[(x / 32)].buf = word; - // } - abort(); + for (int x = 0; x < bitlen; x += 32) { + //Use memcpy to get around alignment issues for txdata + uint32_t word; + memcpy(&word, &buffer_to_send[x / 8], 4); + hw->data_buf[(x / 32)].buf = word; + } } /** @@ -481,28 +444,29 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s */ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // HAL_ASSERT(byte_id + len <= 64); - // HAL_ASSERT(len > 0); - // HAL_ASSERT(byte_id >= 0); - // // while (len > 0) { - // uint32_t word; - // int offset = byte_id % 4; - // int copy_len = 4 - offset; - // if (copy_len > len) { - // copy_len = len; - // } - // // //read-modify-write - // if (copy_len != 4) { - // word = hw->data_buf[byte_id / 4].buf; //read - // } - // memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify - // hw->data_buf[byte_id / 4].buf = word; //write - // // data += copy_len; - // byte_id += copy_len; - // len -= copy_len; - // } - abort(); + HAL_ASSERT(byte_id + len <= 64); + HAL_ASSERT(len > 0); + HAL_ASSERT(byte_id >= 0); + + while (len > 0) { + uint32_t word; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + //read-modify-write + if (copy_len != 4) { + word = hw->data_buf[byte_id / 4].buf; //read + } + memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify + hw->data_buf[byte_id / 4].buf = word; //write + + data += copy_len; + byte_id += copy_len; + len -= copy_len; + } } /** @@ -514,17 +478,15 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t */ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // for (int x = 0; x < bitlen; x += 32) { - // //Do a memcpy to get around possible alignment issues in rx_buffer - // uint32_t word = hw->data_buf[x / 32].buf; - // int len = bitlen - x; - // if (len > 32) { - // len = 32; - // } - // memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); - // } - abort(); + for (int x = 0; x < bitlen; x += 32) { + //Do a memcpy to get around possible alignment issues in rx_buffer + uint32_t word = hw->data_buf[x / 32].buf; + int len = bitlen - x; + if (len > 32) { + len = 32; + } + memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); + } } /** @@ -537,20 +499,19 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz */ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // while (len > 0) { - // uint32_t word = hw->data_buf[byte_id / 4].buf; - // int offset = byte_id % 4; - // int copy_len = 4 - offset; - // if (copy_len > len) { - // copy_len = len; - // } - // // memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); - // byte_id += copy_len; - // out_data += copy_len; - // len -= copy_len; - // } - abort(); + while (len > 0) { + uint32_t word = hw->data_buf[byte_id / 4].buf; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); + byte_id += copy_len; + out_data += copy_len; + len -= copy_len; + } } /*------------------------------------------------------------------------------ @@ -565,13 +526,11 @@ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t * */ static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (pos_cs) { - // hw->misc.master_cs_pol |= (1 << cs); - // } else { - // hw->misc.master_cs_pol &= ~(1 << cs); - // } - abort(); + if (pos_cs) { + hw->misc.master_cs_pol |= (1 << cs); + } else { + hw->misc.master_cs_pol &= ~(1 << cs); + } } /** @@ -582,9 +541,7 @@ static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_ */ static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.wr_bit_order = lsbfirst; - abort(); + hw->ctrl.wr_bit_order = lsbfirst; } /** @@ -595,9 +552,7 @@ static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) */ static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.rd_bit_order = lsbfirst; - abort(); + hw->ctrl.rd_bit_order = lsbfirst; } /** @@ -608,22 +563,20 @@ static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) */ static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //Configure polarity - // if (mode == 0) { - // hw->misc.ck_idle_edge = 0; - // hw->user.ck_out_edge = 0; - // } else if (mode == 1) { - // hw->misc.ck_idle_edge = 0; - // hw->user.ck_out_edge = 1; - // } else if (mode == 2) { - // hw->misc.ck_idle_edge = 1; - // hw->user.ck_out_edge = 1; - // } else if (mode == 3) { - // hw->misc.ck_idle_edge = 1; - // hw->user.ck_out_edge = 0; - // } - abort(); + //Configure polarity + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 1; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 0; + } } /** @@ -634,30 +587,28 @@ static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) */ static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (mode == 0) { - // hw->misc.ck_idle_edge = 0; - // hw->user.rsck_i_edge = 0; - // hw->user.tsck_i_edge = 0; - // hw->slave.clk_mode_13 = 0; - // } else if (mode == 1) { - // hw->misc.ck_idle_edge = 0; - // hw->user.rsck_i_edge = 1; - // hw->user.tsck_i_edge = 1; - // hw->slave.clk_mode_13 = 1; - // } else if (mode == 2) { - // hw->misc.ck_idle_edge = 1; - // hw->user.rsck_i_edge = 1; - // hw->user.tsck_i_edge = 1; - // hw->slave.clk_mode_13 = 0; - // } else if (mode == 3) { - // hw->misc.ck_idle_edge = 1; - // hw->user.rsck_i_edge = 0; - // hw->user.tsck_i_edge = 0; - // hw->slave.clk_mode_13 = 1; - // } - // hw->slave.rsck_data_out = 0; - abort(); + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 0; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 1; + } + hw->slave.rsck_data_out = 0; } /** @@ -668,9 +619,7 @@ static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma */ static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.doutdin = !half_duplex; - abort(); + hw->user.doutdin = !half_duplex; } /** @@ -683,9 +632,7 @@ static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) */ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.sio = sio_mode; - abort(); + hw->user.sio = sio_mode; } /** @@ -696,18 +643,16 @@ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) */ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t line_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; - // hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; - // hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); - // hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); - // hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); - // hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); - // hw->ctrl.fread_dual = (line_mode.data_lines == 2); - // hw->user.fwrite_dual = (line_mode.data_lines == 2); - // hw->ctrl.fread_quad = (line_mode.data_lines == 4); - // hw->user.fwrite_quad = (line_mode.data_lines == 4); - abort(); + hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; + hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; + hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); + hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); + hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); + hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); + hw->ctrl.fread_dual = (line_mode.data_lines == 2); + hw->user.fwrite_dual = (line_mode.data_lines == 2); + hw->ctrl.fread_quad = (line_mode.data_lines == 4); + hw->user.fwrite_quad = (line_mode.data_lines == 4); } /** @@ -718,9 +663,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li */ static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_conf.dma_slv_seg_trans_en = seg_trans; - abort(); + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; } /** @@ -731,14 +674,12 @@ static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) */ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; - // hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; - // hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; - // hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; - // hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; - // hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; - abort(); + hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; + hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; + hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; + hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; + hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; + hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; } /** @@ -749,9 +690,7 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) */ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; - abort(); + hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; } /*------------------------------------------------------------------------------ @@ -765,9 +704,7 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) */ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->clock.val = *(uint32_t *)val; - abort(); + hw->clock.val = *(uint32_t *)val; } /** @@ -781,10 +718,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl */ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return (fapb / (pre * n)); - abort(); - return (int)0; + return (fapb / (pre * n)); } /** @@ -799,66 +733,66 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) */ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // typeof(GPSPI2.clock) reg; - // int eff_clk; - // // //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. - // if (hz > ((fapb / 4) * 3)) { - // //Using Fapb directly will give us the best result here. - // reg.clkcnt_l = 0; - // reg.clkcnt_h = 0; - // reg.clkcnt_n = 0; - // reg.clkdiv_pre = 0; - // reg.clk_equ_sysclk = 1; - // eff_clk = fapb; - // } else { - // //For best duty cycle resolution, we want n to be as close to 32 as possible, but - // //we also need a pre/n combo that gets us as close as possible to the intended freq. - // //To do this, we bruteforce n and calculate the best pre to go along with that. - // //If there's a choice between pre/n combos that give the same result, use the one - // //with the higher n. - // int pre, n, h, l; - // int bestn = -1; - // int bestpre = -1; - // int besterr = 0; - // int errval; - // for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. - // //Effectively, this does pre=round((fapb/n)/hz). - // pre = ((fapb / n) + (hz / 2)) / hz; - // if (pre <= 0) { - // pre = 1; - // } - // if (pre > 16) { - // pre = 16; - // } - // errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); - // if (bestn == -1 || errval <= besterr) { - // besterr = errval; - // bestn = n; - // bestpre = pre; - // } - // } - // // n = bestn; - // pre = bestpre; - // l = n; - // //This effectively does round((duty_cycle*n)/256) - // h = (duty_cycle * n + 127) / 256; - // if (h <= 0) { - // h = 1; - // } - // // reg.clk_equ_sysclk = 0; - // reg.clkcnt_n = n - 1; - // reg.clkdiv_pre = pre - 1; - // reg.clkcnt_h = h - 1; - // reg.clkcnt_l = l - 1; - // eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); - // } - // if (out_reg != NULL) { - // *(uint32_t *)out_reg = reg.val; - // } - // return eff_clk; - abort(); - return (int)0; + typeof(GPSPI2.clock) reg; + int eff_clk; + + //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. + if (hz > ((fapb / 4) * 3)) { + //Using Fapb directly will give us the best result here. + reg.clkcnt_l = 0; + reg.clkcnt_h = 0; + reg.clkcnt_n = 0; + reg.clkdiv_pre = 0; + reg.clk_equ_sysclk = 1; + eff_clk = fapb; + } else { + //For best duty cycle resolution, we want n to be as close to 32 as possible, but + //we also need a pre/n combo that gets us as close as possible to the intended freq. + //To do this, we bruteforce n and calculate the best pre to go along with that. + //If there's a choice between pre/n combos that give the same result, use the one + //with the higher n. + int pre, n, h, l; + int bestn = -1; + int bestpre = -1; + int besterr = 0; + int errval; + for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. + //Effectively, this does pre=round((fapb/n)/hz). + pre = ((fapb / n) + (hz / 2)) / hz; + if (pre <= 0) { + pre = 1; + } + if (pre > 16) { + pre = 16; + } + errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); + if (bestn == -1 || errval <= besterr) { + besterr = errval; + bestn = n; + bestpre = pre; + } + } + + n = bestn; + pre = bestpre; + l = n; + //This effectively does round((duty_cycle*n)/256) + h = (duty_cycle * n + 127) / 256; + if (h <= 0) { + h = 1; + } + + reg.clk_equ_sysclk = 0; + reg.clkcnt_n = n - 1; + reg.clkdiv_pre = pre - 1; + reg.clkcnt_h = h - 1; + reg.clkcnt_l = l - 1; + eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); + } + if (out_reg != NULL) { + *(uint32_t *)out_reg = reg.val; + } + return eff_clk; } /** @@ -878,13 +812,10 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ */ static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // spi_ll_clock_val_t reg_val; - // int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); - // spi_ll_master_set_clock_by_reg(hw, ®_val); - // return freq; - abort(); - return (int)0; + spi_ll_clock_val_t reg_val; + int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); + spi_ll_master_set_clock_by_reg(hw, ®_val); + return freq; } /** @@ -898,8 +829,6 @@ static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int d */ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - abort(); } /** @@ -913,8 +842,6 @@ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int dela */ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - abort(); } /** @@ -925,10 +852,8 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela */ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user1.cs_hold_time = hold; - // hw->user.cs_hold = hold ? 1 : 0; - abort(); + hw->user1.cs_hold_time = hold; + hw->user.cs_hold = hold ? 1 : 0; } /** @@ -942,10 +867,18 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) */ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user1.cs_setup_time = setup - 1; - // hw->user.cs_setup = setup ? 1 : 0; - abort(); + hw->user1.cs_setup_time = setup - 1; + hw->user.cs_setup = setup ? 1 : 0; +} + +/** + * Determine and unify the default level of mosi line when bus free + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level) +{ + hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state } /*------------------------------------------------------------------------------ @@ -960,11 +893,9 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) */ static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (bitlen > 0) { - // hw->ms_dlen.ms_data_bitlen = bitlen - 1; - // } - abort(); + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } } /** @@ -975,11 +906,9 @@ static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (bitlen > 0) { - // hw->ms_dlen.ms_data_bitlen = bitlen - 1; - // } - abort(); + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } } /** @@ -990,9 +919,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //This is not used in esp32c3 - abort(); + //This is not used in esp32c5 } /** @@ -1003,9 +930,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // //This is not used in esp32c3 - abort(); + //This is not used in esp32c5 } /** @@ -1019,10 +944,8 @@ static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user2.usr_command_bitlen = bitlen - 1; - // hw->user.usr_command = bitlen ? 1 : 0; - abort(); + hw->user2.usr_command_bitlen = bitlen - 1; + hw->user.usr_command = bitlen ? 1 : 0; } /** @@ -1036,10 +959,8 @@ static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) */ static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user1.usr_addr_bitlen = bitlen - 1; - // hw->user.usr_addr = bitlen ? 1 : 0; - abort(); + hw->user1.usr_addr_bitlen = bitlen - 1; + hw->user.usr_addr = bitlen ? 1 : 0; } /** @@ -1054,23 +975,21 @@ static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) */ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (lsbfirst) { - // /* The output address start from the LSB of the highest byte, i.e. - // * addr[24] -> addr[31] - // * ... - // * addr[0] -> addr[7] - // * So swap the byte order to let the LSB sent first. - // */ - // addr = HAL_SWAP32(addr); - // //otherwise only addr register is sent - // hw->addr.val = addr; - // } else { - // // shift the address to MSB of addr register. - // // output address will be sent from MSB to LSB of addr register - // hw->addr.val = addr << (32 - addrlen); - // } - abort(); + if (lsbfirst) { + /* The output address start from the LSB of the highest byte, i.e. + * addr[24] -> addr[31] + * ... + * addr[0] -> addr[7] + * So swap the byte order to let the LSB sent first. + */ + addr = HAL_SWAP32(addr); + //otherwise only addr register is sent + hw->addr.val = addr; + } else { + // shift the address to MSB of addr register. + // output address will be sent from MSB to LSB of addr register + hw->addr.val = addr << (32 - addrlen); + } } /** @@ -1085,18 +1004,16 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, */ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // if (lsbfirst) { - // // The output command start from bit0 to bit 15, kept as is. - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); - // } else { - // /* Output command will be sent from bit 7 to 0 of command_value, and - // * then bit 15 to 8 of the same register field. Shift and swap to send - // * more straightly. - // */ - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); - // } - abort(); + if (lsbfirst) { + // The output command start from bit0 to bit 15, kept as is. + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); + } else { + /* Output command will be sent from bit 7 to 0 of command_value, and + * then bit 15 to 8 of the same register field. Shift and swap to send + * more straightly. + */ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); + } } /** @@ -1110,10 +1027,8 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b */ static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.usr_dummy = dummy_n ? 1 : 0; - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); - abort(); + hw->user.usr_dummy = dummy_n ? 1 : 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); } /** @@ -1124,9 +1039,7 @@ static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) */ static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.usr_miso = enable; - abort(); + hw->user.usr_miso = enable; } /** @@ -1137,9 +1050,7 @@ static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) */ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->user.usr_mosi = enable; - abort(); + hw->user.usr_mosi = enable; } /** @@ -1151,10 +1062,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) */ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->slave1.slv_data_bitlen; - abort(); - return (uint32_t)0; + return hw->slave1.slv_data_bitlen; } /*------------------------------------------------------------------------------ @@ -1163,63 +1071,52 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) //helper macros to generate code for each interrupts #define FOR_EACH_ITEM(op, list) do { list(op) } while(0) #define INTR_LIST(item) \ - item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \ - item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done, dma_int_raw.slv_rd_buf_done, dma_int_clr.slv_rd_buf_done, dma_int_set.slv_rd_buf_done_int_set) \ - item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done, dma_int_raw.slv_wr_buf_done, dma_int_clr.slv_wr_buf_done, dma_int_set.slv_wr_buf_done_int_set) \ - item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done, dma_int_raw.slv_rd_dma_done, dma_int_clr.slv_rd_dma_done, dma_int_set.slv_rd_dma_done_int_set) \ - item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done, dma_int_raw.slv_wr_dma_done, dma_int_clr.slv_wr_dma_done, dma_int_set.slv_wr_dma_done_int_set) \ - item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7, dma_int_raw.slv_cmd7, dma_int_clr.slv_cmd7, dma_int_set.slv_cmd7_int_set) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8, dma_int_raw.slv_cmd8, dma_int_clr.slv_cmd8, dma_int_set.slv_cmd8_int_set) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9, dma_int_raw.slv_cmd9, dma_int_clr.slv_cmd9, dma_int_set.slv_cmd9_int_set) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda, dma_int_raw.slv_cmda, dma_int_clr.slv_cmda, dma_int_set.slv_cmda_int_set) + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr, dma_int_set.trans_done_int_set) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr, dma_int_set.slv_rd_buf_done_int_set) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr, dma_int_set.slv_wr_buf_done_int_set) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr, dma_int_set.slv_rd_dma_done_int_set) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr, dma_int_set.slv_wr_dma_done_int_set) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr, dma_int_set.dma_seg_trans_done_int_set) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr, dma_int_set.slv_cmd7_int_set) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr, dma_int_set.slv_cmd8_int_set) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr, dma_int_set.slv_cmd9_int_set) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr, dma_int_set.slv_cmda_int_set) static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; - // FOR_EACH_ITEM(ENA_INTR, INTR_LIST); - // ef ENA_INTR - abort(); +#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; + FOR_EACH_ITEM(ENA_INTR, INTR_LIST); +#undef ENA_INTR } static inline void spi_ll_disable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; - // FOR_EACH_ITEM(DIS_INTR, INTR_LIST); - // ef DIS_INTR - abort(); +#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; + FOR_EACH_ITEM(DIS_INTR, INTR_LIST); +#undef DIS_INTR } static inline void spi_ll_set_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; - // FOR_EACH_ITEM(SET_INTR, INTR_LIST); - // ef SET_INTR - abort(); +#define SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; + FOR_EACH_ITEM(SET_INTR, INTR_LIST); +#undef SET_INTR } static inline void spi_ll_clear_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; - // FOR_EACH_ITEM(CLR_INTR, INTR_LIST); - // ef CLR_INTR - abort(); +#define CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; + FOR_EACH_ITEM(CLR_INTR, INTR_LIST); +#undef CLR_INTR } static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // ine GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; - // FOR_EACH_ITEM(GET_INTR, INTR_LIST); - // return false; - // ef GET_INTR - abort(); - return (bool)0; +#define GET_INTR(intr_bit, _, sta_reg, ...) if (intr_mask & (intr_bit) && hw->sta_reg) return true; + FOR_EACH_ITEM(GET_INTR, INTR_LIST); + return false; +#undef GET_INTR } #undef FOR_EACH_ITEM @@ -1232,9 +1129,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) */ static inline void spi_ll_disable_int(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_ena.trans_done = 0; - abort(); + hw->dma_int_ena.trans_done_int_ena = 0; } /** @@ -1244,9 +1139,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw) */ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_clr.trans_done = 1; - abort(); + hw->dma_int_clr.trans_done_int_clr = 1; } /** @@ -1256,9 +1149,7 @@ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) */ static inline void spi_ll_set_int_stat(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_set.trans_done_int_set = 1; - abort(); + hw->dma_int_set.trans_done_int_set = 1; } /** @@ -1268,9 +1159,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw) */ static inline void spi_ll_enable_int(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->dma_int_ena.trans_done = 1; - abort(); + hw->dma_int_ena.trans_done_int_ena = 1; } /*------------------------------------------------------------------------------ @@ -1278,28 +1167,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) *----------------------------------------------------------------------------*/ static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; - // hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; - // hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; - // hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; - abort(); + hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; } static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->slave1.slv_data_bitlen / 8; - abort(); - return (int)0; + return hw->slave1.slv_data_bitlen / 8; } static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return hw->slave1.slv_last_addr; - abort(); - return (uint32_t)0; + return hw->slave1.slv_last_addr; } #undef SPI_LL_RST_MASK @@ -1312,46 +1193,43 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) */ static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // uint8_t cmd_base = 0x00; - // switch (cmd_t) - // { - // case SPI_CMD_HD_WRBUF: - // cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; - // break; - // case SPI_CMD_HD_RDBUF: - // cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; - // break; - // case SPI_CMD_HD_WRDMA: - // cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; - // break; - // case SPI_CMD_HD_RDDMA: - // cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; - // break; - // case SPI_CMD_HD_SEG_END: - // cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; - // break; - // case SPI_CMD_HD_EN_QPI: - // cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; - // break; - // case SPI_CMD_HD_WR_END: - // cmd_base = SPI_LL_BASE_CMD_HD_WR_END; - // break; - // case SPI_CMD_HD_INT0: - // cmd_base = SPI_LL_BASE_CMD_HD_INT0; - // break; - // case SPI_CMD_HD_INT1: - // cmd_base = SPI_LL_BASE_CMD_HD_INT1; - // break; - // case SPI_CMD_HD_INT2: - // cmd_base = SPI_LL_BASE_CMD_HD_INT2; - // break; - // default: - // HAL_ASSERT(cmd_base); - // } - // return cmd_base; - abort(); - return (uint8_t)0; + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; } /** @@ -1362,28 +1240,27 @@ static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) */ static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); - // uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit - // // if (line_mode.data_lines == 2) { - // if (line_mode.addr_lines == 2) { - // cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit - // } else { - // cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit - // } - // } else if (line_mode.data_lines == 4) { - // if (line_mode.addr_lines == 4) { - // cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit - // } else { - // cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit - // } - // } - // if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { - // cmd_mod = 0x00; - // } - // // return cmd_base | cmd_mod; - abort(); - return (uint16_t)0; + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; } /** @@ -1393,10 +1270,7 @@ static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line */ static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) { - // TODO: [ESP32C5] IDF-8698, IDF-8699 - // return 8; - abort(); - return (int)0; + return 8; } #ifdef __cplusplus diff --git a/components/hal/esp32c6/include/hal/spi_ll.h b/components/hal/esp32c6/include/hal/spi_ll.h index b253d7e45d2..05de203fc30 100644 --- a/components/hal/esp32c6/include/hal/spi_ll.h +++ b/components/hal/esp32c6/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -307,7 +307,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw) /** * Reset SPI CPU TX FIFO * - * On ESP32C3, this function is not seperated + * On ESP32C6, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ @@ -320,7 +320,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) /** * Reset SPI CPU RX FIFO * - * On ESP32C3, this function is not seperated + * On ESP32C6, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ @@ -903,7 +903,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) { - //This is not used in esp32c3 + //This is not used in esp32c6 } /** @@ -914,7 +914,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) { - //This is not used in esp32c3 + //This is not used in esp32c6 } /** diff --git a/components/idf_test/include/esp32c5/.gitkeep b/components/idf_test/include/esp32c5/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/idf_test/include/esp32c5/idf_performance_target.h b/components/idf_test/include/esp32c5/idf_performance_target.h index dd3f635e549..c6a6eb89791 100644 --- a/components/idf_test/include/esp32c5/idf_performance_target.h +++ b/components/idf_test/include/esp32c5/idf_performance_target.h @@ -5,3 +5,9 @@ */ #pragma once + +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 27 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 16 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 24 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 13 diff --git a/components/soc/esp32c2/spi_periph.c b/components/soc/esp32c2/spi_periph.c index b2f7e416b21..5ae7aed529f 100644 --- a/components/soc/esp32c2/spi_periph.c +++ b/components/soc/esp32c2/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c index b2f7e416b21..5ae7aed529f 100644 --- a/components/soc/esp32c3/spi_periph.c +++ b/components/soc/esp32c3/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in index f8d4368a55e..c74b0d8ce45 100644 --- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -39,6 +39,10 @@ config SOC_RTC_MEM_SUPPORTED bool default y +config SOC_GPSPI_SUPPORTED + bool + default y + config SOC_I2C_SUPPORTED bool default y @@ -279,6 +283,42 @@ config SOC_SPI_MAX_CS_NUM int default 6 +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_SPI_SUPPORT_CLK_XTAL + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 256 + config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y diff --git a/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h b/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h index d461f87967a..325c0cc51be 100644 --- a/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h @@ -359,16 +359,16 @@ typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6) /** * @brief Array initializer for all supported clock sources of SPI */ -#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} +#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} /** * @brief Type of SPI clock source. */ -typedef enum { // TODO: [ESP32C5] IDF-8698, IDF-8699 (inherit from C6) - SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ - SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ +typedef enum { SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */ SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */ } soc_periph_spi_clk_src_t; //////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h index df6b6db7a28..28b1b67bb7d 100644 --- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -41,7 +41,7 @@ // #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 // #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726 // #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687 -// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8698, IDF-8699 +#define SOC_GPSPI_SUPPORTED 1 // #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684 #define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 @@ -379,23 +379,23 @@ #define SOC_SPI_PERIPH_CS_NUM(i) 6 #define SOC_SPI_MAX_CS_NUM 6 -// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 -// #define SOC_SPI_SUPPORT_DDRCLK 1 -// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -// #define SOC_SPI_SUPPORT_CD_SIG 1 -// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 -// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -// #define SOC_SPI_SUPPORT_CLK_XTAL 1 -// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1 +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define SOC_SPI_SUPPORT_CLK_XTAL 1 +// #define SOC_SPI_SUPPORT_CLK_PLL_F160M 1 // #define SOC_SPI_SUPPORT_CLK_RC_FAST 1 // Peripheral supports DIO, DOUT, QIO, or QOUT // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) -// #define SOC_MEMSPI_IS_INDEPENDENT 1 -// #define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 256 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ // #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) diff --git a/components/soc/esp32c5/beta3/include/soc/spi_pins.h b/components/soc/esp32c5/beta3/include/soc/spi_pins.h index e50f1b1c43a..918fc1ef664 100644 --- a/components/soc/esp32c5/beta3/include/soc/spi_pins.h +++ b/components/soc/esp32c5/beta3/include/soc/spi_pins.h @@ -1,25 +1,18 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -// TODO: [ESP32C5] IDF-8698 (inherit from C6) - -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_CS 24 -#define SPI_IOMUX_PIN_NUM_CLK 29 -#define SPI_IOMUX_PIN_NUM_MOSI 30 -#define SPI_IOMUX_PIN_NUM_MISO 25 -#define SPI_IOMUX_PIN_NUM_WP 26 -#define SPI_IOMUX_PIN_NUM_HD 28 +// MSPI pin defined in io_mux_reg.h +// IOMUX pin for GPSPI2 #define SPI2_FUNC_NUM 2 #define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_HD 4 #define SPI2_IOMUX_PIN_NUM_WP 5 #define SPI2_IOMUX_PIN_NUM_CLK 6 #define SPI2_IOMUX_PIN_NUM_MOSI 7 -#define SPI2_IOMUX_PIN_NUM_CS 16 +#define SPI2_IOMUX_PIN_NUM_CS 12 diff --git a/components/soc/esp32c5/beta3/include/soc/spi_struct.h b/components/soc/esp32c5/beta3/include/soc/spi_struct.h index 6ff9c1e942d..b9fdba155a9 100644 --- a/components/soc/esp32c5/beta3/include/soc/spi_struct.h +++ b/components/soc/esp32c5/beta3/include/soc/spi_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1348,201 +1348,6 @@ typedef union { uint32_t val; } spi_wn_reg_t; -/** Type of w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_w1_reg_t; - -/** Type of w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_w2_reg_t; - -/** Type of w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_w3_reg_t; - -/** Type of w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_w4_reg_t; - -/** Type of w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_w5_reg_t; - -/** Type of w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_w6_reg_t; - -/** Type of w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_w7_reg_t; - -/** Type of w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_w8_reg_t; - -/** Type of w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_w9_reg_t; - -/** Type of w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_w10_reg_t; - -/** Type of w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_w11_reg_t; - -/** Type of w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_w12_reg_t; - -/** Type of w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_w13_reg_t; - -/** Type of w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_w14_reg_t; - -/** Type of w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_w15_reg_t; - /** Group: Version register */ /** Type of date register @@ -1577,7 +1382,7 @@ typedef struct spi_dev_t { volatile spi_dma_int_ena_reg_t dma_int_ena; volatile spi_dma_int_clr_reg_t dma_int_clr; volatile spi_dma_int_raw_reg_t dma_int_raw; - volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_st_reg_t dma_int_sta; volatile spi_dma_int_set_reg_t dma_int_set; uint32_t reserved_048[20]; volatile spi_wn_reg_t data_buf[16]; diff --git a/components/soc/esp32c5/beta3/spi_periph.c b/components/soc/esp32c5/beta3/spi_periph.c new file mode 100644 index 00000000000..934cc245008 --- /dev/null +++ b/components/soc/esp32c5/beta3/spi_periph.c @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/spi_periph.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + { + // MSPI on P4 has dedicated iomux pins + .spiclk_out = -1, + .spiclk_in = -1, + .spid_out = -1, + .spiq_out = -1, + .spiwp_out = -1, + .spihd_out = -1, + .spid_in = -1, + .spiq_in = -1, + .spiwp_in = -1, + .spihd_in = -1, + .spics_out = {-1}, + .spics_in = -1, + .spiclk_iomux_pin = -1, + .spid_iomux_pin = -1, + .spiq_iomux_pin = -1, + .spiwp_iomux_pin = -1, + .spihd_iomux_pin = -1, + .spics0_iomux_pin = -1, + .irq = -1, + .irq_dma = -1, + .module = -1, + .hw = NULL, + .func = -1, + }, { + .spiclk_out = FSPICLK_OUT_MUX_IDX, + .spiclk_in = FSPICLK_IN_IDX, + .spid_out = FSPID_OUT_IDX, + .spiq_out = FSPIQ_OUT_IDX, + .spiwp_out = FSPIWP_OUT_IDX, + .spihd_out = FSPIHD_OUT_IDX, + .spid_in = FSPID_IN_IDX, + .spiq_in = FSPIQ_IN_IDX, + .spiwp_in = FSPIWP_IN_IDX, + .spihd_in = FSPIHD_IN_IDX, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, + .spics_in = FSPICS0_IN_IDX, + .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, + .irq = ETS_GPSPI2_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_GPSPI2_MODULE, + .hw = &GPSPI2, + .func = SPI2_FUNC_NUM, + }, +}; diff --git a/components/soc/esp32c6/spi_periph.c b/components/soc/esp32c6/spi_periph.c index 4969841aec3..ea10937f582 100644 --- a/components/soc/esp32c6/spi_periph.c +++ b/components/soc/esp32c6/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32h2/spi_periph.c b/components/soc/esp32h2/spi_periph.c index 8a9fe4d7816..213bed6def4 100644 --- a/components/soc/esp32h2/spi_periph.c +++ b/components/soc/esp32h2/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c index 90f30522d9d..5a629b6604c 100644 --- a/components/soc/esp32p4/spi_periph.c +++ b/components/soc/esp32p4/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32s2/spi_periph.c b/components/soc/esp32s2/spi_periph.c index 0ba96136021..7bf01d0e32e 100644 --- a/components/soc/esp32s2/spi_periph.c +++ b/components/soc/esp32s2/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/components/soc/esp32s3/spi_periph.c b/components/soc/esp32s3/spi_periph.c index a1098d035fe..91fdc873551 100644 --- a/components/soc/esp32s3/spi_periph.c +++ b/components/soc/esp32s3/spi_periph.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/spi_periph.h" -#include "stddef.h" /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc diff --git a/docs/en/api-reference/peripherals/spi_master.rst b/docs/en/api-reference/peripherals/spi_master.rst index fadf01d781d..8ce1b85d580 100644 --- a/docs/en/api-reference/peripherals/spi_master.rst +++ b/docs/en/api-reference/peripherals/spi_master.rst @@ -473,12 +473,12 @@ GPIO Matrix and IO_MUX .. only:: not esp32 - {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"} - {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"} - {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"} - {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"} - {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"} - {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"} + {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="12"} + {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} + {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} + {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} + {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6", esp32c5="4"} + {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5"} Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it. @@ -524,10 +524,10 @@ The main parameter that determines the transfer speed for large transactions is Transaction Duration ^^^^^^^^^^^^^^^^^^^^ -{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"} -{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"} -{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"} -{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"} +{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32c5="27"} +{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32c5="16"} +{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32c5="24"} +{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32c5="13"} Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions. diff --git a/docs/zh_CN/api-reference/peripherals/spi_master.rst b/docs/zh_CN/api-reference/peripherals/spi_master.rst index 7589032e36b..656d3b73780 100644 --- a/docs/zh_CN/api-reference/peripherals/spi_master.rst +++ b/docs/zh_CN/api-reference/peripherals/spi_master.rst @@ -473,12 +473,12 @@ GPIO 矩阵与 IO_MUX 管脚 .. only:: not esp32 - {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"} - {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"} - {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"} - {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"} - {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"} - {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"} + {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="12"} + {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} + {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} + {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} + {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6", esp32c5="4"} + {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11", esp32c5="5"} 芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。 @@ -524,10 +524,10 @@ GPIO 矩阵与 IO_MUX 管脚 传输事务持续时间 ^^^^^^^^^^^^^^^^^^^^ -{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"} -{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"} -{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"} -{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"} +{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32c5="27"} +{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32c5="16"} +{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32c5="24"} +{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32c5="13"} 传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。 From 8625ed252ea334ec4214e546028c1bf04a3ef4c2 Mon Sep 17 00:00:00 2001 From: wanlei Date: Thu, 7 Mar 2024 12:20:13 +0800 Subject: [PATCH 09/15] fix(spi): test_apps mv idf_perform_test to esp_driver_spi domain --- .../test_driver_utils/test_spi_utils.c | 5 +- .../test_apps/.build-test-rules.yml | 10 ++- .../components/spi_bench_mark/CMakeLists.txt | 4 + .../spi_bench_mark/include/spi_performance.h | 86 +++++++++++++++++++ .../test_apps/{spi => }/master/CMakeLists.txt | 5 -- .../test_apps/{spi => }/master/README.md | 0 .../{spi => }/master/main/CMakeLists.txt | 3 +- .../test_apps/master/main/idf_component.yml | 7 ++ .../{spi => }/master/main/test_app_main.c | 0 .../{spi => }/master/main/test_spi_bus_lock.c | 0 .../{spi => }/master/main/test_spi_master.c | 13 ++- .../{spi => }/master/main/test_spi_sio.c | 0 .../master/partition_table_esp32_flash.csv | 0 .../{spi => }/master/pytest_spi_master.py | 1 - .../{spi => }/master/sdkconfig.ci.defaults | 0 .../master/sdkconfig.ci.freertos_compliance | 0 .../master/sdkconfig.ci.freertos_flash | 0 .../{spi => }/master/sdkconfig.ci.iram_safe | 0 .../{spi => }/master/sdkconfig.ci.release | 0 .../{spi => }/master/sdkconfig.defaults | 0 .../{spi => }/master/sdkconfig.defaults.esp32 | 0 .../master/sdkconfig.defaults.esp32s2 | 0 .../master/sdkconfig.defaults.esp32s3 | 0 .../test_apps/{spi => }/param/CMakeLists.txt | 5 -- .../test_apps/{spi => }/param/README.md | 0 .../{spi => }/param/main/CMakeLists.txt | 2 +- .../test_apps/param/main/idf_component.yml | 9 ++ .../{spi => }/param/main/test_app_main.c | 0 .../{spi => }/param/main/test_spi_param.c | 1 + .../{spi => }/param/pytest_spi_param.py | 1 - .../{spi => }/param/sdkconfig.defaults | 0 .../test_apps/{spi => }/slave/CMakeLists.txt | 5 -- .../test_apps/{spi => }/slave/README.md | 0 .../{spi => }/slave/main/CMakeLists.txt | 2 +- .../test_apps/slave/main/idf_component.yml | 5 ++ .../{spi => }/slave/main/test_app_main.c | 0 .../{spi => }/slave/main/test_spi_slave.c | 0 .../slave/main/test_spi_slave_queue.c | 0 .../{spi => }/slave/pytest_spi_slave.py | 1 - .../{spi => }/slave/sdkconfig.ci.defaults | 0 .../{spi => }/slave/sdkconfig.ci.iram_safe | 0 .../{spi => }/slave/sdkconfig.defaults | 0 .../{spi => }/slave_hd/CMakeLists.txt | 5 -- .../test_apps/{spi => }/slave_hd/README.md | 0 .../{spi => }/slave_hd/main/CMakeLists.txt | 2 +- .../test_apps/slave_hd/main/idf_component.yml | 7 ++ .../{spi => }/slave_hd/main/test_app_main.c | 0 .../slave_hd/main/test_spi_slave_hd.c | 0 .../{spi => }/slave_hd/pytest_spi_slave_hd.py | 1 - .../{spi => }/slave_hd/sdkconfig.defaults | 0 .../include/esp32/idf_performance_target.h | 11 --- .../include/esp32c2/idf_performance_target.h | 6 -- .../include/esp32c3/idf_performance_target.h | 17 ---- .../include/esp32c5/idf_performance_target.h | 6 -- .../include/esp32c6/idf_performance_target.h | 6 -- .../include/esp32h2/idf_performance_target.h | 6 -- .../include/esp32p4/idf_performance_target.h | 7 -- .../include/esp32s2/idf_performance_target.h | 6 -- .../include/esp32s3/idf_performance_target.h | 6 -- 59 files changed, 141 insertions(+), 110 deletions(-) create mode 100644 components/esp_driver_spi/test_apps/components/spi_bench_mark/CMakeLists.txt create mode 100644 components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h rename components/esp_driver_spi/test_apps/{spi => }/master/CMakeLists.txt (86%) rename components/esp_driver_spi/test_apps/{spi => }/master/README.md (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/main/CMakeLists.txt (80%) create mode 100644 components/esp_driver_spi/test_apps/master/main/idf_component.yml rename components/esp_driver_spi/test_apps/{spi => }/master/main/test_app_main.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/main/test_spi_bus_lock.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/main/test_spi_master.c (98%) rename components/esp_driver_spi/test_apps/{spi => }/master/main/test_spi_sio.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/partition_table_esp32_flash.csv (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/pytest_spi_master.py (99%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.ci.defaults (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.ci.freertos_compliance (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.ci.freertos_flash (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.ci.iram_safe (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.ci.release (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.defaults (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.defaults.esp32 (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.defaults.esp32s2 (100%) rename components/esp_driver_spi/test_apps/{spi => }/master/sdkconfig.defaults.esp32s3 (100%) rename components/esp_driver_spi/test_apps/{spi => }/param/CMakeLists.txt (67%) rename components/esp_driver_spi/test_apps/{spi => }/param/README.md (100%) rename components/esp_driver_spi/test_apps/{spi => }/param/main/CMakeLists.txt (76%) create mode 100644 components/esp_driver_spi/test_apps/param/main/idf_component.yml rename components/esp_driver_spi/test_apps/{spi => }/param/main/test_app_main.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/param/main/test_spi_param.c (99%) rename components/esp_driver_spi/test_apps/{spi => }/param/pytest_spi_param.py (99%) rename components/esp_driver_spi/test_apps/{spi => }/param/sdkconfig.defaults (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave/CMakeLists.txt (86%) rename components/esp_driver_spi/test_apps/{spi => }/slave/README.md (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave/main/CMakeLists.txt (81%) create mode 100644 components/esp_driver_spi/test_apps/slave/main/idf_component.yml rename components/esp_driver_spi/test_apps/{spi => }/slave/main/test_app_main.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave/main/test_spi_slave.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave/main/test_spi_slave_queue.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave/pytest_spi_slave.py (99%) rename components/esp_driver_spi/test_apps/{spi => }/slave/sdkconfig.ci.defaults (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave/sdkconfig.ci.iram_safe (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave/sdkconfig.defaults (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave_hd/CMakeLists.txt (67%) rename components/esp_driver_spi/test_apps/{spi => }/slave_hd/README.md (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave_hd/main/CMakeLists.txt (75%) create mode 100644 components/esp_driver_spi/test_apps/slave_hd/main/idf_component.yml rename components/esp_driver_spi/test_apps/{spi => }/slave_hd/main/test_app_main.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave_hd/main/test_spi_slave_hd.c (100%) rename components/esp_driver_spi/test_apps/{spi => }/slave_hd/pytest_spi_slave_hd.py (99%) rename components/esp_driver_spi/test_apps/{spi => }/slave_hd/sdkconfig.defaults (100%) diff --git a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c index ad6a698e687..8b997e62df9 100644 --- a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c +++ b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c @@ -7,6 +7,7 @@ #include "driver/spi_slave.h" #include "esp_log.h" #include "driver/gpio.h" +#include "esp_private/gpio.h" #include "hal/gpio_hal.h" #include "esp_rom_gpio.h" @@ -220,13 +221,13 @@ void master_free_device_bus(spi_device_handle_t spi) void spitest_gpio_output_sel(uint32_t gpio_num, int func, uint32_t signal_idx) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_func_sel(gpio_num, func); esp_rom_gpio_connect_out_signal(gpio_num, signal_idx, 0, 0); } void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx) { - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_func_sel(gpio_num, func); esp_rom_gpio_connect_in_signal(gpio_num, signal_idx, 0); } diff --git a/components/esp_driver_spi/test_apps/.build-test-rules.yml b/components/esp_driver_spi/test_apps/.build-test-rules.yml index f2306768be4..1639bbf5cd2 100644 --- a/components/esp_driver_spi/test_apps/.build-test-rules.yml +++ b/components/esp_driver_spi/test_apps/.build-test-rules.yml @@ -3,8 +3,10 @@ - esp_mm # for cache - esp_driver_spi - esp_driver_gpio + depends_filepatterns: + - components/driver/test_apps/components/test_driver_utils/**/* -components/esp_driver_spi/test_apps/spi/master: +components/esp_driver_spi/test_apps/master: disable: - if: SOC_GPSPI_SUPPORTED != 1 disable_test: @@ -13,7 +15,7 @@ components/esp_driver_spi/test_apps/spi/master: reason: not supported # TODO: IDF-8942 <<: *spi_depends_default -components/esp_driver_spi/test_apps/spi/param: +components/esp_driver_spi/test_apps/param: disable: - if: SOC_GPSPI_SUPPORTED != 1 disable_test: @@ -22,7 +24,7 @@ components/esp_driver_spi/test_apps/spi/param: reason: not supported # TODO: IDF-8942 <<: *spi_depends_default -components/esp_driver_spi/test_apps/spi/slave: +components/esp_driver_spi/test_apps/slave: disable: - if: SOC_GPSPI_SUPPORTED != 1 disable_test: @@ -31,7 +33,7 @@ components/esp_driver_spi/test_apps/spi/slave: reason: not supported # TODO: IDF-8942 <<: *spi_depends_default -components/esp_driver_spi/test_apps/spi/slave_hd: +components/esp_driver_spi/test_apps/slave_hd: disable: - if: SOC_GPSPI_SUPPORTED != 1 - if: SOC_SPI_SUPPORT_SLAVE_HD_VER2 != 1 diff --git a/components/esp_driver_spi/test_apps/components/spi_bench_mark/CMakeLists.txt b/components/esp_driver_spi/test_apps/components/spi_bench_mark/CMakeLists.txt new file mode 100644 index 00000000000..d5466bd3f76 --- /dev/null +++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/CMakeLists.txt @@ -0,0 +1,4 @@ + +idf_component_register( + INCLUDE_DIRS "include" +) diff --git a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h new file mode 100644 index 00000000000..7636ef00143 --- /dev/null +++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#if CONFIG_IDF_TARGET_ESP32 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 16*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 +#if !CONFIG_FREERTOS_SMP // IDF-5223 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 34 // TODO: IDF-5180 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 // TODO: IDF-5180 +#else +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 50 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 50 +#endif + +#elif CONFIG_IDF_TARGET_ESP32S2 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 + +#elif CONFIG_IDF_TARGET_ESP32S3 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 + +#elif CONFIG_IDF_TARGET_ESP32C2 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 23 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 18 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 47 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 42 + +#elif CONFIG_IDF_TARGET_ESP32C3 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 +#if !CONFIG_FREERTOS_SMP // IDF-5223 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 +#else +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 17 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 60 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 60 +#endif + +#elif CONFIG_IDF_TARGET_ESP32C6 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 34 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 + +#elif CONFIG_IDF_TARGET_ESP32H2 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 25 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 61 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 54 + +#elif CONFIG_IDF_TARGET_ESP32P4 +//TODO: IDF-8313 update after chips back and PLL setup +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 10*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 1000 + +#elif CONFIG_IDF_TARGET_ESP32C5 +#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 27 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 16 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 24 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 13 + +#else +#endif diff --git a/components/esp_driver_spi/test_apps/spi/master/CMakeLists.txt b/components/esp_driver_spi/test_apps/master/CMakeLists.txt similarity index 86% rename from components/esp_driver_spi/test_apps/spi/master/CMakeLists.txt rename to components/esp_driver_spi/test_apps/master/CMakeLists.txt index 72e52621b38..a089345e26a 100644 --- a/components/esp_driver_spi/test_apps/spi/master/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/master/CMakeLists.txt @@ -4,11 +4,6 @@ cmake_minimum_required(VERSION 3.16) # "Trim" the build. Include the minimal set of components, main, and anything it depends on. set(COMPONENTS main) -set(EXTRA_COMPONENT_DIRS - "$ENV{IDF_PATH}/tools/unit-test-app/components" - "$ENV{IDF_PATH}/components/driver/test_apps/components" -) - include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(spi_master_test) diff --git a/components/esp_driver_spi/test_apps/spi/master/README.md b/components/esp_driver_spi/test_apps/master/README.md similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/README.md rename to components/esp_driver_spi/test_apps/master/README.md diff --git a/components/esp_driver_spi/test_apps/spi/master/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt similarity index 80% rename from components/esp_driver_spi/test_apps/spi/master/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/master/main/CMakeLists.txt index f8d95ad31e2..9b34511e991 100644 --- a/components/esp_driver_spi/test_apps/spi/master/main/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt @@ -6,11 +6,10 @@ set(srcs "test_spi_bus_lock.c" ) - # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register( SRCS ${srcs} - PRIV_REQUIRES test_utils esp_driver_spi test_driver_utils spi_flash + PRIV_REQUIRES esp_driver_spi spi_flash WHOLE_ARCHIVE ) diff --git a/components/esp_driver_spi/test_apps/master/main/idf_component.yml b/components/esp_driver_spi/test_apps/master/main/idf_component.yml new file mode 100644 index 00000000000..3e1127ae0fd --- /dev/null +++ b/components/esp_driver_spi/test_apps/master/main/idf_component.yml @@ -0,0 +1,7 @@ +dependencies: + test_utils: + path: ${IDF_PATH}/tools/unit-test-app/components/test_utils + test_driver_utils: + path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils + spi_bench_mark: + path: ${IDF_PATH}/components/esp_driver_spi/test_apps/components/spi_bench_mark diff --git a/components/esp_driver_spi/test_apps/spi/master/main/test_app_main.c b/components/esp_driver_spi/test_apps/master/main/test_app_main.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/main/test_app_main.c rename to components/esp_driver_spi/test_apps/master/main/test_app_main.c diff --git a/components/esp_driver_spi/test_apps/spi/master/main/test_spi_bus_lock.c b/components/esp_driver_spi/test_apps/master/main/test_spi_bus_lock.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/main/test_spi_bus_lock.c rename to components/esp_driver_spi/test_apps/master/main/test_spi_bus_lock.c diff --git a/components/esp_driver_spi/test_apps/spi/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c similarity index 98% rename from components/esp_driver_spi/test_apps/spi/master/main/test_spi_master.c rename to components/esp_driver_spi/test_apps/master/main/test_spi_master.c index 1375978d3ae..24e30ff6b78 100644 --- a/components/esp_driver_spi/test_apps/spi/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c @@ -22,6 +22,7 @@ #include "esp_log.h" #include "test_utils.h" #include "test_spi_utils.h" +#include "spi_performance.h" const static char TAG[] = "test_spi"; @@ -1416,7 +1417,8 @@ TEST_CASE("spi_speed", "[spi]") ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM - TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); #endif //acquire the bus to send polling transactions faster @@ -1433,7 +1435,8 @@ TEST_CASE("spi_speed", "[spi]") ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM - TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); #endif //release the bus @@ -1452,7 +1455,8 @@ TEST_CASE("spi_speed", "[spi]") ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM - TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); #endif //acquire the bus to send polling transactions faster @@ -1469,7 +1473,8 @@ TEST_CASE("spi_speed", "[spi]") ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM - TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); + TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2])); #endif //release the bus diff --git a/components/esp_driver_spi/test_apps/spi/master/main/test_spi_sio.c b/components/esp_driver_spi/test_apps/master/main/test_spi_sio.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/main/test_spi_sio.c rename to components/esp_driver_spi/test_apps/master/main/test_spi_sio.c diff --git a/components/esp_driver_spi/test_apps/spi/master/partition_table_esp32_flash.csv b/components/esp_driver_spi/test_apps/master/partition_table_esp32_flash.csv similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/partition_table_esp32_flash.csv rename to components/esp_driver_spi/test_apps/master/partition_table_esp32_flash.csv diff --git a/components/esp_driver_spi/test_apps/spi/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py similarity index 99% rename from components/esp_driver_spi/test_apps/spi/master/pytest_spi_master.py rename to components/esp_driver_spi/test_apps/master/pytest_spi_master.py index 7315d363a30..88e58f9b296 100644 --- a/components/esp_driver_spi/test_apps/spi/master/pytest_spi_master.py +++ b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - import pytest diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.defaults b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.defaults similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.defaults rename to components/esp_driver_spi/test_apps/master/sdkconfig.ci.defaults diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_compliance b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_compliance similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_compliance rename to components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_compliance diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_flash b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_flash similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.freertos_flash rename to components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_flash diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.iram_safe b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.iram_safe similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.iram_safe rename to components/esp_driver_spi/test_apps/master/sdkconfig.ci.iram_safe diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.release b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.release similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.ci.release rename to components/esp_driver_spi/test_apps/master/sdkconfig.ci.release diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults b/components/esp_driver_spi/test_apps/master/sdkconfig.defaults similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/master/sdkconfig.defaults diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32 b/components/esp_driver_spi/test_apps/master/sdkconfig.defaults.esp32 similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32 rename to components/esp_driver_spi/test_apps/master/sdkconfig.defaults.esp32 diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s2 b/components/esp_driver_spi/test_apps/master/sdkconfig.defaults.esp32s2 similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s2 rename to components/esp_driver_spi/test_apps/master/sdkconfig.defaults.esp32s2 diff --git a/components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s3 b/components/esp_driver_spi/test_apps/master/sdkconfig.defaults.esp32s3 similarity index 100% rename from components/esp_driver_spi/test_apps/spi/master/sdkconfig.defaults.esp32s3 rename to components/esp_driver_spi/test_apps/master/sdkconfig.defaults.esp32s3 diff --git a/components/esp_driver_spi/test_apps/spi/param/CMakeLists.txt b/components/esp_driver_spi/test_apps/param/CMakeLists.txt similarity index 67% rename from components/esp_driver_spi/test_apps/spi/param/CMakeLists.txt rename to components/esp_driver_spi/test_apps/param/CMakeLists.txt index 683bf0ee2ce..83f0cb7142e 100644 --- a/components/esp_driver_spi/test_apps/spi/param/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/param/CMakeLists.txt @@ -4,10 +4,5 @@ cmake_minimum_required(VERSION 3.16) # "Trim" the build. Include the minimal set of components, main, and anything it depends on. set(COMPONENTS main) -set(EXTRA_COMPONENT_DIRS - "$ENV{IDF_PATH}/tools/unit-test-app/components" - "$ENV{IDF_PATH}/components/driver/test_apps/components" -) - include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(spi_param_test) diff --git a/components/esp_driver_spi/test_apps/spi/param/README.md b/components/esp_driver_spi/test_apps/param/README.md similarity index 100% rename from components/esp_driver_spi/test_apps/spi/param/README.md rename to components/esp_driver_spi/test_apps/param/README.md diff --git a/components/esp_driver_spi/test_apps/spi/param/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/param/main/CMakeLists.txt similarity index 76% rename from components/esp_driver_spi/test_apps/spi/param/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/param/main/CMakeLists.txt index 802e5b84a03..b2a85587cee 100644 --- a/components/esp_driver_spi/test_apps/spi/param/main/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/param/main/CMakeLists.txt @@ -9,6 +9,6 @@ set(srcs # the component can be registered as WHOLE_ARCHIVE idf_component_register( SRCS ${srcs} - PRIV_REQUIRES test_utils driver test_driver_utils esp_serial_slave_link + PRIV_REQUIRES esp_driver_spi WHOLE_ARCHIVE ) diff --git a/components/esp_driver_spi/test_apps/param/main/idf_component.yml b/components/esp_driver_spi/test_apps/param/main/idf_component.yml new file mode 100644 index 00000000000..f4502bc8244 --- /dev/null +++ b/components/esp_driver_spi/test_apps/param/main/idf_component.yml @@ -0,0 +1,9 @@ +dependencies: + test_utils: + path: ${IDF_PATH}/tools/unit-test-app/components/test_utils + test_driver_utils: + path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils + spi_bench_mark: + path: ${IDF_PATH}/components/esp_driver_spi/test_apps/components/spi_bench_mark + esp_serial_slave_link: + path: ${IDF_PATH}/components/driver/test_apps/components/esp_serial_slave_link diff --git a/components/esp_driver_spi/test_apps/spi/param/main/test_app_main.c b/components/esp_driver_spi/test_apps/param/main/test_app_main.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/param/main/test_app_main.c rename to components/esp_driver_spi/test_apps/param/main/test_app_main.c diff --git a/components/esp_driver_spi/test_apps/spi/param/main/test_spi_param.c b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c similarity index 99% rename from components/esp_driver_spi/test_apps/spi/param/main/test_spi_param.c rename to components/esp_driver_spi/test_apps/param/main/test_spi_param.c index 5c8f44332d5..e94994298ae 100644 --- a/components/esp_driver_spi/test_apps/spi/param/main/test_spi_param.c +++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c @@ -11,6 +11,7 @@ #include "test_spi_utils.h" #include "driver/spi_master.h" #include "driver/spi_slave.h" +#include "spi_performance.h" #if SOC_SPI_SUPPORT_SLAVE_HD_VER2 #include "esp_serial_slave_link/essl_spi.h" diff --git a/components/esp_driver_spi/test_apps/spi/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py similarity index 99% rename from components/esp_driver_spi/test_apps/spi/param/pytest_spi_param.py rename to components/esp_driver_spi/test_apps/param/pytest_spi_param.py index 4a1d8d7e56d..fa1c3f86ad9 100644 --- a/components/esp_driver_spi/test_apps/spi/param/pytest_spi_param.py +++ b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - import pytest diff --git a/components/esp_driver_spi/test_apps/spi/param/sdkconfig.defaults b/components/esp_driver_spi/test_apps/param/sdkconfig.defaults similarity index 100% rename from components/esp_driver_spi/test_apps/spi/param/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/param/sdkconfig.defaults diff --git a/components/esp_driver_spi/test_apps/spi/slave/CMakeLists.txt b/components/esp_driver_spi/test_apps/slave/CMakeLists.txt similarity index 86% rename from components/esp_driver_spi/test_apps/spi/slave/CMakeLists.txt rename to components/esp_driver_spi/test_apps/slave/CMakeLists.txt index 7cc8d06266b..272b5680b6c 100644 --- a/components/esp_driver_spi/test_apps/spi/slave/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/slave/CMakeLists.txt @@ -4,11 +4,6 @@ cmake_minimum_required(VERSION 3.16) # "Trim" the build. Include the minimal set of components, main, and anything it depends on. set(COMPONENTS main) -set(EXTRA_COMPONENT_DIRS - "$ENV{IDF_PATH}/tools/unit-test-app/components" - "$ENV{IDF_PATH}/components/driver/test_apps/components" -) - include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(spi_slave_test) diff --git a/components/esp_driver_spi/test_apps/spi/slave/README.md b/components/esp_driver_spi/test_apps/slave/README.md similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave/README.md rename to components/esp_driver_spi/test_apps/slave/README.md diff --git a/components/esp_driver_spi/test_apps/spi/slave/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/slave/main/CMakeLists.txt similarity index 81% rename from components/esp_driver_spi/test_apps/spi/slave/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/slave/main/CMakeLists.txt index 58b237b1806..3c0adce0842 100644 --- a/components/esp_driver_spi/test_apps/spi/slave/main/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/slave/main/CMakeLists.txt @@ -10,6 +10,6 @@ set(srcs # the component can be registered as WHOLE_ARCHIVE idf_component_register( SRCS ${srcs} - PRIV_REQUIRES test_utils driver test_driver_utils spi_flash + PRIV_REQUIRES esp_driver_spi spi_flash WHOLE_ARCHIVE ) diff --git a/components/esp_driver_spi/test_apps/slave/main/idf_component.yml b/components/esp_driver_spi/test_apps/slave/main/idf_component.yml new file mode 100644 index 00000000000..7a92181a687 --- /dev/null +++ b/components/esp_driver_spi/test_apps/slave/main/idf_component.yml @@ -0,0 +1,5 @@ +dependencies: + test_utils: + path: ${IDF_PATH}/tools/unit-test-app/components/test_utils + test_driver_utils: + path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils diff --git a/components/esp_driver_spi/test_apps/spi/slave/main/test_app_main.c b/components/esp_driver_spi/test_apps/slave/main/test_app_main.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave/main/test_app_main.c rename to components/esp_driver_spi/test_apps/slave/main/test_app_main.c diff --git a/components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave.c b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave.c rename to components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c diff --git a/components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave_queue.c b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave_queue.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave/main/test_spi_slave_queue.c rename to components/esp_driver_spi/test_apps/slave/main/test_spi_slave_queue.c diff --git a/components/esp_driver_spi/test_apps/spi/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py similarity index 99% rename from components/esp_driver_spi/test_apps/spi/slave/pytest_spi_slave.py rename to components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py index f468b8d4dfc..e3637da3589 100644 --- a/components/esp_driver_spi/test_apps/spi/slave/pytest_spi_slave.py +++ b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - import pytest diff --git a/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.defaults b/components/esp_driver_spi/test_apps/slave/sdkconfig.ci.defaults similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.defaults rename to components/esp_driver_spi/test_apps/slave/sdkconfig.ci.defaults diff --git a/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.iram_safe b/components/esp_driver_spi/test_apps/slave/sdkconfig.ci.iram_safe similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave/sdkconfig.ci.iram_safe rename to components/esp_driver_spi/test_apps/slave/sdkconfig.ci.iram_safe diff --git a/components/esp_driver_spi/test_apps/spi/slave/sdkconfig.defaults b/components/esp_driver_spi/test_apps/slave/sdkconfig.defaults similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/slave/sdkconfig.defaults diff --git a/components/esp_driver_spi/test_apps/spi/slave_hd/CMakeLists.txt b/components/esp_driver_spi/test_apps/slave_hd/CMakeLists.txt similarity index 67% rename from components/esp_driver_spi/test_apps/spi/slave_hd/CMakeLists.txt rename to components/esp_driver_spi/test_apps/slave_hd/CMakeLists.txt index 810b90fb6cf..858e0cd4eb7 100644 --- a/components/esp_driver_spi/test_apps/spi/slave_hd/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/slave_hd/CMakeLists.txt @@ -4,10 +4,5 @@ cmake_minimum_required(VERSION 3.16) # "Trim" the build. Include the minimal set of components, main, and anything it depends on. set(COMPONENTS main) -set(EXTRA_COMPONENT_DIRS - "$ENV{IDF_PATH}/tools/unit-test-app/components" - "$ENV{IDF_PATH}/components/driver/test_apps/components" -) - include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(spi_slave_hd_test) diff --git a/components/esp_driver_spi/test_apps/spi/slave_hd/README.md b/components/esp_driver_spi/test_apps/slave_hd/README.md similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave_hd/README.md rename to components/esp_driver_spi/test_apps/slave_hd/README.md diff --git a/components/esp_driver_spi/test_apps/spi/slave_hd/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/slave_hd/main/CMakeLists.txt similarity index 75% rename from components/esp_driver_spi/test_apps/spi/slave_hd/main/CMakeLists.txt rename to components/esp_driver_spi/test_apps/slave_hd/main/CMakeLists.txt index 12e108533d7..6b887151669 100644 --- a/components/esp_driver_spi/test_apps/spi/slave_hd/main/CMakeLists.txt +++ b/components/esp_driver_spi/test_apps/slave_hd/main/CMakeLists.txt @@ -9,6 +9,6 @@ set(srcs # the component can be registered as WHOLE_ARCHIVE idf_component_register( SRCS ${srcs} - PRIV_REQUIRES test_utils driver test_driver_utils esp_serial_slave_link sdmmc + PRIV_REQUIRES esp_driver_spi WHOLE_ARCHIVE ) diff --git a/components/esp_driver_spi/test_apps/slave_hd/main/idf_component.yml b/components/esp_driver_spi/test_apps/slave_hd/main/idf_component.yml new file mode 100644 index 00000000000..518a1d68335 --- /dev/null +++ b/components/esp_driver_spi/test_apps/slave_hd/main/idf_component.yml @@ -0,0 +1,7 @@ +dependencies: + test_utils: + path: ${IDF_PATH}/tools/unit-test-app/components/test_utils + test_driver_utils: + path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils + esp_serial_slave_link: + path: ${IDF_PATH}/components/driver/test_apps/components/esp_serial_slave_link diff --git a/components/esp_driver_spi/test_apps/spi/slave_hd/main/test_app_main.c b/components/esp_driver_spi/test_apps/slave_hd/main/test_app_main.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave_hd/main/test_app_main.c rename to components/esp_driver_spi/test_apps/slave_hd/main/test_app_main.c diff --git a/components/esp_driver_spi/test_apps/spi/slave_hd/main/test_spi_slave_hd.c b/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave_hd/main/test_spi_slave_hd.c rename to components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c diff --git a/components/esp_driver_spi/test_apps/spi/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py similarity index 99% rename from components/esp_driver_spi/test_apps/spi/slave_hd/pytest_spi_slave_hd.py rename to components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py index 054c842dd9d..6bcdb80f804 100644 --- a/components/esp_driver_spi/test_apps/spi/slave_hd/pytest_spi_slave_hd.py +++ b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - import pytest diff --git a/components/esp_driver_spi/test_apps/spi/slave_hd/sdkconfig.defaults b/components/esp_driver_spi/test_apps/slave_hd/sdkconfig.defaults similarity index 100% rename from components/esp_driver_spi/test_apps/spi/slave_hd/sdkconfig.defaults rename to components/esp_driver_spi/test_apps/slave_hd/sdkconfig.defaults diff --git a/components/idf_test/include/esp32/idf_performance_target.h b/components/idf_test/include/esp32/idf_performance_target.h index 9d53efd10c8..c222734ef4b 100644 --- a/components/idf_test/include/esp32/idf_performance_target.h +++ b/components/idf_test/include/esp32/idf_performance_target.h @@ -28,17 +28,6 @@ #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 90000 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1900000 -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 16*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 -#if !CONFIG_FREERTOS_SMP // IDF-5223 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 34 // TODO: IDF-5180 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 // TODO: IDF-5180 -#else -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 50 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 50 -#endif - // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/components/idf_test/include/esp32c2/idf_performance_target.h b/components/idf_test/include/esp32c2/idf_performance_target.h index 916caf4eca6..ecf20664e89 100644 --- a/components/idf_test/include/esp32c2/idf_performance_target.h +++ b/components/idf_test/include/esp32c2/idf_performance_target.h @@ -27,12 +27,6 @@ #define IDF_PERFORMANCE_MAX_ECDSA_P192_VERIFY_OP 32000 #define IDF_PERFORMANCE_MAX_ECDSA_P256_VERIFY_OP 49000 -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 23 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 18 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 47 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 42 - // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/components/idf_test/include/esp32c3/idf_performance_target.h b/components/idf_test/include/esp32c3/idf_performance_target.h index a59a6ab7c80..f7b04ca6638 100644 --- a/components/idf_test/include/esp32c3/idf_performance_target.h +++ b/components/idf_test/include/esp32c3/idf_performance_target.h @@ -20,23 +20,6 @@ #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 670000 -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 -#if !CONFIG_FREERTOS_SMP // IDF-5223 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 -#else -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 17 -#endif - -#if !CONFIG_FREERTOS_SMP // IDF-5223 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 -#else -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 60 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 60 -#endif - // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/components/idf_test/include/esp32c5/idf_performance_target.h b/components/idf_test/include/esp32c5/idf_performance_target.h index c6a6eb89791..dd3f635e549 100644 --- a/components/idf_test/include/esp32c5/idf_performance_target.h +++ b/components/idf_test/include/esp32c5/idf_performance_target.h @@ -5,9 +5,3 @@ */ #pragma once - -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 27 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 16 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 24 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 13 diff --git a/components/idf_test/include/esp32c6/idf_performance_target.h b/components/idf_test/include/esp32c6/idf_performance_target.h index 7fa8f6cd94f..5ca63dcaa48 100644 --- a/components/idf_test/include/esp32c6/idf_performance_target.h +++ b/components/idf_test/include/esp32c6/idf_performance_target.h @@ -17,12 +17,6 @@ #define IDF_PERFORMANCE_MAX_ECDSA_P192_VERIFY_OP 18000 #define IDF_PERFORMANCE_MAX_ECDSA_P256_VERIFY_OP 27000 -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 34 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 - #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 10 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 10 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 10 diff --git a/components/idf_test/include/esp32h2/idf_performance_target.h b/components/idf_test/include/esp32h2/idf_performance_target.h index aed083a057b..03517947609 100644 --- a/components/idf_test/include/esp32h2/idf_performance_target.h +++ b/components/idf_test/include/esp32h2/idf_performance_target.h @@ -28,12 +28,6 @@ #define IDF_PERFORMANCE_MAX_ECDSA_P192_VERIFY_OP 44000 #define IDF_PERFORMANCE_MAX_ECDSA_P256_VERIFY_OP 67000 -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 25 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 61 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 54 - // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/components/idf_test/include/esp32p4/idf_performance_target.h b/components/idf_test/include/esp32p4/idf_performance_target.h index d1efc6b4af3..ae02683c52f 100644 --- a/components/idf_test/include/esp32p4/idf_performance_target.h +++ b/components/idf_test/include/esp32p4/idf_performance_target.h @@ -4,13 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -//TODO: IDF-8313 update after chips back and PLL setup -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 10*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 1000 - /* Spinlock performance on esp32p4 is slower. May need to adjust these values once IDF-7898 is fixed */ #define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 380 #define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 135 diff --git a/components/idf_test/include/esp32s2/idf_performance_target.h b/components/idf_test/include/esp32s2/idf_performance_target.h index 51693fb76c8..07baf2ca51d 100644 --- a/components/idf_test/include/esp32s2/idf_performance_target.h +++ b/components/idf_test/include/esp32s2/idf_performance_target.h @@ -23,12 +23,6 @@ #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 62000 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1850000 -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 - #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 3 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 3 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 3 diff --git a/components/idf_test/include/esp32s3/idf_performance_target.h b/components/idf_test/include/esp32s3/idf_performance_target.h index f987259f76b..9f485b382c2 100644 --- a/components/idf_test/include/esp32s3/idf_performance_target.h +++ b/components/idf_test/include/esp32s3/idf_performance_target.h @@ -21,12 +21,6 @@ #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 80000 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 2500000 -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 - // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 From 9f34e4e9d91b45fc57f046bb90e43e47a8fcc40c Mon Sep 17 00:00:00 2001 From: Sumeet Singh Date: Thu, 15 Feb 2024 11:39:36 +0530 Subject: [PATCH 10/15] feat(nimble): read multiple variable length characteristics --- components/bt/host/nimble/nimble | 2 +- components/bt/host/nimble/port/include/esp_nimble_cfg.h | 4 ++++ components/bt/porting/nimble/include/nimble/nimble_opt_auto.h | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index f5459aae80f..f710ba9e81b 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit f5459aae80fe0ee7ea2b8387e8b6f9d6b556ca2c +Subproject commit f710ba9e81be20dbb7083282c6e280edf9c8dc02 diff --git a/components/bt/host/nimble/port/include/esp_nimble_cfg.h b/components/bt/host/nimble/port/include/esp_nimble_cfg.h index d837d17ec14..3da9d557d8e 100644 --- a/components/bt/host/nimble/port/include/esp_nimble_cfg.h +++ b/components/bt/host/nimble/port/include/esp_nimble_cfg.h @@ -610,6 +610,10 @@ #define MYNEWT_VAL_BLE_GATT_READ_MULT (MYNEWT_VAL_BLE_ROLE_CENTRAL) #endif +#ifndef MYNEWT_VAL_BLE_GATT_READ_MULT_VAR +#define MYNEWT_VAL_BLE_GATT_READ_MULT_VAR (MYNEWT_VAL_BLE_ROLE_CENTRAL) +#endif + #ifndef MYNEWT_VAL_BLE_GATT_READ_UUID #define MYNEWT_VAL_BLE_GATT_READ_UUID (MYNEWT_VAL_BLE_ROLE_CENTRAL) #endif diff --git a/components/bt/porting/nimble/include/nimble/nimble_opt_auto.h b/components/bt/porting/nimble/include/nimble/nimble_opt_auto.h index daf21533486..c4baec843be 100644 --- a/components/bt/porting/nimble/include/nimble/nimble_opt_auto.h +++ b/components/bt/porting/nimble/include/nimble/nimble_opt_auto.h @@ -84,6 +84,10 @@ extern "C" { #define NIMBLE_BLE_ATT_CLT_READ_MULT \ (MYNEWT_VAL(BLE_GATT_READ_MULT)) +#undef NIMBLE_BLE_ATT_CLT_READ_MULT_VAR +#define NIMBLE_BLE_ATT_CLT_READ_MULT_VAR \ + (MYNEWT_VAL(BLE_GATT_READ_MULT_VAR)) + #undef NIMBLE_BLE_ATT_CLT_READ_GROUP_TYPE #define NIMBLE_BLE_ATT_CLT_READ_GROUP_TYPE \ (MYNEWT_VAL(BLE_GATT_DISC_ALL_SVCS)) From 508d9a6a227b718598bcf5c026279dd6377d31a6 Mon Sep 17 00:00:00 2001 From: "radek.tandler" Date: Thu, 7 Mar 2024 11:30:35 +0100 Subject: [PATCH 11/15] fix(nvs): Fixed Page::findItem performance degradation Wrong condition gating the hash map use causing performance degradation was corrected The condition enabling use of hash map when page is searched for Item was modified to correct the bug introduced by commit addressing delete of any BLOB_INDEX Items. This correction returns the performance of findItem to the state before previous change. --- components/nvs_flash/src/nvs_page.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/nvs_flash/src/nvs_page.cpp b/components/nvs_flash/src/nvs_page.cpp index f6ae0ed2f46..c06ea202dfd 100644 --- a/components/nvs_flash/src/nvs_page.cpp +++ b/components/nvs_flash/src/nvs_page.cpp @@ -882,7 +882,7 @@ esp_err_t Page::findItem(uint8_t nsIndex, ItemType datatype, const char* key, si // For BLOB_DATA, we may need to search for all chunk indexes, so the hash list won't help // mHashIndex caluclates hash from nsIndex, key, chunkIdx // We may not use mHashList if datatype is BLOB_DATA and chunkIdx is CHUNK_ANY as CHUNK_ANY is used by BLOB_INDEX - if (nsIndex != NS_ANY && key != NULL && (datatype == ItemType::BLOB_DATA && chunkIdx != CHUNK_ANY)) { + if (nsIndex != NS_ANY && key != NULL && (datatype != ItemType::BLOB_DATA || chunkIdx != CHUNK_ANY)) { size_t cachedIndex = mHashList.find(start, Item(nsIndex, datatype, 0, key, chunkIdx)); if (cachedIndex < ENTRY_COUNT) { start = cachedIndex; From 881782f83d2e5974f2ab6bf0df4ca15581619484 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 5 Mar 2024 16:16:46 +0800 Subject: [PATCH 12/15] feat(esp32c5mp): add soc files part 2 --- .../beta3/include/soc/Kconfig.soc_caps.in | 4 +- .../soc/esp32c5/beta3/include/soc/soc_caps.h | 2 +- components/soc/esp32c5/mp/gpio_periph.c | 75 +++ .../mp/include/soc/Kconfig.soc_caps.in | 312 ++++++++++ .../soc/esp32c5/mp/include/soc/clic_reg.h | 108 ++++ .../soc/esp32c5/mp/include/soc/clint_reg.h | 76 +++ .../esp32c5/mp/include/soc/clk_tree_defs.h | 515 ++++++++++++++++ .../soc/esp32c5/mp/include/soc/dport_access.h | 108 ++++ .../soc/esp32c5/mp/include/soc/ext_mem_defs.h | 133 +++++ .../soc/esp32c5/mp/include/soc/gpio_num.h | 52 ++ .../soc/esp32c5/mp/include/soc/gpio_pins.h | 19 + .../esp32c5/mp/include/soc/i2c_ana_mst_reg.h | 220 +++++++ .../esp32c5/mp/include/soc/interrupt_reg.h | 11 + components/soc/esp32c5/mp/include/soc/mmu.h | 33 ++ .../soc/esp32c5/mp/include/soc/periph_defs.h | 86 +++ .../soc/esp32c5/mp/include/soc/regi2c_bbpll.h | 175 ++++++ .../soc/esp32c5/mp/include/soc/regi2c_defs.h | 29 + .../esp32c5/mp/include/soc/regi2c_dig_reg.h | 64 ++ .../esp32c5/mp/include/soc/reset_reasons.h | 57 ++ .../soc/esp32c5/mp/include/soc/rtc_io_reg.h | 8 + .../esp32c5/mp/include/soc/rtc_io_struct.h | 19 + components/soc/esp32c5/mp/include/soc/soc.h | 243 ++++++++ .../soc/esp32c5/mp/include/soc/soc_caps.h | 561 ++++++++++++++++++ .../soc/esp32c5/mp/include/soc/soc_pins.h | 16 + .../soc/esp32c5/mp/include/soc/spi_pins.h | 25 + .../soc/esp32c5/mp/include/soc/system_reg.h | 12 + .../soc/esp32c5/mp/include/soc/uart_channel.h | 20 + .../soc/esp32c5/mp/include/soc/uart_pins.h | 48 ++ .../soc/esp32c5/mp/include/soc/wdev_reg.h | 13 + components/soc/esp32c5/mp/interrupts.c | 90 +++ components/soc/esp32c5/mp/uart_periph.c | 114 ++++ 31 files changed, 3245 insertions(+), 3 deletions(-) create mode 100644 components/soc/esp32c5/mp/include/soc/clic_reg.h create mode 100644 components/soc/esp32c5/mp/include/soc/clint_reg.h create mode 100644 components/soc/esp32c5/mp/include/soc/clk_tree_defs.h create mode 100644 components/soc/esp32c5/mp/include/soc/dport_access.h create mode 100644 components/soc/esp32c5/mp/include/soc/ext_mem_defs.h create mode 100644 components/soc/esp32c5/mp/include/soc/gpio_num.h create mode 100644 components/soc/esp32c5/mp/include/soc/gpio_pins.h create mode 100644 components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h create mode 100644 components/soc/esp32c5/mp/include/soc/interrupt_reg.h create mode 100644 components/soc/esp32c5/mp/include/soc/mmu.h create mode 100644 components/soc/esp32c5/mp/include/soc/periph_defs.h create mode 100644 components/soc/esp32c5/mp/include/soc/regi2c_bbpll.h create mode 100644 components/soc/esp32c5/mp/include/soc/regi2c_defs.h create mode 100644 components/soc/esp32c5/mp/include/soc/regi2c_dig_reg.h create mode 100644 components/soc/esp32c5/mp/include/soc/reset_reasons.h create mode 100644 components/soc/esp32c5/mp/include/soc/rtc_io_reg.h create mode 100644 components/soc/esp32c5/mp/include/soc/rtc_io_struct.h create mode 100644 components/soc/esp32c5/mp/include/soc/soc.h create mode 100644 components/soc/esp32c5/mp/include/soc/soc_pins.h create mode 100644 components/soc/esp32c5/mp/include/soc/spi_pins.h create mode 100644 components/soc/esp32c5/mp/include/soc/system_reg.h create mode 100644 components/soc/esp32c5/mp/include/soc/uart_channel.h create mode 100644 components/soc/esp32c5/mp/include/soc/uart_pins.h create mode 100644 components/soc/esp32c5/mp/include/soc/wdev_reg.h diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in index c74b0d8ce45..1266c4d2a8c 100644 --- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -200,8 +200,8 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP default y config SOC_RTCIO_PIN_COUNT - bool - default n + int + default 0 config SOC_I2C_NUM int diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h index 28b1b67bb7d..d90e3693876 100644 --- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -215,7 +215,7 @@ // #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) /*-------------------------- RTCIO CAPS --------------------------------------*/ -#define SOC_RTCIO_PIN_COUNT 0 +#define SOC_RTCIO_PIN_COUNT 0UL // #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, // * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.) // * when the pins are switched to RTC function. diff --git a/components/soc/esp32c5/mp/gpio_periph.c b/components/soc/esp32c5/mp/gpio_periph.c index e69de29bb2d..bd23783dd96 100644 --- a/components/soc/esp32c5/mp/gpio_periph.c +++ b/components/soc/esp32c5/mp/gpio_periph.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_periph.h" + +const uint32_t GPIO_PIN_MUX_REG[] = { + IO_MUX_GPIO0_REG, + IO_MUX_GPIO1_REG, + IO_MUX_GPIO2_REG, + IO_MUX_GPIO3_REG, + IO_MUX_GPIO4_REG, + IO_MUX_GPIO5_REG, + IO_MUX_GPIO6_REG, + IO_MUX_GPIO7_REG, + IO_MUX_GPIO8_REG, + IO_MUX_GPIO9_REG, + IO_MUX_GPIO10_REG, + IO_MUX_GPIO11_REG, + IO_MUX_GPIO12_REG, + IO_MUX_GPIO13_REG, + IO_MUX_GPIO14_REG, + IO_MUX_GPIO15_REG, + IO_MUX_GPIO16_REG, + IO_MUX_GPIO17_REG, + IO_MUX_GPIO18_REG, + IO_MUX_GPIO19_REG, + IO_MUX_GPIO20_REG, + IO_MUX_GPIO21_REG, + IO_MUX_GPIO22_REG, + IO_MUX_GPIO23_REG, + IO_MUX_GPIO24_REG, + IO_MUX_GPIO25_REG, + IO_MUX_GPIO26_REG, + IO_MUX_GPIO27_REG, + IO_MUX_GPIO28_REG, +}; + +_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); + +const uint32_t GPIO_HOLD_MASK[] = { + BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(6), //GPIO6 + BIT(7), //GPIO7 + BIT(8), //GPIO8 + BIT(9), //GPIO9 + BIT(10), //GPIO10 + BIT(11), //GPIO11 + BIT(12), //GPIO12 + BIT(13), //GPIO13 + BIT(14), //GPIO14 + BIT(15), //GPIO15 + BIT(16), //GPIO16 + BIT(17), //GPIO17 + BIT(18), //GPIO18 + BIT(19), //GPIO19 + BIT(20), //GPIO20 + BIT(21), //GPIO21 + BIT(22), //GPIO22 + BIT(23), //GPIO23 + BIT(24), //GPIO24 + BIT(25), //GPIO25 + BIT(26), //GPIO26 + BIT(27), //GPIO27 + BIT(28), //GPIO28 +}; + +_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in index 51b3aa0d109..e11a8f94bb9 100644 --- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in @@ -2,3 +2,315 @@ # This file is auto-generated from SoC caps # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### + +config SOC_UART_SUPPORTED + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_EFUSE_SUPPORTED + bool + default y + +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_SPI_FLASH_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_40M + bool + default y + +config SOC_XTAL_SUPPORT_48M + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 1 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 7 + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CACHE_FREEZE_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_CLIC_SUPPORTED + bool + default y + +config SOC_INT_HW_NESTED_SUPPORTED + bool + default y + +config SOC_BRANCH_PREDICTOR_SUPPORTED + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE + hex + default 0x100 + +config SOC_CPU_HAS_PMA + bool + default y + +config SOC_CPU_IDRAM_SPLIT_USING_PMP + bool + default y + +config SOC_GPIO_PIN_COUNT + int + default 29 + +config SOC_GPIO_IN_RANGE_MAX + int + default 30 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 30 + +config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + bool + default y + +config SOC_RTCIO_PIN_COUNT + int + default 0 + +config SOC_I2C_NUM + int + default 1 + +config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_CHANNEL_NUM + int + default 6 + +config SOC_MMU_PERIPH_NUM + int + default 1 + +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 1 + +config SOC_MMU_DI_VADDR_SHARED + bool + default y + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_SUPPORT_RC_FAST + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 64 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_UART_NUM + int + default 3 + +config SOC_UART_HP_NUM + int + default 2 + +config SOC_UART_LP_NUM + int + default 1 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_LP_UART_FIFO_LEN + int + default 16 + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + +config SOC_PM_SUPPORT_VDDSDIO_PD + bool + default y + +config SOC_PM_SUPPORT_TOP_PD + bool + default y + +config SOC_PM_SUPPORT_HP_AON_PD + bool + default y + +config SOC_PM_SUPPORT_RTC_PERIPH_PD + bool + default y + +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + +config SOC_CLK_OSC_SLOW_SUPPORTED + bool + default y + +config SOC_CLK_RC32K_SUPPORTED + bool + default y + +config SOC_RCC_IS_INDEPENDENT + bool + default y diff --git a/components/soc/esp32c5/mp/include/soc/clic_reg.h b/components/soc/esp32c5/mp/include/soc/clic_reg.h new file mode 100644 index 00000000000..324cfd8c8ab --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/clic_reg.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define NLBITS 3 +#define CLIC_EXT_INTR_NUM_OFFSET 16 +#define DUALCORE_CLIC_CTRL_OFF 0x10000 + +#define DR_REG_CLIC_BASE ( 0x20800000 ) +#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 ) + +#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0) +/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NMBITS 0x00000003 +#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S)) +#define CLIC_INT_CONFIG_NMBITS_V 0x3 +#define CLIC_INT_CONFIG_NMBITS_S 5 +/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NLBITS 0x0000000F +#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S)) +#define CLIC_INT_CONFIG_NLBITS_V 0xF +#define CLIC_INT_CONFIG_NLBITS_S 1 +/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: .*/ +#define CLIC_INT_CONFIG_NVBITS (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_M (BIT(0)) +#define CLIC_INT_CONFIG_NVBITS_V 0x1 +#define CLIC_INT_CONFIG_NVBITS_S 0 + +#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4) +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_CTLBITS 0x0000000F +#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S)) +#define CLIC_INT_INFO_CTLBITS_V 0xF +#define CLIC_INT_INFO_CTLBITS_S 21 +/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_VERSION 0x000000FF +#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S)) +#define CLIC_INT_INFO_VERSION_V 0xFF +#define CLIC_INT_INFO_VERSION_S 13 +/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */ +/*description: .*/ +#define CLIC_INT_INFO_NUM_INT 0x00001FFF +#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S)) +#define CLIC_INT_INFO_NUM_INT_V 0x1FFF +#define CLIC_INT_INFO_NUM_INT_S 0 + +#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8) +/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_CPU_INT_THRESH 0x000000FF +#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S)) +#define CLIC_CPU_INT_THRESH_V 0xFF +#define CLIC_CPU_INT_THRESH_S 24 + +#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4) +/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: .*/ +#define CLIC_INT_CTL 0x000000FF +#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S)) +#define CLIC_INT_CTL_V 0xFF +#define CLIC_INT_CTL_S 24 +/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_MODE 0x00000003 +#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S)) +#define CLIC_INT_ATTR_MODE_V 0x3 +#define CLIC_INT_ATTR_MODE_S 22 +/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_TRIG 0x00000003 +#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S)) +#define CLIC_INT_ATTR_TRIG_V 0x3 +#define CLIC_INT_ATTR_TRIG_S 17 +/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_ATTR_SHV (BIT(16)) +#define CLIC_INT_ATTR_SHV_M (BIT(16)) +#define CLIC_INT_ATTR_SHV_V 0x1 +#define CLIC_INT_ATTR_SHV_S 16 +/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IE (BIT(8)) +#define CLIC_INT_IE_M (BIT(8)) +#define CLIC_INT_IE_V 0x1 +#define CLIC_INT_IE_S 8 +/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define CLIC_INT_IP (BIT(0)) +#define CLIC_INT_IP_M (BIT(0)) +#define CLIC_INT_IP_V 0x1 +#define CLIC_INT_IP_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/clint_reg.h b/components/soc/esp32c5/mp/include/soc/clint_reg.h new file mode 100644 index 00000000000..7fa9daf2ed3 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/clint_reg.h @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/*CLINT MINT*/ +#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0) +/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_SIP BIT(0) +#define CLINT_CPU_MINT_SIP_M BIT(0) +#define CLINT_CPU_MINT_SIP_V 1 +#define CLINT_CPU_MINT_SIP_S 0 + +#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000) +/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S)) +#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_S 0 + +#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004) +/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S)) +#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_S 0 + +#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010) +/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: .*/ +#define CLINT_MINT_SAMPLING_MODE 0x00000003 +#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S)) +#define CLINT_MINT_SAMPLING_MODE_V 0x3 +#define CLINT_MINT_SAMPLING_MODE_S 4 +/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1 +#define CLINT_MINT_COUNTER_OVERFLOW_S 3 +/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_EN (BIT(0)) +#define CLINT_MINT_COUNTER_EN_M (BIT(0)) +#define CLINT_MINT_COUNTER_EN_V 0x1 +#define CLINT_MINT_COUNTER_EN_S 0 + +#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8) +/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S)) +#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_S 0 + +#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC) +/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S)) +#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h b/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h new file mode 100644 index 00000000000..f780ca4af11 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h @@ -0,0 +1,515 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ************************* ESP32C5 Root Clock Source **************************** + * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) + * + * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + * + * 2) External 40/48MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) Internal 32kHz RC Oscillator: RC32K + * + * The exact frequency of this clock can be computed in runtime through calibration. + * + * 5) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + * + * 6) External Slow Clock (optional): OSC_SLOW + * + * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the + * RTC_SLOW_CLK. + * + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + */ + +// TODO: [ESP32C5] IDF-8642 (inherit from C6) +/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ + +// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] +// {loc}: EXT, INT +// {type}: XTAL, RC +// [attr] - optional: [frequency], FAST, SLOW +/** + * @brief Root clock + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ + SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ + SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ +} soc_root_clk_t; + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL_F160M = 2, /*!< Select PLL_F160M_CLK as CPU_CLK source (PLL_F160M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ + SOC_CPU_CLK_SRC_PLL_F240M = 3, /*!< Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ + SOC_CPU_CLK_SRC_PLL = SOC_CPU_CLK_SRC_PLL_F240M, // TODO: [IDF-8642] remove this alias + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_XTAL = 2, /*!< Select XTAL_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ +} soc_rtc_fast_clk_src_t; + +/** + * @brief Possible main XTAL frequency options on the target + * @note Enum values equal to the frequency value in MHz + * @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for + * the supported ones. + */ +typedef enum { + SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */ + SOC_XTAL_FREQ_48M = 48, /*!< 48MHz XTAL */ +} soc_xtal_freq_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_SPLL, /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ + // For LP peripherals + SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */ + + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// + +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6) + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M/*, SOC_MOD_CLK_RC_FAST*/, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { + GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { + TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ +} soc_periph_tg_clk_src_legacy_t; + +//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of RMT + */ +#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of RMT clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6) + RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ +} soc_periph_rmt_clk_src_t; + +/** + * @brief Type of RMT clock source, reserved for the legacy RMT driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6) + RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */ + RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */ +} soc_periph_rmt_clk_src_legacy_t; + +//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Temperature Sensor + */ +#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of Temp Sensor clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8727 (inherit from C6) + TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +} soc_periph_temperature_sensor_clk_src_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8722 (inherit from C6) + UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ +} soc_periph_uart_clk_src_legacy_t; + +/** + * @brief Type of LP_UART clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6) + LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */ + LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ + LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */ +} soc_periph_lp_uart_clk_src_t; + +//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MCPWM Timer + */ +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM timer clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_timer_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Capture Timer + */ +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM capture clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_capture_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Carrier + */ +#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of MCPWM carrier clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6) + MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ +} soc_periph_mcpwm_carrier_clk_src_t; + +///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2S + */ +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} + +/** + * @brief I2S clock source enum + */ +typedef enum { // TODO: [ESP32C5] IDF-8713 (inherit from C6) + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ + I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ +} soc_periph_i2s_clk_src_t; + +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2C + */ +#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of I2C clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8694, IDF-8696 (inherit from C6) + I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ +} soc_periph_i2c_clk_src_t; + +///////////////////////////////////////////////LP_I2C/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LP_I2C + */ +#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} + +/** + * @brief Type of LP_I2C clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6) + LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */ + LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */ + LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */ +} soc_periph_lp_i2c_clk_src_t; + +/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SPI + */ +#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of SPI clock source. + */ +typedef enum { // TODO: [ESP32C5] IDF-8698, IDF-8699 (inherit from C6) + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ +} soc_periph_spi_clk_src_t; + +//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SDM + */ +#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Sigma Delta Modulator clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8687 (inherit from C6) + SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_sdm_clk_src_t; + +//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Glitch Filter + */ +#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} + +/** + * @brief Glitch filter clock source + */ + +typedef enum { // TODO: [ESP32C5] IDF-8718 (inherit from C6) + GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ +} soc_periph_glitch_filter_clk_src_t; + +//////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of TWAI + */ +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} + +/** + * @brief TWAI clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6) + TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +} soc_periph_twai_clk_src_t; + +//////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of ADC digital controller + */ +#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief ADC digital controller clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6) + ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ +} soc_periph_adc_digi_clk_src_t; + +//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MWDT + */ +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief MWDT clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8650 (inherit from C6) + MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ + MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */ +} soc_periph_mwdt_clk_src_t; + +//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of LEDC + */ +#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of LEDC clock source, reserved for the legacy LEDC driver + */ +typedef enum { // TODO: [ESP32C5] IDF-8684 (inherit from C6) + LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ + LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + + LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ +} soc_periph_ledc_clk_src_legacy_t; + +//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of PARLIO + */ +#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M} + +/** + * @brief PARLIO clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6) + PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ + PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ +} soc_periph_parlio_clk_src_t; + +//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// +/** + * @brief Array initializer for all supported clock sources of MSPI digital controller + */ +#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL} +/** + * @brief MSPI digital controller clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8649 + MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */ + MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ +} soc_periph_mspi_clk_src_t; + +//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// +typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) + CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ + CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ + CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */ + CLKOUT_SIG_CPU = 16, /*!< CPU clock */ + CLKOUT_SIG_AHB = 17, /*!< AHB clock */ + CLKOUT_SIG_APB = 18, /*!< APB clock */ + CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ + CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ + CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ + CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ + CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ + CLKOUT_SIG_INVALID = 0xFF, +} soc_clkout_sig_id_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/dport_access.h b/components/soc/esp32c5/mp/include/soc/dport_access.h new file mode 100644 index 00000000000..fc00e87e1ce --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/dport_access.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/ext_mem_defs.h b/components/soc/esp32c5/mp/include/soc/ext_mem_defs.h new file mode 100644 index 00000000000..4438de09f64 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/ext_mem_defs.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + + +#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) + +#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range +#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range + +#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW +#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH + +#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW +#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH + +#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr) +#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr) +#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr) +#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr) + +#define SOC_MMU_ACCESS_FLASH 0 +#define SOC_MMU_ACCESS_SPIRAM BIT(9) +#define SOC_MMU_VALID BIT(10) +#define SOC_MMU_SENSITIVE BIT(11) +#define SOC_MMU_INVALID_MASK BIT(10) +#define SOC_MMU_INVALID 0 + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define SOC_MMU_VALID_VAL_MASK (SOC_MMU_ACCESS_SPIRAM-1) +/** + * Max MMU available paddr page num. + * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define SOC_MMU_MAX_PADDR_PAGE_NUM 512 +//MMU entry num +#define SOC_MMU_ENTRY_NUM 512 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & SOC_MMU_VADDR_MASK + */ +#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1) + +#define SOC_MMU_DBUS_VADDR_BASE 0x42000000 +#define SOC_MMU_IBUS_VADDR_BASE 0x42000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 512 MMU entries, needs 0x1FF to hold it. + * + * Therefore, 0x1FF,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF + +/** + * - If high linear address isn't 0, this means MMU can recognize these addresses + * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range. + * Under this condition, we use the max linear space. + */ +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +/** + * I/D share the MMU linear address range + */ +#ifndef __cplusplus +_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); +#endif + + +/** + * ROM flash mmap driver needs below definitions + */ +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x400 + +#define ICACHE_MMU_SIZE 0x200 +#define DCACHE_MMU_SIZE 0x200 + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) 0x200 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/gpio_num.h b/components/soc/esp32c5/mp/include/soc/gpio_num.h new file mode 100644 index 00000000000..a18acca7da6 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/gpio_num.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO number + */ +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_MAX, +} gpio_num_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/gpio_pins.h b/components/soc/esp32c5/mp/include/soc/gpio_pins.h new file mode 100644 index 00000000000..c630ae47649 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/gpio_pins.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h new file mode 100644 index 00000000000..4089e68b3e0 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) +/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_V 0x1 +#define I2C_ANA_MST_I2C0_BUSY_S 25 +/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_S 0 + +#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) +/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_V 0x1 +#define I2C_ANA_MST_I2C1_BUSY_S 25 +/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_S 0 + +#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) +/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_STATUS 0x000000FF +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_V 0xFF +#define I2C_ANA_MST_I2C0_STATUS_S 24 +/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C0_CONF_S 0 + +#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) +/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_STATUS 0x000000FF +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_V 0xFF +#define I2C_ANA_MST_I2C1_STATUS_S 24 +/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C1_CONF_S 0 + +#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) +/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF +#define I2C_ANA_MST_BURST_CTRL_S 0 + +#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) +/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 +/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) +#define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) +#define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 +/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) +#define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) +#define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 +/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_DONE (BIT(0)) +#define I2C_ANA_MST_BURST_DONE_M (BIT(0)) +#define I2C_ANA_MST_BURST_DONE_V 0x1 +#define I2C_ANA_MST_BURST_DONE_S 0 + +#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) +/* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS0 0x000000FF +#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S)) +#define I2C_ANA_MST_ANA_STATUS0_V 0xFF +#define I2C_ANA_MST_ANA_STATUS0_S 24 +/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) +#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF0_S 0 + +#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) +/* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS1 0x000000FF +#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) +#define I2C_ANA_MST_ANA_STATUS1_V 0xFF +#define I2C_ANA_MST_ANA_STATUS1_S 24 +/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) +#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF1_S 0 + +#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) +/* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS2 0x000000FF +#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S)) +#define I2C_ANA_MST_ANA_STATUS2_V 0xFF +#define I2C_ANA_MST_ANA_STATUS2_S 24 +/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S)) +#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF2_S 0 + +#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) +/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 +/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) +/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 +/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) +/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ARBITER_DIS (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_V 0x1 +#define I2C_ANA_MST_ARBITER_DIS_S 11 +/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) +/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_NOUSE 0xFFFFFFFF +#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF +#define I2C_ANA_MST_NOUSE_S 0 + +#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) +/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_CLK_EN (BIT(28)) +#define I2C_ANA_MST_CLK_EN_M (BIT(28)) +#define I2C_ANA_MST_CLK_EN_V 0x1 +#define I2C_ANA_MST_CLK_EN_S 28 +/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/*description: .*/ +#define I2C_ANA_MST_DATE 0x0FFFFFFF +#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_V 0xFFFFFFF +#define I2C_ANA_MST_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/interrupt_reg.h b/components/soc/esp32c5/mp/include/soc/interrupt_reg.h new file mode 100644 index 00000000000..659b7b8536b --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/interrupt_reg.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/clic_reg.h" +#include "soc/soc_caps.h" + +#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG) +#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF) diff --git a/components/soc/esp32c5/mp/include/soc/mmu.h b/components/soc/esp32c5/mp/include/soc/mmu.h new file mode 100644 index 00000000000..5660077bbae --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/mmu.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/ext_mem_defs.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 1 +#define SOC_MMU_PAGES_PER_REGION 256 +#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK (SOC_MMU_VALID - 1) +#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash +#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM0_CACHE_ADDRESS_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START +#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/periph_defs.h b/components/soc/esp32c5/mp/include/soc/periph_defs.h new file mode 100644 index 00000000000..b438aee3f3e --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/periph_defs.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/interrupts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5-PERIPH] (inherit from C6) + +typedef enum { + /* HP peripherals */ + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, // USB Serial Jtag + PERIPH_I2C_MODULE, + PERIPH_I2S_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_MSPI0_MODULE, //SPI0 + PERIPH_MSPI1_MODULE, //SPI1 + PERIPH_GPSPI2_MODULE, //SPI2 + PERIPH_TWAI0_MODULE, + PERIPH_TWAI1_MODULE, + PERIPH_RNG_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_ECC_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_MCPWM0_MODULE, + PERIPH_ETM_MODULE, + PERIPH_PARLIO_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_TEMPSENSOR_MODULE, + PERIPH_ASSIST_DEBUG_MODULE, + PERIPH_INT_MATRIX_MODULE, + PERIPH_PVT_MONITOR_MODULE, + PERIPH_BITSCRAMBLER_MODULE, + PERIPH_KEY_MANAGE_MODULE, + PERIPH_ECDSA_MODULE, + PERIPH_MEM_MONITOR_MODULE, + PERIPH_TEE_MODULE, + PERIPH_HP_APM_MODULE, + /* LP peripherals */ + PERIPH_LP_I2C0_MODULE, + PERIPH_LP_UART0_MODULE, + PERIPH_LP_TEE_MODULE, + PERIPH_LP_APM_MODULE, + PERIPH_LP_ANA_PERI_MODULE, + PERIPH_LP_PERI_MODULE, + PERIPH_HUK_MODULE, + PERIPH_OTP_DEBUG_MODULE, + /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, + PERIPH_ANA_I2C_MASTER_MODULE, + PERIPH_MODEM_ETM_MODULE, + PERIPH_MODEM_ADC_COMMON_FE_MODULE, + PERIPH_MODULE_MAX + /* !!! Don't append soc modules here !!! */ +} periph_module_t; + +#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/regi2c_bbpll.h b/components/soc/esp32c5/mp/include/soc/regi2c_bbpll.h new file mode 100644 index 00000000000..e698a4b530c --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/regi2c_bbpll.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_OC_VCO_DBIAS 9 +#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1 +#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 diff --git a/components/soc/esp32c5/mp/include/soc/regi2c_defs.h b/components/soc/esp32c5/mp/include/soc/regi2c_defs.h new file mode 100644 index 00000000000..0cfa9d75a06 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/regi2c_defs.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +/* Analog function control register */ +#define I2C_MST_ANA_CONF0_REG 0x600AF818 +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) + + +#define ANA_CONFIG_REG 0x600AF81C +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + + +#define ANA_CONFIG2_REG 0x600AF820 +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) diff --git a/components/soc/esp32c5/mp/include/soc/regi2c_dig_reg.h b/components/soc/esp32c5/mp/include/soc/regi2c_dig_reg.h new file mode 100644 index 00000000000..16b1ebd10a1 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/regi2c_dig_reg.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_dig_reg.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_DIG_REG 0x6D +#define I2C_DIG_REG_HOSTID 0 + +#define I2C_DIG_REG_EXT_RTC_DREG 4 +#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_RTC_DREG 4 +#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_RTC_DREG 5 +#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG 6 +#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_DIG_DREG 6 +#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_DIG_DREG 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_OR_EN_CONT_CAL 9 +#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7 +#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7 + +#define I2C_DIG_REG_XPD_RTC_REG 13 +#define I2C_DIG_REG_XPD_RTC_REG_MSB 2 +#define I2C_DIG_REG_XPD_RTC_REG_LSB 2 + +#define I2C_DIG_REG_XPD_DIG_REG 13 +#define I2C_DIG_REG_XPD_DIG_REG_MSB 3 +#define I2C_DIG_REG_XPD_DIG_REG_LSB 3 + +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32c5/mp/include/soc/reset_reasons.h b/components/soc/esp32c5/mp/include/soc/reset_reasons.h new file mode 100644 index 00000000000..7f221eaf8c2 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/reset_reasons.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + + +// TODO: [ESP32C5] IDF-8660 Check reset reasons for MP version +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system) + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system) + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system) + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system) + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system) + RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system) + RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system) + RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 + RESET_REASON_CORE_PWR_GLITCH = 0x19, // Glitch on power resets the digital core and rtc module + RESET_REASON_CPU0_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this) +} soc_reset_reason_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/rtc_io_reg.h b/components/soc/esp32c5/mp/include/soc/rtc_io_reg.h new file mode 100644 index 00000000000..0b46132b7f3 --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/rtc_io_reg.h @@ -0,0 +1,8 @@ +/** + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/lp_gpio_reg.h" diff --git a/components/soc/esp32c5/mp/include/soc/rtc_io_struct.h b/components/soc/esp32c5/mp/include/soc/rtc_io_struct.h new file mode 100644 index 00000000000..f265383d20b --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/rtc_io_struct.h @@ -0,0 +1,19 @@ +/** + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/lp_gpio_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef lp_gpio_dev_t rtc_io_dev_t; +#define RTCIO LP_GPIO + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/soc.h b/components/soc/esp32c5/mp/include/soc/soc.h new file mode 100644 index 00000000000..3cf20c4c3ac --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/soc.h @@ -0,0 +1,243 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +#define REG_UHCI_BASE(i) (DR_REG_UHCI_BASE) // only one UHCI on C5 +#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5 +#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 +#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 +#define REG_SPI_BASE(i) (DR_REG_GPSPI2_BASE) // only one GPSPI on C5 +#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5 +#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5 +#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define EFUSE_CLK_FREQ_ROM ( 20*1000000) +#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ ( 40*1000000 ) +#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) +#define REF_CLK_FREQ ( 1000000 ) +#define XTAL_CLK_FREQ (40*1000000) +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x44000000 +#define SOC_EXTRAM_DATA_LOW 0x42000000 +#define SOC_EXTRAM_DATA_HIGH 0x44000000 +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40040000 +#define SOC_DROM_MASK_LOW 0x40000000 +#define SOC_DROM_MASK_HIGH 0x40040000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40860000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40860000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C5 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50004000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50004000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50004000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40860000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40860000 + +#define MAP_DRAM_TO_IRAM(addr) (addr) +#define MAP_IRAM_TO_DRAM(addr) (addr) + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40860000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40860000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40860000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40860000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IROM_HIGH - SOC_IROM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// Debug region, not used by software +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4085c8d0 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated + +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index 972389e04d9..b8902be3d6b 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -3,3 +3,564 @@ * * SPDX-License-Identifier: Apache-2.0 */ + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725 +#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722 +// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 +// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 +// #define SOC_GPTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8705 +// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683 +// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709 +// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 +// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693 +// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686 +// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: [ESP32C5] IDF-8716 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727 +// #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32C5] IDF-8622, IDF-8674 +// #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8637 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32C5] IDF-8674, need check +#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8674 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 +// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 +// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726 +// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687 +// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8698, IDF-8699 +// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684 +// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696 +#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 +// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8624 +// #define SOC_RSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8620 +// #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616 +// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619 +// #define SOC_ECC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8625 +#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622 +// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623 +// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 +// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614 +// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 +// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 +// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 +// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 +// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719 +// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634 +// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633 +// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8642 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8663 +// #define SOC_WDT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8650 +#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32C5] IDF-8715 +// #define SOC_BITSCRAMBLER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8711 +// #define SOC_ECDSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8618 +// #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 +// #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_40M 1 +#define SOC_XTAL_SUPPORT_48M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +// #define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +// #define SOC_AES_GDMA (1) + +// #define SOC_AES_SUPPORT_AES_128 (1) +// #define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (1U) +// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) +#define SOC_ADC_MAX_CHANNEL_NUM (7) +// #define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +// #define SOC_ADC_DIGI_MAX_BITWIDTH (12) +// #define SOC_ADC_DIGI_MIN_BITWIDTH (12) +// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +// #define SOC_ADC_DIGI_MONITOR_NUM (2) +// #define SOC_ADC_DIGI_RESULT_BYTES (4) +// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ +// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +// #define SOC_ADC_RTC_MIN_BITWIDTH (12) +// #define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ + +/*!< Interrupt */ +// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) + +/*!< ADC power control is shared by PWDET */ +// #define SOC_ADC_SHARED_POWER 1 + +// ESP32C5-TODO: Copy from esp32C5, need check +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +// #define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +// #define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_CACHE_FREEZE_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_CLIC_SUPPORTED 1 +#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting +#define SOC_BRANCH_PREDICTOR_SUPPORTED 1 + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x100 // bytes + +#define SOC_CPU_HAS_PMA 1 +#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +// #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +// #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +// #define SOC_AHB_GDMA_VERSION 1U +// #define SOC_GDMA_NUM_GROUPS_MAX 1U +// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule + +/*-------------------------- ETM CAPS --------------------------------------*/ +// #define SOC_ETM_GROUPS 1U // Number of ETM groups +// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// TODO: [ESP32C5] IDF-8717 +// ESP32-C5 has 1 GPIO peripheral +// #define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 29 +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 +// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 + +// Target has the full LP IO subsystem +// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup +// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U< SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +// #define SOC_MEMSPI_IS_INDEPENDENT 1 +// #define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +// #define SOC_SPI_MEM_SUPPORT_WRAP (1) + +// TODO: [ESP32C5] IDF-8649 +#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +// TODO: [ESP32C5] IDF-8707 +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +// #define SOC_TIMER_SUPPORT_ETM (1) + +/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ +// #define SOC_MWDT_SUPPORT_XTAL (1) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +// #define SOC_TWAI_CONTROLLER_NUM 2 +// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 +// #define SOC_TWAI_BRP_MIN 2 +// #define SOC_TWAI_BRP_MAX 32768 +// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- eFuse CAPS----------------------------*/ +// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +// #define SOC_EFUSE_DIS_PAD_JTAG 1 +// #define SOC_EFUSE_DIS_USB_JTAG 1 +// #define SOC_EFUSE_DIS_DIRECT_BOOT 1 +// #define SOC_EFUSE_SOFT_DIS_JTAG 1 +// #define SOC_EFUSE_DIS_ICACHE 1 +// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block + +/*-------------------------- Secure Boot CAPS----------------------------*/ +// #define SOC_SECURE_BOOT_V2_RSA 1 +// #define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // TODO: [ESP32C5] IDF-8674 +// #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +// #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) // TODO: [ESP32C5] IDF-8622 +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 // TODO: [ESP32C5] IDF-8622 + +/*------------------------ Anti DPA (Security) CAPS --------------------------*/ +// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART) +#define SOC_UART_NUM (3) +#define SOC_UART_HP_NUM (2) +#define SOC_UART_LP_NUM (1U) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ +// #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +// #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ +// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +// #define SOC_COEX_HW_PTI (1) + +/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ +// #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +/*-------------------------- Power Management CAPS ----------------------------*/ +// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) +// #define SOC_PM_SUPPORT_BT_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) +// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! Date: Tue, 5 Mar 2024 10:42:12 +0530 Subject: [PATCH 13/15] fix(nimble): Exposed the baud rate for hci uart in menuconfig --- components/bt/host/nimble/Kconfig.in | 29 +++++++++++++++++++ .../host/nimble/port/include/esp_nimble_cfg.h | 4 +-- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index 1163d4d7974..a30b0f46fe4 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -942,9 +942,35 @@ menu "Host-controller Transport" help Uart port + choice BT_NIMBLE_HCI_USE_UART_BAUDRATE + prompt "Uart Hci Baud Rate" + default UART_BAUDRATE_921600 + depends on BT_CONTROLLER_DISABLED && BT_NIMBLE_TRANSPORT_UART + help + Uart Baud Rate + + config UART_BAUDRATE_115200 + bool "115200" + config UART_BAUDRATE_230400 + bool "230400" + config UART_BAUDRATE_460800 + bool "460800" + config UART_BAUDRATE_921600 + bool "921600" + endchoice + + config BT_NIMBLE_HCI_UART_BAUDRATE + depends on BT_CONTROLLER_DISABLED && BT_NIMBLE_TRANSPORT_UART + int + default 115200 if UART_BAUDRATE_115200 + default 230400 if UART_BAUDRATE_230400 + default 460800 if UART_BAUDRATE_460800 + default 921600 if UART_BAUDRATE_921600 + choice BT_NIMBLE_USE_HCI_UART_PARITY prompt "Uart PARITY" default UART_PARITY_NONE + depends on BT_CONTROLLER_DISABLED && BT_NIMBLE_TRANSPORT_UART help Uart Parity @@ -960,16 +986,19 @@ menu "Host-controller Transport" int default 0 if !UART_PARITY_NONE default 1 if UART_PARITY_NONE + depends on BT_CONTROLLER_DISABLED && BT_NIMBLE_TRANSPORT_UART config BT_NIMBLE_TRANSPORT_UART_PARITY_ODD int default 0 if !UART_PARITY_ODD default 1 if UART_PARITY_ODD + depends on BT_CONTROLLER_DISABLED && BT_NIMBLE_TRANSPORT_UART config BT_NIMBLE_TRANSPORT_UART_PARITY_EVEN int default 0 if !UART_PARITY_EVEN default 1 if UART_PARITY_EVEN + depends on BT_CONTROLLER_DISABLED && BT_NIMBLE_TRANSPORT_UART config BT_NIMBLE_UART_RX_PIN int "UART Rx pin" diff --git a/components/bt/host/nimble/port/include/esp_nimble_cfg.h b/components/bt/host/nimble/port/include/esp_nimble_cfg.h index d837d17ec14..90b38a43c25 100644 --- a/components/bt/host/nimble/port/include/esp_nimble_cfg.h +++ b/components/bt/host/nimble/port/include/esp_nimble_cfg.h @@ -1792,7 +1792,7 @@ #endif #endif -#if CONFIG_BT_CONTROLLER_DISABLED +#if CONFIG_BT_CONTROLLER_DISABLED && CONFIG_BT_NIMBLE_TRANSPORT_UART #ifndef MYNEWT_VAL_BLE_TRANSPORT_UART_PORT #define MYNEWT_VAL_BLE_TRANSPORT_UART_PORT CONFIG_BT_NIMBLE_TRANSPORT_UART_PORT #endif @@ -1814,7 +1814,7 @@ #endif #ifndef MYNEWT_VAL_BLE_TRANSPORT_UART_BAUDRATE -#define MYNEWT_VAL_BLE_TRANSPORT_UART_BAUDRATE (921600) +#define MYNEWT_VAL_BLE_TRANSPORT_UART_BAUDRATE CONFIG_BT_NIMBLE_HCI_UART_BAUDRATE #endif #ifndef MYNEWT_VAL_BLE_TRANSPORT_UART_DATA_BITS From 9046bf1645da1a8d49d7927b9836a6c380ec3e3c Mon Sep 17 00:00:00 2001 From: Omar Chebib Date: Fri, 1 Mar 2024 12:26:08 +0800 Subject: [PATCH 14/15] fix(espcoredump): Reconfigure the stack guard when using custom coredump stack --- .../port/riscv/esp_core_dump_port_impl.h | 5 ++++ components/espcoredump/src/core_dump_common.c | 26 ++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/components/espcoredump/include_core_dump/port/riscv/esp_core_dump_port_impl.h b/components/espcoredump/include_core_dump/port/riscv/esp_core_dump_port_impl.h index 4efcb065787..fa2db73afbb 100644 --- a/components/espcoredump/include_core_dump/port/riscv/esp_core_dump_port_impl.h +++ b/components/espcoredump/include_core_dump/port/riscv/esp_core_dump_port_impl.h @@ -11,6 +11,7 @@ * @brief Core dump port interface implementation for RISC-V. */ +#include "sdkconfig.h" #include "esp_core_dump_types.h" #include "esp_app_format.h" @@ -24,6 +25,10 @@ extern "C" { */ typedef struct { uint32_t sp; +#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD + uint32_t sp_min; + uint32_t sp_max; +#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD } core_dump_stack_context_t; /** diff --git a/components/espcoredump/src/core_dump_common.c b/components/espcoredump/src/core_dump_common.c index 2030ce4eae8..250db58d1e8 100644 --- a/components/espcoredump/src/core_dump_common.c +++ b/components/espcoredump/src/core_dump_common.c @@ -12,6 +12,9 @@ #include "esp_rom_sys.h" #include "esp_core_dump_port.h" #include "esp_core_dump_common.h" +#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD +#include "esp_private/hw_stack_guard.h" +#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD const static char TAG[] __attribute__((unused)) = "esp_core_dump_common"; @@ -71,12 +74,25 @@ FORCE_INLINE_ATTR void esp_core_dump_setup_stack(void) //esp_cpu_clear_watchpoint(1); //esp_cpu_set_watchpoint(1, s_coredump_stack, 1, ESP_WATCHPOINT_STORE); +#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD + /* Save the current area we are watching to restore it later */ + esp_hw_stack_guard_get_bounds(&s_stack_context.sp_min, &s_stack_context.sp_max); + /* Since the stack is going to change, make sure we disable protection or an exception would be triggered */ + esp_hw_stack_guard_monitor_stop(); +#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD + /* Replace the stack pointer depending on the architecture, but save the * current stack pointer, in order to be able too restore it later. * This function must be inlined. */ esp_core_dump_replace_sp(s_core_dump_sp, &s_stack_context); ESP_COREDUMP_LOGI("Backing up stack @ %p and use core dump stack @ %p", s_stack_context.sp, esp_cpu_get_sp()); + +#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD + /* Re-enable the stack guard to check if the stack is big enough for coredump generation */ + esp_hw_stack_guard_set_bounds((uint32_t) s_coredump_stack, (uint32_t) s_core_dump_sp); + esp_hw_stack_guard_monitor_start(); +#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD } /** @@ -110,10 +126,18 @@ FORCE_INLINE_ATTR void esp_core_dump_report_stack_usage(void) /* Restore the stack pointer. */ ESP_COREDUMP_LOGI("Restoring stack @ %p", s_stack_context.sp); +#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD + esp_hw_stack_guard_monitor_stop(); +#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD esp_core_dump_restore_sp(&s_stack_context); +#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD + /* Monitor the same stack area that was set before replacing the stack pointer */ + esp_hw_stack_guard_set_bounds(s_stack_context.sp_min, s_stack_context.sp_max); + esp_hw_stack_guard_monitor_start(); +#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD } -#else // CONFIG_ESP_COREDUMP_STACK_SIZE > 0 +#else // CONFIG_ESP_COREDUMP_STACK_SIZE == 0 /* Here, we are not going to use a custom stack for coredump. Make sure the current configuration doesn't require one. */ #if CONFIG_ESP_COREDUMP_USE_STACK_SIZE From 3a9dd08979e4738eed3160e4f9a00fbf242312d7 Mon Sep 17 00:00:00 2001 From: Ren Pei Ying Date: Fri, 8 Mar 2024 17:43:36 +0800 Subject: [PATCH 15/15] docs: Provide Chinese translation for api-reference/system/ulp_instruction_set.rst --- .../system/ulp_instruction_set.rst | 145 +- .../system/ulp_instruction_set.rst | 1472 ++++++++++++++++- 2 files changed, 1545 insertions(+), 72 deletions(-) diff --git a/docs/en/api-reference/system/ulp_instruction_set.rst b/docs/en/api-reference/system/ulp_instruction_set.rst index e39617845ee..7fb77934abb 100644 --- a/docs/en/api-reference/system/ulp_instruction_set.rst +++ b/docs/en/api-reference/system/ulp_instruction_set.rst @@ -1,6 +1,8 @@ {IDF_TARGET_NAME} ULP Coprocessor Instruction Set ================================================= +:link_to_translation:`zh_CN:[中文]` + This document provides details about the instructions used by {IDF_TARGET_NAME} ULP FSM coprocessor assembler. ULP FSM coprocessor has 4 16-bit general purpose registers, labeled R0, R1, R2, R3. It also has an 8-bit counter register (``stage_cnt``) which can be used to implement loops. Stage count register is accessed using special instructions. @@ -51,7 +53,7 @@ Note About Addressing ST R1, R2, 4 // offset = 4 bytes; Mem[R2 + 4 / 4] = R1 - In this case, the value in R1 is stored at the memory location pointed by [R2 + offset / 4] + In this case, the value in R1 is stored at the memory location pointed by [R2 + offset / 4]. Consider the following code:: @@ -66,7 +68,7 @@ Note About Addressing ST R2, R1, 0 // write value of R2 into the first array element, // i.e., array[0] - ST R2, R1, 4 // write value of R2 into the second array element + ST R2, R1, 4 // write value of R2 into the second array element, // (4 byte offset), i.e., array[1] ADD R1, R1, 2 // this increments address by 2 words (8 bytes) @@ -76,7 +78,7 @@ Note About Addressing Note About Instruction Execution Time ------------------------------------- -ULP coprocessor is clocked from ``RTC_FAST_CLK``, which is normally derived from the internal 8MHz oscillator. Applications which need to know exact ULP clock frequency can calibrate it against the main XTAL clock:: +ULP coprocessor is clocked from ``RTC_FAST_CLK``, which is normally derived from the internal 8 MHz oscillator. Applications which need to know exact ULP clock frequency can calibrate it against the main XTAL clock:: #include "soc/rtc.h" @@ -88,18 +90,18 @@ ULP coprocessor needs certain number of clock cycles to fetch each instruction, Instruction fetch time is: -- 2 clock cycles — for instructions following ALU and branch instructions. -- 4 clock cycles — in other cases. +- 2 clock cycles — for instructions following ALU and branch instructions +- 4 clock cycles — in other cases Note that when accessing RTC memories and RTC registers, ULP coprocessor has lower priority than the main CPUs. This means that ULP coprocessor execution may be suspended while the main CPUs access same memory region as the ULP. .. only:: esp32s2 or esp32s3 Difference Between ESP32 ULP and {IDF_TARGET_NAME} ULP Instruction Sets - ----------------------------------------------------------------------- + ------------------------------------------------------------------------- + + Compared to the ESP32 ULP FSM coprocessor, the {IDF_TARGET_NAME} ULP FSM coprocessor has an extended instruction set. The {IDF_TARGET_NAME} ULP FSM is not binary compatible with ESP32 ULP FSM, but a ESP32 ULP FSM assembled program is expected to work on the {IDF_TARGET_NAME} ULP FSM after rebuilding. - Compared to the ESP32 ULP FSM coprocessor, the {IDF_TARGET_NAME} ULP FSM coprocessor has an extended instruction set. The {IDF_TARGET_NAME} ULP FSM is not binary compatible with ESP32 ULP FSM, - but a ESP32 ULP FSM assembled program is expected to work on the {IDF_TARGET_NAME} ULP FSM after rebuilding. The list of the new instructions that was added to the {IDF_TARGET_NAME} ULP FSM is: ``LDL``, ``LDH``, ``STL``, ``STH``, ``ST32``, ``STO``, ``STI``, ``STI32``. @@ -307,11 +309,11 @@ The detailed description of all instructions is presented below: **Description** - The instruction does a logical shift to left of the source register by the number of bits from another source register or a 16-bit signed value and stores the result to the destination register. + The instruction does a logical shift to left of the source register by the number of bits from another source register or a 16-bit signed value and stores the result to the destination register. .. note:: - Shift operations which are greater than 15 bits have undefined results. + Shift operations which are greater than 15 bits have undefined results. **Examples**:: @@ -339,10 +341,10 @@ The detailed description of all instructions is presented below: **Operands** - **Rdst** - Register R[0..3] - **Rsrc1** - Register R[0..3] - **Rsrc2** - Register R[0..3] - **Imm** - 16-bit signed value + - **Rdst** - Register R[0..3] + - **Rsrc1** - Register R[0..3] + - **Rsrc2** - Register R[0..3] + - **Imm** - 16-bit signed value **Cycles** @@ -395,7 +397,7 @@ The detailed description of all instructions is presented below: .. note:: - Note that when a label is used as an immediate, the address of the label will be converted from bytes to words. This is because LD, ST, and JUMP instructions expect the address register value to be expressed in words rather than bytes. See the section :ref:`ulp-fsm-addressing` for more details. + Note that when a label is used as an immediate, the address of the label will be converted from bytes to words. This is because ``LD``, ``ST``, and ``JUMP`` instructions expect the address register value to be expressed in words rather than bytes. See the section :ref:`ulp-fsm-addressing` for more details. **Examples**:: @@ -432,7 +434,7 @@ The detailed description of all instructions is presented below: **Description** - The instruction stores the 16-bit value of Rsrc to the lower half-word of memory with address Rdst+offset. The upper half-word is written with the current program counter (PC) (expressed in words, shifted left by 5 bits) OR'd with Rdst (0..3):: + The instruction stores the 16-bit value of Rsrc to the lower half-word of memory with address Rdst + offset. The upper half-word is written with the current program counter (PC) (expressed in words, shifted left by 5 bits) OR'd with Rdst (0..3):: Mem[Rdst + offset / 4]{31:0} = {PC[10:0], 3'b0, Rdst, Rsrc[15:0]} @@ -458,7 +460,7 @@ The detailed description of all instructions is presented below: .. only:: esp32s2 or esp32s3 **STL** – Store Data to the Lower 16 Bits of 32-bit Memory - ---------------------------------------------------------------- + ---------------------------------------------------------- **Syntax** @@ -506,7 +508,7 @@ The detailed description of all instructions is presented below: **STH** – Store data to the higher 16 bits of 32-bit memory - ------------------------------------------------------------ + ----------------------------------------------------------- **Syntax** @@ -630,7 +632,7 @@ The detailed description of all instructions is presented below: **STI** – Store data to the 32-bits memory with auto increment of predefined offset address - ------------------------------------------------------------------------------------------- + ----------------------------------------------------------------------------------------------- **Syntax** @@ -650,8 +652,7 @@ The detailed description of all instructions is presented below: The instruction stores the 16-bit value of Rsrc to the lower and upper half-word of memory with address [Rdst + offset / 4]. - The offset value is auto incremented when the STI instruction is called twice. Make sure to execute the ``STO`` instruction - to set the offset value before executing the STI instruction:: + The offset value is auto incremented when the STI instruction is called twice. Make sure to execute the ``STO`` instruction to set the offset value before executing the STI instruction:: Mem[Rdst + offset / 4]{15:0/31:16} = {Rsrc[15:0]} Mem[Rdst + offset / 4]{15:0/31:16} = {Label[1:0],Rsrc[13:0]} @@ -666,8 +667,8 @@ The detailed description of all instructions is presented below: STI R1, R2 // MEM[R2 + 8 / 4][31:16] = R1 - **STI32** – Store 32-bits data to the 32-bits memory with auto increment of adress offset - ----------------------------------------------------------------------------------------- + **STI32** – Store 32-bits data to the 32-bits memory with auto increment of address offset + ---------------------------------------------------------------------------------------------- **Syntax** @@ -687,8 +688,7 @@ The detailed description of all instructions is presented below: The instruction stores 11 bits of the PC value, label value and the 16-bit value of Rsrc to the 32-bit memory with address [Rdst + offset / 4]. - The offset value is auto incremented each time the STI32 instruction is called. Make sure to execute the ``STO`` instruction - to set the offset value before executing the STI32 instruction:: + The offset value is auto incremented each time the STI32 instruction is called. Make sure to execute the ``STO`` instruction to set the offset value before executing the STI32 instruction:: Mem[Rdst + offset / 4]{31:0} = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]} @@ -845,12 +845,12 @@ The detailed description of all instructions is presented below: - **Rdst** – Register R[0..3] containing address to jump to (expressed in 32-bit words) - **ImmAddr** – 13 bits address (expressed in bytes), aligned to 4 bytes - **Condition**: - - EQ – jump if last ALU operation result was zero - - OV – jump if last ALU has set overflow flag + - EQ – jump if the last ALU operation result was zero + - OV – jump if the last ALU has set overflow flag **Cycles** - 2 cycles to execute, 2 cycles to fetch next instruction + 2 cycles to execute, 2 cycles to fetch next instruction. **Description** @@ -896,7 +896,7 @@ The detailed description of all instructions is presented below: .. only:: esp32 - Conditions **LT**, **GE**, **LE** and **GT**: 2 cycles to execute, 2 cycles to fetch next instruction + Conditions **LT**, **GE**, **LE** and **GT**: 2 cycles to execute, 2 cycles to fetch next instruction. Conditions **LE** and **GT** are implemented in the assembler using one **JUMPR** instruction:: @@ -919,7 +919,7 @@ The detailed description of all instructions is presented below: .. only:: esp32s2 or esp32s3 - Conditions **EQ**, **GT** and **LT**: 2 cycles to execute, 2 cycles to fetch next instruction + Conditions **EQ**, **GT** and **LT**: 2 cycles to execute, 2 cycles to fetch next instruction. Conditions **LE** and **GE** are implemented in the assembler using two **JUMPR** instructions:: @@ -960,7 +960,7 @@ The detailed description of all instructions is presented below: **Operands** - - **Step** – relative shift from current position, in bytes + - **Step** – relative shift from current position, in bytes - **Threshold** – threshold value for branch condition - **Condition**: - **EQ** (equal) – jump if value in stage_cnt == threshold @@ -973,7 +973,7 @@ The detailed description of all instructions is presented below: .. only:: esp32 - Conditions **LE**, **LT**, **GE**: 2 cycles to execute, 2 cycles to fetch next instruction + Conditions **LE**, **LT**, **GE**: 2 cycles to execute, 2 cycles to fetch next instruction. Conditions **EQ**, **GT** are implemented in the assembler using two **JUMPS** instructions:: @@ -994,7 +994,7 @@ The detailed description of all instructions is presented below: .. only:: esp32s2 or esp32s3 - 2 cycles to execute, 2 cycles to fetch next instruction + 2 cycles to execute, 2 cycles to fetch next instruction. **Description** @@ -1014,6 +1014,7 @@ The detailed description of all instructions is presented below: **STAGE_RST** – Reset Stage Count Register ------------------------------------------ + **Syntax** **STAGE_RST** @@ -1052,7 +1053,7 @@ The detailed description of all instructions is presented below: **Description** - The instruction increments the stage count register by the given value. + The instruction increments the stage count register by the given value **Examples**:: @@ -1069,6 +1070,7 @@ The detailed description of all instructions is presented below: ---------------------------------------------- **Syntax** + **STAGE_DEC** **Value** **Operands** @@ -1081,7 +1083,7 @@ The detailed description of all instructions is presented below: **Description** - The instruction decrements the stage count register by the given value. + The instruction decrements the stage count register by the given value **Examples**:: @@ -1112,11 +1114,11 @@ The detailed description of all instructions is presented below: **Description** - The instruction halts the ULP coprocessor and restarts the ULP wakeup timer, if it is enabled. + The instruction halts the ULP coprocessor and restarts the ULP wakeup timer, if it is enabled **Examples**:: - 1: HALT // Halt the coprocessor + 1: HALT // Halt the coprocessor **WAKE** – Wake up the Chip @@ -1179,7 +1181,7 @@ The detailed description of all instructions is presented below: **Operands** - - **sleep_reg** – 0..4, selects one of ``SENS_ULP_CP_SLEEP_CYCx_REG`` registers. + - **sleep_reg** – 0..4, selects one of ``SENS_ULP_CP_SLEEP_CYCx_REG`` registers **Cycles** @@ -1187,7 +1189,7 @@ The detailed description of all instructions is presented below: **Description** - The instruction selects which of the ``SENS_ULP_CP_SLEEP_CYCx_REG`` (x = 0..4) register values is to be used by the ULP wakeup timer as wakeup period. By default, the value from ``SENS_ULP_CP_SLEEP_CYC0_REG`` is used. + The instruction selects which of the ``SENS_ULP_CP_SLEEP_CYCx_REG`` (x = 0..4) register values is to be used by the ULP wakeup timer as wakeup period. By default, the value from ``SENS_ULP_CP_SLEEP_CYC0_REG`` is used **Examples**:: @@ -1202,19 +1204,19 @@ The detailed description of all instructions is presented below: **Syntax** - **WAIT** **Cycles** + **WAIT** **Cycles** **Operands** - - **Cycles** – number of cycles for wait + - **Cycles** – number of cycles for wait **Cycles** - 2 + **Cycles** cycles to execute, 4 cycles to fetch next instruction + (2 + **Cycles**) cycles to execute, 4 cycles to fetch next instruction **Description** - The instruction delays for given number of cycles. + The instruction delays for a given number of cycles. **Examples**:: @@ -1239,11 +1241,11 @@ The detailed description of all instructions is presented below: **Cycles** - 2 + **Wait_Delay** + 3 * TSENS_CLK to execute, 4 cycles to fetch next instruction + (2 + **Wait_Delay** + 3 * TSENS_CLK) to execute, 4 cycles to fetch next instruction **Description** - The instruction performs measurement using TSENS and stores the result into a general purpose register. + The instruction performs measurement using TSENS and stores the result into a general purpose register **Examples**:: @@ -1279,17 +1281,19 @@ The detailed description of all instructions is presented below: **Description** - The instruction makes measurements from ADC. - -**Examples**:: + The instruction makes measurements from ADC .. only:: esp32 - 1: ADC R1, 0, 1 // Measure value using ADC1 channel 0 and store result into R1 + **Examples**:: + + 1: ADC R1, 0, 1 // Measure value using ADC1 channel 0 and store result into R1 .. only:: esp32s2 or esp32s3 - 1: ADC R1, 0, 1 // Measure value using ADC1 pad 2 and store result into R1 + **Examples**:: + + 1: ADC R1, 0, 1 // Measure value using ADC1 pad 2 and store result into R1 .. only:: esp32 @@ -1302,13 +1306,13 @@ The detailed description of all instructions is presented below: **Operands** - - **Sub_addr** – Address within the I2C slave to read. - - **High*, *Low** — Define range of bits to read. Bits outside of [High, Low] range are masked. - - **Slave_sel** - Index of I2C slave address to use. + - **Sub_addr** – Address within the I2C slave to read + - **High*, *Low** — Define range of bits to read. Bits outside of [High, Low] range are masked + - **Slave_sel** - Index of I2C slave address to use **Cycles** - Execution time mostly depends on I2C communication time. 4 cycles to fetch next instruction. + Execution time mostly depends on I2C communication time. 4 cycles to fetch next instruction **Description** @@ -1328,22 +1332,22 @@ The detailed description of all instructions is presented below: **Operands** - - **Sub_addr** – Address within the I2C slave to write. - - **Value** – 8-bit value to be written. - - **High**, **Low** — Define range of bits to write. Bits outside of [High, Low] range are masked. - - **Slave_sel** - Index of I2C slave address to use. + - **Sub_addr** – Address within the I2C slave to write + - **Value** – 8-bit value to be written + - **High**, **Low** — Define range of bits to write. Bits outside of [High, Low] range are masked + - **Slave_sel** - Index of I2C slave address to use **Cycles** - Execution time mostly depends on I2C communication time. 4 cycles to fetch next instruction. + Execution time mostly depends on I2C communication time. 4 cycles to fetch next instruction **Description** - ``I2C_WR`` instruction writes one byte to I2C slave with index ``Slave_sel``. Slave address (in 7-bit format) has to be set in advance into ``SENS_I2C_SLAVE_ADDRx`` register field, where ``x == Slave_sel``. + ``I2C_WR`` instruction writes one byte to I2C slave address with index ``Slave_sel``. Slave address (in 7-bit format) has to be set in advance into the ``SENS_I2C_SLAVE_ADDRx`` register field, where ``x == Slave_sel``. **Examples**:: - 1: I2C_WR 0x20, 0x33, 7, 0, 1 // Write byte 0x33 to sub-address 0x20 of slave with address set in SENS_I2C_SLAVE_ADDR1. + 1: I2C_WR 0x20, 0x33, 7, 0, 1 // Write byte 0x33 to sub-address 0x20 of slave with address set in SENS_I2C_SLAVE_ADDR1. **REG_RD** – Read from Peripheral Register @@ -1393,7 +1397,7 @@ The detailed description of all instructions is presented below: **Operands** - - **Addr** – Register address, in 32-bit words. + - **Addr** – Register address, in 32-bit words - **High** – Register end bit number - **Low** – Register start bit number - **Data** – Value to write, 8 bits @@ -1406,21 +1410,21 @@ The detailed description of all instructions is presented below: The instruction writes up to 8 bits from an immediate data value into a peripheral register: ``REG[Addr][High:Low] = data``. -.. only:: esp32 + .. only:: esp32 - This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the register, as seen from the ULP, can be calculated from the address of the same register on the DPORT bus as follows:: + This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the register, as seen from the ULP, can be calculated from the address of the same register on the DPORT bus as follows:: - addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 + addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 -.. only:: esp32s2 or esp32s3 + .. only:: esp32s2 or esp32s3 - This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the register, as seen from the ULP, can be calculated from the address of the same register on the PeriBUS1 as follows:: + This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the register, as seen from the ULP, can be calculated from the address of the same register on the PeriBUS1 as follows:: - addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4 + addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4 **Examples**:: - 1: REG_WR 0x120, 7, 0, 0x10 // set 8 bits: REG[0x120][7:0] = 0x10 + 1: REG_WR 0x120, 7, 0, 0x10 // set 8 bits: REG[0x120][7:0] = 0x10 Convenience Macros for Peripheral Registers Access @@ -1428,8 +1432,7 @@ Convenience Macros for Peripheral Registers Access ULP source files are passed through C preprocessor before the assembler. This allows certain macros to be used to facilitate access to peripheral registers. -Some existing macros are defined in ``soc/soc_ulp.h`` header file. These macros allow access to the fields of peripheral registers by their names. -Peripheral registers names which can be used with these macros are the ones defined in ``soc/rtc_cntl_reg.h``, ``soc/rtc_io_reg.h``, ``soc/sens_reg.h``, and ``soc/rtc_i2c_reg.h``. +Some existing macros are defined in ``soc/soc_ulp.h`` header file. These macros allow access to the fields of peripheral registers by their names. Peripheral registers' names which can be used with these macros are the ones defined in ``soc/rtc_cntl_reg.h``, ``soc/rtc_io_reg.h``, ``soc/sens_reg.h``, and ``soc/rtc_i2c_reg.h``. READ_RTC_REG(rtc_reg, low_bit, bit_width) Read up to 16 bits from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0. For example:: diff --git a/docs/zh_CN/api-reference/system/ulp_instruction_set.rst b/docs/zh_CN/api-reference/system/ulp_instruction_set.rst index 22fce385057..c796dcac4f7 100644 --- a/docs/zh_CN/api-reference/system/ulp_instruction_set.rst +++ b/docs/zh_CN/api-reference/system/ulp_instruction_set.rst @@ -1 +1,1471 @@ -.. include:: ../../../en/api-reference/system/ulp_instruction_set.rst +{IDF_TARGET_NAME} ULP 协处理器指令 +================================================= + +:link_to_translation:`en:[English]` + +本文档详细介绍了 {IDF_TARGET_NAME} ULP FSM 协处理器汇编程序使用的指令。 + +ULP FSM 协处理器有 4 个 16 位通用寄存器，分别标记为 R0、R1、R2、R3，还有一个 8 位计数器寄存器 (``stage_cnt``) 用来实现循环。可以用特殊指令来访问阶段计数寄存器。 + +ULP 协处理器可以访问 8 K 字节大小的 RTC_SLOW_MEM 内存区域。内存以 32 位字单位寻址。它还可以访问 ``RTC_CNTL``、``RTC_IO`` 和 ``SENS`` 外设中的外设寄存器。 + +所有指令都是 32 位。跳转指令、ALU 指令、外设寄存器和内存访问指令在 1 个周期内执行。与外设（TSENS、ADC 和 I2C）相关的指令所需的周期不同，具体取决于外设操作。 + +指令语法不区分大小写。无论是寄存器名称还是指令名称，都可以任意混合使用大小写字母。 + +.. _ulp-fsm-addressing: + +寻址注意事项 +----------------- + +对于 {IDF_TARGET_NAME} ULP FSM 协处理器的 ``JUMP``、``ST``、``LD`` 系列指令，地址参数应以如下方式表示（具体取决于使用的地址参数类型）： + +- 当地址参数作为标签时，指令中的地址应为 32 位字。 + + 对于示例程序:: + + entry: + NOP + NOP + NOP + NOP + loop: + MOVE R1, loop + JUMP R1 + + 当此程序被汇编和链接时，标签 ``loop`` 的地址将为 16 字节。然而 ``JUMP`` 指令期望寄存器 ``R1`` 中存储的地址以 32 位字表示。由于这种情况较为常见，汇编程序会在生成 ``MOVE`` 指令时将标签 ``loop`` 的地址从字节转换为字。因此，生成的代码相当于:: + + 0000 NOP + 0004 NOP + 0008 NOP + 000c NOP + 0010 MOVE R1, 4 + 0014 JUMP R1 + +- 另一种情况是，``MOVE`` 指令的参数不是标签，而是常量。此时汇编程序将 **直接使用该常量** ，不进行任何转换:: + + .set val, 0x10 + MOVE R1, val + + 在这种情况下，加载到 ``R1`` 的值为 ``0x10``。 + + 但是，当使用立即数作为 ``LD`` 和 ``ST`` 指令的偏移量时，汇编程序会认为地址参数是字节，并在执行指令前将其转换为 32 位字:: + + ST R1, R2, 4 // offset = 4 bytes; Mem[R2 + 4 / 4] = R1 + + 在这种情况下， R1 中的值存储在 [R2 + offset / 4] 指向的内存位置。 + + 请看以下代码:: + + .global array + array: .long 0 + .long 0 + .long 0 + .long 0 + + MOVE R1, array + MOVE R2, 0x1234 + ST R2, R1, 0 // 将 R2 的值写入第一个数组元素， + // 即 array[0] + + ST R2, R1, 4 // 将 R2 的值写入第二个数组元素， + //（4 字节偏移量），即 array[1] + + ADD R1, R1, 2 // 将地址递增 2 个字（8 个字节） + ST R2, R1, 0 // 将 R2 的值写入第三个数组元素， + // 即 array[2] + +指令执行时间注意事项 +--------------------------------- + +ULP 协处理器的时钟 ``RTC_FAST_CLK`` 通常来自内部的 8 MHz 振荡器。如果应用程序需要获知精确 ULP 时钟频率，可以根据主 XTAL 时钟进行校准:: + + #include "soc/rtc.h" + + // calibrate 8M/256 clock against XTAL, get 8M/256 clock period + uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100); + uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period; + +ULP 协处理器在获取每个指令时需要一定的时钟周期，执行时同样需要一定的时钟周期，此周期数取决于具体的指令。下文详细列出了每个指令所需的执行时间信息。 + +指令获取时间： + +- 2 个时钟周期 - ALU 和分支类的指令 +- 4 个时钟周期 - 其他指令 + +注意，访问 RTC 存储器和 RTC 寄存器时，ULP 协处理器的优先级低于主 CPU。这意味着当主 CPU 与 ULP 访问同一块内存区域时，ULP 协处理器需要等待，主 CPU 会优先访问。 + +.. only:: esp32s2 or esp32s3 + + ESP32 ULP 和 {IDF_TARGET_NAME} ULP 指令集的区别 + ----------------------------------------------------------------------- + + 与 ESP32 ULP FSM 协处理器相比，{IDF_TARGET_NAME} ULP FSM 协处理器具有扩展的指令集。{IDF_TARGET_NAME} ULP FSM 与 ESP32 ULP FSM 二进制不兼容，但在重新构建后，ESP32 ULP FSM 的汇编程序应能在 {IDF_TARGET_NAME} ULP FSM 上运行。 + + 添加到 {IDF_TARGET_NAME} ULP FSM 的新指令包括：``LDL``、``LDH``、``STL``、``STH``、``ST32``、``STO``、``STI``、``STI32``。 + + +以下是所有指令的详细描述： + +**NOP** - 无操作 +---------------------- + +**语法** + + **NOP** + +**操作数** + + 无 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 不执行任何操作，只增加 PC + +**示例**:: + + 1: NOP + + +**ADD** - 做加法运算 +----------------------------------------- + +**语法** + + **ADD** **Rdst, Rsrc1, Rsrc2** + + **ADD** **Rdst, Rsrc1, imm** + + +**操作数** + + - **Rdst** - 寄存器 R[0..3] + - **Rsrc1** - 寄存器 R[0..3] + - **Rsrc2** - 寄存器 R[0..3] + - **Imm** - 16 位有符号值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令将源寄存器与另一个源寄存器中的值相加或与一个 16 位有符号值相加，并将结果存储在目标寄存器中。 + +**示例**:: + + 1: ADD R1, R2, R3 // R1 = R2 + R3 + + 2: Add R1, R2, 0x1234 // R1 = R2 + 0x1234 + + 3: .set value1, 0x03 // constant value1=0x03 + Add R1, R2, value1 // R1 = R2 + value1 + + 4: .global label // declaration of variable label + add R1, R2, label // R1 = R2 + label + ... + label: nop // definition of variable label + + +**SUB** - 做减法运算 +-------------------------------- + +**语法** + + **SUB** **Rdst, Rsrc1, Rsrc2** + + **SUB** **Rdst, Rsrc1, imm** + +**操作数** + + - **Rdst** - 寄存器 R[0..3] + - **Rsrc1** - 寄存器 R[0..3] + - **Rsrc2** - 寄存器 R[0..3] + - **Imm** - 16 位有符号值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令将两个源寄存器中的值相减，或从一个源寄存器中减去一个 16 位有符号值，并将结果存储到目标寄存器中。 + +**示例**:: + + 1: SUB R1, R2, R3 // R1 = R2 - R3 + + 2: sub R1, R2, 0x1234 // R1 = R2 - 0x1234 + + 3: .set value1, 0x03 // constant value1=0x03 + SUB R1, R2, value1 // R1 = R2 - value1 + 4: .global label // declaration of variable label + SUB R1, R2, label // R1 = R2 - label + .... + label: nop // definition of variable label + + +**AND** - 两个操作数的按位与 +---------------------------------------- + +**语法** + + **AND** **Rdst, Rsrc1, Rsrc2** + + **AND** **Rdst, Rsrc1, imm** + +**操作数** + + - **Rdst** - 寄存器 R[0..3] + - **Rsrc1** - 寄存器 R[0..3] + - **Rsrc2** - 寄存器 R[0..3] + - **Imm** - 16 位有符号值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令对源寄存器的值和另一个源寄存器的值或一个 16 位有符号值进行按位与操作，并将结果存储到目标寄存器中。 + +**示例**:: + + 1: AND R1, R2, R3 // R1 = R2 & R3 + + 2: AND R1, R2, 0x1234 // R1 = R2 & 0x1234 + + 3: .set value1, 0x03 // constant value1=0x03 + AND R1, R2, value1 // R1 = R2 & value1 + + 4: .global label // declaration of variable label + AND R1, R2, label // R1 = R2 & label + ... + label: nop // definition of variable label + + +**OR** - 两个操作数的按位或 +------------------------------------------- + +**语法** + + **OR** **Rdst, Rsrc1, Rsrc2** + + **OR** **Rdst, Rsrc1, imm** + +**操作数** + + - **Rdst** - 寄存器 R[0..3] + - **Rsrc1** - 寄存器 R[0..3] + - **Rsrc2** - 寄存器 R[0..3] + - **Imm** - 16 位有符号值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令对源寄存器的值和另一个源寄存器的值或一个 16 位有符号值进行按位或操作，并将结果存储到目标寄存器中。 + +**示例**:: + + 1: OR R1, R2, R3 // R1 = R2 || R3 + + 2: OR R1, R2, 0x1234 // R1 = R2 || 0x1234 + + 3: .set value1, 0x03 // constant value1=0x03 + OR R1, R2, value1 // R1 = R2 || value1 + + 4: .global label // declaration of variable label + OR R1, R2, label // R1 = R2 || label + ... + label: nop // definition of variable label + + +**LSH** - 逻辑左移 +---------------------------- + +**语法** + + **LSH** **Rdst, Rsrc1, Rsrc2** + + **LSH** **Rdst, Rsrc1, imm** + +**操作数** + + - **Rdst** - 寄存器 R[0..3] + - **Rsrc1** - 寄存器 R[0..3] + - **Rsrc2** - 寄存器 R[0..3] + - **Imm** - 16 位有符号值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令对源寄存器进行逻辑左移，移动的位数由另一个源寄存器或一个16位有符号值确定，并将结果存储到目标寄存器中。 + +.. note:: + + 大于 15 位的移位操作结果不确定。 + +**示例**:: + + 1: LSH R1, R2, R3 // R1 = R2 << R3 + + 2: LSH R1, R2, 0x03 // R1 = R2 << 0x03 + + 3: .set value1, 0x03 // constant value1=0x03 + LSH R1, R2, value1 // R1 = R2 << value1 + + 4: .global label // declaration of variable label + LSH R1, R2, label // R1 = R2 << label + ... + label: nop // definition of variable label + + +**RSH** - 逻辑右移 +----------------------------- + +**语法** + + **RSH** **Rdst, Rsrc1, Rsrc2** + + **RSH** **Rdst, Rsrc1, imm** + +**操作数** + + - **Rdst** - 寄存器 R[0..3] + - **Rsrc1** - 寄存器 R[0..3] + - **Rsrc2** - 寄存器 R[0..3] + - **Imm** - 16 位有符号值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令对源寄存器进行逻辑右移，移动的位数由另一个源寄存器或一个 16 位有符号值确定，并将结果存储到目标寄存器中。 + +.. note:: + + 大于 15 位的移位操作结果未定义。 + +**示例**:: + + 1: RSH R1, R2, R3 // R1 = R2 >> R3 + + 2: RSH R1, R2, 0x03 // R1 = R2 >> 0x03 + + 3: .set value1, 0x03 // constant value1=0x03 + RSH R1, R2, value1 // R1 = R2 >> value1 + + 4: .global label // declaration of variable label + RSH R1, R2, label // R1 = R2 >> label + label: nop // definition of variable label + + +**MOVE** – 移动到寄存器 +--------------------------- + +**语法** + + **MOVE** **Rdst, Rsrc** + + **MOVE** **Rdst, imm** + +**操作数** + + - **Rdst** – 寄存器 R[0..3] + - **Rsrc** – 寄存器 R[0..3] + - **Imm** – 16 位有符号值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令将源寄存器的值或一个 16 位有符号值移动到目标寄存器。 + +.. note:: + + 注意，当标签用作立即数时，标签的地址会从字节转换为字。这是因为对于 ``LD``、``ST`` 和 ``JUMP`` 指令，地址寄存器的值应以字表示，而不以字节表示。更多详细信息请参阅 :ref:`ulp-fsm-addressing`。 + + +**示例**:: + + 1: MOVE R1, R2 // R1 = R2 + + 2: MOVE R1, 0x03 // R1 = 0x03 + + 3: .set value1, 0x03 // constant value1=0x03 + MOVE R1, value1 // R1 = value1 + + 4: .global label // declaration of label + MOVE R1, label // R1 = address_of(label) / 4 + ... + label: nop // definition of label + + +**ST** – 将数据存储到内存中 +--------------------------------- + +**语法** + + **ST** **Rsrc, Rdst, offset** + +**操作数** + + - **Rsrc** – 寄存器 R[0..3]，保存要存储的 16 位值 + - **Rdst** – 寄存器 R[0..3]，目标地址，以 32 位字为单位 + - **Offset** – 13 位有符号值，以字节表示 + +**周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令将 Rsrc 的 16 位值存储到目标内存地址 [Rdst + offset] 中，存储的数据占目标内存中一个字的低半部分，而高半部分由当前程序计数器 PC 的值（以字为单位，左移 5 位）与 Rdst（0..3）进行逻辑“或”运算:: + + Mem[Rdst + offset / 4]{31:0} = {PC[10:0], 3'b0, Rdst, Rsrc[15:0]} + + 应用程序可以使用高 16 位来确定 ULP 程序中的哪条指令将某个特定的字写入了内存。 + +.. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。更多信息请参阅 :ref:`ulp-fsm-addressing`。 + +**示例**:: + + 1: ST R1, R2, 0x12 // MEM[R2 + 0x12 / 4] = R1 + + 2: .data // Data section definition + Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + MOVE R1, 1 // R1 = 1 + MOVE R2, Addr1 // R2 = Addr1 + ST R1, R2, offs // MEM[R2 + 0 / 4] = R1 + // MEM[Addr1 + 0] will be 32'h600001 + +.. only:: esp32s2 or esp32s3 + + **STL** – 将数据存储到 32 位内存的低 16 位 + ---------------------------------------------------------------- + + **语法** + + **STL** **Rsrc, Rdst, offset, Label** + + **操作数** + + - **Rsrc** – 寄存器 R[0..3]，保存要存储的 16 位值 + - **Rdst** – 寄存器 R[0..3]，目标地址，以 32 位字为单位 + - **Offset** – 11 位有符号值，以字节为单位的偏移 + - **Label** – 用户定义的 2 位无符号值 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将 Rsrc 的 16 位值存储到地址为 [Rdst + offset / 4] 的内存的低半字中:: + + Mem[Rdst + offset / 4]{15:0} = {Rsrc[15:0]} + Mem[Rdst + offset / 4]{15:0} = {Label[1:0],Rsrc[13:0]} + + ``ST`` 和 ``STL`` 命令可以互换使用，以保持对早期版本 ULP 核的向后兼容性。 + + .. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。更多信息请参阅 :ref:`ulp-fsm-addressing`。 + + **示例**:: + + 1: STL R1, R2, 0x12 // MEM[R2 + 0x12 / 4] = R1 + + 2: .data // Data section definition + Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + MOVE R1, 1 // R1 = 1 + MOVE R2, Addr1 // R2 = Addr1 + STL R1, R2, offs // MEM[R2 + 0 / 4] = R1 + // MEM[Addr1 + 0] will be 32'hxxxx0001 + 3: + MOVE R1, 1 // R1 = 1 + STL R1, R2, 0x12, 1 // MEM[R2 + 0x12 / 4] = 0xxxxx4001 + + + **STH** – 将数据存储到 32 位内存的高 16 位 + ------------------------------------------------------------ + + **语法** + + **STH** **Rsrc, Rdst, offset, Label** + + **操作数** + + - **Rsrc** – 寄存器 R[0..3]，保存要存储的 16 位值 + - **Rdst** – 寄存器 R[0..3]，目标地址，以 32 位字为单位 + - **Offset** – 11 位有符号值，以字节为单位的偏移 + - **Label** – 用户定义的 2 位无符号值 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将 Rsrc 的 16 位值存储到地址为 [Rdst + offset / 4] 的内存的高半字中:: + + Mem[Rdst + offset / 4]{31:16} = {Rsrc[15:0]} + Mem[Rdst + offset / 4]{31:16} = {Label[1:0],Rsrc[13:0]} + + .. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。更多信息请参阅 :ref:`ulp-fsm-addressing`。 + + **示例**:: + + 1: STH R1, R2, 0x12 // MEM[R2 + 0x12 / 4][31:16] = R1 + + 2: .data // Data section definition + Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + MOVE R1, 1 // R1 = 1 + MOVE R2, Addr1 // R2 = Addr1 + STH R1, R2, offs // MEM[R2 + 0 / 4] = R1 + // MEM[Addr1 + 0] will be 32'h0001xxxx + 3: + MOVE R1, 1 // R1 = 1 + STH R1, R2, 0x12, 1 // MEM[R2 + 0x12 / 4] 0x4001xxxx + + + **ST32** – 将 32 位数据存储到 32 位内存 + --------------------------------------------------- + + **语法** + + **ST32** **Rsrc, Rdst, offset, Label** + + **操作数** + + - **Rsrc** – 寄存器 R[0..3]，保存要存储的 16 位值 + - **Rdst** – 寄存器 R[0..3]，目标地址，以 32 位字为单位 + - **Offset** – 11 位有符号值，以字节为单位的偏移 + - **Label** – 用户定义的 2 位无符号值 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将 PC 的 11 位值，标签值和 Rsrc 的 16 位值存储到地址为 [Rdst + offset / 4] 的 32 位内存中:: + + Mem[Rdst + offset / 4]{31:0} = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]} + + .. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。更多信息请参阅 :ref:`ulp-fsm-addressing`。 + + **示例**:: + + 1: ST32 R1, R2, 0x12, 0 // MEM[R2 + 0x12 / 4][31:0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]} + + 2: .data // Data section definition + Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + MOVE R1, 1 // R1 = 1 + MOVE R2, Addr1 // R2 = Addr1 + ST32 R1, R2, offs, 1 // MEM[R2 + 0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]} + // MEM[Addr1 + 0] will be 32'h00010001 + + + **STO** – 设置自动递增操作的偏移值 + ------------------------------------------------------- + + **语法** + + **STO** **offset** + + **操作数** + + - **Offset** – 11 位有符号值，以字节为单位的偏移 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将 16 位值设置到偏移寄存器:: + + offset = value / 4 + + .. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。更多信息请参阅 :ref:`ulp-fsm-addressing`。 + + **示例**:: + + 1: STO 0x12 // Offset = 0x12 / 4 + + 2: .data // Data section definition + Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + STO offs // Offset = 0x00 + + + **STI** – 将数据存储到 32 位内存中，并自动递增预定义地址偏移 + ------------------------------------------------------------------------------------------- + + **语法** + + **STI** **Rsrc, Rdst, Label** + + **操作数** + + - **Rsrc** – 寄存器 R[0..3]，保存要存储的 16 位值 + - **Rdst** – 寄存器 R[0..3]，目标地址，以 32 位字为单位 + - **Label** – 用户定义的 2 位无符号值 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将 Rsrc 的 16 位值存储到地址为 [Rdst + offset / 4] 的内存的低半字和高半字中。 + + 当 STI 指令被调用两次时，会自增偏移量。请确保在执行 STI 指令之前，执行 ``STO`` 指令来设置该偏移值:: + + Mem[Rdst + offset / 4]{15:0/31:16} = {Rsrc[15:0]} + Mem[Rdst + offset / 4]{15:0/31:16} = {Label[1:0],Rsrc[13:0]} + + **示例**:: + + 1: STO 4 // Set offset to 4 + STI R1, R2 // MEM[R2 + 4 / 4][15:0] = R1 + STI R1, R2 // MEM[R2 + 4 / 4][31:16] = R1 + // offset += (1 * 4) //offset is incremented by 1 word + STI R1, R2 // MEM[R2 + 8 / 4][15:0] = R1 + STI R1, R2 // MEM[R2 + 8 / 4][31:16] = R1 + + + **STI32** – 将 32 位数据存储到 32 位内存中，并自动递增地址偏移 + ----------------------------------------------------------------------------------------- + + **语法** + + **STI32** **Rsrc, Rdst, Label** + + **操作数** + + - **Rsrc** – 寄存器 R[0..3]，保存要存储的 16 位值 + - **Rdst** – 寄存器 R[0..3]，目标地址，以 32 位字为单位 + - **Label** – 用户定义的 2 位无符号值 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将 PC 的 11 位值，标签值和 Rsrc 的 16 位值存储到地址为 [Rdst + offset / 4] 的 32 位内存中。 + + 每次调用 STI32 指令时，偏移值都会自动增加。确保在执行 STI32 指令之前，执行 ``STO`` 指令来设置偏移值:: + + Mem[Rdst + offset / 4]{31:0} = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]} + + **示例**:: + + 1: STO 0x12 + STI32 R1, R2, 0 // MEM[R2 + 0x12 / 4][31:0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]} + // offset += (1 * 4) //offset is incremented by 1 word + STI32 R1, R2, 0 // MEM[R2 + 0x16 / 4][31:0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]} + + +**LD** – 从内存中加载数据 +------------------------------------ + +**语法** + + **LD** **Rdst, Rsrc, offset** + +**操作数** + + - **Rdst** – 寄存器 R[0..3]，目标寄存器 + - **Rsrc** – 寄存器 R[0..3]，保存目标地址，以 32 位字为单位 + - **Offset** – 13 位有符号值，以字节为单位的偏移量 + +**周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令将地址为 [Rsrc + offset / 4] 的内存中的 16 位低半字加载到目标寄存器 Rdst 中:: + + Rdst[15:0] = Mem[Rsrc + offset / 4][15:0] + +.. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。详情请参阅 :ref:`ulp-fsm-addressing`。 + +**示例**:: + + 1: LD R1, R2, 0x12 // R1 = MEM[R2 + 0x12 / 4] + + 2: .data // Data section definition + Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + MOVE R1, 1 // R1 = 1 + MOVE R2, Addr1 // R2 = Addr1 / 4 (address of label is converted into words) + LD R1, R2, offs // R1 = MEM[R2 + 0] + // R1 will be 123 + +.. only:: esp32s2 or esp32s3 + + **LDL** – 从 32 位内存的低半字中加载数据 + ------------------------------------------------- + + **语法** + + **LDL** **Rdst, Rsrc, offset** + + **操作数** + + - **Rdst** – 寄存器 R[0..3]，目标寄存器 + - **Rsrc** – 寄存器 R[0..3]，保存目标地址，以 32 位字为单位 + - **Offset** – 13 位有符号值，以字节为单位的偏移量 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将地址为 [Rsrc + offset / 4] 的内存中的 16 位低半字加载到目标寄存器 Rdst 中:: + + Rdst[15:0] = Mem[Rsrc + offset / 4][15:0] + + ``LD`` 和 ``LDL`` 命令可以互换使用，以保持对早期版本 ULP 核的向后兼容性。 + + .. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。更多信息请参阅 :ref:`ulp-fsm-addressing`。 + + **示例**:: + + 1: LDL R1, R2, 0x12 // R1 = MEM[R2 + 0x12 / 4] + + 2: .data // Data section definition + Addr1: .word 123 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + MOVE R1, 1 // R1 = 1 + MOVE R2, Addr1 // R2 = Addr1 / 4 (address of label is converted into words) + LDL R1, R2, offs // R1 = MEM[R2 + 0] + // R1 will be 123 + + + **LDH** – 从 32 位内存的高半字加载数据 + -------------------------------------------------------------- + + **语法** + + **LDH** **Rdst, Rsrc, offset** + + **操作数** + + - **Rdst** – 寄存器 R[0..3]，目标寄存器 + - **Rsrc** – 寄存器 R[0..3]，保存目标地址，以 32 位字为单位 + - **Offset** – 13 位有符号值，以字节为单位的偏移 + + **周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令将地址为 [Rsrc + offset / 4] 的内存中的 16 位高半字加载到目标寄存器 Rdst 中:: + + Rdst[15:0] = Mem[Rsrc + offset / 4][15:0] + + .. note:: + + 注意，以字节为单位指定的偏移量会在执行前被转换为 32 位字偏移量。更多信息请参阅 :ref:`ulp-fsm-addressing`。 + + **示例**:: + + 1: LDH R1, R2, 0x12 // R1 = MEM[R2 + 0x12 / 4] + + 2: .data // Data section definition + Addr1: .word 0x12345678 // Define label Addr1 16 bit + .set offs, 0x00 // Define constant offs + .text // Text section definition + MOVE R1, 1 // R1 = 1 + MOVE R2, Addr1 // R2 = Addr1 / 4 (address of label is converted into words) + LDH R1, R2, offs // R1 = MEM[R2 + 0] + // R1 will be 0x1234 + + +**JUMP** – 跳转到绝对地址 +------------------------------- + +**语法** + + **JUMP** **Rdst** + + **JUMP** **ImmAddr** + + **JUMP** **Rdst, Condition** + + **JUMP** **ImmAddr, Condition** + + +**操作数** + + - **Rdst** – 寄存器 R[0..3] 包含要跳转到的地址（以 32 位字表示） + - **ImmAddr** – 13 位地址（以字节表示），对齐为 4 字节 + - **Condition**： + - EQ – 如果最后的 ALU 操作结果为零，则跳转 + - OV – 如果最后的 ALU 设置了溢出 flag，则跳转 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 2 个周期。 + +**描述** + + 该指令跳转到指定的地址。既可以无条件跳转，也可以基于 ALU flag 跳转。 + +**示例**:: + + 1: JUMP R1 // Jump to address in R1 (address in R1 is in 32-bit words) + + 2: JUMP 0x120, EQ // Jump to address 0x120 (in bytes) if ALU result is zero + + 3: JUMP label // Jump to label + ... + label: nop // Definition of label + + 4: .global label // Declaration of global label + + MOVE R1, label // R1 = label (value loaded into R1 is in words) + JUMP R1 // Jump to label + ... + label: nop // Definition of label + + +**JUMPR** – 跳转到相对偏移（条件基于 R0） +------------------------------------------------------------- + +**语法** + + **JUMPR** **Step, Threshold, Condition** + +**操作数** + + - **Step** – 相对于当前位置的偏移量，以字节为单位 + - **Threshold** – 分支条件的阈值 + - **Condition**： + - **EQ** (等于) – 如果 R0 中的值 == 阈值，则跳转 + - **LT** (小于) – 如果 R0 中的值 < 阈值，则跳转 + - **LE** (小于或等于) – 如果 R0 中的值 <= 阈值，则跳转 + - **GT** (大于) – 如果 R0 中的值 > 阈值，则跳转 + - **GE** (大于或等于) – 如果 R0 中的值 >= 阈值，则跳转 + +**周期** + +.. only:: esp32 + + 条件 **LT**，**GE**，**LE** 和 **GT**：执行需要 2 个周期，获取下一条指令需要 2 个周期。 + + 条件 **LE** 和 **GT** 在汇编程序中用一个 **JUMPR** 指令实现:: + + // JUMPR target, threshold, GT 的实现为： + + JUMPR target, threshold+1, GE + + // JUMPR target, threshold, LE 的实现为： + + JUMPR target, threshold + 1, LT + + 条件 **EQ** 在汇编程序中用两个 **JUMPR** 指令实现:: + + // JUMPR target, threshold, EQ 的实现为： + + JUMPR next, threshold + 1, GE + JUMPR target, threshold, GE + next: + + +.. only:: esp32s2 or esp32s3 + + 条件 **EQ**，**GT** 和 **LT**：执行需要 2 个周期，获取下一条指令需要 2 个周期。 + + 条件 **LE** 和 **GE** 在汇编程序中使用两个 **JUMPR** 指令实现:: + + // JUMPR target, threshold, LE is implemented as: + + JUMPR target, threshold, EQ + JUMPR target, threshold, LT + + // JUMPR target, threshold, GE is implemented as: + + JUMPR target, threshold, EQ + JUMPR target, threshold, GT + + 因此，执行时间取决于所用分支：要么执行 2 个周期 + 获取 2 个周期，要么执行 4 个周期 + 获取 4 个周期。 + + +**描述** + + 如果条件为真，该指令会跳转到相对地址。条件是指 R0 寄存器的值和阈值的比较结果。 + +**示例**:: + + 1:pos: JUMPR 16, 20, GE // Jump to address (position + 16 bytes) if value in R0 >= 20 + + 2: // Down counting loop using R0 register + MOVE R0, 16 // load 16 into R0 + label: SUB R0, R0, 1 // R0-- + NOP // do something + JUMPR label, 1, GE // jump to label if R0 >= 1 + + +**JUMPS** – 跳转到相对地址（条件基于阶段数） +------------------------------------------------------- + +**语法** + + **JUMPS** **步骤, 阈值, 条件** + +**操作数** + + - **步骤** – 相对于当前位置的偏移，以字节为单位 + - **阈值** – 分支条件的阈值 + - **条件**： + - **EQ** (等于) – 如果 stage_cnt == 阈值，则跳转 + - **LT** (小于) – 如果 stage_cnt < 阈值，则跳转 + - **LE** (小于或等于) - 如果 stage_cnt <= 阈值，则跳转 + - **GT** (大于) – 如果 stage_cnt > 阈值，则跳转 + - **GE** (大于或等于) — 如果 stage_cnt >= 阈值，则跳转 + +**周期** + +.. only:: esp32 + + 条件 **LE**, **LT**, **GE**：执行需要 2 个周期，获取下一条指令需要 2 个周期。 + + 条件 **EQ**, **GT** 在汇编程序中用两个 **JUMPS** 指令实现:: + + // JUMPS target, threshold, EQ 的实现为： + + JUMPS next, threshold, LT + JUMPS target, threshold, LE + next: + + // JUMPS target, threshold, GT 的实现为: + + JUMPS next, threshold, LE + JUMPS target, threshold, GE + next: + + 因此，执行时间取决于所用分支：要么执行 2 个周期 + 获取 2 个周期，要么执行 4 个周期 + 获取 4 个周期。 + + +.. only:: esp32s2 or esp32s3 + + 执行需要 2 个周期，获取下一条指令需要 2 个周期。 + + +**描述** + + 如果条件为真，指令将跳转到相对地址。条件是计数寄存器的值和阈值的比较结果。 + +**示例**:: + + 1:pos: JUMPS 16, 20, EQ // Jump to (position + 16 bytes) if stage_cnt == 20 + + 2: // Up counting loop using stage count register + STAGE_RST // set stage_cnt to 0 + label: STAGE_INC 1 // stage_cnt++ + NOP // do something + JUMPS label, 16, LT // jump to label if stage_cnt < 16 + + +**STAGE_RST** – 重置阶段计数寄存器 +------------------------------------------ + +**语法** + + **STAGE_RST** + +**操作数** + + 无操作数 + +**描述** + + 该指令将阶段计数寄存器设置为 0 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**示例**:: + + 1: STAGE_RST // 重置阶段计数寄存器 + + +**STAGE_INC** – 增加阶段计数寄存器 +---------------------------------------------- + +**语法** + + **STAGE_INC** **值** + +**操作数** + + - **值** – 8 位值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期。 + +**描述** + + 该指令将给定值增加到阶段计数寄存 + +**示例**:: + + 1: STAGE_INC 10 // stage_cnt += 10 + + 2: // Up counting loop example: + STAGE_RST // set stage_cnt to 0 + label: STAGE_INC 1 // stage_cnt++ + NOP // do something + JUMPS label, 16, LT // jump to label if stage_cnt < 16 + + +**STAGE_DEC** – 减少阶段计数寄存器 +---------------------------------------------- + +**语法** + + **STAGE_DEC** **值** + +**操作数** + + - **值** – 8 位值 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令从阶段计数寄存器中减去给定值 + +**示例**:: + + 1: STAGE_DEC 10 // stage_cnt -= 10; + + 2: // Down counting loop example + STAGE_RST // set stage_cnt to 0 + STAGE_INC 16 // increment stage_cnt to 16 + label: STAGE_DEC 1 // stage_cnt--; + NOP // do something + JUMPS label, 0, GT // jump to label if stage_cnt > 0 + + +**HALT** – 结束程序 +-------------------------- + +**语法** + + **HALT** + +**操作数** + + 无操作数 + +**周期** + + 执行需要 2 个周期 + +**描述** + + 该指令会停止 ULP 协处理器并重新启动 ULP 唤醒定时器（如果定时器已启用） + +**示例**:: + + 1: HALT // Halt the coprocessor + + +**WAKE** – 唤醒芯片 +--------------------------- + +**语法** + + **WAKE** + +**操作数** + + 无操作数 + +**周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令从 ULP 协处理器向 RTC 控制器发送一个中断。 + + - 如果 SoC 处于深度睡眠模式并启用了 ULP 唤醒，会唤醒 SoC。 + + - 如果 SoC 不处在深度睡眠模式，并且在 RTC_CNTL_INT_ENA_REG 寄存器中设置了 ULP 中断位 (RTC_CNTL_ULP_CP_INT_ENA)，则会触发 RTC 中断。 + +.. note:: + + 注意，在使用 WAKE 指令前，ULP 程序可能需要等待 RTC 控制器就绪，才能唤醒主 CPU。此信息通过 RTC_CNTL_LOW_POWER_ST_REG 寄存器的 RTC_CNTL_RDY_FOR_WAKEUP 位来指示。当 RTC_CNTL_RDY_FOR_WAKEUP 为零时，执行 WAKE 指令唤醒无效。如果希望在主 CPU 不处于睡眠模式时使用 WAKE 指令，可以用 RTC_CNTL_LOW_POWER_ST_REG 的 RTC_CNTL_MAIN_STATE_IN_IDLE 位（位 27）来检查主 CPU 状态，确定其处于正常模式还是睡眠模式。 + +**示例**:: + + 1: is_rdy_for_wakeup: // Read RTC_CNTL_RDY_FOR_WAKEUP bit + READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_RDY_FOR_WAKEUP) + AND r0, r0, 1 + JUMP is_rdy_for_wakeup, eq // Retry until the bit is set + WAKE // Trigger wake up + REG_WR 0x006, 24, 24, 0 // Stop ULP timer (clear RTC_CNTL_ULP_CP_SLP_TIMER_EN) + HALT // Stop the ULP program + // After these instructions, SoC will wake up, + // and ULP will not run again until started by the main program. + + 1: check_wakeup: // Read RTC_CNTL_RDY_FOR_WAKEUP and RTC_CNTL_MAIN_STATE_IN_IDLE bit + READ_RTC_REG(RTC_CNTL_LOW_POWER_ST_REG, 27, 1) + MOVE r1, r0 // Copy result in to r1 + READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_RDY_FOR_WAKEUP) + OR r0, r0, r1 + JUMP check_wakeup, eq // Retry until either of the bit are set + WAKE // Trigger wake up + HALT // Stop the ULP program + + +.. only:: esp32 + + **SLEEP** – 设置 ULP 唤醒计时器周期 + --------------------------------------- + + **语法** + + **SLEEP** **sleep_reg** + + **操作数** + + - **sleep_reg** – 0..4，选择一个 ``SENS_ULP_CP_SLEEP_CYCx_REG`` 寄存器 + + **周期** + + 执行需要 2 个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令决定 ULP 唤醒计时器使用哪一个 ``SENS_ULP_CP_SLEEP_CYCx_REG`` (x = 0..4) 寄存器值作为唤醒周期。默认情况下，使用 ``SENS_ULP_CP_SLEEP_CYC0_REG`` 的值 + + **示例**:: + + 1: SLEEP 1 // Use period set in SENS_ULP_CP_SLEEP_CYC1_REG + + 2: .set sleep_reg, 4 // Set constant + SLEEP sleep_reg // Use period set in SENS_ULP_CP_SLEEP_CYC4_REG + + +**WAIT** – 等待一定的周期数 +------------------------------------- + +**语法** + + **WAIT** **Cycles** + +**操作数** + + - **Cycles** – 等待的周期数 + +**周期** + + 执行需要 (2 + **Cycles**) 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令指示延迟一定的周期数。 + +**示例**:: + + 1: WAIT 10 // Do nothing for 10 cycles + + 2: .set wait_cnt, 10 // Set a constant + WAIT wait_cnt // wait for 10 cycles + +.. only:: not esp32 + + **TSENS** – 使用温度传感器进行测量 + -------------------------------------------- + + **语法** + + - **TSENS** **Rdst, Wait_Delay** + + **操作数** + + - **Rdst** – 目标寄存器 R[0..3]，结果将存储到此寄存器 + - **Wait_Delay** – 执行测量所需的周期数 + + **周期** + + 执行需要（2 + **Wait_Delay** + 3 * TSENS_CLK）个周期，获取下一条指令需要 4 个周期 + + **描述** + + 该指令使用 TSENS 进行测量，并将结果存储到通用寄存器 + + **示例**:: + + 1: TSENS R1, 1000 // Measure temperature sensor for 1000 cycles, + // and store result to R1 + + +**ADC** – 使用 ADC 进行测量 +--------------------------------- + +**语法** + + - **ADC** **Rdst, Sar_sel, Mux** + + - **ADC** **Rdst, Sar_sel, Mux, 0** — 形式已弃用 + +**操作数** + + - **Rdst** – 目标寄存器 R[0..3]，结果将存储到此寄存器 + - **Sar_sel** – 选择 ADC：0 = SARADC1，1 = SARADC2 + +.. only:: esp32 + + - **Mux** - 启用 ADC 通道，通道号为 [Mux-1]。如果传递了 Mux 值 1，会使用 ADC 通道 0。 + +.. only:: esp32s2 or esp32s3 + + - **Mux** - 选择的 PAD，SARADC Pad[Mux-1] 被启用。如果传递了 Mux 值 1，会使用 ADC pad 0。 + +**周期** + + 执行需要 ``23 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SARx_SAMPLE_CYCLE + SARx_SAMPLE_BIT`` 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令通过 ADC 进行测量 + +.. only:: esp32 + + **示例** :: + + 1: ADC R1, 0, 1 // Measure value using ADC1 channel 0 and store result into R1 + +.. only:: esp32s2 or esp32s3 + + **示例** :: + + 1: ADC R1, 0, 1 // Measure value using ADC1 pad 2 and store result into R1 + +.. only:: esp32 + + **I2C_RD** - 从 I2C 从机中读取单字节 + ---------------------------------------------- + + **语法** + + - **I2C_RD** **Sub_addr, High, Low, Slave_sel** + + **操作数** + + - **Sub_addr** – 要从 I2C 从机中读取的地址 + - **High*, *Low** — 定义要读取的位的范围。[High, Low] 以外的位会被屏蔽 + - **Slave_sel** - 要使用的 I2C 从机地址的索引 + + **周期** + + 执行时间主要取决于 I2C 通信时间。获取下一条指令需要 4 个周期 + + **描述** + + ``I2C_RD`` 指令从索引为 ``Slave_sel`` 的 I2C 从机读取一个字节。从机地址（格式为 7 位）必须预先设置到寄存器字段 ``SENS_I2C_SLAVE_ADDRx`` 中，其中 ``x == Slave_sel``。 8 位读取结果存储到 ``R0`` 寄存器。 + + **示例**:: + + 1: I2C_RD 0x10, 7, 0, 0 // Read byte from sub-address 0x10 of slave with address set in SENS_I2C_SLAVE_ADDR0 + + + **I2C_WR** - 向 I2C 从机写入单字节 + ----------------------------------------- + + **语法** + + - **I2C_WR** **Sub_addr, Value, High, Low, Slave_sel** + + **操作数** + + - **Sub_addr** – I2C 从机内要写入的地址 + - **Value** – 要写入的 8 位值 + - **High**, **Low** — 定义要写入的位范围。[High, Low] 范围外的位会被屏蔽 + - **Slave_sel** - 要使用的 I2C 从机地址的索引 + + **周期** + + 执行时间主要取决于 I2C 通信时间。获取下一条指令需要 4 个周期 + + **描述** + + ``I2C_WR`` 指令向索引为 ``Slave_sel`` 的 I2C 从机地址写入一个字节。从机地址（格式为 7 位）必须预先设置到寄存器字段 ``SENS_I2C_SLAVE_ADDRx`` 中，其中 ``x == Slave_sel``。 + + **示例**:: + + 1: I2C_WR 0x20, 0x33, 7, 0, 1 // Write byte 0x33 to sub-address 0x20 of slave with address set in SENS_I2C_SLAVE_ADDR1. + + +**REG_RD** – 从外设寄存器读取 +------------------------------------------ + +**语法** + + **REG_RD** **Addr, High, Low** + +**操作数** + + - **Addr** – 寄存器地址，以 32 位字为单位 + - **High** – 寄存器结束位号 + - **Low** – 寄存器起始位号 + +**周期** + + 执行需要 4 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令从外设寄存器读取最多 16 位到一个通用寄存器：``R0 = REG[Addr][High:Low]``。 + +.. only:: esp32 + + 该指令可以访问 RTC_CNTL、RTC_IO、SENS 和 RTC_I2C 外设中的寄存器。从 ULP 中看到的寄存器地址可以根据 DPORT 总线上相同寄存器的地址计算得出，如下所示:: + + addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 + +.. only:: esp32s2 or esp32s3 + + 该指令可以访问 RTC_CNTL、RTC_IO、SENS 和 RTC_I2C 外设中的寄存器。从 ULP 看到的寄存器地址可以根据 PeriBUS1 总线上相同寄存器的地址计算得出，如下所示:: + + addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4 + +**示例**:: + + 1: REG_RD 0x120, 7, 4 // load 4 bits: R0 = {12'b0, REG[0x120][7:4]} + + +**REG_WR** – 写入外设寄存器 +----------------------------------------- + +**语法** + + **REG_WR** **Addr, High, Low, Data** + +**操作数** + + - **Addr** – 寄存器地址，以 32 位字为单位 + - **High** – 寄存器结束位号 + - **Low** – 寄存器起始位号 + - **Data** – 要写入的值，8 位 + +**周期** + + 执行需要 8 个周期，获取下一条指令需要 4 个周期 + +**描述** + + 该指令将一个立即数的最多 8 位写入到外设寄存器中：``REG[Addr][High:Low] = data``。 + + .. only:: esp32 + + 此指令可以访问 RTC_CNTL、RTC_IO、SENS 和 RTC_I2C 外设中的寄存器。从 ULP 看到的寄存器地址可以根据 DPORT 总线上同一寄存器的地址计算得出，如下所示:: + + addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 + + .. only:: esp32s2 or esp32s3 + + 此指令可以访问 RTC_CNTL 、 RTC_IO 、 SENS 和 RTC_I2C 外设中的寄存器。从 ULP 看到的寄存器地址可以根据 PeriBUS1 上同一寄存器的地址按如下方式计算:: + + addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4 + +**示例**:: + + 1: REG_WR 0x120, 7, 0, 0x10 // set 8 bits: REG[0x120][7:0] = 0x10 + + +方便的外设寄存器访问宏 +-------------------------------------------------- + +ULP 源文件在进入汇编程序之前先通过 C 预处理器，因此可以使用某些宏来方便地访问外设寄存器。 + +一些现有的宏定义在 ``soc/soc_ulp.h`` 头文件中，这些宏允许通过的名称访问外设寄存器的字段。可以通过这些宏使用的外设寄存器名称定义在 ``soc/rtc_cntl_reg.h``、``soc/rtc_io_reg.h``、``soc/sens_reg.h`` 和 ``soc/rtc_i2c_reg.h`` 中。 + +READ_RTC_REG(rtc_reg, low_bit, bit_width) + 将 rtc_reg[low_bit + bit_width - 1 : low_bit] 中的数读到 R0，最多 16 位。如:: + + #include "soc/soc_ulp.h" + #include "soc/rtc_cntl_reg.h" + + /* 将 RTC_CNTL_TIME0_REG 的低 16 位读入 R0 */ + READ_RTC_REG(RTC_CNTL_TIME0_REG, 0, 16) + +READ_RTC_FIELD(rtc_reg, field) + 将 rtc_reg 的一个字段读取到 R0，最多 16 位。如:: + + #include "soc/soc_ulp.h" + #include "soc/sens_reg.h" + + /* 将 SENS_SAR_SLAVE_ADDR3_REG 的 8 位 SENS_TSENS_OUT 字段读入 R0 */ + READ_RTC_FIELD(SENS_SAR_SLAVE_ADDR3_REG, SENS_TSENS_OUT) + +WRITE_RTC_REG(rtc_reg, low_bit, bit_width, value) + 将立即数写入 rtc_reg[low_bit + bit_width - 1 : low_bit]，最多 8 位。如:: + + #include "soc/soc_ulp.h" + #include "soc/rtc_io_reg.h" + + /* 设置 RTC_GPIO_OUT_W1TS_REG 中 RTC_GPIO_OUT_DATA_W1TS 字段的 BIT(2) */ + WRITE_RTC_REG(RTC_GPIO_OUT_W1TS_REG, RTC_GPIO_OUT_DATA_W1TS_S + 2, 1, 1) + +WRITE_RTC_FIELD(rtc_reg, field, value) + 将立即数写入 rtc_reg 的一个字段，最多 8 位。如:: + + #include "soc/soc_ulp.h" + #include "soc/rtc_cntl_reg.h" + + /* 将 RTC_CNTL_STATE0_REG 的 RTC_CNTL_ULP_CP_SLP_TIMER_EN 字段设置为 0 */ + WRITE_RTC_FIELD(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN, 0)