diff --git a/.github/workflows/pre_commit_check.yml b/.github/workflows/pre_commit_check.yml index 859f56780710..d1d51bedaaf0 100644 --- a/.github/workflows/pre_commit_check.yml +++ b/.github/workflows/pre_commit_check.yml @@ -40,3 +40,5 @@ jobs: echo "" exit 1 fi + # Run pre-commit for PowerShell scripts check + pre-commit run --hook-stage manual check-powershell-scripts --from-ref base_ref --to-ref pr_ref --show-diff-on-failure diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 58f42a995a05..fc0403e0c42a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -30,4 +30,5 @@ include: - '.gitlab/ci/integration_test.yml' - '.gitlab/ci/host-test.yml' - '.gitlab/ci/deploy.yml' + - '.gitlab/ci/post_deploy.yml' - '.gitlab/ci/test-win.yml' diff --git a/.gitlab/CODEOWNERS b/.gitlab/CODEOWNERS index e59da32928a2..0d61759339c3 100644 --- a/.gitlab/CODEOWNERS +++ b/.gitlab/CODEOWNERS @@ -170,6 +170,7 @@ /docs/**/api-reference/system/ @esp-idf-codeowners/system /docs/**/security/ @esp-idf-codeowners/security /docs/**/migration-guides/ @esp-idf-codeowners/docs @esp-idf-codeowners/all-maintainers +/docs/**/contribute/install-pre-commit-hook.rst @esp-idf-codeowners/ci @esp-idf-codeowners/tools /examples/README.md @esp-idf-codeowners/docs @esp-idf-codeowners/ci /examples/**/*.py @esp-idf-codeowners/ci @esp-idf-codeowners/tools diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml index d4261990708b..ae74e4165fa0 100644 --- a/.gitlab/ci/build.yml +++ b/.gitlab/ci/build.yml @@ -112,6 +112,22 @@ fast_template_app: BUILD_COMMAND_ARGS: "-p" #------------------------------------------------------------------------------ +####################### +# gnu_static_analyzer # +####################### +gcc_static_analyzer: + extends: + - .build_template_app_template + - .rules:build:target_test + stage: pre_check + tags: [build, shiny] + variables: + CI_CCACHE_DISABLE: 1 + ANALYZING_APP: "examples/get-started/hello_world" + script: + - echo "CONFIG_COMPILER_STATIC_ANALYZER=y" >> ${ANALYZING_APP}/sdkconfig.defaults + - python -m idf_build_apps build -vv -p ${ANALYZING_APP} -t all + ######################################## # Clang Build Apps Without Tests Cases # ######################################## diff --git a/.gitlab/ci/docs.yml b/.gitlab/ci/docs.yml index a7154a630642..5faea6d96be8 100644 --- a/.gitlab/ci/docs.yml +++ b/.gitlab/ci/docs.yml @@ -171,6 +171,7 @@ build_docs_pdf: - job: fast_template_app artifacts: false optional: true + allow_failure: true # TODO IDFCI-2216 artifacts: paths: - docs/_build/*/*/latex/* @@ -182,6 +183,7 @@ build_docs_pdf_prod: - .build_docs_template - .doc-rules:build:docs-full-prod dependencies: [] # Stop build_docs jobs from downloading all previous job's artifacts + allow_failure: true # TODO IDFCI-2216 artifacts: paths: - docs/_build/*/*/latex/* diff --git a/.gitlab/ci/host-test.yml b/.gitlab/ci/host-test.yml index 04e2612f40bd..bd6293a67126 100644 --- a/.gitlab/ci/host-test.yml +++ b/.gitlab/ci/host-test.yml @@ -395,6 +395,6 @@ test_idf_pytest_plugin: junit: XUNIT_RESULT.xml script: - cd ${IDF_PATH}/tools/ci/dynamic_pipelines/tests/test_report_generator - - python -m unittest test_target_test_report_generator.py + - python -m unittest test_report_generator.py - cd ${IDF_PATH}/tools/ci/idf_pytest - pytest --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml diff --git a/.gitlab/ci/post_deploy.yml b/.gitlab/ci/post_deploy.yml new file mode 100644 index 000000000000..0c28b5475118 --- /dev/null +++ b/.gitlab/ci/post_deploy.yml @@ -0,0 +1,12 @@ +generate_failed_jobs_report: + stage: post_deploy + tags: [build, shiny] + image: $ESP_ENV_IMAGE + when: always + artifacts: + expire_in: 1 week + when: always + paths: + - job_report.html + script: + - python tools/ci/dynamic_pipelines/scripts/generate_report.py --report-type job diff --git a/.gitlab/ci/pre_commit.yml b/.gitlab/ci/pre_commit.yml index fbcd965fed7a..49449106e738 100644 --- a/.gitlab/ci/pre_commit.yml +++ b/.gitlab/ci/pre_commit.yml @@ -45,3 +45,36 @@ check_pre_commit: paths: - .cache/submodule_archives policy: pull + +check_powershell: + extends: + - .before_script:minimal + stage: pre_check + image: docker:latest + services: + - docker:dind + tags: + - dind + - amd64 + needs: + - pipeline_variables + variables: + # cache pre_commit + PRE_COMMIT_HOME: "$CI_PROJECT_DIR/.cache/pre-commit" + rules: + - changes: + - "*.ps1" + script: + - apk add python3 + - apk add py3-pip + - pip install pre-commit --break-system-packages + - pre-commit run --hook-stage manual check-powershell-scripts --files $MODIFIED_FILES + cache: + - key: pre_commit-cache-${LATEST_GIT_TAG} + paths: + - .cache/pre-commit + policy: pull + - key: submodule-cache-${LATEST_GIT_TAG} + paths: + - .cache/submodule_archives + policy: pull diff --git a/.gitlab/ci/rules.yml b/.gitlab/ci/rules.yml index 9fab5014d9d8..9cf84cf871f7 100644 --- a/.gitlab/ci/rules.yml +++ b/.gitlab/ci/rules.yml @@ -66,6 +66,8 @@ - "tools/ci/check_esp_memory_utils_headers.sh" - "tools/ci/check_blobs.sh" - "tools/ci/check_public_headers.py" + - "tools/ci/check_register_rw_half_word.cmake" + - "tools/ci/check_register_rw_half_word.py" .patterns-host_test: &patterns-host_test - ".gitlab/ci/host-test.yml" diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 08a5656cd89f..c4f9e8990a74 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -224,6 +224,11 @@ repos: name: shellcheck dash (export.sh) args: ['--shell', 'dash', '-x'] files: 'export.sh' + - repo: https://github.com/espressif/esp-pwsh-check + rev: v1.0.1 + hooks: + - id: check-powershell-scripts + stages: [manual] - repo: https://github.com/espressif/esp-idf-sbom.git rev: v0.13.0 hooks: diff --git a/CMakeLists.txt b/CMakeLists.txt index 722b07b973e6..b381db84844d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -96,7 +96,7 @@ if(CMAKE_C_COMPILER_ID MATCHES "Clang") list(APPEND compile_options "-Wno-pointer-bool-conversion") # mbedTLS md5.c triggers this warning in md5_test_buf (false positive) list(APPEND compile_options "-Wno-string-concatenation") - # multiple cases of implict convertions between unrelated enum types + # multiple cases of implicit conversions between unrelated enum types list(APPEND compile_options "-Wno-enum-conversion") # When IRAM_ATTR is specified both in function declaration and definition, # it produces different section names, since section names include __COUNTER__. @@ -201,10 +201,18 @@ if(CONFIG_COMPILER_DISABLE_GCC13_WARNINGS) "-Wno-dangling-reference") endif() +if(CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS) + if(NOT CMAKE_C_COMPILER_ID MATCHES "Clang") + idf_build_replace_option_from_property(COMPILE_OPTIONS "-Werror" "-Werror=all") + endif() +endif() + # GCC-specific options if(CMAKE_C_COMPILER_ID STREQUAL "GNU") - list(APPEND compile_options "-fstrict-volatile-bitfields" - ) + list(APPEND compile_options "-fstrict-volatile-bitfields") + if(CONFIG_COMPILER_STATIC_ANALYZER) + list(APPEND compile_options "-fanalyzer") + endif() endif() if(CONFIG_ESP_SYSTEM_USE_EH_FRAME) diff --git a/Kconfig b/Kconfig index f99751e7a171..d7240e63290f 100644 --- a/Kconfig +++ b/Kconfig @@ -48,6 +48,10 @@ mainmenu "Espressif IoT Development Framework Configuration" bool default "y" if IDF_TOOLCHAIN="clang" + config IDF_TOOLCHAIN_GCC + bool + default "y" if IDF_TOOLCHAIN="gcc" + config IDF_TARGET_ARCH_RISCV bool default "n" @@ -537,6 +541,20 @@ mainmenu "Espressif IoT Development Framework Configuration" This option can be enabled for RISC-V targets only. + config COMPILER_DISABLE_DEFAULT_ERRORS + bool "Disable errors for default warnings" + default "y" + help + Enable this option if you do not want default warnings to be considered as errors, + especially when updating IDF. + + This is a temporary flag that could help to allow upgrade while having + some time to address the warnings raised by those default warnings. + Alternatives are: + 1) fix code (preferred), + 2) remove specific warnings, + 3) do not consider specific warnings as error. + config COMPILER_DISABLE_GCC12_WARNINGS bool "Disable new warnings introduced in GCC 12" default "n" @@ -606,6 +624,13 @@ mainmenu "Espressif IoT Development Framework Configuration" Places orphan sections without a warning/error message. endchoice + config COMPILER_STATIC_ANALYZER + bool "Enable compiler static analyzer" + default "n" + depends on IDF_TOOLCHAIN_GCC + help + Enable compiler static analyzer. This may produce false-positive results and increases compile time. + endmenu # Compiler Options menu "Component config" diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index ca817d0c6a5e..c318399d963d 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -360,9 +360,9 @@ menu "Bootloader config" # options, allowing to turn on "allow insecure options" and have secure boot with # "skip validation when existing deep sleep". Keeping this to avoid a breaking change, # but - as noted in help - it invalidates the integrity of Secure Boot checks - depends on SOC_RTC_FAST_MEM_SUPPORTED && ((SECURE_BOOT && SECURE_BOOT_INSECURE) || !SECURE_BOOT) + depends on ((SECURE_BOOT && SECURE_BOOT_INSECURE) || !SECURE_BOOT) default n - select BOOTLOADER_RESERVE_RTC_MEM + select BOOTLOADER_RESERVE_RTC_MEM if SOC_RTC_FAST_MEM_SUPPORTED help This option disables the normal validation of an image coming out of deep sleep (checksums, SHA256, and signature). This is a trade-off diff --git a/components/bootloader_support/include/esp_secure_boot.h b/components/bootloader_support/include/esp_secure_boot.h index f15207fd0f1d..93396b1fe332 100644 --- a/components/bootloader_support/include/esp_secure_boot.h +++ b/components/bootloader_support/include/esp_secure_boot.h @@ -63,6 +63,42 @@ extern "C" { #include "esp_efuse_table.h" #endif +/** + * @brief Secure Boot Signature Block Version field + */ +typedef enum { + ESP_SECURE_BOOT_V1_ECDSA = 0, /*!< Secure Boot v1 */ + ESP_SECURE_BOOT_V2_RSA = 2, /*!< Secure Boot v2 with RSA key */ + ESP_SECURE_BOOT_V2_ECDSA = 3, /*!< Secure Boot v2 with ECDSA key */ +} esp_secure_boot_sig_scheme_t; + +#if CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME +#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V1_ECDSA +#elif CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME +#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V2_RSA +#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME +#define ESP_SECURE_BOOT_SCHEME ESP_SECURE_BOOT_V2_ECDSA +#endif + +#if CONFIG_SECURE_BOOT || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT +/** @brief Get the selected secure boot scheme key type + * + * @return key type for the selected secure boot scheme + */ +static inline char* esp_secure_boot_get_scheme_name(esp_secure_boot_sig_scheme_t scheme) +{ + switch (scheme) { + case ESP_SECURE_BOOT_V2_RSA: + return "RSA"; + case ESP_SECURE_BOOT_V1_ECDSA: + case ESP_SECURE_BOOT_V2_ECDSA: + return "ECDSA"; + default: + return "Unknown"; + } +} +#endif + /** @brief Is secure boot currently enabled in hardware? * * This means that the ROM bootloader code will only boot diff --git a/components/bootloader_support/private_include/bootloader_utility.h b/components/bootloader_support/private_include/bootloader_utility.h index 3867ad4778b2..94040cf41a9e 100644 --- a/components/bootloader_support/private_include/bootloader_utility.h +++ b/components/bootloader_support/private_include/bootloader_utility.h @@ -56,9 +56,14 @@ __attribute__((__noreturn__)) void bootloader_utility_load_boot_image(const boot /** * @brief Load that application which was worked before we go to the deep sleep. * + * If chip supports the RTC memory: * Checks the reboot reason if it is the deep sleep and has a valid partition in the RTC memory * then try to load the application which was worked before we go to the deep sleep. * + * If chip does not support the RTC memory: + * Checks the reboot reason if it is the deep sleep then the partition table is read + * to select and load an application which was worked before we go to the deep sleep. + * */ void bootloader_utility_load_boot_image_from_deep_sleep(void); #endif diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index bcd36bc6dc5c..a3654ec3dd31 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -66,19 +66,22 @@ __attribute__((weak)) void bootloader_clock_configure(void) } #endif -//TODO: [ESP32C61] IDF-9274, basic rtc support -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 - // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue - // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader - clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST; -#else // Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader // RTC_FAST clock source will be switched to RC_FAST at application startup clk_cfg.fast_clk_src = rtc_clk_fast_src_get(); if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) { clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV; } + +#if CONFIG_IDF_TARGET_ESP32C6 + if (efuse_hal_chip_revision() == 0) { + // Some of ESP32C6-ECO0 chip's SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue, + // which will cause the chip to be unable to capture the reset reason when it is reset. + // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader + clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST; + } #endif + rtc_clk_init(clk_cfg); } diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index b28aa656aa9c..4e469b40183e 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -461,15 +461,33 @@ static void set_actual_ota_seq(const bootloader_state_t *bs, int index) void bootloader_utility_load_boot_image_from_deep_sleep(void) { if (esp_rom_get_reset_reason(0) == RESET_REASON_CORE_DEEP_SLEEP) { +#if SOC_RTC_FAST_MEM_SUPPORTED esp_partition_pos_t *partition = bootloader_common_get_rtc_retain_mem_partition(); - if (partition != NULL) { + esp_image_metadata_t image_data; + if (partition != NULL && bootloader_load_image_no_verify(partition, &image_data) == ESP_OK) { + ESP_LOGI(TAG, "Fast booting app from partition at offset 0x%"PRIx32, partition->offset); + bootloader_common_update_rtc_retain_mem(NULL, true); + load_image(&image_data); + } +#else // !SOC_RTC_FAST_MEM_SUPPORTED + bootloader_state_t bs = {0}; + if (bootloader_utility_load_partition_table(&bs)) { + int index_of_last_loaded_app = FACTORY_INDEX; + esp_ota_select_entry_t otadata[2]; + if (bs.ota_info.size && bootloader_common_read_otadata(&bs.ota_info, otadata) == ESP_OK) { + int active_otadata = bootloader_common_get_active_otadata(otadata); + if (active_otadata != -1) { + index_of_last_loaded_app = (otadata[active_otadata].ota_seq - 1) % bs.app_count; + } + } + esp_partition_pos_t partition = index_to_partition(&bs, index_of_last_loaded_app); esp_image_metadata_t image_data; - if (bootloader_load_image_no_verify(partition, &image_data) == ESP_OK) { - ESP_LOGI(TAG, "Fast booting app from partition at offset 0x%"PRIx32, partition->offset); - bootloader_common_update_rtc_retain_mem(NULL, true); + if (partition.size && bootloader_load_image_no_verify(&partition, &image_data) == ESP_OK) { + ESP_LOGI(TAG, "Fast booting app from partition at offset 0x%"PRIx32, partition.offset); load_image(&image_data); } } +#endif // !SOC_RTC_FAST_MEM_SUPPORTED ESP_LOGE(TAG, "Fast booting is not successful"); ESP_LOGI(TAG, "Try to load an app as usual with all validations"); } diff --git a/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_app.c b/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_app.c index e62e881a6679..054adff3d35e 100644 --- a/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_app.c +++ b/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_app.c @@ -70,7 +70,7 @@ esp_err_t esp_secure_boot_verify_ecdsa_signature_block(const esp_secure_boot_sig return ESP_FAIL; } - if (sig_block->version != 0) { + if (sig_block->version != ESP_SECURE_BOOT_SCHEME) { ESP_LOGE(TAG, "image has invalid signature version field 0x%08"PRIx32" (image without a signature?)", sig_block->version); return ESP_FAIL; } diff --git a/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_bootloader.c b/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_bootloader.c index ef39baee03c2..9118f1c65d17 100644 --- a/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_bootloader.c +++ b/components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_bootloader.c @@ -69,7 +69,7 @@ esp_err_t esp_secure_boot_verify_ecdsa_signature_block(const esp_secure_boot_sig return ESP_FAIL; } - if (sig_block->version != 0) { + if (sig_block->version != ESP_SECURE_BOOT_SCHEME) { ESP_LOGE(TAG, "image has invalid signature version field 0x%08" PRIx32 " (image without a signature?)", sig_block->version); return ESP_FAIL; } diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot.c b/components/bootloader_support/src/secure_boot_v2/secure_boot.c index a7de5d439dea..c9d58ebee651 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot.c +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c index fc2aed1792de..8dc886e67d5d 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_app.c @@ -44,6 +44,10 @@ static esp_err_t validate_signature_block(const ets_secure_boot_sig_block_t *blo || block->block_crc != esp_rom_crc32_le(0, (uint8_t *)block, CRC_SIGN_BLOCK_LEN)) { return ESP_FAIL; } + if (block->version != ESP_SECURE_BOOT_SCHEME) { + ESP_LOGE(TAG, "%s signing scheme selected but signature block generated for %s scheme", esp_secure_boot_get_scheme_name(ESP_SECURE_BOOT_SCHEME), esp_secure_boot_get_scheme_name(block->version)); + return ESP_FAIL; + } return ESP_OK; } diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c index a32900388669..a6537078459f 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c @@ -61,6 +61,10 @@ static esp_err_t validate_signature_block(const ets_secure_boot_sig_block_t *blo || block->block_crc != esp_rom_crc32_le(0, (uint8_t *)block, CRC_SIGN_BLOCK_LEN)) { return ESP_FAIL; } + if (block->version != ESP_SECURE_BOOT_SCHEME) { + ESP_LOGE(TAG, "%s signing scheme selected but signature block generated for %s scheme", esp_secure_boot_get_scheme_name(ESP_SECURE_BOOT_SCHEME), esp_secure_boot_get_scheme_name(block->version)); + return ESP_FAIL; + } return ESP_OK; } @@ -148,9 +152,21 @@ esp_err_t esp_secure_boot_verify_sbv2_signature_block(const ets_secure_boot_sign int sb_result = ets_secure_boot_verify_signature(sig_block, image_digest, trusted.key_digests[0], verified_digest); #else ets_secure_boot_key_digests_t trusted_key_digests = {0}; + bool valid_sig_blk = false; for (unsigned i = 0; i < SECURE_BOOT_NUM_BLOCKS; i++) { + if (sig_block->block[i].version != ESP_SECURE_BOOT_SCHEME) { + ESP_LOGD(TAG, "%s signing scheme selected but signature block %d generated for %s scheme", esp_secure_boot_get_scheme_name(ESP_SECURE_BOOT_SCHEME), i, esp_secure_boot_get_scheme_name(sig_block->block[i].version)); + continue; + } else { + valid_sig_blk = true; + } trusted_key_digests.key_digests[i] = &trusted.key_digests[i]; } + if (valid_sig_blk != true) { + ESP_LOGE(TAG, "No signature block generated for valid scheme"); + ESP_LOGE(TAG, "%s signing scheme selected but no signature block for the selected scheme", esp_secure_boot_get_scheme_name(ESP_SECURE_BOOT_SCHEME)); + return ESP_FAIL; + } // Key revocation happens in ROM bootloader. // Do NOT allow key revocation while verifying application diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index d32a6d372cbb..6dd5ef9b3780 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -575,7 +575,7 @@ if(CONFIG_BT_ENABLED) if(CONFIG_BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT) list(APPEND srcs "porting/npl/freertos/src/npl_os_freertos.c" - "porting/nimble/src/os_msys_init.c" + "porting/mem/os_msys_init.c" ) if(CONFIG_BT_CONTROLLER_DISABLED) @@ -585,7 +585,6 @@ if(CONFIG_BT_ENABLED) endif() list(APPEND include_dirs porting/include - porting/nimble/include porting/npl/freertos/include porting/transport/include ) @@ -727,7 +726,6 @@ if(CONFIG_BT_ENABLED) "host/nimble/port/src/nvs_port.c" ) list(APPEND include_dirs - porting/include host/nimble/nimble/porting/nimble/include host/nimble/port/include host/nimble/nimble/nimble/transport/include @@ -756,9 +754,8 @@ if(CONFIG_BT_ENABLED) endif() list(APPEND include_dirs + porting/include host/nimble/nimble/porting/npl/freertos/include - host/nimble/nimble/porting/nimble/include - host/nimble/nimble/nimble/include ) endif() diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c index 38ae519a56d6..29c3332604bd 100644 --- a/components/bt/controller/esp32c2/bt.c +++ b/components/bt/controller/esp32c2/bt.c @@ -16,7 +16,10 @@ #include "sdkconfig.h" +#if CONFIG_BT_NIMBLE_ENABLED #include "nimble/nimble_port.h" +#endif // CONFIG_BT_NIMBLE_ENABLED + #include "nimble/nimble_port_freertos.h" #ifdef ESP_PLATFORM @@ -28,7 +31,7 @@ #endif #include "nimble/nimble_npl_os.h" -#include "nimble/ble_hci_trans.h" +#include "ble_hci_trans.h" #include "os/endian.h" #include "esp_bt.h" diff --git a/components/bt/controller/esp32c5/bt.c b/components/bt/controller/esp32c5/bt.c index 7e13c7124c99..17794564355e 100644 --- a/components/bt/controller/esp32c5/bt.c +++ b/components/bt/controller/esp32c5/bt.c @@ -15,7 +15,9 @@ #include "sdkconfig.h" +#if CONFIG_BT_NIMBLE_ENABLED #include "nimble/nimble_port.h" +#endif // CONFIG_BT_NIMBLE_ENABLED #include "nimble/nimble_port_freertos.h" #include "esp_private/esp_modem_clock.h" @@ -28,7 +30,7 @@ #endif // CONFIG_SW_COEXIST_ENABLE #include "nimble/nimble_npl_os.h" -#include "nimble/ble_hci_trans.h" +#include "ble_hci_trans.h" #include "os/endian.h" #include "esp_bt.h" @@ -121,7 +123,7 @@ typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end); ************************************************************************ */ extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs); -extern int ble_controller_init(esp_bt_controller_config_t *cfg); +extern int r_ble_controller_init(esp_bt_controller_config_t *cfg); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED extern int r_ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size); extern int r_ble_log_deinit_async(void); @@ -129,12 +131,12 @@ extern void r_ble_log_async_select_dump_buffers(uint8_t buffers); extern void r_ble_log_async_output_dump_all(bool output); extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED -extern int ble_controller_deinit(void); -extern int ble_controller_enable(uint8_t mode); -extern int ble_controller_disable(void); +extern int r_ble_controller_deinit(void); +extern int r_ble_controller_enable(uint8_t mode); +extern int r_ble_controller_disable(void); extern int esp_register_ext_funcs (struct ext_funcs_t *); extern void esp_unregister_ext_funcs (void); -extern int esp_ble_ll_set_public_addr(const uint8_t *addr); +extern int r_esp_ble_ll_set_public_addr(const uint8_t *addr); extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func); extern void esp_unregister_npl_funcs (void); extern void npl_freertos_mempool_deinit(void); @@ -149,15 +151,17 @@ extern void os_msys_deinit(void); extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra); extern void esp_ble_set_wakeup_overhead(uint32_t overhead); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ -extern void esp_ble_change_rtc_freq(uint32_t freq); +extern void r_esp_ble_change_rtc_freq(uint32_t freq); extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, const uint8_t *our_priv_key, uint8_t *out_dhkey); extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv); -extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); -extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); +extern int r_ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); +extern int r_ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); +extern int r_ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); extern char *ble_controller_get_compile_version(void); +extern int esp_ble_register_bb_funcs(void); +extern void esp_ble_unregister_bb_funcs(void); extern uint32_t _bt_bss_start; extern uint32_t _bt_bss_end; extern uint32_t _bt_controller_bss_start; @@ -723,7 +727,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) goto free_mem; } - ble_get_npl_element_info(cfg, &npl_info); + r_ble_get_npl_element_info(cfg, &npl_info); npl_freertos_set_controller_npl_info(&npl_info); if (npl_freertos_mempool_init() != 0) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed"); @@ -780,13 +784,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) coex_init(); #endif // CONFIG_SW_COEXIST_ENABLE - ret = ble_controller_init(cfg); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); - goto modem_deint; - } - - ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version()); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED interface_func_t bt_controller_log_interface; bt_controller_log_interface = esp_bt_controller_log_interface; @@ -804,11 +801,23 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) #endif // CONFIG_BT_CONTROLLER_LOG_DUMP if (ret != ESP_OK) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret); - goto controller_init_err; + goto modem_deint; } #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED + ret = esp_ble_register_bb_funcs(); + if (ret != ESP_OK) { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "esp_ble_register_bb_funcs failed %d", ret); + goto modem_deint; + } + + ret = r_ble_controller_init(cfg); + if (ret != ESP_OK) { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "r_ble_controller_init failed %d", ret); + goto modem_deint; + } - esp_ble_change_rtc_freq(slow_clk_freq); + ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version()); + r_esp_ble_change_rtc_freq(slow_clk_freq); ble_controller_scan_duplicate_config(); @@ -825,7 +834,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) } ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT)); swap_in_place(mac, 6); - esp_ble_ll_set_public_addr(mac); + r_esp_ble_ll_set_public_addr(mac); ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; @@ -835,13 +844,13 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) free_controller: controller_sleep_deinit(); + os_msys_deinit(); + r_ble_controller_deinit(); +modem_deint: + esp_ble_unregister_bb_funcs(); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED -controller_init_err: r_ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED - os_msys_deinit(); - ble_controller_deinit(); -modem_deint: esp_phy_modem_deinit(); // modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE); modem_clock_module_disable(PERIPH_BT_MODULE); @@ -872,10 +881,11 @@ esp_err_t esp_bt_controller_deinit(void) // modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE); modem_clock_module_disable(PERIPH_BT_MODULE); + r_ble_controller_deinit(); + esp_ble_unregister_bb_funcs(); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED r_ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED - ble_controller_deinit(); #if CONFIG_BT_NIMBLE_ENABLED /* De-initialize default event queue */ @@ -920,7 +930,7 @@ esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode) coex_enable(); #endif // CONFIG_SW_COEXIST_ENABLE - if (ble_controller_enable(mode) != 0) { + if (r_ble_controller_enable(mode) != 0) { ret = ESP_FAIL; goto error; } @@ -948,7 +958,7 @@ esp_err_t esp_bt_controller_disable(void) ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); return ESP_FAIL; } - if (ble_controller_disable() != 0) { + if (r_ble_controller_disable() != 0) { return ESP_FAIL; } #if CONFIG_SW_COEXIST_ENABLE @@ -1082,7 +1092,7 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ case ESP_BLE_PWR_TYPE_DEFAULT: case ESP_BLE_PWR_TYPE_ADV: case ESP_BLE_PWR_TYPE_SCAN: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; @@ -1095,7 +1105,7 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ case ESP_BLE_PWR_TYPE_CONN_HDL6: case ESP_BLE_PWR_TYPE_CONN_HDL7: case ESP_BLE_PWR_TYPE_CONN_HDL8: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { stat = ESP_OK; } break; @@ -1115,13 +1125,13 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - if (ble_txpwr_set(power_type, handle, power_level) == 0) { + if (r_ble_txpwr_set(power_type, handle, power_level) == 0) { stat = ESP_OK; } break; @@ -1141,7 +1151,7 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) case ESP_BLE_PWR_TYPE_ADV: case ESP_BLE_PWR_TYPE_SCAN: case ESP_BLE_PWR_TYPE_DEFAULT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: @@ -1152,7 +1162,7 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) case ESP_BLE_PWR_TYPE_CONN_HDL6: case ESP_BLE_PWR_TYPE_CONN_HDL7: case ESP_BLE_PWR_TYPE_CONN_HDL8: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); break; default: return ESP_PWR_LVL_INVALID; @@ -1174,11 +1184,11 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - tx_level = ble_txpwr_get(power_type, handle); + tx_level = r_ble_txpwr_get(power_type, handle); break; default: return ESP_PWR_LVL_INVALID; diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index ed005edc70d6..489327f02810 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -15,7 +15,9 @@ #include "sdkconfig.h" +#if CONFIG_BT_NIMBLE_ENABLED #include "nimble/nimble_port.h" +#endif // CONFIG_BT_NIMBLE_ENABLED #include "nimble/nimble_port_freertos.h" #include "esp_private/esp_modem_clock.h" @@ -28,7 +30,7 @@ #endif // CONFIG_ESP_COEX_ENABLED #include "nimble/nimble_npl_os.h" -#include "nimble/ble_hci_trans.h" +#include "ble_hci_trans.h" #include "os/endian.h" #include "esp_bt.h" @@ -123,7 +125,7 @@ typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end); ************************************************************************ */ extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs); -extern int ble_controller_init(esp_bt_controller_config_t *cfg); +extern int r_ble_controller_init(esp_bt_controller_config_t *cfg); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED extern int r_ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size); extern int r_ble_log_deinit_async(void); @@ -131,12 +133,12 @@ extern void r_ble_log_async_select_dump_buffers(uint8_t buffers); extern void r_ble_log_async_output_dump_all(bool output); extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED -extern int ble_controller_deinit(void); -extern int ble_controller_enable(uint8_t mode); -extern int ble_controller_disable(void); +extern int r_ble_controller_deinit(void); +extern int r_ble_controller_enable(uint8_t mode); +extern int r_ble_controller_disable(void); extern int esp_register_ext_funcs (struct ext_funcs_t *); extern void esp_unregister_ext_funcs (void); -extern int esp_ble_ll_set_public_addr(const uint8_t *addr); +extern int r_esp_ble_ll_set_public_addr(const uint8_t *addr); extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func); extern void esp_unregister_npl_funcs (void); extern void npl_freertos_mempool_deinit(void); @@ -149,17 +151,19 @@ extern int os_msys_init(void); extern void os_msys_deinit(void); #if CONFIG_FREERTOS_USE_TICKLESS_IDLE extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra); -extern void esp_ble_set_wakeup_overhead(uint32_t overhead); +extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead); #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ -extern void esp_ble_change_rtc_freq(uint32_t freq); +extern void r_esp_ble_change_rtc_freq(uint32_t freq); extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, const uint8_t *our_priv_key, uint8_t *out_dhkey); extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv); -extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); -extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); +extern int r_ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); +extern int r_ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); +extern int r_ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); extern char *ble_controller_get_compile_version(void); +extern int esp_ble_register_bb_funcs(void); +extern void esp_ble_unregister_bb_funcs(void); extern uint32_t _bt_bss_start; extern uint32_t _bt_bss_end; extern uint32_t _bt_controller_bss_start; @@ -551,7 +555,7 @@ static void sleep_modem_ble_mac_modem_state_deinit(void) void sleep_modem_light_sleep_overhead_set(uint32_t overhead) { - esp_ble_set_wakeup_overhead(overhead); + r_esp_ble_set_wakeup_overhead(overhead); } #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ @@ -577,6 +581,9 @@ esp_err_t controller_sleep_init(void) goto error; } #if CONFIG_FREERTOS_USE_TICKLESS_IDLE +#if CONFIG_BT_LE_SLEEP_ENABLE && !CONFIG_MAC_BB_PD +#error "CONFIG_MAC_BB_PD required for BLE light sleep to run properly" +#endif // CONFIG_BT_LE_SLEEP_ENABLE && !CONFIG_MAC_BB_PD /* Create a new regdma link for BLE related register restoration */ rc = sleep_modem_ble_mac_modem_state_init(1); assert(rc == 0); @@ -744,7 +751,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) goto free_mem; } - ble_get_npl_element_info(cfg, &npl_info); + r_ble_get_npl_element_info(cfg, &npl_info); npl_freertos_set_controller_npl_info(&npl_info); if (npl_freertos_mempool_init() != 0) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed"); @@ -821,14 +828,20 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) goto modem_deint; } #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED - ret = ble_controller_init(cfg); + ret = esp_ble_register_bb_funcs(); + if (ret != ESP_OK) { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "esp_ble_register_bb_funcs failed %d", ret); + goto modem_deint; + } + + ret = r_ble_controller_init(cfg); if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "r_ble_controller_init failed %d", ret); goto modem_deint; } ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version()); - esp_ble_change_rtc_freq(slow_clk_freq); + r_esp_ble_change_rtc_freq(slow_clk_freq); ble_controller_scan_duplicate_config(); @@ -845,7 +858,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) } ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT)); swap_in_place(mac, 6); - esp_ble_ll_set_public_addr(mac); + r_esp_ble_ll_set_public_addr(mac); ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; @@ -856,8 +869,9 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) free_controller: controller_sleep_deinit(); os_msys_deinit(); - ble_controller_deinit(); + r_ble_controller_deinit(); modem_deint: + esp_ble_unregister_bb_funcs(); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED r_ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED @@ -891,7 +905,8 @@ esp_err_t esp_bt_controller_deinit(void) modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE); modem_clock_module_disable(PERIPH_BT_MODULE); - ble_controller_deinit(); + r_ble_controller_deinit(); + esp_ble_unregister_bb_funcs(); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED r_ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED @@ -939,7 +954,7 @@ esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode) coex_enable(); #endif // CONFIG_SW_COEXIST_ENABLE - if (ble_controller_enable(mode) != 0) { + if (r_ble_controller_enable(mode) != 0) { ret = ESP_FAIL; goto error; } @@ -967,7 +982,7 @@ esp_err_t esp_bt_controller_disable(void) ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); return ESP_FAIL; } - if (ble_controller_disable() != 0) { + if (r_ble_controller_disable() != 0) { return ESP_FAIL; } #if CONFIG_SW_COEXIST_ENABLE @@ -1101,7 +1116,7 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ case ESP_BLE_PWR_TYPE_DEFAULT: case ESP_BLE_PWR_TYPE_ADV: case ESP_BLE_PWR_TYPE_SCAN: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; @@ -1114,7 +1129,7 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ case ESP_BLE_PWR_TYPE_CONN_HDL6: case ESP_BLE_PWR_TYPE_CONN_HDL7: case ESP_BLE_PWR_TYPE_CONN_HDL8: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { stat = ESP_OK; } break; @@ -1134,13 +1149,13 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - if (ble_txpwr_set(power_type, handle, power_level) == 0) { + if (r_ble_txpwr_set(power_type, handle, power_level) == 0) { stat = ESP_OK; } break; @@ -1160,7 +1175,7 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) case ESP_BLE_PWR_TYPE_ADV: case ESP_BLE_PWR_TYPE_SCAN: case ESP_BLE_PWR_TYPE_DEFAULT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: @@ -1171,7 +1186,7 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) case ESP_BLE_PWR_TYPE_CONN_HDL6: case ESP_BLE_PWR_TYPE_CONN_HDL7: case ESP_BLE_PWR_TYPE_CONN_HDL8: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); break; default: return ESP_PWR_LVL_INVALID; @@ -1193,11 +1208,11 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - tx_level = ble_txpwr_get(power_type, handle); + tx_level = r_ble_txpwr_get(power_type, handle); break; default: return ESP_PWR_LVL_INVALID; diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 248b2058ac03..adb10d4981f5 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -15,7 +15,9 @@ #include "sdkconfig.h" +#if CONFIG_BT_NIMBLE_ENABLED #include "nimble/nimble_port.h" +#endif // CONFIG_BT_NIMBLE_ENABLED #include "nimble/nimble_port_freertos.h" #include "esp_private/esp_modem_clock.h" @@ -28,7 +30,7 @@ #endif // CONFIG_ESP_COEX_ENABLED #include "nimble/nimble_npl_os.h" -#include "nimble/ble_hci_trans.h" +#include "ble_hci_trans.h" #include "os/endian.h" #include "esp_bt.h" @@ -59,8 +61,8 @@ ************************************************************************ */ #define NIMBLE_PORT_LOG_TAG "BLE_INIT" -#define OSI_COEX_VERSION 0x00010006 -#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD +#define OSI_COEX_VERSION 0x00010006 +#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD #define EXT_FUNC_VERSION 0x20221122 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 @@ -115,7 +117,7 @@ typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end); ************************************************************************ */ extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs); -extern int ble_controller_init(esp_bt_controller_config_t *cfg); +extern int r_ble_controller_init(esp_bt_controller_config_t *cfg); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED extern int r_ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size); extern int r_ble_log_deinit_async(void); @@ -123,35 +125,37 @@ extern void r_ble_log_async_select_dump_buffers(uint8_t buffers); extern void r_ble_log_async_output_dump_all(bool output); extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED -extern int ble_controller_deinit(void); -extern int ble_controller_enable(uint8_t mode); -extern int ble_controller_disable(void); +extern int r_ble_controller_deinit(void); +extern int r_ble_controller_enable(uint8_t mode); +extern int r_ble_controller_disable(void); extern int esp_register_ext_funcs (struct ext_funcs_t *); extern void esp_unregister_ext_funcs (void); -extern int esp_ble_ll_set_public_addr(const uint8_t *addr); +extern int r_esp_ble_ll_set_public_addr(const uint8_t *addr); extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func); extern void esp_unregister_npl_funcs (void); extern void npl_freertos_mempool_deinit(void); extern uint32_t r_os_cputime_get32(void); extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks); -#if CONFIG_FREERTOS_USE_TICKLESS_IDLE -extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra); -extern void esp_ble_set_wakeup_overhead(uint32_t overhead); -#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ -extern void esp_ble_change_rtc_freq(uint32_t freq); extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg, uint32_t us_to_enabled); extern void r_ble_rtc_wake_up_state_clr(void); extern int os_msys_init(void); extern void os_msys_deinit(void); +#if CONFIG_FREERTOS_USE_TICKLESS_IDLE +extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra); +extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead); +#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ +extern void r_esp_ble_change_rtc_freq(uint32_t freq); extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, const uint8_t *our_priv_key, uint8_t *out_dhkey); extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv); -extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); -extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); +extern int r_ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); +extern int r_ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); +extern int r_ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); extern char *ble_controller_get_compile_version(void); +extern int esp_ble_register_bb_funcs(void); +extern void esp_ble_unregister_bb_funcs(void); extern uint32_t _bt_bss_start; extern uint32_t _bt_bss_end; extern uint32_t _bt_controller_bss_start; @@ -538,9 +542,10 @@ static void sleep_modem_ble_mac_modem_state_deinit(void) void sleep_modem_light_sleep_overhead_set(uint32_t overhead) { - esp_ble_set_wakeup_overhead(overhead); + r_esp_ble_set_wakeup_overhead(overhead); } -#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE +#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */ + esp_err_t controller_sleep_init(void) { @@ -716,7 +721,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) goto free_mem; } - ble_get_npl_element_info(cfg, &npl_info); + r_ble_get_npl_element_info(cfg, &npl_info); npl_freertos_set_controller_npl_info(&npl_info); if (npl_freertos_mempool_init() != 0) { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed"); @@ -730,10 +735,10 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) */ ble_npl_eventq_init(nimble_port_get_dflt_eventq()); #endif // CONFIG_BT_NIMBLE_ENABLED - /* Enable BT-related clocks */ modem_clock_module_enable(PERIPH_BT_MODULE); modem_clock_module_mac_reset(PERIPH_BT_MODULE); + /* Select slow clock source for BT momdule */ #if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL); slow_clk_freq = 100000; @@ -771,6 +776,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) #if CONFIG_SW_COEXIST_ENABLE coex_init(); #endif // CONFIG_SW_COEXIST_ENABLE + #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED interface_func_t bt_controller_log_interface; bt_controller_log_interface = esp_bt_controller_log_interface; @@ -791,16 +797,20 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) goto modem_deint; } #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED + ret = esp_ble_register_bb_funcs(); + if (ret != ESP_OK) { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "esp_ble_register_bb_funcs failed %d", ret); + goto modem_deint; + } - ret = ble_controller_init(cfg); + ret = r_ble_controller_init(cfg); if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "r_ble_controller_init failed %d", ret); goto modem_deint; } ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version()); - - esp_ble_change_rtc_freq(slow_clk_freq); + r_esp_ble_change_rtc_freq(slow_clk_freq); ble_controller_scan_duplicate_config(); @@ -815,10 +825,9 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret); goto free_controller; } - ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT)); swap_in_place(mac, 6); - esp_ble_ll_set_public_addr(mac); + r_esp_ble_ll_set_public_addr(mac); ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; @@ -829,8 +838,9 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) free_controller: controller_sleep_deinit(); os_msys_deinit(); - ble_controller_deinit(); + r_ble_controller_deinit(); modem_deint: + esp_ble_unregister_bb_funcs(); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED r_ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED @@ -862,7 +872,8 @@ esp_err_t esp_bt_controller_deinit(void) modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE); modem_clock_module_disable(PERIPH_BT_MODULE); - ble_controller_deinit(); + r_ble_controller_deinit(); + esp_ble_unregister_bb_funcs(); #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED r_ble_log_deinit_async(); #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED @@ -910,7 +921,7 @@ esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode) coex_enable(); #endif // CONFIG_SW_COEXIST_ENABLE - if (ble_controller_enable(mode) != 0) { + if (r_ble_controller_enable(mode) != 0) { ret = ESP_FAIL; goto error; } @@ -938,7 +949,7 @@ esp_err_t esp_bt_controller_disable(void) ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); return ESP_FAIL; } - if (ble_controller_disable() != 0) { + if (r_ble_controller_disable() != 0) { return ESP_FAIL; } #if CONFIG_SW_COEXIST_ENABLE @@ -1072,7 +1083,7 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ case ESP_BLE_PWR_TYPE_DEFAULT: case ESP_BLE_PWR_TYPE_ADV: case ESP_BLE_PWR_TYPE_SCAN: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; @@ -1085,7 +1096,7 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ case ESP_BLE_PWR_TYPE_CONN_HDL6: case ESP_BLE_PWR_TYPE_CONN_HDL7: case ESP_BLE_PWR_TYPE_CONN_HDL8: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { stat = ESP_OK; } break; @@ -1105,13 +1116,13 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - if (ble_txpwr_set(power_type, handle, power_level) == 0) { + if (r_ble_txpwr_set(power_type, handle, power_level) == 0) { stat = ESP_OK; } break; @@ -1131,7 +1142,7 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) case ESP_BLE_PWR_TYPE_ADV: case ESP_BLE_PWR_TYPE_SCAN: case ESP_BLE_PWR_TYPE_DEFAULT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: @@ -1142,7 +1153,7 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) case ESP_BLE_PWR_TYPE_CONN_HDL6: case ESP_BLE_PWR_TYPE_CONN_HDL7: case ESP_BLE_PWR_TYPE_CONN_HDL8: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); break; default: return ESP_PWR_LVL_INVALID; @@ -1164,11 +1175,11 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - tx_level = ble_txpwr_get(power_type, handle); + tx_level = r_ble_txpwr_get(power_type, handle); break; default: return ESP_PWR_LVL_INVALID; diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32 index a4d7731a95db..405cac4cba9c 160000 --- a/components/bt/controller/lib_esp32 +++ b/components/bt/controller/lib_esp32 @@ -1 +1 @@ -Subproject commit a4d7731a95db8a6cfb98e5068b6757c32ecfaa2a +Subproject commit 405cac4cba9c010ed2f378d7f202f62a3bee8f7a diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index 3878fc3d687e..8ddd8acac498 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit 3878fc3d687ed70798952e25bdb2514e023d80dc +Subproject commit 8ddd8acac498fcbb76b5a39c5c7d4025238298ab diff --git a/components/bt/controller/lib_esp32c5/esp32c5-bt-lib b/components/bt/controller/lib_esp32c5/esp32c5-bt-lib index 45dda7a690af..3996803d35bc 160000 --- a/components/bt/controller/lib_esp32c5/esp32c5-bt-lib +++ b/components/bt/controller/lib_esp32c5/esp32c5-bt-lib @@ -1 +1 @@ -Subproject commit 45dda7a690af994e8e6a41cc3b029506335d169f +Subproject commit 3996803d35bcb79283bb7dcff60a11092339a838 diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib index 405de6817353..c2b9d7c8c2ab 160000 --- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib +++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib @@ -1 +1 @@ -Subproject commit 405de68173533500319e9e2eb1c5bb13ca0a60f5 +Subproject commit c2b9d7c8c2ab4872ffe4f0501c4753fcbc96ba48 diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib index 586a22726421..c2c9f4161f2e 160000 --- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib +++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib @@ -1 +1 @@ -Subproject commit 586a22726421eff1bf1bd6e57f378de1f51b8f72 +Subproject commit c2c9f4161f2ed200dbbcec71fbfd26da0241f376 diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h index ea52baf00e54..75fd3419e6e6 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h @@ -661,21 +661,55 @@ typedef struct { esp_bt_octet16_t oob_r; /*!< the 128 bits of randomizer value */ } esp_ble_local_oob_data_t; +/** +* @brief Definition of the authentication failed reason +*/ +typedef enum { + // Failure reason defined in Bluetooth Core Spec 5.0 Vol3, Part H, 3.5.5 + ESP_AUTH_SMP_PASSKEY_FAIL = 78, /*!< The user input of passkey failed */ + ESP_AUTH_SMP_OOB_FAIL, /*!< The OOB data is not available */ + ESP_AUTH_SMP_PAIR_AUTH_FAIL, /*!< The authentication requirements cannot be met */ + ESP_AUTH_SMP_CONFIRM_VALUE_FAIL, /*!< The confirm value does not match the calculated comparison value */ + ESP_AUTH_SMP_PAIR_NOT_SUPPORT, /*!< Pairing is not supported by the device */ + ESP_AUTH_SMP_ENC_KEY_SIZE, /*!< The resultant encryption key size is not long enough */ + ESP_AUTH_SMP_INVALID_CMD, /*!< The SMP command received is not supported by this device */ + ESP_AUTH_SMP_UNKNOWN_ERR, /*!< Pairing failed due to an unspecified reason */ + ESP_AUTH_SMP_REPEATED_ATTEMPT, /*!< Pairing or authentication procedure is disallowed */ + ESP_AUTH_SMP_INVALID_PARAMETERS, /*!< The command length is invalid or that a parameter is outside the specified range */ + ESP_AUTH_SMP_DHKEY_CHK_FAIL, /*!< The DHKey Check value received doesn’t match the one calculated by the local device */ + ESP_AUTH_SMP_NUM_COMP_FAIL, /*!< The confirm values in the numeric comparison protocol do not match */ + ESP_AUTH_SMP_BR_PARING_IN_PROGR, /*!< Pairing Request sent over the BR/EDR transport is in progress */ + ESP_AUTH_SMP_XTRANS_DERIVE_NOT_ALLOW, /*!< The BR/EDR Link Key or BLE LTK cannot be used to derive */ + + // Failure reason defined in Bluedroid Host + ESP_AUTH_SMP_INTERNAL_ERR, /*!< Internal error in pairing procedure */ + ESP_AUTH_SMP_UNKNOWN_IO, /*!< Unknown IO capability, unable to decide association model */ + ESP_AUTH_SMP_INIT_FAIL, /*!< SMP pairing initiation failed */ + ESP_AUTH_SMP_CONFIRM_FAIL, /*!< The confirm value does not match */ + ESP_AUTH_SMP_BUSY, /*!< Pending security request on going */ + ESP_AUTH_SMP_ENC_FAIL, /*!< The Controller failed to start encryption */ + ESP_AUTH_SMP_STARTED, /*!< SMP pairing process started */ + ESP_AUTH_SMP_RSP_TIMEOUT, /*!< Security Manager timeout due to no SMP command being received */ + ESP_AUTH_SMP_DIV_NOT_AVAIL, /*!< Encrypted Diversifier value not available */ + ESP_AUTH_SMP_UNSPEC_ERR, /*!< Unspecified failed reason */ + ESP_AUTH_SMP_CONN_TOUT, /*!< Pairing process failed due to connection timeout */ +} esp_ble_auth_fail_rsn_t; + /** * @brief Structure associated with ESP_AUTH_CMPL_EVT */ typedef struct { - esp_bd_addr_t bd_addr; /*!< BD address peer device. */ - bool key_present; /*!< Valid link key value in key element */ - esp_link_key key; /*!< Link key associated with peer device. */ - uint8_t key_type; /*!< The type of Link Key */ - bool success; /*!< TRUE of authentication succeeded, FALSE if failed. */ - uint8_t fail_reason; /*!< The HCI reason/error code for when success=FALSE */ - esp_ble_addr_type_t addr_type; /*!< Peer device address type */ - esp_bt_dev_type_t dev_type; /*!< Device type */ - esp_ble_auth_req_t auth_mode; /*!< authentication mode */ -} esp_ble_auth_cmpl_t; /*!< The ble authentication complete cb type */ + esp_bd_addr_t bd_addr; /*!< BD address of peer device */ + bool key_present; /*!< True if the link key value is valid; false otherwise */ + esp_link_key key; /*!< Link key associated with peer device */ + uint8_t key_type; /*!< The type of link key */ + bool success; /*!< True if authentication succeeded; false otherwise */ + esp_ble_auth_fail_rsn_t fail_reason; /*!< The HCI reason/error code for failure when success is false */ + esp_ble_addr_type_t addr_type; /*!< Peer device address type */ + esp_bt_dev_type_t dev_type; /*!< Device type */ + esp_ble_auth_req_t auth_mode; /*!< Authentication mode */ +} esp_ble_auth_cmpl_t; /*!< The ble authentication complete cb type */ /** * @brief union associated with ble security diff --git a/components/bt/host/bluedroid/hci/hci_hal_h4.c b/components/bt/host/bluedroid/hci/hci_hal_h4.c index a2ee1d1121be..9663126ad62b 100644 --- a/components/bt/host/bluedroid/hci/hci_hal_h4.c +++ b/components/bt/host/bluedroid/hci/hci_hal_h4.c @@ -36,7 +36,7 @@ #include "stack/hcimsgs.h" #if ((BT_CONTROLLER_INCLUDED == TRUE) && SOC_ESP_NIMBLE_CONTROLLER) -#include "nimble/ble_hci_trans.h" +#include "ble_hci_trans.h" #endif #if (C2H_FLOW_CONTROL_INCLUDED == TRUE) diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c b/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c index 9d937b718e2e..9ddf746ae9b1 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c @@ -330,7 +330,7 @@ void btm_ble_remove_resolving_list_entry_complete(UINT8 *p, UINT16 evt_len) BTM_TRACE_DEBUG("%s status = %d", __func__, status); if (!btm_ble_deq_resolving_pending(pseudo_bda)) { - BTM_TRACE_ERROR("%s no pending resolving list operation", __func__); + BTM_TRACE_DEBUG("%s no pending resolving list operation", __func__); return; } diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index a1f5999ee87d..73112f9b4068 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit a1f5999ee87d73c1d71e1e90991fafde4a951ec3 +Subproject commit 73112f9b4068ef7dc541c88c555ff829bebb9f8f diff --git a/components/bt/porting/nimble/include/nimble/ble_hci_trans.h b/components/bt/porting/include/ble_hci_trans.h similarity index 93% rename from components/bt/porting/nimble/include/nimble/ble_hci_trans.h rename to components/bt/porting/include/ble_hci_trans.h index 5bbf92246014..05267b6be77e 100644 --- a/components/bt/porting/nimble/include/nimble/ble_hci_trans.h +++ b/components/bt/porting/include/ble_hci_trans.h @@ -1,20 +1,7 @@ /* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 */ #ifndef H_HCI_TRANSPORT_ diff --git a/components/bt/porting/mem/bt_osi_mem.h b/components/bt/porting/include/bt_osi_mem.h similarity index 100% rename from components/bt/porting/mem/bt_osi_mem.h rename to components/bt/porting/include/bt_osi_mem.h diff --git a/components/bt/porting/nimble/include/os/endian.h b/components/bt/porting/include/os/endian.h similarity index 100% rename from components/bt/porting/nimble/include/os/endian.h rename to components/bt/porting/include/os/endian.h diff --git a/components/bt/porting/nimble/include/os/os.h b/components/bt/porting/include/os/os.h similarity index 100% rename from components/bt/porting/nimble/include/os/os.h rename to components/bt/porting/include/os/os.h diff --git a/components/bt/porting/nimble/include/os/os_error.h b/components/bt/porting/include/os/os_error.h similarity index 100% rename from components/bt/porting/nimble/include/os/os_error.h rename to components/bt/porting/include/os/os_error.h diff --git a/components/bt/porting/nimble/include/os/os_mbuf.h b/components/bt/porting/include/os/os_mbuf.h similarity index 99% rename from components/bt/porting/nimble/include/os/os_mbuf.h rename to components/bt/porting/include/os/os_mbuf.h index e6fd6b907e60..c6ea6b6e85df 100644 --- a/components/bt/porting/nimble/include/os/os_mbuf.h +++ b/components/bt/porting/include/os/os_mbuf.h @@ -65,7 +65,7 @@ struct os_mbuf_pool { /** - * A packet header structure that preceeds the mbuf packet headers. + * A packet header structure that proceeds the mbuf packet headers. */ struct os_mbuf_pkthdr { /** @@ -89,7 +89,7 @@ struct os_mbuf { */ uint8_t *om_data; /** - * Flags associated with this buffer, see OS_MBUF_F_* defintions + * Flags associated with this buffer, see OS_MBUF_F_* definitions */ uint8_t om_flags; /** diff --git a/components/bt/porting/nimble/include/os/os_mempool.h b/components/bt/porting/include/os/os_mempool.h similarity index 100% rename from components/bt/porting/nimble/include/os/os_mempool.h rename to components/bt/porting/include/os/os_mempool.h diff --git a/components/bt/porting/nimble/include/os/queue.h b/components/bt/porting/include/os/queue.h similarity index 81% rename from components/bt/porting/nimble/include/os/queue.h rename to components/bt/porting/include/os/queue.h index c184a394edbf..868f9abfa4fc 100644 --- a/components/bt/porting/nimble/include/os/queue.h +++ b/components/bt/porting/include/os/queue.h @@ -1,33 +1,27 @@ /* - * Copyright (c) 1991, 1993 - * The Regents of the University of California. All rights reserved. + * SPDX-FileCopyrightText: 2015-2022 The Apache Software Foundation (ASF) * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * SPDX-License-Identifier: Apache-2.0 * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. + * SPDX-FileContributor: 2019-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 * - * @(#)queue.h 8.5 (Berkeley) 8/20/94 - * $FreeBSD: src/sys/sys/queue.h,v 1.32.2.7 2002/04/17 14:21:02 des Exp $ + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. */ #ifndef _QUEUE_H_ diff --git a/components/bt/porting/nimble/include/os/util.h b/components/bt/porting/include/os/util.h similarity index 100% rename from components/bt/porting/nimble/include/os/util.h rename to components/bt/porting/include/os/util.h diff --git a/components/bt/porting/nimble/src/os_msys_init.c b/components/bt/porting/mem/os_msys_init.c similarity index 96% rename from components/bt/porting/nimble/src/os_msys_init.c rename to components/bt/porting/mem/os_msys_init.c index bf4f4145166e..1a121e6d0b50 100644 --- a/components/bt/porting/nimble/src/os_msys_init.c +++ b/components/bt/porting/mem/os_msys_init.c @@ -82,12 +82,12 @@ static struct os_mempool os_msys_init_2_mempool; #endif #if CONFIG_BT_LE_MSYS_INIT_IN_CONTROLLER -extern int esp_ble_msys_init(uint16_t msys_size1, uint16_t msys_size2, uint16_t msys_cnt1, uint16_t msys_cnt2, uint8_t from_heap); -extern void esp_ble_msys_deinit(void); +extern int r_esp_ble_msys_init(uint16_t msys_size1, uint16_t msys_size2, uint16_t msys_cnt1, uint16_t msys_cnt2, uint8_t from_heap); +extern void r_esp_ble_msys_deinit(void); int os_msys_init(void) { - return esp_ble_msys_init(SYSINIT_MSYS_1_MEMBLOCK_SIZE, + return r_esp_ble_msys_init(SYSINIT_MSYS_1_MEMBLOCK_SIZE, SYSINIT_MSYS_2_MEMBLOCK_SIZE, OS_MSYS_1_BLOCK_COUNT, OS_MSYS_2_BLOCK_COUNT, @@ -96,7 +96,7 @@ int os_msys_init(void) void os_msys_deinit(void) { - esp_ble_msys_deinit(); + r_esp_ble_msys_deinit(); } #else // CONFIG_BT_LE_MSYS_INIT_IN_CONTROLLER diff --git a/components/bt/porting/nimble/include/nimble/ble.h b/components/bt/porting/nimble/include/nimble/ble.h deleted file mode 100644 index f037d3565b83..000000000000 --- a/components/bt/porting/nimble/include/nimble/ble.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 The Apache Software Foundation (ASF) - * - * SPDX-License-Identifier: Apache-2.0 - * - * SPDX-FileContributor: 2019-2022 Espressif Systems (Shanghai) CO LTD - */ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef H_BLE_ -#define H_BLE_ - -#include -#include -#include "syscfg/syscfg.h" -#include "os/os.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* The number of advertising instances */ -#define BLE_ADV_INSTANCES (MYNEWT_VAL(BLE_MULTI_ADV_INSTANCES) + 1) - -/* BLE encryption block definitions */ -#define BLE_ENC_BLOCK_SIZE (16) - -/* 4 byte header + 251 byte payload. */ -#define BLE_ACL_MAX_PKT_SIZE 255 - -struct ble_encryption_block -{ - uint8_t key[BLE_ENC_BLOCK_SIZE]; - uint8_t plain_text[BLE_ENC_BLOCK_SIZE]; - uint8_t cipher_text[BLE_ENC_BLOCK_SIZE]; -}; - -/* - * BLE MBUF structure: - * - * The BLE mbuf structure is as follows. Note that this structure applies to - * the packet header mbuf (not mbufs that are part of a "packet chain"): - * struct os_mbuf (16) - * struct os_mbuf_pkthdr (8) - * struct ble_mbuf_hdr (8) - * Data buffer (payload size, in bytes) - * - * The BLE mbuf header contains the following: - * flags: bitfield with the following values - * 0x01: Set if there was a match on the whitelist - * 0x02: Set if a connect request was transmitted upon receiving pdu - * 0x04: Set the first time we transmit the PDU (used to detect retry). - * channel: The logical BLE channel PHY channel # (0 - 39) - * crcok: flag denoting CRC check passed (1) or failed (0). - * rssi: RSSI, in dBm. - */ -struct ble_mbuf_hdr_rxinfo -{ - uint16_t flags; - uint8_t channel; - uint8_t handle; - int8_t rssi; - /* XXX: we could just use single phy_mode field */ - int8_t phy; - uint8_t phy_mode; -#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LL_PRIVACY) - int8_t rpa_index; -#endif -#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LL_EXT_ADV) - void *user_data; -#endif -}; - -/* - * Flag definitions for rxinfo - * - * Note: it's ok to have symbols with the same values as long as they cannot be - * set for the same PDU (e.g. one use by scanner, other one used by - * connection) - */ -#define BLE_MBUF_HDR_F_CONN_CREDIT (0x8000) -#define BLE_MBUF_HDR_F_IGNORED (0x8000) -#define BLE_MBUF_HDR_F_SCAN_REQ_TXD (0x4000) -#define BLE_MBUF_HDR_F_INITA_RESOLVED (0x2000) -#define BLE_MBUF_HDR_F_TARGETA_RESOLVED (0x2000) -#define BLE_MBUF_HDR_F_EXT_ADV_SEC (0x1000) -#define BLE_MBUF_HDR_F_EXT_ADV (0x0800) -#define BLE_MBUF_HDR_F_RESOLVED (0x0400) -#define BLE_MBUF_HDR_F_AUX_PTR_WAIT (0x0200) -#define BLE_MBUF_HDR_F_AUX_INVALID (0x0100) -#define BLE_MBUF_HDR_F_CRC_OK (0x0080) -#define BLE_MBUF_HDR_F_DEVMATCH (0x0040) -#define BLE_MBUF_HDR_F_MIC_FAILURE (0x0020) -#define BLE_MBUF_HDR_F_SCAN_RSP_TXD (0x0010) -#define BLE_MBUF_HDR_F_SCAN_RSP_RXD (0x0008) -#define BLE_MBUF_HDR_F_RXSTATE_MASK (0x0007) - -/* Transmit info. NOTE: no flags defined */ -struct ble_mbuf_hdr_txinfo -{ - uint8_t flags; - uint8_t reserve0; - uint8_t pyld_len; - uint8_t hdr_byte; - uint16_t offset; -}; - -struct ble_mbuf_hdr -{ - union { - struct ble_mbuf_hdr_rxinfo rxinfo; - struct ble_mbuf_hdr_txinfo txinfo; - }; - uint32_t beg_cputime; - uint32_t rem_usecs; -}; - -#define BLE_MBUF_HDR_IGNORED(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_IGNORED)) - -#define BLE_MBUF_HDR_SCAN_REQ_TXD(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_SCAN_REQ_TXD)) - -#define BLE_MBUF_HDR_EXT_ADV_SEC(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_EXT_ADV_SEC)) - -#define BLE_MBUF_HDR_EXT_ADV(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_EXT_ADV)) - -#define BLE_MBUF_HDR_DEVMATCH(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_DEVMATCH)) - -#define BLE_MBUF_HDR_SCAN_RSP_RXD(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_SCAN_RSP_RXD)) - -#define BLE_MBUF_HDR_AUX_INVALID(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_AUX_INVALID)) - -#define BLE_MBUF_HDR_WAIT_AUX(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_AUX_PTR_WAIT)) - -#define BLE_MBUF_HDR_CRC_OK(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_CRC_OK)) - -#define BLE_MBUF_HDR_MIC_FAILURE(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_MIC_FAILURE)) - -#define BLE_MBUF_HDR_RESOLVED(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_RESOLVED)) - -#define BLE_MBUF_HDR_INITA_RESOLVED(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_INITA_RESOLVED)) - -#define BLE_MBUF_HDR_TARGETA_RESOLVED(hdr) \ - (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_TARGETA_RESOLVED)) - -#define BLE_MBUF_HDR_RX_STATE(hdr) \ - ((uint8_t)((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_RXSTATE_MASK)) - -#define BLE_MBUF_HDR_PTR(om) \ - (struct ble_mbuf_hdr *)((uint8_t *)om + sizeof(struct os_mbuf) + \ - sizeof(struct os_mbuf_pkthdr)) - -/* BLE mbuf overhead per packet header mbuf */ -#define BLE_MBUF_PKTHDR_OVERHEAD \ - (sizeof(struct os_mbuf_pkthdr) + sizeof(struct ble_mbuf_hdr)) - -#define BLE_MBUF_MEMBLOCK_OVERHEAD \ - (sizeof(struct os_mbuf) + BLE_MBUF_PKTHDR_OVERHEAD) - -/* Length of host user header. Only contains the peer's connection handle. */ -#define BLE_MBUF_HS_HDR_LEN (2) - -#define BLE_DEV_ADDR_LEN (6) -extern uint8_t g_dev_addr[BLE_DEV_ADDR_LEN]; -extern uint8_t g_random_addr[BLE_DEV_ADDR_LEN]; - -/* BLE Error Codes (Core v4.2 Vol 2 part D) */ -enum ble_error_codes -{ - /* An "error" code of 0x0 means success */ - BLE_ERR_SUCCESS = 0x00, - BLE_ERR_UNKNOWN_HCI_CMD = 0x01, - BLE_ERR_UNK_CONN_ID = 0x02, - BLE_ERR_HW_FAIL = 0x03, - BLE_ERR_PAGE_TMO = 0x04, - BLE_ERR_AUTH_FAIL = 0x05, - BLE_ERR_PINKEY_MISSING = 0x06, - BLE_ERR_MEM_CAPACITY = 0x07, - BLE_ERR_CONN_SPVN_TMO = 0x08, - BLE_ERR_CONN_LIMIT = 0x09, - BLE_ERR_SYNCH_CONN_LIMIT = 0x0a, - BLE_ERR_ACL_CONN_EXISTS = 0x0b, - BLE_ERR_CMD_DISALLOWED = 0x0c, - BLE_ERR_CONN_REJ_RESOURCES = 0x0d, - BLE_ERR_CONN_REJ_SECURITY = 0x0e, - BLE_ERR_CONN_REJ_BD_ADDR = 0x0f, - BLE_ERR_CONN_ACCEPT_TMO = 0x10, - BLE_ERR_UNSUPPORTED = 0x11, - BLE_ERR_INV_HCI_CMD_PARMS = 0x12, - BLE_ERR_REM_USER_CONN_TERM = 0x13, - BLE_ERR_RD_CONN_TERM_RESRCS = 0x14, - BLE_ERR_RD_CONN_TERM_PWROFF = 0x15, - BLE_ERR_CONN_TERM_LOCAL = 0x16, - BLE_ERR_REPEATED_ATTEMPTS = 0x17, - BLE_ERR_NO_PAIRING = 0x18, - BLE_ERR_UNK_LMP = 0x19, - BLE_ERR_UNSUPP_REM_FEATURE = 0x1a, - BLE_ERR_SCO_OFFSET = 0x1b, - BLE_ERR_SCO_ITVL = 0x1c, - BLE_ERR_SCO_AIR_MODE = 0x1d, - BLE_ERR_INV_LMP_LL_PARM = 0x1e, - BLE_ERR_UNSPECIFIED = 0x1f, - BLE_ERR_UNSUPP_LMP_LL_PARM = 0x20, - BLE_ERR_NO_ROLE_CHANGE = 0x21, - BLE_ERR_LMP_LL_RSP_TMO = 0x22, - BLE_ERR_LMP_COLLISION = 0x23, - BLE_ERR_LMP_PDU = 0x24, - BLE_ERR_ENCRYPTION_MODE = 0x25, - BLE_ERR_LINK_KEY_CHANGE = 0x26, - BLE_ERR_UNSUPP_QOS = 0x27, - BLE_ERR_INSTANT_PASSED = 0x28, - BLE_ERR_UNIT_KEY_PAIRING = 0x29, - BLE_ERR_DIFF_TRANS_COLL = 0x2a, - /* BLE_ERR_RESERVED = 0x2b */ - BLE_ERR_QOS_PARM = 0x2c, - BLE_ERR_QOS_REJECTED = 0x2d, - BLE_ERR_CHAN_CLASS = 0x2e, - BLE_ERR_INSUFFICIENT_SEC = 0x2f, - BLE_ERR_PARM_OUT_OF_RANGE = 0x30, - /* BLE_ERR_RESERVED = 0x31 */ - BLE_ERR_PENDING_ROLE_SW = 0x32, - /* BLE_ERR_RESERVED = 0x33 */ - BLE_ERR_RESERVED_SLOT = 0x34, - BLE_ERR_ROLE_SW_FAIL = 0x35, - BLE_ERR_INQ_RSP_TOO_BIG = 0x36, - BLE_ERR_SEC_SIMPLE_PAIR = 0x37, - BLE_ERR_HOST_BUSY_PAIR = 0x38, - BLE_ERR_CONN_REJ_CHANNEL = 0x39, - BLE_ERR_CTLR_BUSY = 0x3a, - BLE_ERR_CONN_PARMS = 0x3b, - BLE_ERR_DIR_ADV_TMO = 0x3c, - BLE_ERR_CONN_TERM_MIC = 0x3d, - BLE_ERR_CONN_ESTABLISHMENT = 0x3e, - BLE_ERR_MAC_CONN_FAIL = 0x3f, - BLE_ERR_COARSE_CLK_ADJ = 0x40, - BLE_ERR_TYPE0_SUBMAP_NDEF = 0x41, - BLE_ERR_UNK_ADV_INDENT = 0x42, - BLE_ERR_LIMIT_REACHED = 0x43, - BLE_ERR_OPERATION_CANCELLED = 0x44, - BLE_ERR_PACKET_TOO_LONG = 0x45, - BLE_ERR_MAX = 0xff -}; - -/* HW error codes */ -#define BLE_HW_ERR_DO_NOT_USE (0) /* XXX: reserve this one for now */ -#define BLE_HW_ERR_HCI_SYNC_LOSS (1) - -/* Own Bluetooth Device address type */ -#define BLE_OWN_ADDR_PUBLIC (0x00) -#define BLE_OWN_ADDR_RANDOM (0x01) -#define BLE_OWN_ADDR_RPA_PUBLIC_DEFAULT (0x02) -#define BLE_OWN_ADDR_RPA_RANDOM_DEFAULT (0x03) - -/* Bluetooth Device address type */ -#define BLE_ADDR_PUBLIC (0x00) -#define BLE_ADDR_RANDOM (0x01) -#define BLE_ADDR_PUBLIC_ID (0x02) -#define BLE_ADDR_RANDOM_ID (0x03) - -#define BLE_ADDR_ANY (&(ble_addr_t) { 0, {0, 0, 0, 0, 0, 0} }) - -#define BLE_ADDR_IS_RPA(addr) (((addr)->type == BLE_ADDR_RANDOM) && \ - ((addr)->val[5] & 0xc0) == 0x40) -#define BLE_ADDR_IS_NRPA(addr) (((addr)->type == BLE_ADDR_RANDOM) && \ - ((addr)->val[5] & 0xc0) == 0x00) -#define BLE_ADDR_IS_STATIC(addr) (((addr)->type == BLE_ADDR_RANDOM) && \ - ((addr)->val[5] & 0xc0) == 0xc0) - -typedef struct { - uint8_t type; - uint8_t val[6]; -} ble_addr_t; - - -static inline int ble_addr_cmp(const ble_addr_t *a, const ble_addr_t *b) -{ - int type_diff; - - type_diff = a->type - b->type; - if (type_diff != 0) { - return type_diff; - } - - return memcmp(a->val, b->val, sizeof(a->val)); -} - -#ifdef __cplusplus -} -#endif - -#endif /* H_BLE_ */ diff --git a/components/bt/porting/nimble/include/nimble/nimble_opt.h b/components/bt/porting/nimble/include/nimble/nimble_opt.h deleted file mode 100644 index f0e988b27b0a..000000000000 --- a/components/bt/porting/nimble/include/nimble/nimble_opt.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef H_NIMBLE_OPT_ -#define H_NIMBLE_OPT_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Include automatically-generated settings. */ -#include "nimble/nimble_opt_auto.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/components/bt/porting/nimble/include/nimble/nimble_opt_auto.h b/components/bt/porting/nimble/include/nimble/nimble_opt_auto.h deleted file mode 100644 index c4baec843bee..000000000000 --- a/components/bt/porting/nimble/include/nimble/nimble_opt_auto.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 The Apache Software Foundation (ASF) - * - * SPDX-License-Identifier: Apache-2.0 - * - * SPDX-FileContributor: 2019-2022 Espressif Systems (Shanghai) CO LTD - */ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef H_NIMBLE_OPT_AUTO_ -#define H_NIMBLE_OPT_AUTO_ - -#include "syscfg/syscfg.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*** - * Automatic options. - * - * These settings are generated automatically from the user-specified syscfg - * settings. - */ - -#undef NIMBLE_BLE_ADVERTISE -#define NIMBLE_BLE_ADVERTISE \ - (MYNEWT_VAL(BLE_ROLE_BROADCASTER) || MYNEWT_VAL(BLE_ROLE_PERIPHERAL)) - -#undef NIMBLE_BLE_SCAN -#define NIMBLE_BLE_SCAN \ - (MYNEWT_VAL(BLE_ROLE_CENTRAL) || MYNEWT_VAL(BLE_ROLE_OBSERVER)) - -#undef NIMBLE_BLE_CONNECT -#define NIMBLE_BLE_CONNECT \ - (MYNEWT_VAL(BLE_ROLE_CENTRAL) || MYNEWT_VAL(BLE_ROLE_PERIPHERAL)) - - -/** Supported client ATT commands. */ - -#undef NIMBLE_BLE_ATT_CLT_FIND_INFO -#define NIMBLE_BLE_ATT_CLT_FIND_INFO \ - (MYNEWT_VAL(BLE_GATT_DISC_ALL_DSCS)) - -#undef NIMBLE_BLE_ATT_CLT_FIND_TYPE -#define NIMBLE_BLE_ATT_CLT_FIND_TYPE \ - (MYNEWT_VAL(BLE_GATT_DISC_SVC_UUID)) - -#undef NIMBLE_BLE_ATT_CLT_READ_TYPE -#define NIMBLE_BLE_ATT_CLT_READ_TYPE \ - (MYNEWT_VAL(BLE_GATT_FIND_INC_SVCS) || \ - MYNEWT_VAL(BLE_GATT_DISC_ALL_CHRS) || \ - MYNEWT_VAL(BLE_GATT_DISC_CHRS_UUID) || \ - MYNEWT_VAL(BLE_GATT_READ_UUID)) - -#undef NIMBLE_BLE_ATT_CLT_READ -#define NIMBLE_BLE_ATT_CLT_READ \ - (MYNEWT_VAL(BLE_GATT_READ) || \ - MYNEWT_VAL(BLE_GATT_READ_LONG) || \ - MYNEWT_VAL(BLE_GATT_FIND_INC_SVCS)) - -#undef NIMBLE_BLE_ATT_CLT_READ_BLOB -#define NIMBLE_BLE_ATT_CLT_READ_BLOB \ - (MYNEWT_VAL(BLE_GATT_READ_LONG)) - -#undef NIMBLE_BLE_ATT_CLT_READ_MULT -#define NIMBLE_BLE_ATT_CLT_READ_MULT \ - (MYNEWT_VAL(BLE_GATT_READ_MULT)) - -#undef NIMBLE_BLE_ATT_CLT_READ_MULT_VAR -#define NIMBLE_BLE_ATT_CLT_READ_MULT_VAR \ - (MYNEWT_VAL(BLE_GATT_READ_MULT_VAR)) - -#undef NIMBLE_BLE_ATT_CLT_READ_GROUP_TYPE -#define NIMBLE_BLE_ATT_CLT_READ_GROUP_TYPE \ - (MYNEWT_VAL(BLE_GATT_DISC_ALL_SVCS)) - -#undef NIMBLE_BLE_ATT_CLT_WRITE -#define NIMBLE_BLE_ATT_CLT_WRITE \ - (MYNEWT_VAL(BLE_GATT_WRITE)) - -#undef NIMBLE_BLE_ATT_CLT_SIGNED_WRITE -#define NIMBLE_BLE_ATT_CLT_SIGNED_WRITE \ - (MYNEWT_VAL(BLE_GATT_SIGNED_WRITE)) - -#undef NIMBLE_BLE_ATT_CLT_WRITE_NO_RSP -#define NIMBLE_BLE_ATT_CLT_WRITE_NO_RSP \ - (MYNEWT_VAL(BLE_GATT_WRITE_NO_RSP)) - -#undef NIMBLE_BLE_ATT_CLT_PREP_WRITE -#define NIMBLE_BLE_ATT_CLT_PREP_WRITE \ - (MYNEWT_VAL(BLE_GATT_WRITE_LONG)) - -#undef NIMBLE_BLE_ATT_CLT_EXEC_WRITE -#define NIMBLE_BLE_ATT_CLT_EXEC_WRITE \ - (MYNEWT_VAL(BLE_GATT_WRITE_LONG)) - -#undef NIMBLE_BLE_ATT_CLT_NOTIFY -#define NIMBLE_BLE_ATT_CLT_NOTIFY \ - (MYNEWT_VAL(BLE_GATT_NOTIFY)) - -#undef NIMBLE_BLE_ATT_CLT_INDICATE -#define NIMBLE_BLE_ATT_CLT_INDICATE \ - (MYNEWT_VAL(BLE_GATT_INDICATE)) - -/** Security manager settings. */ - -#undef NIMBLE_BLE_SM -#define NIMBLE_BLE_SM (MYNEWT_VAL(BLE_SM_LEGACY) || MYNEWT_VAL(BLE_SM_SC)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/components/bt/porting/nimble/include/nimble/nimble_port.h b/components/bt/porting/nimble/include/nimble/nimble_port.h deleted file mode 100644 index 0035fee6c344..000000000000 --- a/components/bt/porting/nimble/include/nimble/nimble_port.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#ifndef _NIMBLE_PORT_H -#define _NIMBLE_PORT_H - -#include "sdkconfig.h" -#include "esp_err.h" -#include "nimble/nimble_npl.h" - -#define NIMBLE_CORE (CONFIG_BT_NIMBLE_PINNED_TO_CORE < CONFIG_FREERTOS_NUMBER_OF_CORES ? CONFIG_BT_NIMBLE_PINNED_TO_CORE : tskNO_AFFINITY) - -#define NIMBLE_HS_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE - -#if SOC_ESP_NIMBLE_CONTROLLER && CONFIG_BT_CONTROLLER_ENABLED -#define NIMBLE_LL_STACK_SIZE CONFIG_BT_LE_CONTROLLER_TASK_STACK_SIZE -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* @brief nimble_port_init - Initialize controller and NimBLE host stack -* -* @return esp_err_t - ESP_OK ( if success) -* Error code in case of failure -*/ -esp_err_t nimble_port_init(void); - -/** -* @brief nimble_port_deinit - Deinitialize controller and NimBLE host stack -* -* @return esp_err_t - ESP_OK ( if success) -* Error code in case of failure -*/ -esp_err_t nimble_port_deinit(void); - -void nimble_port_run(void); -int nimble_port_stop(void); - -/** - * @brief esp_nimble_init - Initialize the NimBLE host stack - * - * @return esp_err_t - */ -esp_err_t esp_nimble_init(void); - -/** - * @brief esp_nimble_deinit - Deinitialize the NimBLE host stack - * - * @return esp_err_t - */ -esp_err_t esp_nimble_deinit(void); - -struct ble_npl_eventq *nimble_port_get_dflt_eventq(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* _NIMBLE_PORT_H */ diff --git a/components/bt/porting/nimble/include/nimble/nimble_npl.h b/components/bt/porting/npl/freertos/include/nimble/nimble_npl.h similarity index 83% rename from components/bt/porting/nimble/include/nimble/nimble_npl.h rename to components/bt/porting/npl/freertos/include/nimble/nimble_npl.h index c11a2972dfd8..c9482044b749 100644 --- a/components/bt/porting/nimble/include/nimble/nimble_npl.h +++ b/components/bt/porting/npl/freertos/include/nimble/nimble_npl.h @@ -1,20 +1,7 @@ /* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. + * SPDX-License-Identifier: Apache-2.0 */ #ifndef _NIMBLE_NPL_H_ diff --git a/components/bt/porting/npl/freertos/src/npl_os_freertos.c b/components/bt/porting/npl/freertos/src/npl_os_freertos.c index c93a2224d779..29e2567d553d 100644 --- a/components/bt/porting/npl/freertos/src/npl_os_freertos.c +++ b/components/bt/porting/npl/freertos/src/npl_os_freertos.c @@ -1,9 +1,7 @@ /* - * SPDX-FileCopyrightText: 2019-2023 The Apache Software Foundation (ASF) + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 - * - * SPDX-FileContributor: 2019-2024 Espressif Systems (Shanghai) CO LTD */ #include @@ -18,7 +16,6 @@ #include "freertos/timers.h" #include "freertos/portable.h" #include "nimble/npl_freertos.h" -#include "nimble/nimble_port.h" #include "os/os_mempool.h" #include "esp_log.h" @@ -481,32 +478,32 @@ IRAM_ATTR npl_freertos_mutex_release(struct ble_npl_mutex *mu) ble_npl_error_t npl_freertos_sem_init(struct ble_npl_sem *sem, uint16_t tokens) { - struct ble_npl_sem_freertos *semaphor = NULL; + struct ble_npl_sem_freertos *semaphore = NULL; #if OS_MEM_ALLOC if (!os_memblock_from(&ble_freertos_sem_pool,sem->sem)) { sem->sem = os_memblock_get(&ble_freertos_sem_pool); - semaphor = (struct ble_npl_sem_freertos *)sem->sem; + semaphore = (struct ble_npl_sem_freertos *)sem->sem; - if (!semaphor) { + if (!semaphore) { return BLE_NPL_INVALID_PARAM; } - memset(semaphor, 0, sizeof(*semaphor)); - semaphor->handle = xSemaphoreCreateCounting(128, tokens); - BLE_LL_ASSERT(semaphor->handle); + memset(semaphore, 0, sizeof(*semaphore)); + semaphore->handle = xSemaphoreCreateCounting(128, tokens); + BLE_LL_ASSERT(semaphore->handle); } #else if(!sem->sem) { sem->sem = malloc(sizeof(struct ble_npl_sem_freertos)); - semaphor = (struct ble_npl_sem_freertos *)sem->sem; + semaphore = (struct ble_npl_sem_freertos *)sem->sem; - if (!semaphor) { + if (!semaphore) { return BLE_NPL_INVALID_PARAM; } - memset(semaphor, 0, sizeof(*semaphor)); - semaphor->handle = xSemaphoreCreateCounting(128, tokens); - BLE_LL_ASSERT(semaphor->handle); + memset(semaphore, 0, sizeof(*semaphore)); + semaphore->handle = xSemaphoreCreateCounting(128, tokens); + BLE_LL_ASSERT(semaphore->handle); } #endif @@ -516,19 +513,19 @@ npl_freertos_sem_init(struct ble_npl_sem *sem, uint16_t tokens) ble_npl_error_t npl_freertos_sem_deinit(struct ble_npl_sem *sem) { - struct ble_npl_sem_freertos *semaphor = (struct ble_npl_sem_freertos *)sem->sem; + struct ble_npl_sem_freertos *semaphore = (struct ble_npl_sem_freertos *)sem->sem; - if (!semaphor) { + if (!semaphore) { return BLE_NPL_INVALID_PARAM; } - BLE_LL_ASSERT(semaphor->handle); - vSemaphoreDelete(semaphor->handle); + BLE_LL_ASSERT(semaphore->handle); + vSemaphoreDelete(semaphore->handle); #if OS_MEM_ALLOC - os_memblock_put(&ble_freertos_sem_pool,semaphor); + os_memblock_put(&ble_freertos_sem_pool,semaphore); #else - free((void *)semaphor); + free((void *)semaphore); #endif sem->sem = NULL; @@ -540,22 +537,22 @@ IRAM_ATTR npl_freertos_sem_pend(struct ble_npl_sem *sem, ble_npl_time_t timeout) { BaseType_t woken; BaseType_t ret; - struct ble_npl_sem_freertos *semaphor = (struct ble_npl_sem_freertos *)sem->sem; + struct ble_npl_sem_freertos *semaphore = (struct ble_npl_sem_freertos *)sem->sem; - if (!semaphor) { + if (!semaphore) { return BLE_NPL_INVALID_PARAM; } - BLE_LL_ASSERT(semaphor->handle); + BLE_LL_ASSERT(semaphore->handle); if (in_isr()) { BLE_LL_ASSERT(timeout == 0); - ret = xSemaphoreTakeFromISR(semaphor->handle, &woken); + ret = xSemaphoreTakeFromISR(semaphore->handle, &woken); if( woken == pdTRUE ) { portYIELD_FROM_ISR(); } } else { - ret = xSemaphoreTake(semaphor->handle, timeout); + ret = xSemaphoreTake(semaphore->handle, timeout); } return ret == pdPASS ? BLE_NPL_OK : BLE_NPL_TIMEOUT; @@ -566,21 +563,21 @@ IRAM_ATTR npl_freertos_sem_release(struct ble_npl_sem *sem) { BaseType_t ret; BaseType_t woken; - struct ble_npl_sem_freertos *semaphor = (struct ble_npl_sem_freertos *)sem->sem; + struct ble_npl_sem_freertos *semaphore = (struct ble_npl_sem_freertos *)sem->sem; - if (!semaphor) { + if (!semaphore) { return BLE_NPL_INVALID_PARAM; } - BLE_LL_ASSERT(semaphor->handle); + BLE_LL_ASSERT(semaphore->handle); if (in_isr()) { - ret = xSemaphoreGiveFromISR(semaphor->handle, &woken); + ret = xSemaphoreGiveFromISR(semaphore->handle, &woken); if( woken == pdTRUE ) { portYIELD_FROM_ISR(); } } else { - ret = xSemaphoreGive(semaphor->handle); + ret = xSemaphoreGive(semaphore->handle); } BLE_LL_ASSERT(ret == pdPASS); @@ -773,8 +770,8 @@ npl_freertos_callout_deinit(struct ble_npl_callout *co) uint16_t IRAM_ATTR npl_freertos_sem_get_count(struct ble_npl_sem *sem) { - struct ble_npl_sem_freertos *semaphor = (struct ble_npl_sem_freertos *)sem->sem; - return uxSemaphoreGetCount(semaphor->handle); + struct ble_npl_sem_freertos *semaphore = (struct ble_npl_sem_freertos *)sem->sem; + return uxSemaphoreGetCount(semaphore->handle); } diff --git a/components/console/CMakeLists.txt b/components/console/CMakeLists.txt index 2343e088ff5c..09eecbd20911 100644 --- a/components/console/CMakeLists.txt +++ b/components/console/CMakeLists.txt @@ -37,3 +37,7 @@ idf_component_register(SRCS ${srcs} PRIV_REQUIRES esp_driver_uart esp_driver_usb_serial_jtag ) + +if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10085 + target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer") +endif() diff --git a/components/console/commands.c b/components/console/commands.c index 4ac0725dc71e..a07e743e1271 100644 --- a/components/console/commands.c +++ b/components/console/commands.c @@ -94,6 +94,23 @@ esp_err_t esp_console_deinit(void) return ESP_OK; } +void esp_console_rm_item_free_hint(cmd_item_t *item) +{ + SLIST_REMOVE(&s_cmd_list, item, cmd_item_, next); + free(item->hint); +} + +esp_err_t esp_console_cmd_deregister(const char *cmd_name) +{ + cmd_item_t *item = (cmd_item_t *)find_command_by_name(cmd_name); + if (item == NULL) { + return ESP_ERR_INVALID_ARG; + } + esp_console_rm_item_free_hint(item); + heap_caps_free(item); + return ESP_OK; +} + esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd) { cmd_item_t *item = NULL; @@ -116,8 +133,7 @@ esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd) } } else { // remove from list and free the old hint, because we will alloc new hint for the command - SLIST_REMOVE(&s_cmd_list, item, cmd_item_, next); - free(item->hint); + esp_console_rm_item_free_hint(item); } item->command = cmd->command; item->help = cmd->help; diff --git a/components/console/esp_console.h b/components/console/esp_console.h index 6fd3b8142459..0f0891f04472 100644 --- a/components/console/esp_console.h +++ b/components/console/esp_console.h @@ -235,6 +235,16 @@ typedef struct { */ esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd); +/** + * @brief Deregister console command + * @param cmd_name Name of the command to be deregistered. Must not be NULL, must not contain spaces. + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if command is not registered + */ +esp_err_t esp_console_cmd_deregister(const char *cmd_name); + /** * @brief Run command line * @param cmdline command line (command name followed by a number of arguments) diff --git a/components/console/test_apps/console/main/test_console.c b/components/console/test_apps/console/main/test_console.c index 36e22553b8c7..1e56db049c6e 100644 --- a/components/console/test_apps/console/main/test_console.c +++ b/components/console/test_apps/console/main/test_console.c @@ -307,3 +307,44 @@ TEST_CASE("esp console help command - --verbose sub command", "[console][ignore] TEST_ESP_OK(esp_console_start_repl(s_repl)); vTaskDelay(pdMS_TO_TICKS(5000)); } + +TEST_CASE("esp console deregister commands", "[console][ignore]") +{ + esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); + esp_console_dev_uart_config_t uart_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); + TEST_ESP_OK(esp_console_new_repl_uart(&uart_config, &repl_config, &s_repl)); + + TEST_ESP_OK(esp_console_cmd_register(&cmd_a)); + TEST_ESP_OK(esp_console_cmd_register(&s_quit_cmd)); + TEST_ESP_OK(esp_console_register_help_command()); + TEST_ESP_OK(esp_console_cmd_register(&cmd_z)); + // deregister a non-existing cmd, should return "ESP_ERR_INVALID_ARG" + TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_console_cmd_deregister("abcdefg")); + // deregister cmd_a + TEST_ESP_OK(esp_console_cmd_deregister(cmd_a.command)); + TEST_ESP_OK(esp_console_start_repl(s_repl)); + vTaskDelay(pdMS_TO_TICKS(5000)); +} + +TEST_CASE("esp console re-register commands", "[console][ignore]") +{ + esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); + esp_console_dev_uart_config_t uart_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); + TEST_ESP_OK(esp_console_new_repl_uart(&uart_config, &repl_config, &s_repl)); + + TEST_ESP_OK(esp_console_cmd_register(&cmd_a)); + TEST_ESP_OK(esp_console_cmd_register(&s_quit_cmd)); + TEST_ESP_OK(esp_console_cmd_register(&cmd_z)); + TEST_ESP_OK(esp_console_register_help_command()); + + // deregister cmd_z and cmd_a + TEST_ESP_OK(esp_console_cmd_deregister(cmd_z.command)); + TEST_ESP_OK(esp_console_cmd_deregister(cmd_a.command)); + + // re-register cmd_z and cmd_a + TEST_ESP_OK(esp_console_cmd_register(&cmd_z)); + TEST_ESP_OK(esp_console_cmd_register(&cmd_a)); + + TEST_ESP_OK(esp_console_start_repl(s_repl)); + vTaskDelay(pdMS_TO_TICKS(5000)); +} diff --git a/components/console/test_apps/console/pytest_console.py b/components/console/test_apps/console/pytest_console.py index be79490c1ce9..a2e99fddd7f5 100644 --- a/components/console/test_apps/console/pytest_console.py +++ b/components/console/test_apps/console/pytest_console.py @@ -261,3 +261,51 @@ def test_console_help_verbose_subcommand(dut: Dut, test_on: str) -> None: # verify help --verbose=1 subcommand dut.write('help --verbose=1') dut.expect_exact(help_verbose_info) + + +@pytest.mark.parametrize( + 'config', [ + pytest.param('defaults'), + ] +) +@pytest.mark.parametrize( + 'test_on', [ + pytest.param('host', marks=[pytest.mark.linux, pytest.mark.host_test]), + pytest.param('target', marks=[pytest.mark.esp32, pytest.mark.esp32c3, pytest.mark.generic]), + pytest.param('qemu', marks=[pytest.mark.esp32, pytest.mark.host_test, pytest.mark.qemu]), + ] +) +def test_console_help_deregister(dut: Dut, test_on: str) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('"esp console deregister commands"') + + dut.expect_exact('esp>', timeout=5) + dut.write('help') + + # in the test sequence, command a is registered before registering command z, then + # command a is deregistered; therefore, console shall not print command a's description + cmd_a_description, cmd_z_description = 'should appear first in help', 'should appear last in help' + dut.expect_exact(cmd_z_description, not_matching=cmd_a_description) + + +@pytest.mark.parametrize( + 'config', [ + pytest.param('defaults'), + ] +) +@pytest.mark.parametrize( + 'test_on', [ + pytest.param('host', marks=[pytest.mark.linux, pytest.mark.host_test]), + pytest.param('target', marks=[pytest.mark.esp32, pytest.mark.esp32c3, pytest.mark.generic]), + pytest.param('qemu', marks=[pytest.mark.esp32, pytest.mark.host_test, pytest.mark.qemu]), + ] +) +def test_console_help_re_register(dut: Dut, test_on: str) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('"esp console re-register commands"') + + dut.expect_exact('esp>', timeout=5) + dut.write('help') + + dut.expect_exact('should appear last in help', timeout=5) + dut.expect_exact('should appear first in help', timeout=5) diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index e350e1a72f74..16cebcc43223 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -111,4 +111,9 @@ else() esp_driver_uart esp_driver_ledc esp_driver_parlio esp_driver_usb_serial_jtag LDFRAGMENTS ${ldfragments} ) + if(CONFIG_SOC_ADC_SUPPORTED AND + CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO GCC-366 + set_source_files_properties(deprecated/adc_legacy.c + PROPERTIES COMPILE_FLAGS "-Wno-analyzer-use-of-uninitialized-value") + endif() endif() diff --git a/components/driver/deprecated/rmt_legacy.c b/components/driver/deprecated/rmt_legacy.c index 16d120725b4f..67e8133df2b1 100644 --- a/components/driver/deprecated/rmt_legacy.c +++ b/components/driver/deprecated/rmt_legacy.c @@ -27,6 +27,7 @@ #include "hal/rmt_ll.h" #include "hal/gpio_hal.h" #include "esp_rom_gpio.h" +#include "esp_compiler.h" #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR" #define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR" @@ -1061,6 +1062,7 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr #if SOC_RMT_SUPPORT_RX_PINGPONG if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") // False-positive detection. TODO GCC-366 #if !CONFIG_SPIRAM_USE_MALLOC p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size); #else @@ -1074,6 +1076,7 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr ESP_LOGE(TAG, "RMT malloc fail"); return ESP_FAIL; } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size; } #endif @@ -1237,7 +1240,7 @@ esp_err_t rmt_translator_get_context(const size_t *item_num, void **context) { ESP_RETURN_ON_FALSE(item_num && context, ESP_ERR_INVALID_ARG, TAG, "invalid arguments"); - // the address of tx_len_rem is directlly passed to the callback, + // the address of tx_len_rem is directly passed to the callback, // so it's possible to get the object address from that rmt_obj_t *obj = __containerof(item_num, rmt_obj_t, tx_len_rem); *context = obj->tx_context; diff --git a/components/driver/deprecated/rtc_temperature_legacy.c b/components/driver/deprecated/rtc_temperature_legacy.c index 97e700fa804e..d0da188faab0 100644 --- a/components/driver/deprecated/rtc_temperature_legacy.c +++ b/components/driver/deprecated/rtc_temperature_legacy.c @@ -11,6 +11,7 @@ #include "esp_types.h" #include "esp_log.h" #include "esp_check.h" +#include "esp_compiler.h" #include "freertos/FreeRTOS.h" #include "esp_private/regi2c_ctrl.h" #include "soc/regi2c_saradc.h" @@ -110,7 +111,9 @@ esp_err_t temp_sensor_stop(void) esp_err_t temp_sensor_read_raw(uint32_t *tsens_out) { ESP_RETURN_ON_FALSE(tsens_out != NULL, ESP_ERR_INVALID_ARG, TAG, "no tsens_out specified"); + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-use-of-uninitialized-value") // False-positive detection. TODO GCC-366 *tsens_out = temperature_sensor_ll_get_raw_value(); + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-use-of-uninitialized-value") return ESP_OK; } diff --git a/components/efuse/CMakeLists.txt b/components/efuse/CMakeLists.txt index e0f57b1d3431..b42eb753de0c 100644 --- a/components/efuse/CMakeLists.txt +++ b/components/efuse/CMakeLists.txt @@ -94,3 +94,10 @@ set(EFUSE_TEST_TABLE_CSV_PATH "${COMPONENT_DIR}/test/esp_efuse_test_table.csv") add_custom_target(efuse_test_table COMMAND "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py" ${EFUSE_TEST_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG}) + +################### +# GNU analyzer excludes +if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10086 + set_source_files_properties(src/esp_efuse_utility.c + PROPERTIES COMPILE_FLAGS "-fno-analyzer") +endif() diff --git a/components/esp-tls/esp_tls_error_capture.c b/components/esp-tls/esp_tls_error_capture.c index 67d6ec90cb41..f5dbcf5dbe01 100644 --- a/components/esp-tls/esp_tls_error_capture.c +++ b/components/esp-tls/esp_tls_error_capture.c @@ -7,6 +7,7 @@ #include #include "esp_tls.h" #include "esp_tls_error_capture_internal.h" +#include "esp_compiler.h" typedef struct esp_tls_error_storage { struct esp_tls_last_error parent; /*!< standard esp-tls last error container */ @@ -34,11 +35,13 @@ void esp_tls_internal_event_tracker_capture(esp_tls_error_handle_t h, uint32_t t esp_tls_error_handle_t esp_tls_internal_event_tracker_create(void) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") // Allocating internal error storage which extends the parent type // `esp_tls_last_error` defined at interface level struct esp_tls_error_storage* storage = calloc(1, sizeof(struct esp_tls_error_storage)); return &storage->parent; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } void esp_tls_internal_event_tracker_destroy(esp_tls_error_handle_t h) diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c index 7fb2f68dcac7..381ad55f8d19 100644 --- a/components/esp_adc/adc_continuous.c +++ b/components/esp_adc/adc_continuous.c @@ -37,7 +37,6 @@ #include "adc_continuous_internal.h" #include "esp_private/adc_dma.h" #include "adc_dma_internal.h" -#include "esp_dma_utils.h" #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #include "esp_cache.h" #include "esp_private/esp_cache_private.h" @@ -192,11 +191,7 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi } //malloc internal buffer used by DMA - esp_dma_mem_info_t dma_mem_info = { - .extra_heap_caps = (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA), - .dma_alignment_bytes = 4, - }; - esp_dma_capable_calloc(1, hdl_config->conv_frame_size * INTERNAL_BUF_NUM, &dma_mem_info, (void **)&adc_ctx->rx_dma_buf, NULL); + adc_ctx->rx_dma_buf = heap_caps_calloc(INTERNAL_BUF_NUM, hdl_config->conv_frame_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT); if (!adc_ctx->rx_dma_buf) { ret = ESP_ERR_NO_MEM; goto cleanup; @@ -205,7 +200,7 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi //malloc dma descriptor uint32_t dma_desc_num_per_frame = (hdl_config->conv_frame_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED; uint32_t dma_desc_max_num = dma_desc_num_per_frame * INTERNAL_BUF_NUM; - esp_dma_capable_calloc(1, (sizeof(dma_descriptor_t)) * dma_desc_max_num, &dma_mem_info, (void **)&adc_ctx->hal.rx_desc, &adc_ctx->adc_desc_size); + adc_ctx->hal.rx_desc = heap_caps_aligned_calloc(ADC_DMA_DESC_ALIGN, dma_desc_max_num, sizeof(dma_descriptor_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT); if (!adc_ctx->hal.rx_desc) { ret = ESP_ERR_NO_MEM; goto cleanup; @@ -550,12 +545,12 @@ esp_err_t adc_continuous_flush_pool(adc_continuous_handle_t handle) return ESP_OK; } -esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t * const unit_id, adc_channel_t * const channel) +esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t *const unit_id, adc_channel_t *const channel) { return adc_io_to_channel(io_num, unit_id, channel); } -esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int * const io_num) +esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int *const io_num) { return adc_channel_to_io(unit_id, channel, io_num); } diff --git a/components/esp_adc/adc_dma_internal.h b/components/esp_adc/adc_dma_internal.h index 5cdc73e2bae0..747ea7d5cc41 100644 --- a/components/esp_adc/adc_dma_internal.h +++ b/components/esp_adc/adc_dma_internal.h @@ -32,6 +32,8 @@ typedef struct { intr_handle_t dma_intr_hdl; } adc_dma_t; +#define ADC_DMA_DESC_ALIGN 4 + #ifdef __cplusplus } #endif diff --git a/components/esp_common/include/esp_compiler.h b/components/esp_common/include/esp_compiler.h index 3e278aa9c0dc..6c82a407cc2e 100644 --- a/components/esp_common/include/esp_compiler.h +++ b/components/esp_common/include/esp_compiler.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,7 +11,7 @@ /* * The likely and unlikely macro pairs: * These macros are useful to place when application - * knows the majority ocurrence of a decision paths, + * knows the majority occurrence of a decision paths, * placing one of these macros can hint the compiler * to reorder instructions producing more optimized * code. @@ -52,3 +52,31 @@ #define ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_STR(member, value) .member = value, #define ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(member) #endif + +#define __COMPILER_PRAGMA__(string) _Pragma(#string) +#define _COMPILER_PRAGMA_(string) __COMPILER_PRAGMA__(string) + +#if __clang__ +#define ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE(warning) \ + __COMPILER_PRAGMA__(clang diagnostic push) \ + __COMPILER_PRAGMA__(clang diagnostic ignored "-Wunknown-warning-option") \ + __COMPILER_PRAGMA__(clang diagnostic ignored warning) +#define ESP_COMPILER_DIAGNOSTIC_POP(warning) \ + __COMPILER_PRAGMA__(clang diagnostic pop) +#elif __GNUC__ +#define ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE(warning) \ + __COMPILER_PRAGMA__(GCC diagnostic push) \ + __COMPILER_PRAGMA__(GCC diagnostic ignored "-Wpragmas") \ + __COMPILER_PRAGMA__(GCC diagnostic ignored warning) +#define ESP_COMPILER_DIAGNOSTIC_POP(warning) \ + __COMPILER_PRAGMA__(GCC diagnostic pop) +#else +#define ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE(warning) +#define ESP_COMPILER_DIAGNOSTIC_POP(warning) +#endif + +#if __clang_analyzer__ || CONFIG_COMPILER_STATIC_ANALYZER +#define ESP_STATIC_ANALYZER_CHECK(_expr_, _ret_) do { if ((_expr_)) { return (_ret_); } } while(0) +#else +#define ESP_STATIC_ANALYZER_CHECK(_expr_, _ret_) +#endif diff --git a/components/esp_driver_gptimer/CMakeLists.txt b/components/esp_driver_gptimer/CMakeLists.txt index 99dc8b360837..143387a4d313 100644 --- a/components/esp_driver_gptimer/CMakeLists.txt +++ b/components/esp_driver_gptimer/CMakeLists.txt @@ -1,24 +1,23 @@ idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() set(srcs) set(public_include "include") if(CONFIG_SOC_GPTIMER_SUPPORTED) list(APPEND srcs "src/gptimer.c" - "src/gptimer_priv.c") + "src/gptimer_common.c") endif() if(CONFIG_SOC_TIMER_SUPPORT_ETM) list(APPEND srcs "src/gptimer_etm.c") endif() -if(${target} STREQUAL "linux") - set(requires "") -else() - set(requires esp_pm) -endif() +set(requires esp_pm) idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} - REQUIRES "${requires}" + REQUIRES ${requires} LDFRAGMENTS "linker.lf" ) diff --git a/components/esp_driver_gptimer/src/gptimer.c b/components/esp_driver_gptimer/src/gptimer.c index 6fd66b9b95a3..452f4a60f067 100644 --- a/components/esp_driver_gptimer/src/gptimer.c +++ b/components/esp_driver_gptimer/src/gptimer.c @@ -17,76 +17,14 @@ #include "esp_err.h" #include "esp_log.h" #include "esp_check.h" -#include "esp_pm.h" #include "driver/gptimer.h" -#include "hal/timer_types.h" -#include "hal/timer_hal.h" -#include "hal/timer_ll.h" -#include "soc/timer_periph.h" #include "esp_memory_utils.h" -#include "esp_private/periph_ctrl.h" -#include "esp_private/esp_clk.h" -#include "clk_ctrl_os.h" -#include "esp_clk_tree.h" #include "gptimer_priv.h" -#if GPTIMER_USE_RETENTION_LINK -#include "esp_private/sleep_retention.h" -#endif - static const char *TAG = "gptimer"; -#if SOC_PERIPH_CLK_CTRL_SHARED -#define GPTIMER_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() -#else -#define GPTIMER_CLOCK_SRC_ATOMIC() -#endif - -typedef struct gptimer_platform_t { - _lock_t mutex; // platform level mutex lock - gptimer_group_t *groups[SOC_TIMER_GROUPS]; // timer group pool - int group_ref_counts[SOC_TIMER_GROUPS]; // reference count used to protect group install/uninstall -} gptimer_platform_t; - -// gptimer driver platform, it's always a singleton -static gptimer_platform_t s_platform; - -static gptimer_group_t *gptimer_acquire_group_handle(int group_id); -static void gptimer_release_group_handle(gptimer_group_t *group); -static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t src_clk, uint32_t resolution_hz); static void gptimer_default_isr(void *args); -#if GPTIMER_USE_RETENTION_LINK -static esp_err_t sleep_tg_timer_retention_link_cb(void *arg) -{ - uint32_t group_id = *(uint32_t *)arg; - esp_err_t err = sleep_retention_entries_create(tg_timer_regs_retention[group_id].link_list, - tg_timer_regs_retention[group_id].link_num, - REGDMA_LINK_PRI_6, - (group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER : SLEEP_RETENTION_MODULE_TG1_TIMER); - if (err == ESP_OK) { - ESP_LOGD(TAG, "Timer group %ld retention initialization", group_id); - } - ESP_RETURN_ON_ERROR(err, TAG, "Failed to create sleep retention linked list for timer group %ld", group_id); - return err; -} - -static void gptimer_create_retention_module(gptimer_group_t *group) -{ - _lock_acquire(&s_platform.mutex); - int group_id = group->group_id; - if ((group->sleep_retention_initialized == true) && (group->retention_link_created == false)) { - esp_err_t err = sleep_retention_module_allocate((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER : SLEEP_RETENTION_MODULE_TG1_TIMER); - if (err != ESP_OK) { - ESP_LOGW(TAG, "Failed to allocate sleep retention linked list for timer group %d retention, power domain can't turn off", group_id); - } else { - group->retention_link_created = true; - } - } - _lock_release(&s_platform.mutex); -} -#endif - static esp_err_t gptimer_register_to_group(gptimer_t *timer) { gptimer_group_t *group = NULL; @@ -156,6 +94,10 @@ esp_err_t gptimer_new_timer(const gptimer_config_t *config, gptimer_handle_t *re TAG, "invalid interrupt priority:%d", config->intr_priority); } +#if !SOC_TIMER_SUPPORT_SLEEP_RETENTION + ESP_RETURN_ON_FALSE(config->flags.backup_before_sleep == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported"); +#endif // SOC_TIMER_SUPPORT_SLEEP_RETENTION + timer = heap_caps_calloc(1, sizeof(gptimer_t), GPTIMER_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(timer, ESP_ERR_NO_MEM, err, TAG, "no mem for gptimer"); // register timer to the group (because one group can have several timers) @@ -392,8 +334,8 @@ esp_err_t gptimer_start(gptimer_handle_t timer) // the register used by the following LL functions are shared with other API, // which is possible to run along with this function, so we need to protect portENTER_CRITICAL_SAFE(&timer->spinlock); - timer_ll_enable_counter(timer->hal.dev, timer->timer_id, true); timer_ll_enable_alarm(timer->hal.dev, timer->timer_id, timer->flags.alarm_en); + timer_ll_enable_counter(timer->hal.dev, timer->timer_id, true); portEXIT_CRITICAL_SAFE(&timer->spinlock); } else { ESP_RETURN_ON_FALSE_ISR(false, ESP_ERR_INVALID_STATE, TAG, "timer is not enabled yet"); @@ -422,172 +364,6 @@ esp_err_t gptimer_stop(gptimer_handle_t timer) return ESP_OK; } -static gptimer_group_t *gptimer_acquire_group_handle(int group_id) -{ - bool new_group = false; - gptimer_group_t *group = NULL; - - // prevent install timer group concurrently - _lock_acquire(&s_platform.mutex); - if (!s_platform.groups[group_id]) { - group = heap_caps_calloc(1, sizeof(gptimer_group_t), GPTIMER_MEM_ALLOC_CAPS); - if (group) { - new_group = true; - s_platform.groups[group_id] = group; - // initialize timer group members - group->group_id = group_id; - group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; - } - } else { - group = s_platform.groups[group_id]; - } - if (group) { - // someone acquired the group handle means we have a new object that refer to this group - s_platform.group_ref_counts[group_id]++; - } - - if (new_group) { - // !!! HARDWARE SHARED RESOURCE !!! - // the gptimer and watchdog reside in the same the timer group - // we need to increase/decrease the reference count before enable/disable/reset the peripheral - PERIPH_RCC_ACQUIRE_ATOMIC(timer_group_periph_signals.groups[group_id].module, ref_count) { - if (ref_count == 0) { - timer_ll_enable_bus_clock(group_id, true); - timer_ll_reset_register(group_id); - } - } - ESP_LOGD(TAG, "new group (%d) @%p", group_id, group); -#if GPTIMER_USE_RETENTION_LINK - if (group->sleep_retention_initialized != true) { - sleep_retention_module_init_param_t init_param = { - .cbs = { - .create = { - .handle = sleep_tg_timer_retention_link_cb, - .arg = &group_id - }, - }, - .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) - }; - esp_err_t err = sleep_retention_module_init((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER : SLEEP_RETENTION_MODULE_TG1_TIMER, &init_param); - - if (err == ESP_OK) { - group->sleep_retention_initialized = true; - } else { - ESP_LOGW(TAG, "Failed to allocate sleep retention linked list for timer group %d retention", group_id); - } - } -#endif // GPTIMER_USE_RETENTION_LINK - } - _lock_release(&s_platform.mutex); - - return group; -} - -static void gptimer_release_group_handle(gptimer_group_t *group) -{ - int group_id = group->group_id; - bool do_deinitialize = false; - - _lock_acquire(&s_platform.mutex); - s_platform.group_ref_counts[group_id]--; - if (s_platform.group_ref_counts[group_id] == 0) { - assert(s_platform.groups[group_id]); - do_deinitialize = true; - s_platform.groups[group_id] = NULL; - } - - if (do_deinitialize) { - // disable bus clock for the timer group - PERIPH_RCC_RELEASE_ATOMIC(timer_group_periph_signals.groups[group_id].module, ref_count) { - if (ref_count == 0) { - timer_ll_enable_bus_clock(group_id, false); - } - } -#if GPTIMER_USE_RETENTION_LINK - if (group->retention_link_created) { - sleep_retention_module_free((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER : SLEEP_RETENTION_MODULE_TG1_TIMER); - } - if (group->sleep_retention_initialized) { - sleep_retention_module_deinit((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER : SLEEP_RETENTION_MODULE_TG1_TIMER); - } -#endif - free(group); - ESP_LOGD(TAG, "del group (%d)", group_id); - } - _lock_release(&s_platform.mutex); -} - -static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t src_clk, uint32_t resolution_hz) -{ - uint32_t counter_src_hz = 0; - int timer_id = timer->timer_id; - - // TODO: [clk_tree] to use a generic clock enable/disable or acquire/release function for all clock source -#if SOC_TIMER_GROUP_SUPPORT_RC_FAST - if (src_clk == GPTIMER_CLK_SRC_RC_FAST) { - // RC_FAST clock is not enabled automatically on start up, we enable it here manually. - // Note there's a ref count in the enable/disable function, we must call them in pair in the driver. - periph_rtc_dig_clk8m_enable(); - } -#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST - - // get clock source frequency - ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz), - TAG, "get clock source frequency failed"); - -#if CONFIG_PM_ENABLE - bool need_pm_lock = true; - // to make the gptimer work reliable, the source clock must stay alive and unchanged - // driver will create different pm lock for that purpose, according to different clock source - esp_pm_lock_type_t pm_lock_type = ESP_PM_NO_LIGHT_SLEEP; - -#if SOC_TIMER_GROUP_SUPPORT_RC_FAST - if (src_clk == GPTIMER_CLK_SRC_RC_FAST) { - // RC_FAST won't be turn off in sleep and won't change its frequency during DFS - need_pm_lock = false; - } -#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST - -#if SOC_TIMER_GROUP_SUPPORT_APB - if (src_clk == GPTIMER_CLK_SRC_APB) { - // APB clock frequency can be changed during DFS - pm_lock_type = ESP_PM_APB_FREQ_MAX; - } -#endif // SOC_TIMER_GROUP_SUPPORT_APB - -#if CONFIG_IDF_TARGET_ESP32C2 - if (src_clk == GPTIMER_CLK_SRC_PLL_F40M) { - // although PLL_F40M clock is a fixed PLL clock, which is unchangeable - // on ESP32C2, PLL_F40M can be turned off even during DFS (unlike other PLL clocks) - // so we're acquiring a fake "APB" lock here to prevent the system from doing DFS - pm_lock_type = ESP_PM_APB_FREQ_MAX; - } -#endif // CONFIG_IDF_TARGET_ESP32C2 - - if (need_pm_lock) { - sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0 - ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, timer->pm_lock_name, &timer->pm_lock), - TAG, "create pm lock failed"); - } -#endif // CONFIG_PM_ENABLE - - // !!! HARDWARE SHARED RESOURCE !!! - // on some ESP chip, different peripheral's clock source setting are mixed in the same register - // so we need to make this done in an atomic way - GPTIMER_CLOCK_SRC_ATOMIC() { - timer_ll_set_clock_source(timer->hal.dev, timer_id, src_clk); - timer_ll_enable_clock(timer->hal.dev, timer_id, true); - } - timer->clk_src = src_clk; - uint32_t prescale = counter_src_hz / resolution_hz; // potential resolution loss here - timer_ll_set_clock_prescale(timer->hal.dev, timer_id, prescale); - timer->resolution_hz = counter_src_hz / prescale; // this is the real resolution - if (timer->resolution_hz != resolution_hz) { - ESP_LOGW(TAG, "resolution lost, expect %"PRIu32", real %"PRIu32, resolution_hz, timer->resolution_hz); - } - return ESP_OK; -} - static void gptimer_default_isr(void *args) { bool need_yield = false; diff --git a/components/esp_driver_gptimer/src/gptimer_common.c b/components/esp_driver_gptimer/src/gptimer_common.c new file mode 100644 index 000000000000..ea5bf5e8c146 --- /dev/null +++ b/components/esp_driver_gptimer/src/gptimer_common.c @@ -0,0 +1,228 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_check.h" +#include "esp_clk_tree.h" +#include "esp_private/gptimer.h" +#include "gptimer_priv.h" + +static const char *TAG = "gptimer"; + +typedef struct gptimer_platform_t { + _lock_t mutex; // platform level mutex lock + gptimer_group_t *groups[SOC_TIMER_GROUPS]; // timer group pool + int group_ref_counts[SOC_TIMER_GROUPS]; // reference count used to protect group install/uninstall +} gptimer_platform_t; + +// gptimer driver platform, it's always a singleton +static gptimer_platform_t s_platform; + +#if GPTIMER_USE_RETENTION_LINK +static esp_err_t gptimer_create_sleep_retention_link_cb(void *arg) +{ + gptimer_group_t *group = (gptimer_group_t *)arg; + int group_id = group->group_id; + sleep_retention_module_t module = group->sleep_retention_module; + esp_err_t err = sleep_retention_entries_create(tg_timer_reg_retention_info[group_id].regdma_entry_array, + tg_timer_reg_retention_info[group_id].array_size, + REGDMA_LINK_PRI_GPTIMER, module); + ESP_RETURN_ON_ERROR(err, TAG, "create retention link failed"); + return ESP_OK; +} + +void gptimer_create_retention_module(gptimer_group_t *group) +{ + sleep_retention_module_t module = group->sleep_retention_module; + _lock_acquire(&s_platform.mutex); + if (group->retention_link_created == false) { + if (sleep_retention_module_allocate(module) != ESP_OK) { + // even though the sleep retention module create failed, GPTimer driver should still work, so just warning here + ESP_LOGW(TAG, "create retention module for group %d retention, power domain can't turn off", group->group_id); + } else { + group->retention_link_created = true; + } + } + _lock_release(&s_platform.mutex); +} +#endif // GPTIMER_USE_RETENTION_LINK + +gptimer_group_t *gptimer_acquire_group_handle(int group_id) +{ + bool new_group = false; + gptimer_group_t *group = NULL; + + // prevent install timer group concurrently + _lock_acquire(&s_platform.mutex); + if (!s_platform.groups[group_id]) { + group = heap_caps_calloc(1, sizeof(gptimer_group_t), GPTIMER_MEM_ALLOC_CAPS); + if (group) { + new_group = true; + s_platform.groups[group_id] = group; + // initialize timer group members + group->group_id = group_id; + group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; + } + } else { + group = s_platform.groups[group_id]; + } + if (group) { + // someone acquired the group handle means we have a new object that refer to this group + s_platform.group_ref_counts[group_id]++; + } + _lock_release(&s_platform.mutex); + + if (new_group) { + // !!! HARDWARE SHARED RESOURCE !!! + // the gptimer and watchdog reside in the same the timer group + // we need to increase/decrease the reference count before enable/disable/reset the peripheral + PERIPH_RCC_ACQUIRE_ATOMIC(timer_group_periph_signals.groups[group_id].module, ref_count) { + if (ref_count == 0) { + timer_ll_enable_bus_clock(group_id, true); + timer_ll_reset_register(group_id); + } + } +#if GPTIMER_USE_RETENTION_LINK + sleep_retention_module_t module = TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id); + sleep_retention_module_init_param_t init_param = { + .cbs = { + .create = { + .handle = gptimer_create_sleep_retention_link_cb, + .arg = group + }, + }, + .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) + }; + if (sleep_retention_module_init(module, &init_param) == ESP_OK) { + group->sleep_retention_module = module; + } else { + // even though the sleep retention module init failed, RMT driver should still work, so just warning here + ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id); + } +#endif // GPTIMER_USE_RETENTION_LINK + ESP_LOGD(TAG, "new group (%d) @%p", group_id, group); + } + + return group; +} + +void gptimer_release_group_handle(gptimer_group_t *group) +{ + int group_id = group->group_id; + bool do_deinitialize = false; + + _lock_acquire(&s_platform.mutex); + s_platform.group_ref_counts[group_id]--; + if (s_platform.group_ref_counts[group_id] == 0) { + assert(s_platform.groups[group_id]); + do_deinitialize = true; + s_platform.groups[group_id] = NULL; + } + _lock_release(&s_platform.mutex); + + if (do_deinitialize) { + // disable bus clock for the timer group + PERIPH_RCC_RELEASE_ATOMIC(timer_group_periph_signals.groups[group_id].module, ref_count) { + if (ref_count == 0) { + timer_ll_enable_bus_clock(group_id, false); + } + } +#if GPTIMER_USE_RETENTION_LINK + if (group->sleep_retention_module) { + if (group->retention_link_created) { + sleep_retention_module_free(group->sleep_retention_module); + } + sleep_retention_module_deinit(group->sleep_retention_module); + } +#endif + free(group); + ESP_LOGD(TAG, "del group (%d)", group_id); + } +} + +esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t src_clk, uint32_t resolution_hz) +{ + uint32_t counter_src_hz = 0; + int timer_id = timer->timer_id; + + // TODO: [clk_tree] to use a generic clock enable/disable or acquire/release function for all clock source +#if SOC_TIMER_GROUP_SUPPORT_RC_FAST + if (src_clk == GPTIMER_CLK_SRC_RC_FAST) { + // RC_FAST clock is not enabled automatically on start up, we enable it here manually. + // Note there's a ref count in the enable/disable function, we must call them in pair in the driver. + periph_rtc_dig_clk8m_enable(); + } +#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST + + // get clock source frequency + ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz), + TAG, "get clock source frequency failed"); + +#if CONFIG_PM_ENABLE + bool need_pm_lock = true; + // to make the gptimer work reliable, the source clock must stay alive and unchanged + // driver will create different pm lock for that purpose, according to different clock source + esp_pm_lock_type_t pm_lock_type = ESP_PM_NO_LIGHT_SLEEP; + +#if SOC_TIMER_GROUP_SUPPORT_RC_FAST + if (src_clk == GPTIMER_CLK_SRC_RC_FAST) { + // RC_FAST won't be turn off in sleep and won't change its frequency during DFS + need_pm_lock = false; + } +#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST + +#if SOC_TIMER_GROUP_SUPPORT_APB + if (src_clk == GPTIMER_CLK_SRC_APB) { + // APB clock frequency can be changed during DFS + pm_lock_type = ESP_PM_APB_FREQ_MAX; + } +#endif // SOC_TIMER_GROUP_SUPPORT_APB + +#if CONFIG_IDF_TARGET_ESP32C2 + if (src_clk == GPTIMER_CLK_SRC_PLL_F40M) { + // although PLL_F40M clock is a fixed PLL clock, which is unchangeable + // on ESP32C2, PLL_F40M can be turned off even during DFS (unlike other PLL clocks) + // so we're acquiring a fake "APB" lock here to prevent the system from doing DFS + pm_lock_type = ESP_PM_APB_FREQ_MAX; + } +#endif // CONFIG_IDF_TARGET_ESP32C2 + + if (need_pm_lock) { + sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0 + ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, timer->pm_lock_name, &timer->pm_lock), + TAG, "create pm lock failed"); + } +#endif // CONFIG_PM_ENABLE + + // !!! HARDWARE SHARED RESOURCE !!! + // on some ESP chip, different peripheral's clock source setting are mixed in the same register + // so we need to make this done in an atomic way + GPTIMER_CLOCK_SRC_ATOMIC() { + timer_ll_set_clock_source(timer->hal.dev, timer_id, src_clk); + timer_ll_enable_clock(timer->hal.dev, timer_id, true); + } + timer->clk_src = src_clk; + uint32_t prescale = counter_src_hz / resolution_hz; // potential resolution loss here + timer_ll_set_clock_prescale(timer->hal.dev, timer_id, prescale); + timer->resolution_hz = counter_src_hz / prescale; // this is the real resolution + if (timer->resolution_hz != resolution_hz) { + ESP_LOGW(TAG, "resolution lost, expect %"PRIu32", real %"PRIu32, resolution_hz, timer->resolution_hz); + } + return ESP_OK; +} + +esp_err_t gptimer_get_intr_handle(gptimer_handle_t timer, intr_handle_t *ret_intr_handle) +{ + ESP_RETURN_ON_FALSE(timer && ret_intr_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + *ret_intr_handle = timer->intr; + return ESP_OK; +} + +esp_err_t gptimer_get_pm_lock(gptimer_handle_t timer, esp_pm_lock_handle_t *ret_pm_lock) +{ + ESP_RETURN_ON_FALSE(timer && ret_pm_lock, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + *ret_pm_lock = timer->pm_lock; + return ESP_OK; +} diff --git a/components/esp_driver_gptimer/src/gptimer_priv.c b/components/esp_driver_gptimer/src/gptimer_priv.c deleted file mode 100644 index bd834f20145c..000000000000 --- a/components/esp_driver_gptimer/src/gptimer_priv.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_check.h" -#include "esp_private/gptimer.h" -#include "gptimer_priv.h" - -static const char *TAG = "gptimer"; - -esp_err_t gptimer_get_intr_handle(gptimer_handle_t timer, intr_handle_t *ret_intr_handle) -{ - ESP_RETURN_ON_FALSE(timer && ret_intr_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - *ret_intr_handle = timer->intr; - return ESP_OK; -} - -esp_err_t gptimer_get_pm_lock(gptimer_handle_t timer, esp_pm_lock_handle_t *ret_pm_lock) -{ - ESP_RETURN_ON_FALSE(timer && ret_pm_lock, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - *ret_pm_lock = timer->pm_lock; - return ESP_OK; -} diff --git a/components/esp_driver_gptimer/src/gptimer_priv.h b/components/esp_driver_gptimer/src/gptimer_priv.h index fe072c85d43a..3c117af44f9d 100644 --- a/components/esp_driver_gptimer/src/gptimer_priv.h +++ b/components/esp_driver_gptimer/src/gptimer_priv.h @@ -9,13 +9,19 @@ #include #include #include "sdkconfig.h" +#include "soc/soc_caps.h" #include "freertos/FreeRTOS.h" #include "esp_err.h" #include "esp_intr_alloc.h" #include "esp_heap_caps.h" +#include "clk_ctrl_os.h" #include "esp_pm.h" -#include "soc/soc_caps.h" +#include "soc/timer_periph.h" +#include "hal/timer_types.h" #include "hal/timer_hal.h" +#include "hal/timer_ll.h" +#include "esp_private/sleep_retention.h" +#include "esp_private/periph_ctrl.h" #ifdef __cplusplus extern "C" { @@ -41,6 +47,12 @@ extern "C" { #define GPTIMER_USE_RETENTION_LINK (SOC_TIMER_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) +#if SOC_PERIPH_CLK_CTRL_SHARED +#define GPTIMER_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define GPTIMER_CLOCK_SRC_ATOMIC() +#endif + typedef struct gptimer_t gptimer_t; typedef struct gptimer_group_t { @@ -48,8 +60,8 @@ typedef struct gptimer_group_t { portMUX_TYPE spinlock; // to protect per-group register level concurrent access gptimer_t *timers[SOC_TIMER_GROUP_TIMERS_PER_GROUP]; #if GPTIMER_USE_RETENTION_LINK - bool sleep_retention_initialized; // mark if the retention link is initialized - bool retention_link_created; // mark if the retention link is created + sleep_retention_module_t sleep_retention_module; // sleep retention module + bool retention_link_created; // mark if the retention link is created #endif } gptimer_group_t; @@ -87,6 +99,11 @@ struct gptimer_t { } flags; }; +gptimer_group_t *gptimer_acquire_group_handle(int group_id); +void gptimer_release_group_handle(gptimer_group_t *group); +esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t src_clk, uint32_t resolution_hz); +void gptimer_create_retention_module(gptimer_group_t *group); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_gptimer/test_apps/gptimer/CMakeLists.txt b/components/esp_driver_gptimer/test_apps/gptimer/CMakeLists.txt index ba96212bd03e..6e95a94e7705 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/CMakeLists.txt +++ b/components/esp_driver_gptimer/test_apps/gptimer/CMakeLists.txt @@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES) DEPENDS ${elf} ) endif() + +message(STATUS "Checking gptimer registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "timer_group" "pcr" "hp_sys_clkrst" + HAL_MODULES "timer") diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt b/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt index 2768a1f04e1c..39337b4ce696 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt @@ -5,6 +5,10 @@ if(CONFIG_GPTIMER_ISR_IRAM_SAFE) list(APPEND srcs "test_gptimer_iram.c") endif() +if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED AND CONFIG_PM_ENABLE) + list(APPEND srcs "test_gptimer_sleep.c") +endif() + # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer.c b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer.c index 4d3e6b49878c..757c2f715c1c 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer.c +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer.c @@ -13,15 +13,6 @@ #include "soc/soc_caps.h" #include "esp_attr.h" -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TIMER_SUPPORT_SLEEP_RETENTION -#include "esp_random.h" -#include "esp_rom_uart.h" -#include "esp_sleep.h" -#include "esp_private/esp_sleep_internal.h" -#include "esp_private/sleep_cpu.h" -#include "esp_private/esp_pmu.h" -#endif - #if CONFIG_GPTIMER_ISR_IRAM_SAFE #define TEST_ALARM_CALLBACK_ATTR IRAM_ATTR #else @@ -605,82 +596,3 @@ TEST_CASE("gptimer_trig_alarm_with_old_count", "[gptimer]") TEST_ESP_OK(gptimer_disable(timer)); TEST_ESP_OK(gptimer_del_timer(timer)); } - -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TIMER_SUPPORT_SLEEP_RETENTION -static gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS]; -static uint32_t timer_resolution_hz[SOC_TIMER_GROUP_TOTAL_TIMERS]; - -static void test_gptimer_retention(gptimer_config_t *timer_config) -{ - for (int i = 0; i < SOC_TIMER_GROUP_TOTAL_TIMERS; i++) { - TEST_ESP_OK(gptimer_new_timer(timer_config, &timers[i])); - TEST_ESP_OK(gptimer_get_resolution(timers[i], &timer_resolution_hz[i])); - - unsigned long long count_start_value = 0, count_end_value = 0; - - // Let gptimer run for a while - TEST_ESP_OK(gptimer_enable(timers[i])); - TEST_ESP_OK(gptimer_start(timers[i])); - vTaskDelay((esp_random() % 500) / portTICK_PERIOD_MS); - TEST_ESP_OK(gptimer_stop(timers[i])); - TEST_ESP_OK(gptimer_disable(timers[i])); - TEST_ESP_OK(gptimer_get_raw_count(timers[i], &count_start_value)); - - esp_sleep_context_t sleep_ctx; - esp_sleep_set_sleep_context(&sleep_ctx); - TEST_ESP_OK(sleep_cpu_configure(true)); - esp_rom_output_tx_wait_idle(0); - esp_sleep_enable_timer_wakeup(50 * 1000); - esp_light_sleep_start(); - - if (timer_config->flags.backup_before_sleep) { - TEST_ASSERT_EQUAL(PMU_SLEEP_PD_TOP, sleep_ctx.sleep_flags & PMU_SLEEP_PD_TOP); - } else { - TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_flags & PMU_SLEEP_PD_TOP); - } - - TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result); - - TEST_ESP_OK(gptimer_enable(timers[i])); - TEST_ESP_OK(gptimer_start(timers[i])); - - uint32_t random_time_ms = 500 + esp_random() % 2000; - vTaskDelay(random_time_ms / portTICK_PERIOD_MS); - TEST_ESP_OK(gptimer_get_raw_count(timers[i], &count_end_value)); - - // Error tolerance is 2% - TEST_ASSERT_UINT_WITHIN(random_time_ms / 50, random_time_ms, 1000 * (count_end_value - count_start_value) / (unsigned long long)timer_resolution_hz[i]); - - TEST_ESP_OK(gptimer_stop(timers[i])); - TEST_ESP_OK(gptimer_disable(timers[i])); - TEST_ESP_OK(gptimer_del_timer(timers[i])); - TEST_ESP_OK(sleep_cpu_configure(false)); - } -} - -TEST_CASE("gptimer context kept after peripheral powerdown lightsleep with backup_before_sleep enable", "[gptimer]") -{ - printf("install gptimer driver\r\n"); - gptimer_config_t timer_config = { - .resolution_hz = 10 * 1000, // 10KHz, 1 tick = 0.1ms - .clk_src = GPTIMER_CLK_SRC_DEFAULT, - .direction = GPTIMER_COUNT_UP, - .flags.backup_before_sleep = true - }; - - test_gptimer_retention(&timer_config); -} - -TEST_CASE("gptimer context kept after peripheral powerdown lightsleep with backup_before_sleep disable", "[gptimer]") -{ - printf("install gptimer driver\r\n"); - gptimer_config_t timer_config = { - .resolution_hz = 10 * 1000, // 10KHz, 1 tick = 0.1ms - .clk_src = GPTIMER_CLK_SRC_DEFAULT, - .direction = GPTIMER_COUNT_UP, - .flags.backup_before_sleep = false - }; - - test_gptimer_retention(&timer_config); -} -#endif diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c new file mode 100644 index 000000000000..ef4f7909e2af --- /dev/null +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "unity.h" +#include "driver/gptimer.h" +#include "soc/soc_caps.h" +#include "esp_sleep.h" +#include "esp_private/sleep_cpu.h" +#include "esp_private/esp_sleep_internal.h" +#include "esp_private/esp_pmu.h" + +static bool test_gptimer_alarm_stop_callback(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_data) +{ + TaskHandle_t task_handle = (TaskHandle_t)user_data; + BaseType_t high_task_wakeup; + gptimer_stop(timer); + vTaskNotifyGiveFromISR(task_handle, &high_task_wakeup); + return high_task_wakeup == pdTRUE; +} + +/** + * @brief Test the GPTimer driver can still work after light sleep + * + * @param back_up_before_sleep Whether to back up GPTimer registers before sleep + */ +static void test_gptimer_sleep_retention(bool back_up_before_sleep) +{ + TaskHandle_t task_handle = xTaskGetCurrentTaskHandle(); + gptimer_config_t timer_config = { + .resolution_hz = 10000, // 10KHz, 1 tick = 0.1ms + .clk_src = GPTIMER_CLK_SRC_DEFAULT, + .direction = GPTIMER_COUNT_UP, + .flags.backup_before_sleep = back_up_before_sleep, + }; + gptimer_handle_t timer = NULL; + TEST_ESP_OK(gptimer_new_timer(&timer_config, &timer)); + gptimer_event_callbacks_t cbs = { + .on_alarm = test_gptimer_alarm_stop_callback, + }; + TEST_ESP_OK(gptimer_register_event_callbacks(timer, &cbs, task_handle)); + + gptimer_alarm_config_t alarm_config = { + .alarm_count = 10000, // alarm period = 1s + .reload_count = 5000, + .flags.auto_reload_on_alarm = true, + }; + TEST_ESP_OK(gptimer_set_alarm_action(timer, &alarm_config)); + + TEST_ESP_OK(gptimer_enable(timer)); + TEST_ESP_OK(gptimer_start(timer)); + + /// counting from 0 to 10000, it's about 1 second + TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1100))); + uint64_t count_value_before_sleep = 0; + TEST_ESP_OK(gptimer_get_raw_count(timer, &count_value_before_sleep)); + printf("count value before sleep: %llu\n", count_value_before_sleep); + // the count value should near the reload value + TEST_ASSERT_INT_WITHIN(1, 5000, count_value_before_sleep); + + // Note: don't enable the gptimer before going to sleep, ensure no power management lock is acquired by it + TEST_ESP_OK(gptimer_disable(timer)); + + esp_sleep_context_t sleep_ctx; + esp_sleep_set_sleep_context(&sleep_ctx); + printf("go to light sleep for 2 seconds\r\n"); +#if ESP_SLEEP_POWER_DOWN_CPU + TEST_ESP_OK(sleep_cpu_configure(true)); +#endif + TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000)); + TEST_ESP_OK(esp_light_sleep_start()); + + printf("Waked up! Let's see if GPTimer driver can still work...\r\n"); +#if ESP_SLEEP_POWER_DOWN_CPU + TEST_ESP_OK(sleep_cpu_configure(false)); +#endif + + printf("check if the sleep happened as expected\r\n"); + TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result); +#if SOC_TIMER_SUPPORT_SLEEP_RETENTION + if (back_up_before_sleep) { + TEST_ASSERT_EQUAL(PMU_SLEEP_PD_TOP, sleep_ctx.sleep_flags & PMU_SLEEP_PD_TOP); + } +#endif + + uint64_t count_value_after_sleep = 0; + TEST_ESP_OK(gptimer_get_raw_count(timer, &count_value_after_sleep)); + printf("count value after sleep wakeup: %llu\n", count_value_after_sleep); + TEST_ASSERT_EQUAL(count_value_before_sleep, count_value_after_sleep); + + // re-enable the timer and start it + TEST_ESP_OK(gptimer_enable(timer)); + TEST_ESP_OK(gptimer_start(timer)); + + /// this time, the timer should count from 5000 to 10000, it's about 0.5 second + TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(600))); + + TEST_ESP_OK(gptimer_get_raw_count(timer, &count_value_after_sleep)); + printf("gptimer count value: %llu\n", count_value_after_sleep); + // the count value should near the reload value + TEST_ASSERT_INT_WITHIN(1, 5000, count_value_after_sleep); + + TEST_ESP_OK(gptimer_disable(timer)); + TEST_ESP_OK(gptimer_del_timer(timer)); +} + +TEST_CASE("gptimer can work after light sleep", "[gptimer]") +{ + test_gptimer_sleep_retention(false); +#if SOC_TIMER_SUPPORT_SLEEP_RETENTION + test_gptimer_sleep_retention(true); +#endif +} diff --git a/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.ci.release b/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.ci.release index 05634936f485..1a87ebbb4af5 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.ci.release +++ b/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.ci.release @@ -1,9 +1,7 @@ CONFIG_PM_ENABLE=y CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y CONFIG_PM_DFS_INIT_AUTO=y CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y -# For TASK WDT timer PD_TOP sleep retention test -CONFIG_ESP_SLEEP_DEBUG=y -CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y diff --git a/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.defaults b/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.defaults index 1d96fcebe1f9..f365803cb010 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.defaults +++ b/components/esp_driver_gptimer/test_apps/gptimer/sdkconfig.defaults @@ -5,3 +5,6 @@ CONFIG_FREERTOS_HZ=1000 # Disable nano printf, because we need to print the timer count in %llu format CONFIG_NEWLIB_NANO_FORMAT=n + +# primitives for checking sleep internal state +CONFIG_ESP_SLEEP_DEBUG=y diff --git a/components/esp_driver_i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c index afed2c9be402..66d2454a0df6 100644 --- a/components/esp_driver_i2c/i2c_master.c +++ b/components/esp_driver_i2c/i2c_master.c @@ -441,6 +441,8 @@ static void s_i2c_send_commands(i2c_master_bus_handle_t i2c_master, TickType_t t i2c_master->cmd_idx = 0; i2c_master->trans_idx = 0; atomic_store(&i2c_master->status, I2C_STATUS_TIMEOUT); + ESP_LOGE(TAG, "I2C software timeout"); + xSemaphoreGive(i2c_master->cmd_semphr); return; } diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/CMakeLists.txt b/components/esp_driver_i2c/test_apps/i2c_test_apps/CMakeLists.txt index 3ebe26f85d70..ec730ed174d4 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/CMakeLists.txt +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/CMakeLists.txt @@ -23,3 +23,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES) DEPENDS ${elf} ) endif() + +message(STATUS "Checking i2c registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "i2c" "pcr" "hp_sys_clkrst" "lpperi" "lp_clkrst" + HAL_MODULES "i2c") diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/README.md b/components/esp_driver_i2c/test_apps/i2c_test_apps/README.md index bf47d80ec649..3a502b1f86f4 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/README.md +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_jpeg/test_apps/jpeg_test_apps/CMakeLists.txt b/components/esp_driver_jpeg/test_apps/jpeg_test_apps/CMakeLists.txt index 2d8fd6dc23c7..0de9616eba60 100644 --- a/components/esp_driver_jpeg/test_apps/jpeg_test_apps/CMakeLists.txt +++ b/components/esp_driver_jpeg/test_apps/jpeg_test_apps/CMakeLists.txt @@ -12,3 +12,8 @@ project(jpeg_test) target_add_binary_data(jpeg_test.elf "${IDF_PATH}/examples/peripherals/jpeg/jpeg_decode/resources/esp720.jpg" BINARY) target_add_binary_data(jpeg_test.elf "${IDF_PATH}/examples/peripherals/jpeg/jpeg_decode/resources/esp1080.jpg" BINARY) target_add_binary_data(jpeg_test.elf "resources/esp480.rgb" BINARY) + +message(STATUS "Checking jpeg registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "jpeg" "hp_sys_clkrst" + HAL_MODULES "jpeg") diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/CMakeLists.txt b/components/esp_driver_mcpwm/test_apps/mcpwm/CMakeLists.txt index 9bd915a8ce1a..6a3fcc3a3080 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/CMakeLists.txt +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/CMakeLists.txt @@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES) DEPENDS ${elf} ) endif() + +message(STATUS "Checking mcpwm registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "mcpwm" "pcr" "hp_sys_clkrst" + HAL_MODULES "mcpwm") diff --git a/components/esp_driver_parlio/src/parlio_tx.c b/components/esp_driver_parlio/src/parlio_tx.c index 20a0fdc4bcae..3dfeb9f9d0f4 100644 --- a/components/esp_driver_parlio/src/parlio_tx.c +++ b/components/esp_driver_parlio/src/parlio_tx.c @@ -389,10 +389,12 @@ static void IRAM_ATTR parlio_tx_mount_dma_data(parlio_tx_unit_t *tx_unit, const { size_t prepared_length = 0; uint8_t *data = (uint8_t *)buffer; + uint32_t mount_bytes = 0; parlio_dma_desc_t *desc_nc = tx_unit->dma_nodes_nc; while (len) { - uint32_t mount_bytes = len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE ? DMA_DESCRIPTOR_BUFFER_MAX_SIZE : len; + assert(desc_nc); + mount_bytes = len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE ? DMA_DESCRIPTOR_BUFFER_MAX_SIZE : len; len -= mount_bytes; desc_nc->dw0.suc_eof = (len == 0); // whether the last frame desc_nc->dw0.size = mount_bytes; diff --git a/components/esp_driver_parlio/test_apps/.build-test-rules.yml b/components/esp_driver_parlio/test_apps/.build-test-rules.yml index c2c576d51f4f..efce473ee7f9 100644 --- a/components/esp_driver_parlio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_parlio/test_apps/.build-test-rules.yml @@ -3,9 +3,5 @@ components/esp_driver_parlio/test_apps/parlio: disable: - if: SOC_PARLIO_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET in ["esp32h2", "esp32p4"] - temporary: true - reason: IDF-9806 waiting for the fix of the bit shift issue after reset depends_components: - esp_driver_parlio diff --git a/components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt b/components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt index 91e4cdb68b0d..1848fb89df32 100644 --- a/components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt +++ b/components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt @@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES) DEPENDS ${elf} ) endif() + +message(STATUS "Checking parlio registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "parl*io" "pcr" "hp_sys_clkrst" + HAL_MODULES "parlio") diff --git a/components/esp_driver_parlio/test_apps/parlio/README.md b/components/esp_driver_parlio/test_apps/parlio/README.md index 7b822bdb0efd..92d72d31c785 100644 --- a/components/esp_driver_parlio/test_apps/parlio/README.md +++ b/components/esp_driver_parlio/test_apps/parlio/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_board.h b/components/esp_driver_parlio/test_apps/parlio/main/test_board.h index 931cc957f7d1..da22296e39dc 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_board.h +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_board.h @@ -31,6 +31,17 @@ extern "C" { #define TEST_DATA5_GPIO 5 #define TEST_DATA6_GPIO 6 #define TEST_DATA7_GPIO 7 +#elif CONFIG_IDF_TARGET_ESP32C5 +#define TEST_CLK_GPIO 25 +#define TEST_VALID_GPIO 26 +#define TEST_DATA0_GPIO 0 +#define TEST_DATA1_GPIO 1 +#define TEST_DATA2_GPIO 2 +#define TEST_DATA3_GPIO 3 +#define TEST_DATA4_GPIO 4 +#define TEST_DATA5_GPIO 5 +#define TEST_DATA6_GPIO 6 +#define TEST_DATA7_GPIO 7 #elif CONFIG_IDF_TARGET_ESP32H2 #define TEST_CLK_GPIO 10 #define TEST_VALID_GPIO 11 @@ -43,7 +54,7 @@ extern "C" { #define TEST_DATA6_GPIO 8 #define TEST_DATA7_GPIO 9 #elif CONFIG_IDF_TARGET_ESP32P4 -#define TEST_CLK_GPIO 32 +#define TEST_CLK_GPIO 33 #define TEST_VALID_GPIO 36 #define TEST_DATA0_GPIO 20 #define TEST_DATA1_GPIO 21 diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c index 60aacfd5b9ed..cf5f0befcb2a 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c @@ -178,6 +178,8 @@ static void pulse_delimiter_sender_task_i2s(void *args) } } +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-9806 fix the bit shift issue in other target + static void cs_high(spi_transaction_t *trans) { gpio_set_level(TEST_VALID_GPIO, 1); @@ -274,6 +276,7 @@ static void level_delimiter_sender_task_spi(void *args) vTaskDelay(portMAX_DELAY); } } +#endif static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_clk, void (*sender_task_thread)(void *args)) { @@ -339,6 +342,7 @@ static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_ return is_success; } +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-9806 fix the bit shift issue in other target // This test case uses level delimiter TEST_CASE("parallel_rx_unit_level_delimiter_test_via_spi", "[parlio_rx]") { @@ -358,6 +362,7 @@ TEST_CASE("parallel_rx_unit_level_delimiter_test_via_spi", "[parlio_rx]") TEST_ESP_OK(parlio_del_rx_delimiter(deli)); TEST_ASSERT(is_success); } +#endif // This test case uses pulse delimiter TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]") diff --git a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py index dbb3f9d4e069..a6a6d8ec4e1d 100644 --- a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py +++ b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py @@ -5,6 +5,8 @@ @pytest.mark.esp32c6 +@pytest.mark.esp32h2 +@pytest.mark.esp32p4 @pytest.mark.generic @pytest.mark.parametrize( 'config', diff --git a/components/esp_driver_ppa/test_apps/CMakeLists.txt b/components/esp_driver_ppa/test_apps/CMakeLists.txt index dde414194371..903732e97e5c 100644 --- a/components/esp_driver_ppa/test_apps/CMakeLists.txt +++ b/components/esp_driver_ppa/test_apps/CMakeLists.txt @@ -7,3 +7,8 @@ include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) project(ppa_test) + +message(STATUS "Checking ppa registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "ppa" "hp_sys_clkrst" + HAL_MODULES "ppa") diff --git a/components/esp_driver_rmt/src/rmt_private.h b/components/esp_driver_rmt/src/rmt_private.h index 827b9462f580..2cbe57e7a3cb 100644 --- a/components/esp_driver_rmt/src/rmt_private.h +++ b/components/esp_driver_rmt/src/rmt_private.h @@ -73,7 +73,6 @@ typedef dma_descriptor_align4_t rmt_dma_descriptor_t; #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) #define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) -// Use retention link only when the target supports sleep retention and PM is enabled #define RMT_USE_RETENTION_LINK (SOC_RMT_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) typedef struct { diff --git a/components/esp_driver_rmt/src/rmt_tx.c b/components/esp_driver_rmt/src/rmt_tx.c index 2b3478967f97..915b68d0d3e7 100644 --- a/components/esp_driver_rmt/src/rmt_tx.c +++ b/components/esp_driver_rmt/src/rmt_tx.c @@ -1106,6 +1106,7 @@ static void IRAM_ATTR rmt_tx_default_isr(void *args) } #if SOC_RMT_SUPPORT_DMA +ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-null-dereference") // TODO IDF-10235 static bool IRAM_ATTR rmt_dma_tx_eof_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { rmt_tx_channel_t *tx_chan = (rmt_tx_channel_t *)user_data; @@ -1132,4 +1133,5 @@ static bool IRAM_ATTR rmt_dma_tx_eof_cb(gdma_channel_handle_t dma_chan, gdma_eve } return false; } +ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-null-dereference") #endif // SOC_RMT_SUPPORT_DMA diff --git a/components/esp_driver_rmt/test_apps/rmt/CMakeLists.txt b/components/esp_driver_rmt/test_apps/rmt/CMakeLists.txt index 6c44dbcf33de..aec93de5d13d 100644 --- a/components/esp_driver_rmt/test_apps/rmt/CMakeLists.txt +++ b/components/esp_driver_rmt/test_apps/rmt/CMakeLists.txt @@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES) DEPENDS ${elf} ) endif() + +message(STATUS "Checking rmt registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "rmt" "pcr" "hp_sys_clkrst" + HAL_MODULES "rmt") diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/CMakeLists.txt b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/CMakeLists.txt index 40ea327d0b50..f5becedb87fb 100644 --- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/CMakeLists.txt +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/CMakeLists.txt @@ -11,3 +11,8 @@ set(EXTRA_COMPONENT_DIRS include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(sdio) + +message(STATUS "Checking sdio registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "host" "hinf" "slc" "pcr" + HAL_MODULES "sdio") diff --git a/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h b/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h index a9ec0dea7967..cf15c14be8aa 100644 --- a/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h +++ b/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h @@ -55,11 +55,7 @@ extern "C" { .benchmark = { \ .filter_mode = TOUCH_BM_IIR_FILTER_4, \ .jitter_step = 4, \ - .update = { \ - .pos_thresh = TOUCH_UPDATE_BM_POS_THRESH_1_4, \ - .neg_thresh = TOUCH_UPDATE_BM_NEG_THRESH_1_4, \ - .neg_limit = 5, \ - }, \ + .denoise_lvl = 1, \ }, \ .data = { \ .smooth_filter = TOUCH_SMOOTH_IIR_FILTER_2, \ @@ -115,35 +111,6 @@ typedef enum { TOUCH_BM_JITTER_FILTER, /*!< Jitter Filter for benchmark, raw value +/- jitter_step */ } touch_benchmark_filter_mode_t; -/** - * @brief Positive noise limitation of benchmark - * benchmark will only update gradually when - * the smooth data within the positive noise limitation - * - */ -typedef enum { - TOUCH_UPDATE_BM_POS_ALWAYS = -1, /*!< Always update benchmark when (smooth_data - benchmark) > 0 */ - TOUCH_UPDATE_BM_POS_THRESH_1_2 = 0, /*!< Only update benchmark when the (smooth_data - benchmark) < 1/2 * activate_threshold */ - TOUCH_UPDATE_BM_POS_THRESH_3_8, /*!< Only update benchmark when the (smooth_data - benchmark) < 3/8 * activate_threshold */ - TOUCH_UPDATE_BM_POS_THRESH_1_4, /*!< Only update benchmark when the (smooth_data - benchmark) < 1/4 * activate_threshold */ - TOUCH_UPDATE_BM_POS_THRESH_1, /*!< Only update benchmark when the (smooth_data - benchmark) < 1 * activate_threshold */ -} touch_benchmark_pos_thresh_t; - -/** - * @brief Negative noise limitation of benchmark - * benchmark will only update gradually when - * the smooth data within the negative noise limitation - * - */ -typedef enum { - TOUCH_UPDATE_BM_NEG_NEVER = -2, /*!< Never update benchmark when (benchmark - smooth_data) > 0 */ - TOUCH_UPDATE_BM_NEG_ALWAYS = -1, /*!< Always update benchmark when (benchmark - smooth_data) > 0 */ - TOUCH_UPDATE_BM_NEG_THRESH_1_2 = 0, /*!< Only update benchmark when the (benchmark - smooth_data) < 1/2 * activate_threshold */ - TOUCH_UPDATE_BM_NEG_THRESH_3_8, /*!< Only update benchmark when the (benchmark - smooth_data) < 3/8 * activate_threshold */ - TOUCH_UPDATE_BM_NEG_THRESH_1_4, /*!< Only update benchmark when the (benchmark - smooth_data) < 1/4 * activate_threshold */ - TOUCH_UPDATE_BM_NEG_THRESH_1, /*!< Only update benchmark when the (benchmark - smooth_data) < 1 * activate_threshold */ -} touch_benchmark_neg_thresh_t; - /** * @brief Touch channel Infinite Impulse Response (IIR) filter for smooth data * @@ -222,31 +189,11 @@ typedef struct { touch_benchmark_filter_mode_t filter_mode; /*!< Benchmark filter mode. IIR filter and Jitter filter can be selected, * TOUCH_BM_IIR_FILTER_16 is recommended */ - uint32_t jitter_step; /*!< Jitter filter step size, only takes effect when the `filter_mode` is TOUCH_BM_JITTER_FILTER. Range: 0 ~ 15 */ - /** - * @brief Benchmark update strategy - */ - struct { - touch_benchmark_pos_thresh_t pos_thresh; /*!< Select the positive noise threshold. Higher = More noise resistance. - * Range: [-1 ~ 3]. The coefficient of the positive threshold are -1: always; 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; - * Once the data of the channel exceeded the positive threshold (i.e., benchmark + coefficient * touch threshold), - * the benchmark will stop updated to that value. - * -1: ignore the positive threshold and always update the benchmark for positive noise - */ - touch_benchmark_neg_thresh_t neg_thresh; /*!< Select the negative noise threshold. Higher = More noise resistance. - * Range: [-2 ~ 3]. The coefficient of the negative threshold are -2: never; -1: always; 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; - * Once the data of the channel below the negative threshold (i.e., benchmark - coefficient * touch threshold), - * the benchmark will stop updated to that value, - * unless the data keep below the negative threshold for more than the limitation of `neg_limit` - * -1: ignore the negative threshold and always update the benchmark for negative noise - * -2: never update the benchmark for negative noise - */ - uint32_t neg_limit; /*!< Set the time limitation of the negative threshold. - * The benchmark will be updated to the value that below to the negative threshold after the limited time. - * Normally the negative update is used at the beginning, as the initial benchmark is a very large value. - * (the unit of `neg_limit` is the tick of the slow clock source) + uint32_t jitter_step; /*!< Jitter filter step size, only takes effect when the `filter_mode` is TOUCH_BM_JITTER_FILTER. Range: [0 ~ 15] */ + int denoise_lvl; /*!< The denoise level, which determines the noise bouncing range that won't trigger benchmark update. + * Range: [0 ~ 4]. The greater the denoise_lvl is, more noise resistance will be. Specially, `0` stands for no denoise + * Typically, recommend to set this field to 1. */ - } update; /*!< The benchmark update strategy */ } benchmark; /*!< Benchmark filter */ /** * @brief Data configuration diff --git a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c index acc88c09c553..ebf9acecdd6a 100644 --- a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c +++ b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c @@ -282,8 +282,8 @@ esp_err_t touch_sensor_config_filter(touch_sensor_handle_t sens_handle, const to { TOUCH_NULL_POINTER_CHECK(sens_handle); if (filter_cfg) { - ESP_RETURN_ON_FALSE(filter_cfg->benchmark.update.neg_limit >= filter_cfg->data.debounce_cnt, - ESP_ERR_INVALID_ARG, TAG, "The neg_limit should be greater than debounce_cnt"); + ESP_RETURN_ON_FALSE(filter_cfg->benchmark.denoise_lvl >= 0 && filter_cfg->benchmark.denoise_lvl <= 4, + ESP_ERR_INVALID_ARG, TAG, "denoise_lvl is out of range"); } esp_err_t ret = ESP_OK; @@ -297,8 +297,7 @@ esp_err_t touch_sensor_config_filter(touch_sensor_handle_t sens_handle, const to if (filter_cfg->benchmark.filter_mode == TOUCH_BM_JITTER_FILTER) { touch_ll_filter_set_jitter_step(filter_cfg->benchmark.jitter_step); } - touch_ll_filter_set_pos_noise_thresh(filter_cfg->benchmark.update.pos_thresh); - touch_ll_filter_set_neg_noise_thresh(filter_cfg->benchmark.update.neg_thresh, filter_cfg->benchmark.update.neg_limit); + touch_ll_filter_set_denoise_level(filter_cfg->benchmark.denoise_lvl); /* Configure the touch data filter */ touch_ll_filter_set_smooth_mode(filter_cfg->data.smooth_filter); touch_ll_filter_set_active_hysteresis(filter_cfg->data.active_hysteresis); diff --git a/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c index e03b4efc764f..f7623139ddc1 100644 --- a/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c +++ b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c @@ -155,15 +155,15 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se ESP_RETURN_ON_FALSE((usb_serial_jtag_config->rx_buffer_size > USB_SER_JTAG_RX_MAX_SIZE), ESP_ERR_INVALID_ARG, USB_SERIAL_JTAG_TAG, "RX buffer prepared is so small, should larger than 64"); ESP_RETURN_ON_FALSE((usb_serial_jtag_config->tx_buffer_size > 0), ESP_ERR_INVALID_ARG, USB_SERIAL_JTAG_TAG, "TX buffer is not prepared"); p_usb_serial_jtag_obj = (usb_serial_jtag_obj_t*) heap_caps_calloc(1, sizeof(usb_serial_jtag_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); - p_usb_serial_jtag_obj->rx_buf_size = usb_serial_jtag_config->rx_buffer_size; - p_usb_serial_jtag_obj->tx_buf_size = usb_serial_jtag_config->tx_buffer_size; - p_usb_serial_jtag_obj->tx_stash_cnt = 0; - p_usb_serial_jtag_obj->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; if (p_usb_serial_jtag_obj == NULL) { ESP_LOGE(USB_SERIAL_JTAG_TAG, "memory allocate error"); err = ESP_ERR_NO_MEM; goto _exit; } + p_usb_serial_jtag_obj->rx_buf_size = usb_serial_jtag_config->rx_buffer_size; + p_usb_serial_jtag_obj->tx_buf_size = usb_serial_jtag_config->tx_buffer_size; + p_usb_serial_jtag_obj->tx_stash_cnt = 0; + p_usb_serial_jtag_obj->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; p_usb_serial_jtag_obj->rx_ring_buf = xRingbufferCreate(p_usb_serial_jtag_obj->rx_buf_size, RINGBUF_TYPE_BYTEBUF); if (p_usb_serial_jtag_obj->rx_ring_buf == NULL) { diff --git a/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml index 18ab2db959d5..479096d5eace 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml +++ b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml @@ -4,7 +4,7 @@ components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag: disable: - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1 disable_test: - - if: IDF_TARGET in ["esp32p4"] + - if: IDF_TARGET in ["esp32p4", "esp32c5"] temporary: true reason: No runners. depends_components: diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/CMakeLists.txt b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/CMakeLists.txt index 0881e007a7db..e9542886c97c 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/CMakeLists.txt +++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/CMakeLists.txt @@ -6,3 +6,9 @@ set(COMPONENTS main) include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(usb_serial_test) + + +message(STATUS "Checking usb serial jtag registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "usb_serial_jtag" "pcr" "hp_sys_clkrst" + HAL_MODULES "usb_serial_jtag") diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md index ad95e4113393..77a98e02d0a6 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md +++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_eth/test_apps/CMakeLists.txt b/components/esp_eth/test_apps/CMakeLists.txt index 7e4b7ad8d3ff..66d496fdf09a 100644 --- a/components/esp_eth/test_apps/CMakeLists.txt +++ b/components/esp_eth/test_apps/CMakeLists.txt @@ -8,3 +8,8 @@ project(esp_eth_test) idf_component_get_property(lib esp_eth COMPONENT_LIB) target_compile_options(${lib} PRIVATE "-fsanitize=undefined" "-fno-sanitize=shift-base") + +message(STATUS "Checking emac registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "emac*" "hp_system" "hp_sys_clkrst" "lp_clkrst" + HAL_MODULES "emac*") diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c index f2e0cae96258..cfce5043541d 100644 --- a/components/esp_http_client/esp_http_client.c +++ b/components/esp_http_client/esp_http_client.c @@ -662,9 +662,11 @@ static bool init_common_tcp_transport(esp_http_client_handle_t client, const esp } if (config->if_name) { - client->if_name = calloc(1, sizeof(struct ifreq)); - ESP_RETURN_ON_FALSE(client->if_name, false, TAG, "Memory exhausted"); - memcpy(client->if_name, config->if_name, sizeof(struct ifreq)); + if (client->if_name == NULL) { + client->if_name = calloc(1, sizeof(struct ifreq)); + ESP_RETURN_ON_FALSE(client->if_name, false, TAG, "Memory exhausted"); + memcpy(client->if_name, config->if_name, sizeof(struct ifreq)); + } esp_transport_tcp_set_interface_name(transport, client->if_name); } return true; diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 12a05f4682ab..45eb3932693c 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -189,6 +189,10 @@ idf_build_get_property(target IDF_TARGET) add_subdirectory(port/${target}) add_subdirectory(lowpower) +if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10229 + target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer") +endif() + if(NOT BOOTLOADER_BUILD) if(CONFIG_SPIRAM) idf_component_optional_requires(PRIVATE esp_psram) diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index 48c66d11373c..8561d769b03f 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -281,6 +281,8 @@ menu "Hardware Settings" endmenu + orsource "./port/$IDF_TARGET/Kconfig.dcdc" + orsource "./port/$IDF_TARGET/Kconfig.ldo" # Invisible bringup bypass options for esp_hw_support component diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index 1686d46dc8df..4f4d8893c884 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -135,8 +135,8 @@ static esp_err_t do_allocate_gdma_channel(const gdma_channel_search_info_t *sear for (int i = start_group_id; i < end_group_id && search_code; i++) { // loop to search group group = gdma_acquire_group_handle(i, search_info->hal_init); - group->bus_id = search_info->bus_id; ESP_GOTO_ON_FALSE(group, ESP_ERR_NO_MEM, err, TAG, "no mem for group(%d)", i); + group->bus_id = search_info->bus_id; for (int j = 0; j < pairs_per_group && search_code; j++) { // loop to search pair pair = gdma_acquire_pair_handle(group, j); ESP_GOTO_ON_FALSE(pair, ESP_ERR_NO_MEM, err, TAG, "no mem for pair(%d,%d)", i, j); diff --git a/components/esp_hw_support/esp_clock_output.c b/components/esp_hw_support/esp_clock_output.c index e8e3179fa96f..9ad86ce4cffc 100644 --- a/components/esp_hw_support/esp_clock_output.c +++ b/components/esp_hw_support/esp_clock_output.c @@ -63,7 +63,9 @@ static clkout_channel_handle_t* clkout_channel_alloc(soc_clkout_sig_id_t clk_sig (s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].mapped_clock == clk_sig)) { allocated_channel = &s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)]; } - allocated_channel->channel_id = (clock_out_channel_t)IONUM_TO_CLKOUT_CHANNEL(gpio_num); + if (allocated_channel != NULL) { + allocated_channel->channel_id = (clock_out_channel_t)IONUM_TO_CLKOUT_CHANNEL(gpio_num); + } portEXIT_CRITICAL(&s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].clkout_channel_lock); #elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX for (uint32_t channel = 0; channel < CLKOUT_CHANNEL_MAX; channel++) { @@ -117,6 +119,9 @@ static esp_clock_output_mapping_t* clkout_mapping_alloc(clkout_channel_handle_t* if (allocated_mapping == NULL) { allocated_mapping = (esp_clock_output_mapping_t *)malloc(sizeof(esp_clock_output_mapping_t)); + if (!allocated_mapping) { + return NULL; + } allocated_mapping->mapped_io = gpio_num; allocated_mapping->clkout_channel_hdl = channel_hdl; allocated_mapping->ref_cnt = 0; diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 827dce448216..02a2c5762f84 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -277,7 +277,7 @@ void pmu_sleep_shutdown_dcdc(void); * @brief DCDC has taken over power supply, shut down LDO to save power consumption */ void pmu_sleep_shutdown_ldo(void); -#endif +#endif // SOC_DCDC_SUPPORTED /** * @brief Enter deep or light sleep mode @@ -309,9 +309,10 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp /** * @brief Finish sleep process settings and get sleep reject status + * @param dslp True if sleep requests id deep-sleep * @return return sleep reject status */ -bool pmu_sleep_finish(void); +bool pmu_sleep_finish(bool dslp); /** * @brief Initialize PMU related power/clock/digital parameters and functions diff --git a/components/esp_hw_support/include/esp_private/rtc_clk.h b/components/esp_hw_support/include/esp_private/rtc_clk.h index 5c143b839670..52610fa0d1ce 100644 --- a/components/esp_hw_support/include/esp_private/rtc_clk.h +++ b/components/esp_hw_support/include/esp_private/rtc_clk.h @@ -74,12 +74,6 @@ uint32_t rtc_clk_mpll_get_freq(void); #endif //#if SOC_CLK_MPLL_SUPPORTED -/** - * @brief Workaround for C2, S3, C6, H2. Trigger the calibration of PLL. Should be called when the bootloader doesn't provide a good enough PLL accuracy. -*/ -void rtc_clk_recalib_bbpll(void); - - #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/include/esp_sleep.h b/components/esp_hw_support/include/esp_sleep.h index 61579a8e4a5a..ec282ab59fce 100644 --- a/components/esp_hw_support/include/esp_sleep.h +++ b/components/esp_hw_support/include/esp_sleep.h @@ -83,6 +83,9 @@ typedef enum { #endif #if SOC_PM_SUPPORT_TOP_PD ESP_PD_DOMAIN_TOP, //!< SoC TOP +#endif +#if SOC_PM_SUPPORT_CNNT_PD + ESP_PD_DOMAIN_CNNT, //!< Hight-speed connect peripherals power domain #endif ESP_PD_DOMAIN_MAX //!< Number of domains } esp_sleep_pd_domain_t; diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c index 2ed461d28017..69d2abc5d3c6 100644 --- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c @@ -435,7 +435,7 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep, } #endif - return pmu_sleep_finish(); + return pmu_sleep_finish(dslp); } esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool), diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c index 8d0b0a2bc764..66adf7de72fe 100644 --- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c6/sleep_cpu.c @@ -475,7 +475,7 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep, } #endif - return pmu_sleep_finish(); + return pmu_sleep_finish(dslp); } esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool), diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c index c02024771009..c4ed6893094e 100644 --- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32h2/sleep_cpu.c @@ -475,7 +475,7 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep, } #endif - return pmu_sleep_finish(); + return pmu_sleep_finish(dslp); } esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool), diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c index 68f469a66e81..e7756703bc1b 100644 --- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c @@ -429,7 +429,7 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep, } #endif - return pmu_sleep_finish(); + return pmu_sleep_finish(dslp); } esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool), @@ -528,8 +528,9 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void) // Wait another core start to do retention bool smp_skip_retention = false; + smp_retention_state_t another_core_state; while (1) { - smp_retention_state_t another_core_state = atomic_load(&s_smp_retention_state[!core_id]); + another_core_state = atomic_load(&s_smp_retention_state[!core_id]); if (another_core_state == SMP_SKIP_RETENTION) { // If another core skips the retention, the current core should also have to skip it. smp_skip_retention = true; @@ -548,9 +549,12 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void) if ((frame_critical->pmufunc & 0x3) == 0x1) { atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_DONE); // wait another core trigger sleep and wakeup - esp_cpu_wait_for_intr(); while (1) { - ; + // If another core's sleep request is rejected by the hardware, jumps out of blocking. + another_core_state = atomic_load(&s_smp_retention_state[!core_id]); + if (another_core_state == SMP_SKIP_RETENTION) { + break; + } } } else { // Start core1 diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index b46b5dbb4646..292ff23beb69 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -251,6 +251,7 @@ void IRAM_ATTR modem_clock_module_mac_reset(periph_module_t module) #if SOC_IEEE802154_SUPPORTED case PERIPH_IEEE802154_MODULE: modem_syscon_ll_reset_zbmac(ctx->hal->syscon_dev); + modem_syscon_ll_reset_zbmac_apb(ctx->hal->syscon_dev); break; #endif default: @@ -382,8 +383,8 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl modem_clock_hal_enable_ble_rtc_timer_clock(MODEM_CLOCK_instance()->hal, true); #if CONFIG_IDF_TARGET_ESP32H2 if (!rc_clk_en) { - extern void esp_ble_rtc_ticks_delay(uint32_t ticks); - esp_ble_rtc_ticks_delay(2); + extern void r_esp_ble_rtc_ticks_delay(uint32_t ticks); + r_esp_ble_rtc_ticks_delay(2); clk_ll_rc32k_disable(); } #endif // CONFIG_IDF_TARGET_ESP32H2 @@ -391,9 +392,9 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl if (efuse_hal_chip_revision() != 0) { if (src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) { pmu_sleep_enable_hp_sleep_sysclk(true); + modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, true); + modem_clock_domain_clk_gate_disable(MODEM_CLOCK_DOMAIN_WIFIPWR, PMU_HP_ICG_MODEM_CODE_SLEEP); } - modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, true); - modem_clock_domain_clk_gate_disable(MODEM_CLOCK_DOMAIN_WIFIPWR, PMU_HP_ICG_MODEM_CODE_SLEEP); } #endif break; @@ -409,10 +410,13 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl default: break; } +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN]; +#endif MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = src; portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 /* The power domain of the low-power clock source required by the modem * module remains powered on during sleep */ esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ @@ -429,13 +433,16 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl : ESP_PD_DOMAIN_MAX); esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON); +#endif } void modem_clock_deselect_lp_clock_source(periph_module_t module) { assert(IS_MODEM_MODULE(module)); portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN]; +#endif MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = MODEM_CLOCK_LPCLK_SRC_INVALID; switch (module) { @@ -454,9 +461,9 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) if (efuse_hal_chip_revision() != 0) { if (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) { pmu_sleep_enable_hp_sleep_sysclk(false); + modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, false); + modem_clock_domain_clk_gate_enable(MODEM_CLOCK_DOMAIN_WIFIPWR, PMU_HP_ICG_MODEM_CODE_SLEEP); } - modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, false); - modem_clock_domain_clk_gate_enable(MODEM_CLOCK_DOMAIN_WIFIPWR, PMU_HP_ICG_MODEM_CODE_SLEEP); } #endif break; @@ -470,6 +477,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) } portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \ : (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \ @@ -477,4 +485,5 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) : (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \ : ESP_PD_DOMAIN_MAX); esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); +#endif } diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c index 20ef6d1d562c..425b72b17f5e 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c @@ -356,24 +356,6 @@ bool rtc_dig_8m_enabled(void) return clk_ll_rc_fast_digi_is_enabled(); } -// Workaround for bootloader not calibrated well issue. -// Placed in IRAM because disabling BBPLL may influence the cache -void rtc_clk_recalib_bbpll(void) -{ - rtc_cpu_freq_config_t old_config; - rtc_clk_cpu_freq_get_config(&old_config); - - // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. - // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. - // Turn off the BBPLL and do calibration again to fix the issue. - // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's - // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. - if (old_config.source == SOC_CPU_CLK_SRC_PLL) { - rtc_clk_cpu_freq_set_xtal(); - rtc_clk_cpu_freq_set_config(&old_config); - } -} - /* Name used in libphy.a:phy_chip_v7.o * TODO: update the library to use rtc_clk_xtal_freq_get */ diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index 971280ed8ff5..8aeb0611736b 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -405,15 +405,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); */ uint64_t rtc_time_get(void); -/** - * @brief Busy loop until next RTC_SLOW_CLK cycle - * - * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. - * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return - * one RTC_SLOW_CLK cycle later. - */ -void rtc_clk_wait_for_slow_cycle(void); - /** * @brief Enable the rtc digital 8M clock * diff --git a/components/esp_hw_support/port/esp32c5/pmu_sleep.c b/components/esp_hw_support/port/esp32c5/pmu_sleep.c index 6d8e27faf384..262ce0086e6e 100644 --- a/components/esp_hw_support/port/esp32c5/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c5/pmu_sleep.c @@ -274,11 +274,12 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp ; } - return pmu_sleep_finish(); + return pmu_sleep_finish(dslp); } -bool pmu_sleep_finish(void) +bool pmu_sleep_finish(bool dslp) { + (void)dslp; return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev); } diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index 0f4a512e01b3..ec157f07d185 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -18,7 +18,7 @@ #include "soc/chip_revision.h" #include "esp_private/periph_ctrl.h" -static const char *TAG = "rtc_time"; +__attribute__((unused)) static const char *TAG = "rtc_time"; /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of @@ -250,12 +250,6 @@ uint64_t rtc_time_get(void) return 0; } -void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more -{ - // TODO: IDF-5781 - ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet"); -} - uint32_t rtc_clk_freq_cal(uint32_t cal_val) { if (cal_val == 0) { diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h index 81a3fa971147..8d508d5df39b 100644 --- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h @@ -413,15 +413,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); */ uint64_t rtc_time_get(void); -/** - * @brief Busy loop until next RTC_SLOW_CLK cycle - * - * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. - * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return - * one RTC_SLOW_CLK cycle later. - */ -void rtc_clk_wait_for_slow_cycle(void); - /** * @brief Enable the rtc digital 8M clock * diff --git a/components/esp_hw_support/port/esp32c6/pmu_sleep.c b/components/esp_hw_support/port/esp32c6/pmu_sleep.c index 7396e41b8c23..b6c11b8632ed 100644 --- a/components/esp_hw_support/port/esp32c6/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c6/pmu_sleep.c @@ -341,11 +341,12 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp ; } - return pmu_sleep_finish(); + return pmu_sleep_finish(dslp); } -bool pmu_sleep_finish(void) +bool pmu_sleep_finish(bool dslp) { + (void)dslp; return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev); } diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index 3beac67c3c2e..228a713ad9ef 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -362,6 +362,7 @@ soc_xtal_freq_t rtc_clk_xtal_freq_get(void) uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz(); if (xtal_freq_mhz == 0) { ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); + clk_ll_xtal_store_freq_mhz(SOC_XTAL_FREQ_40M); return SOC_XTAL_FREQ_40M; } return (soc_xtal_freq_t)xtal_freq_mhz; @@ -422,25 +423,6 @@ bool rtc_dig_8m_enabled(void) return clk_ll_rc_fast_digi_is_enabled(); } -// Workaround for bootloader not calibrated well issue. -// Placed in IRAM because disabling BBPLL may influence the cache -void rtc_clk_recalib_bbpll(void) -{ - rtc_cpu_freq_config_t old_config; - rtc_clk_cpu_freq_get_config(&old_config); - - // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. - // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. - // Turn off the BBPLL and do calibration again to fix the issue. - // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's - // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. - if (old_config.source == SOC_CPU_CLK_SRC_PLL) { - rtc_clk_cpu_freq_set_xtal(); - rtc_clk_cpu_freq_set_config(&old_config); - } -} - - /* Name used in libphy.a:phy_chip_v7.o * TODO: update the library to use rtc_clk_xtal_freq_get */ diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c index 98896e786c6b..40b535eefd6a 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_time.c +++ b/components/esp_hw_support/port/esp32c6/rtc_time.c @@ -18,7 +18,7 @@ #include "soc/chip_revision.h" #include "esp_private/periph_ctrl.h" -static const char *TAG = "rtc_time"; +__attribute__((unused)) static const char *TAG = "rtc_time"; /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of @@ -257,12 +257,6 @@ uint64_t rtc_time_get(void) return lp_timer_hal_get_cycle_count(); } -void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more -{ - // TODO: IDF-5781 - ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet"); -} - uint32_t rtc_clk_freq_cal(uint32_t cal_val) { if (cal_val == 0) { diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h index 50a428daf856..cdf1e422b4bc 100644 --- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h @@ -413,15 +413,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); */ uint64_t rtc_time_get(void); -/** - * @brief Busy loop until next RTC_SLOW_CLK cycle - * - * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. - * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return - * one RTC_SLOW_CLK cycle later. - */ -void rtc_clk_wait_for_slow_cycle(void); - /** * @brief Enable the rtc digital 8M clock * diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index 4644e1df393c..3a20ede1b94b 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -427,25 +427,6 @@ bool rtc_dig_8m_enabled(void) return clk_ll_rc_fast_digi_is_enabled(); } -// Workaround for bootloader not calibrated well issue. -// Placed in IRAM because disabling BBPLL may influence the cache -void rtc_clk_recalib_bbpll(void) -{ - rtc_cpu_freq_config_t old_config; - rtc_clk_cpu_freq_get_config(&old_config); - - // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. - // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. - // Turn off the BBPLL and do calibration again to fix the issue. - // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's - // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. - if (old_config.source == SOC_CPU_CLK_SRC_PLL) { - rtc_clk_cpu_freq_set_xtal(); - rtc_clk_cpu_freq_set_config(&old_config); - } -} - - /* Name used in libphy.a:phy_chip_v7.o * TODO: update the library to use rtc_clk_xtal_freq_get */ diff --git a/components/esp_hw_support/port/esp32c61/rtc_time.c b/components/esp_hw_support/port/esp32c61/rtc_time.c index 182d32ee3f9a..c3c6f35661fd 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_time.c +++ b/components/esp_hw_support/port/esp32c61/rtc_time.c @@ -17,7 +17,7 @@ #include "soc/chip_revision.h" #include "esp_private/periph_ctrl.h" -static const char *TAG = "rtc_time"; +__attribute__((unused)) static const char *TAG = "rtc_time"; /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of @@ -254,12 +254,6 @@ uint64_t rtc_time_get(void) return 0; } -void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more -{ - // TODO: IDF-5781 - ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet"); -} - uint32_t rtc_clk_freq_cal(uint32_t cal_val) { if (cal_val == 0) { diff --git a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h index ae763dc4a851..dfd1f96f0197 100644 --- a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h @@ -411,15 +411,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); */ uint64_t rtc_time_get(void); -/** - * @brief Busy loop until next RTC_SLOW_CLK cycle - * - * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. - * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return - * one RTC_SLOW_CLK cycle later. - */ -void rtc_clk_wait_for_slow_cycle(void); - /** * @brief Enable the rtc digital 8M clock * diff --git a/components/esp_hw_support/port/esp32h2/pmu_param.c b/components/esp_hw_support/port/esp32h2/pmu_param.c index b15e97b78e97..995c02a243a2 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_param.c +++ b/components/esp_hw_support/port/esp32h2/pmu_param.c @@ -22,7 +22,6 @@ static __attribute__((unused)) const char *TAG = "pmu_param"; #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #endif -//TODO: IDF-6254 #define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \ .dig_power = { \ .vdd_spi_pd_en = 0, \ diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c index a59e81f1ecc4..ab32613ab59d 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c @@ -258,11 +258,12 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp ; } - return ESP_OK; + return pmu_sleep_finish(dslp); } -bool pmu_sleep_finish(void) +bool pmu_sleep_finish(bool dslp) { + (void)dslp; return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev); } diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c index f2ca1ca3ff58..27898a95b411 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c @@ -238,7 +238,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) /** * Switch to FLASH_PLL as cpu clock source. * On ESP32H2, FLASH_PLL frequency is 64MHz. - * PLL must alreay be enabled. + * PLL must already be enabled. */ static void rtc_clk_cpu_freq_to_flash_pll(uint32_t cpu_freq_mhz, uint32_t cpu_divider) { @@ -474,21 +474,3 @@ bool rtc_dig_8m_enabled(void) { return clk_ll_rc_fast_digi_is_enabled(); } - -// Workaround for bootloader not calibrated well issue. -// Placed in IRAM because disabling BBPLL may influence the cache -void rtc_clk_recalib_bbpll(void) -{ - rtc_cpu_freq_config_t old_config; - rtc_clk_cpu_freq_get_config(&old_config); - - // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. - // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. - // Turn off the BBPLL and do calibration again to fix the issue. Flash_PLL comes from the same source as PLL. - // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's - // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. - if (old_config.source == SOC_CPU_CLK_SRC_PLL || old_config.source == SOC_CPU_CLK_SRC_FLASH_PLL) { - rtc_clk_cpu_freq_set_xtal(); - rtc_clk_cpu_freq_set_config(&old_config); - } -} diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c index 708fedcb2047..395be4dc4ab0 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_time.c +++ b/components/esp_hw_support/port/esp32h2/rtc_time.c @@ -18,7 +18,7 @@ #include "soc/chip_revision.h" #include "esp_private/periph_ctrl.h" -static const char *TAG = "rtc_time"; +__attribute__((unused)) static const char *TAG = "rtc_time"; /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of @@ -257,12 +257,6 @@ uint64_t rtc_time_get(void) return lp_timer_hal_get_cycle_count(); } -void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more -{ - // TODO: IDF-6254 - ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet"); -} - uint32_t rtc_clk_freq_cal(uint32_t cal_val) { if (cal_val == 0) { diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.dcdc b/components/esp_hw_support/port/esp32p4/Kconfig.dcdc new file mode 100644 index 000000000000..a4d3ab3d37a8 --- /dev/null +++ b/components/esp_hw_support/port/esp32p4/Kconfig.dcdc @@ -0,0 +1,30 @@ +menu "DCDC Regulator Configurations" + depends on SOC_GP_LDO_SUPPORTED + + config ESP_SLEEP_KEEP_DCDC_ALWAYS_ON + bool "Keep DC-DC power always on during light-sleep" + default y + help + ESP32P4 will switch the power supply to LDO before sleeping, and switch to DCDC after waking up. + These two processes take a long time and may bring some risks for some short duration + light sleep. (DCDC -> LDO: 2.5ms (max), LDO -> DCDC: 1.2 ms) + Enabling this option will make chip powered by DCDC during light sleep to reduce some power switch + risks, this will also increase the power consumption during the light sleep. + + DO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING. + + config ESP_SLEEP_DCM_VSET_VAL_IN_SLEEP + int "DCDC voltage parameter during sleep" + default 14 + range 0 31 + depends on ESP_SLEEP_KEEP_DCDC_ALWAYS_ON + help + This value determines the voltage of the DCDC chip during sleep. The same parameter value may + correspond to different voltage values on different models of DCDC chips. Please update this + value according to the model of external DCDC selected in your hardware solution. + + For the DCDC chip model recommended by ESP, the recommended configuration + values are listed below: + + - TI-TLV62569/TLV62569P: 14 +endmenu diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h index ba2ede21c170..183f8a79fe60 100644 --- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h @@ -432,15 +432,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); */ uint64_t rtc_time_get(void); -/** - * @brief Busy loop until next RTC_SLOW_CLK cycle - * - * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. - * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return - * one RTC_SLOW_CLK cycle later. - */ -void rtc_clk_wait_for_slow_cycle(void); - /** * @brief Enable the rtc digital 8M clock * @@ -494,7 +485,7 @@ void rtc_clk_apll_enable(bool enable); * * @return * - 0 Failed - * - else Sucess + * - else Success */ uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2); diff --git a/components/esp_hw_support/port/esp32p4/pmu_init.c b/components/esp_hw_support/port/esp32p4/pmu_init.c index a0d3c53be26d..92d67002fdf9 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_init.c +++ b/components/esp_hw_support/port/esp32p4/pmu_init.c @@ -79,7 +79,6 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_pa pmu_ll_hp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias); pmu_ll_hp_set_dcm_mode (ctx->hal->dev, mode, anlg->bias.dcm_mode); pmu_ll_hp_set_dcm_vset (ctx->hal->dev, mode, anlg->bias.dcm_vset); - pmu_ll_hp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias); pmu_ll_hp_set_dbg_atten (ctx->hal->dev, mode, anlg->bias.dbg_atten); pmu_ll_hp_set_current_power_off (ctx->hal->dev, mode, anlg->bias.pd_cur); pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, mode, anlg->bias.bias_sleep); diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index 3b0487157cfe..0b3d5cbaf281 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -149,26 +149,35 @@ const pmu_sleep_config_t* pmu_sleep_config_default( iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0; iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0; iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0; - config->power = power_default; - - pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags); - config->param = *pmu_sleep_param_config_default(¶m_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period); if (dslp) { config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period); pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags); config->analog = analog_default; } else { + // Get light sleep digital_default pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags); config->digital = digital_default; + // Get light sleep analog default pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags); #if CONFIG_SPIRAM analog_default.hp_sys.analog.pd_cur = 1; analog_default.lp_sys[PMU_MODE_LP_SLEEP].analog.pd_cur = 1; #endif + +#if CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON + power_default.hp_sys.dig_power.dcdc_switch_pd_en = 0; + analog_default.hp_sys.analog.dcm_vset = CONFIG_ESP_SLEEP_DCM_VSET_VAL_IN_SLEEP; + analog_default.hp_sys.analog.dcm_mode = 1; +#endif config->analog = analog_default; } + + config->power = power_default; + pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags); + config->param = *pmu_sleep_param_config_default(¶m_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period); + return config; } @@ -194,6 +203,8 @@ static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_c static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp) { assert(ctx->hal); + pmu_ll_hp_set_dcm_mode (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dcm_mode); + pmu_ll_hp_set_dcm_vset (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dcm_vset); pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur); pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep); pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_xpd); @@ -250,10 +261,10 @@ void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp) } void pmu_sleep_increase_ldo_volt(void) { - REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, 30); - REG_SET_BIT(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD); + pmu_ll_hp_set_regulator_dbias(&PMU, PMU_MODE_HP_ACTIVE, 30); + pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, 1); // Decrease the DCDC voltage to reduce the voltage difference between the DCDC and the LDO to avoid overshooting the DCDC voltage during wake-up. - REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCM_VSET, 24); + pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, 24); } void pmu_sleep_shutdown_dcdc(void) { @@ -301,19 +312,26 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, ; } - return pmu_sleep_finish(); + return pmu_sleep_finish(dslp); } -TCM_IRAM_ATTR bool pmu_sleep_finish(void) +TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp) { - REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCM_VSET, 27); - if (pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) { - // If sleep is rejected, the hardware wake-up process that turns on DCDC - // is skipped, and software is used to enable DCDC here. - pmu_sleep_enable_dcdc(); - esp_rom_delay_us(950); +#if CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON + if (!dslp) { + // Keep DCDC always on during light sleep, no need to adjust LDO. + } else +#endif + { + pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, 27); + if (pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) { + // If sleep is rejected, the hardware wake-up process that turns on DCDC + // is skipped, and software is used to enable DCDC here. + pmu_sleep_enable_dcdc(); + esp_rom_delay_us(950); + } + pmu_sleep_shutdown_ldo(); } - pmu_sleep_shutdown_ldo(); unsigned chip_version = efuse_hal_chip_revision(); if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) { diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h index b1c3aec17518..a3c48c042028 100644 --- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h @@ -105,7 +105,7 @@ const pmu_lp_system_analog_param_t* pmu_lp_system_analog_param_default(pmu_lp_mo typedef union { struct { uint32_t reserved0 : 21; - uint32_t dcdc_switch_pd_en: 1; + uint32_t dcdc_switch_pd_en: 1; uint32_t mem_dslp : 1; uint32_t mem_pd_en : 1; uint32_t reserved1 : 6; @@ -153,7 +153,9 @@ typedef union { typedef struct { struct { - uint32_t reserved0 : 25; + uint32_t reserved0 : 18; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; uint32_t xpd_bias : 1; uint32_t dbg_atten : 4; uint32_t pd_cur : 1; diff --git a/components/esp_hw_support/port/esp32p4/rtc_time.c b/components/esp_hw_support/port/esp32p4/rtc_time.c index b1a5ae6674de..44c1242f4c34 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_time.c +++ b/components/esp_hw_support/port/esp32p4/rtc_time.c @@ -16,7 +16,7 @@ #include "esp_rom_sys.h" #include "esp_private/periph_ctrl.h" -static const char *TAG = "rtc_time"; +__attribute__((unused)) static const char *TAG = "rtc_time"; /* Calibration of clock frequency is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of @@ -214,12 +214,6 @@ uint64_t rtc_time_get(void) return lp_timer_hal_get_cycle_count(); } -void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more -{ - // TODO: IDF-5781 - ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet"); -} - uint32_t rtc_clk_freq_cal(uint32_t cal_val) { if (cal_val == 0) { diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index a795619b99e5..1416b2862c66 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -187,7 +187,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { - /* There are totally 6 LDO slaves(all on by default). At the moment of swithing LDO slave, LDO voltage will also change instantaneously. + /* There are totally 6 LDO slaves(all on by default). At the moment of switching LDO slave, LDO voltage will also change instantaneously. * LDO slave can reduce the voltage change caused by switching frequency. * CPU frequency <= 40M : just open 3 LDO slaves; CPU frequency = 80M : open 4 LDO slaves; CPU frequency = 160M : open 5 LDO slaves; CPU frequency = 240M : open 6 LDO slaves; * @@ -460,25 +460,6 @@ bool rtc_dig_8m_enabled(void) return clk_ll_rc_fast_digi_is_enabled(); } -// Workaround for bootloader not calibrated well issue. -// Placed in IRAM because disabling BBPLL may influence the cache -void rtc_clk_recalib_bbpll(void) -{ - rtc_cpu_freq_config_t old_config; - rtc_clk_cpu_freq_get_config(&old_config); - - // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. - // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. - // Turn off the BBPLL and do calibration again to fix the issue. - // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's - // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. - if (old_config.source == SOC_CPU_CLK_SRC_PLL) { - rtc_clk_cpu_freq_set_xtal(); - rtc_clk_cpu_freq_set_config(&old_config); - } -} - - /* Name used in libphy.a:phy_chip_v7.o * TODO: update the library to use rtc_clk_xtal_freq_get */ diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 3cd12aa55059..6b510d372681 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -26,7 +26,9 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "soc/soc_caps.h" +#include "soc/chip_revision.h" #include "driver/rtc_io.h" +#include "hal/efuse_hal.h" #include "hal/rtc_io_hal.h" #include "hal/clk_tree_hal.h" @@ -863,6 +865,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH; } } +#elif CONFIG_IDF_TARGET_ESP32P4 + /* Due to esp32p4 eco0 hardware bug, if LP peripheral power domain is powerdowned in sleep, there will be a possibility of + triggering the EFUSE_CRC reset, so disable the power-down of this power domain on lightsleep for ECO0 version. */ + if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { + pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH; + } #endif uint32_t reject_triggers = allow_sleep_rejection ? (s_config.wakeup_triggers & RTC_SLEEP_REJECT_MASK) : 0; @@ -897,8 +905,15 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m #if SOC_PMU_SUPPORTED #if SOC_DCDC_SUPPORTED - s_config.rtc_ticks_at_ldo_prepare = rtc_time_get(); - pmu_sleep_increase_ldo_volt(); +#if CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON + if (!deep_sleep) { + // Keep DCDC always on during light sleep, no need to adjust LDO voltage. + } else +#endif + { + s_config.rtc_ticks_at_ldo_prepare = rtc_time_get(); + pmu_sleep_increase_ldo_volt(); + } #endif pmu_sleep_config_t config; @@ -983,11 +998,18 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m #endif #if SOC_DCDC_SUPPORTED - uint64_t ldo_increased_us = rtc_time_slowclk_to_us(rtc_time_get() - s_config.rtc_ticks_at_ldo_prepare, s_config.rtc_clk_cal_period); - if (ldo_increased_us < LDO_POWER_TAKEOVER_PREPARATION_TIME_US) { - esp_rom_delay_us(LDO_POWER_TAKEOVER_PREPARATION_TIME_US - ldo_increased_us); +#if CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON + if (!deep_sleep) { + // Keep DCDC always on during light sleep, no need to adjust LDO voltage. + } else +#endif + { + uint64_t ldo_increased_us = rtc_time_slowclk_to_us(rtc_time_get() - s_config.rtc_ticks_at_ldo_prepare, s_config.rtc_clk_cal_period); + if (ldo_increased_us < LDO_POWER_TAKEOVER_PREPARATION_TIME_US) { + esp_rom_delay_us(LDO_POWER_TAKEOVER_PREPARATION_TIME_US - ldo_increased_us); + } + pmu_sleep_shutdown_dcdc(); } - pmu_sleep_shutdown_dcdc(); #endif #if SOC_PMU_SUPPORTED @@ -2267,6 +2289,12 @@ static uint32_t get_power_down_flags(void) } #endif +#if SOC_PM_SUPPORT_CNNT_PD + if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON) { + pd_flags |= PMU_SLEEP_PD_CNNT; + } +#endif + #if SOC_PM_SUPPORT_VDDSDIO_PD if (s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option != ESP_PD_OPTION_ON) { pd_flags |= RTC_SLEEP_PD_VDDSDIO; diff --git a/components/esp_hw_support/test_apps/dma/CMakeLists.txt b/components/esp_hw_support/test_apps/dma/CMakeLists.txt index 42e63786a1c7..52d2103edf3e 100644 --- a/components/esp_hw_support/test_apps/dma/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/dma/CMakeLists.txt @@ -8,3 +8,8 @@ include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main esp_psram) project(dma_test) + +message(STATUS "Checking dma registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "*gdma" "pcr" "hp_sys_clkrst" + HAL_MODULES "*gdma") diff --git a/components/esp_hw_support/test_apps/etm/CMakeLists.txt b/components/esp_hw_support/test_apps/etm/CMakeLists.txt index 0d009db6795f..4505a9f1a0c6 100644 --- a/components/esp_hw_support/test_apps/etm/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/etm/CMakeLists.txt @@ -8,3 +8,8 @@ include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main esp_pm) project(etm_test) + +message(STATUS "Checking etm registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "*etm" "pcr" "hp_sys_clkrst" + HAL_MODULES "etm") diff --git a/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v1.c b/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v1.c index 3928d81ed9e7..b50814dd6712 100644 --- a/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v1.c +++ b/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v1.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,6 +19,7 @@ #include "driver/gpio.h" #include "esp_log.h" #include "esp_check.h" +#include "esp_compiler.h" static const char *TAG = "lcd_panel.io.i2c"; @@ -47,6 +48,8 @@ typedef struct { esp_err_t esp_lcd_new_panel_io_i2c_v1(uint32_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io) { + // leak detection of i2c_panel_io because saving i2c_panel_io->base address + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") #if CONFIG_LCD_ENABLE_DEBUG_LOG esp_log_level_set(TAG, ESP_LOG_DEBUG); #endif @@ -78,6 +81,7 @@ esp_err_t esp_lcd_new_panel_io_i2c_v1(uint32_t bus, const esp_lcd_panel_io_i2c_c return ESP_OK; err: return ret; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } static esp_err_t panel_io_i2c_del(esp_lcd_panel_io_t *io) diff --git a/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v2.c b/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v2.c index 77e2e54c632a..9dde28921de9 100644 --- a/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v2.c +++ b/components/esp_lcd/i2c/esp_lcd_panel_io_i2c_v2.c @@ -21,6 +21,8 @@ #include "esp_check.h" #include "freertos/FreeRTOS.h" #include "esp_heap_caps.h" +#include "esp_compiler.h" + static const char *TAG = "lcd_panel.io.i2c"; #define BYTESHIFT(VAR, IDX) (((VAR) >> ((IDX) * 8)) & 0xFF) @@ -56,6 +58,8 @@ esp_err_t esp_lcd_new_panel_io_i2c_v2(i2c_master_bus_handle_t bus, const esp_lcd i2c_master_dev_handle_t i2c_handle = NULL; ESP_GOTO_ON_FALSE(io_config && ret_io, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); ESP_GOTO_ON_FALSE(io_config->control_phase_bytes * 8 > io_config->dc_bit_offset, ESP_ERR_INVALID_ARG, err, TAG, "D/C bit exceeds control bytes"); + // leak detection of i2c_panel_io because saving i2c_panel_io->base address + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") i2c_panel_io = calloc(1, sizeof(lcd_panel_io_i2c_t)); ESP_GOTO_ON_FALSE(i2c_panel_io, ESP_ERR_NO_MEM, err, TAG, "no mem for i2c panel io"); @@ -88,6 +92,7 @@ esp_err_t esp_lcd_new_panel_io_i2c_v2(i2c_master_bus_handle_t bus, const esp_lcd free(i2c_panel_io); } return ret; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } static esp_err_t panel_io_i2c_del(esp_lcd_panel_io_t *io) diff --git a/components/esp_lcd/include/esp_lcd_io_i2c.h b/components/esp_lcd/include/esp_lcd_io_i2c.h index 73ee69e55e0b..7d1b0fc02c95 100644 --- a/components/esp_lcd/include/esp_lcd_io_i2c.h +++ b/components/esp_lcd/include/esp_lcd_io_i2c.h @@ -67,6 +67,43 @@ esp_err_t esp_lcd_new_panel_io_i2c_v1(uint32_t bus, const esp_lcd_panel_io_i2c_c */ esp_err_t esp_lcd_new_panel_io_i2c_v2(i2c_master_bus_handle_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus +/** + * @brief Create LCD panel IO handle + * + * @param[in] bus I2C bus ID, indicates which I2C port to use + * @param[in] io_config IO configuration, for I2C interface + * @param[out] ret_io Returned IO handle + * @return + * - ESP_ERR_INVALID_ARG if parameter is invalid + * - ESP_ERR_NO_MEM if out of memory + * - ESP_OK on success + */ +static inline void esp_lcd_new_panel_io_i2c(uint32_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io) +{ + esp_lcd_new_panel_io_i2c_v1(bus, io_config, ret_io); +} + +/** + * @brief Create LCD panel IO handle + * + * @param[in] bus I2C bus handle, returned from `i2c_new_master_bus` + * @param[in] io_config IO configuration, for I2C interface + * @param[out] ret_io Returned IO handle + * @return + * - ESP_ERR_INVALID_ARG if parameter is invalid + * - ESP_ERR_NO_MEM if out of memory + * - ESP_OK on success + */ +static inline void esp_lcd_new_panel_io_i2c(i2c_master_bus_handle_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io) +{ + esp_lcd_new_panel_io_i2c_v2(bus, io_config, ret_io); +} +#else /** * @brief Create LCD panel IO handle * @@ -80,8 +117,6 @@ esp_err_t esp_lcd_new_panel_io_i2c_v2(i2c_master_bus_handle_t bus, const esp_lcd */ #define esp_lcd_new_panel_io_i2c(bus, io_config, ret_io) _Generic((bus), \ i2c_master_bus_handle_t : esp_lcd_new_panel_io_i2c_v2, \ - default : esp_lcd_new_panel_io_i2c_v1) (bus, io_config, ret_io) \ + default : esp_lcd_new_panel_io_i2c_v1) (bus, io_config, ret_io) -#ifdef __cplusplus -} #endif diff --git a/components/esp_lcd/include/esp_lcd_panel_dev.h b/components/esp_lcd/include/esp_lcd_panel_dev.h index 1a86d2b964b2..f39bdf299faa 100644 --- a/components/esp_lcd/include/esp_lcd_panel_dev.h +++ b/components/esp_lcd/include/esp_lcd_panel_dev.h @@ -20,8 +20,8 @@ extern "C" { typedef struct { int reset_gpio_num; /*!< GPIO used to reset the LCD panel, set to -1 if it's not used */ union { - lcd_rgb_element_order_t color_space; /*!< @deprecated Set RGB color space, please use rgb_ele_order instead */ - lcd_rgb_element_order_t rgb_endian; /*!< @deprecated Set RGB data endian, please use rgb_ele_order instead */ + esp_lcd_color_space_t color_space; /*!< @deprecated Set RGB color space, please use rgb_ele_order instead */ + lcd_color_rgb_endian_t rgb_endian; /*!< @deprecated Set RGB data endian, please use rgb_ele_order instead */ lcd_rgb_element_order_t rgb_ele_order; /*!< Set RGB element order, RGB or BGR */ }; lcd_rgb_data_endian_t data_endian; /*!< Set the data endian for color data larger than 1 byte */ diff --git a/components/esp_lcd/include/esp_lcd_types.h b/components/esp_lcd/include/esp_lcd_types.h index f70858df0f6d..ca15370b93d7 100644 --- a/components/esp_lcd/include/esp_lcd_types.h +++ b/components/esp_lcd/include/esp_lcd_types.h @@ -41,25 +41,15 @@ typedef enum { } lcd_rgb_element_order_t; /** @cond */ -/** - * @brief LCD color space type definition (WRONG!) - * @deprecated RGB and BGR should belong to the same color space, but this enum take them both as two different color spaces. - * If you want to use a enum to describe a color space, please use lcd_color_space_t instead. - */ -typedef enum { - ESP_LCD_COLOR_SPACE_RGB, /*!< Color space: RGB */ - ESP_LCD_COLOR_SPACE_BGR, /*!< Color space: BGR */ - ESP_LCD_COLOR_SPACE_MONOCHROME, /*!< Color space: monochrome */ -} esp_lcd_color_space_t __attribute__((deprecated)); - -// Ensure binary compatibility with lcd_color_rgb_endian_t -ESP_STATIC_ASSERT((lcd_rgb_element_order_t)ESP_LCD_COLOR_SPACE_RGB == LCD_RGB_ELEMENT_ORDER_RGB, "ESP_LCD_COLOR_SPACE_RGB is not compatible with LCD_RGB_ORDER_RGB"); -ESP_STATIC_ASSERT((lcd_rgb_element_order_t)ESP_LCD_COLOR_SPACE_BGR == LCD_RGB_ELEMENT_ORDER_BGR, "ESP_LCD_COLOR_SPACE_BGR is not compatible with LCD_RGB_ORDER_BGR"); - /// for backward compatible typedef lcd_rgb_element_order_t lcd_color_rgb_endian_t; -#define LCD_RGB_ENDIAN_RGB LCD_RGB_ELEMENT_ORDER_RGB -#define LCD_RGB_ENDIAN_BGR LCD_RGB_ELEMENT_ORDER_BGR +#define LCD_RGB_ENDIAN_RGB (lcd_color_rgb_endian_t)LCD_RGB_ELEMENT_ORDER_RGB +#define LCD_RGB_ENDIAN_BGR (lcd_color_rgb_endian_t)LCD_RGB_ELEMENT_ORDER_BGR + +typedef lcd_rgb_element_order_t esp_lcd_color_space_t; +#define ESP_LCD_COLOR_SPACE_RGB (esp_lcd_color_space_t)LCD_RGB_ELEMENT_ORDER_RGB +#define ESP_LCD_COLOR_SPACE_BGR (esp_lcd_color_space_t)LCD_RGB_ELEMENT_ORDER_BGR +#define ESP_LCD_COLOR_SPACE_MONOCHROME (esp_lcd_color_space_t)2 /** @endcond */ /** diff --git a/components/esp_lcd/src/esp_lcd_panel_nt35510.c b/components/esp_lcd/src/esp_lcd_panel_nt35510.c index 5a9e34273898..06e30799127d 100644 --- a/components/esp_lcd/src/esp_lcd_panel_nt35510.c +++ b/components/esp_lcd/src/esp_lcd_panel_nt35510.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,7 @@ #include "driver/gpio.h" #include "esp_log.h" #include "esp_check.h" +#include "esp_compiler.h" static const char *TAG = "lcd_panel.nt35510"; @@ -61,6 +62,8 @@ esp_lcd_new_panel_nt35510(const esp_lcd_panel_io_handle_t io, const esp_lcd_pane esp_err_t ret = ESP_OK; nt35510_panel_t *nt35510 = NULL; ESP_GOTO_ON_FALSE(io && panel_dev_config && ret_panel, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); + // leak detection of nt35510 because saving nt35510->base address + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") nt35510 = calloc(1, sizeof(nt35510_panel_t)); ESP_GOTO_ON_FALSE(nt35510, ESP_ERR_NO_MEM, err, TAG, "no mem for nt35510 panel"); @@ -131,6 +134,7 @@ esp_lcd_new_panel_nt35510(const esp_lcd_panel_io_handle_t io, const esp_lcd_pane free(nt35510); } return ret; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } static esp_err_t panel_nt35510_del(esp_lcd_panel_t *panel) diff --git a/components/esp_lcd/src/esp_lcd_panel_ssd1306.c b/components/esp_lcd/src/esp_lcd_panel_ssd1306.c index fbac5c0884b7..05bc317cd8fc 100644 --- a/components/esp_lcd/src/esp_lcd_panel_ssd1306.c +++ b/components/esp_lcd/src/esp_lcd_panel_ssd1306.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,6 +22,7 @@ #include "driver/gpio.h" #include "esp_log.h" #include "esp_check.h" +#include "esp_compiler.h" static const char *TAG = "lcd_panel.ssd1306"; @@ -73,6 +74,8 @@ esp_err_t esp_lcd_new_panel_ssd1306(const esp_lcd_panel_io_handle_t io, const es ESP_GOTO_ON_FALSE(io && panel_dev_config && ret_panel, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); ESP_GOTO_ON_FALSE(panel_dev_config->bits_per_pixel == 1, ESP_ERR_INVALID_ARG, err, TAG, "bpp must be 1"); esp_lcd_panel_ssd1306_config_t *ssd1306_spec_config = (esp_lcd_panel_ssd1306_config_t *)panel_dev_config->vendor_config; + // leak detection of ssd1306 because saving ssd1306->base address + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") ssd1306 = calloc(1, sizeof(ssd1306_panel_t)); ESP_GOTO_ON_FALSE(ssd1306, ESP_ERR_NO_MEM, err, TAG, "no mem for ssd1306 panel"); @@ -111,6 +114,7 @@ esp_err_t esp_lcd_new_panel_ssd1306(const esp_lcd_panel_io_handle_t io, const es free(ssd1306); } return ret; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } static esp_err_t panel_ssd1306_del(esp_lcd_panel_t *panel) diff --git a/components/esp_lcd/src/esp_lcd_panel_st7789.c b/components/esp_lcd/src/esp_lcd_panel_st7789.c index 8076fce67ab4..5c3625cf07ad 100644 --- a/components/esp_lcd/src/esp_lcd_panel_st7789.c +++ b/components/esp_lcd/src/esp_lcd_panel_st7789.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,6 +24,7 @@ #include "driver/gpio.h" #include "esp_log.h" #include "esp_check.h" +#include "esp_compiler.h" #define ST7789_CMD_RAMCTRL 0xb0 #define ST7789_DATA_LITTLE_ENDIAN_BIT (1 << 3) @@ -66,6 +67,8 @@ esp_lcd_new_panel_st7789(const esp_lcd_panel_io_handle_t io, const esp_lcd_panel esp_err_t ret = ESP_OK; st7789_panel_t *st7789 = NULL; ESP_GOTO_ON_FALSE(io && panel_dev_config && ret_panel, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); + // leak detection of st7789 because saving st7789->base address + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") st7789 = calloc(1, sizeof(st7789_panel_t)); ESP_GOTO_ON_FALSE(st7789, ESP_ERR_NO_MEM, err, TAG, "no mem for st7789 panel"); @@ -139,6 +142,7 @@ esp_lcd_new_panel_st7789(const esp_lcd_panel_io_handle_t io, const esp_lcd_panel free(st7789); } return ret; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } static esp_err_t panel_st7789_del(esp_lcd_panel_t *panel) diff --git a/components/esp_lcd/test_apps/i2c_lcd/README.md b/components/esp_lcd/test_apps/i2c_lcd/README.md index 10a58b27713f..4b3c3e235af6 100644 --- a/components/esp_lcd/test_apps/i2c_lcd/README.md +++ b/components/esp_lcd/test_apps/i2c_lcd/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | This test app is used to test LCDs with I2C interface. diff --git a/components/esp_lcd/test_apps/i2c_lcd_legacy/README.md b/components/esp_lcd/test_apps/i2c_lcd_legacy/README.md index 10a58b27713f..4b3c3e235af6 100644 --- a/components/esp_lcd/test_apps/i2c_lcd_legacy/README.md +++ b/components/esp_lcd/test_apps/i2c_lcd_legacy/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | This test app is used to test LCDs with I2C interface. diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt b/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt index 9a4ba3eaaa27..30d912b096cf 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt @@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES) DEPENDS ${elf} ) endif() + +message(STATUS "Checking mipi_dsi registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "*dsi*" "hp_sys_clkrst" + HAL_MODULES "*dsi*") diff --git a/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt b/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt index 272f66f14fb9..7ab2d486d5f8 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt +++ b/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt @@ -22,3 +22,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES) DEPENDS ${elf} ) endif() + +message(STATUS "Checking rgb_lcd registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "*lcd*" "hp_sys_clkrst" + HAL_MODULES "*lcd*") diff --git a/components/esp_local_ctrl/src/esp_local_ctrl_handler.c b/components/esp_local_ctrl/src/esp_local_ctrl_handler.c index 53db309c71f8..65a6b4ed7a5f 100644 --- a/components/esp_local_ctrl/src/esp_local_ctrl_handler.c +++ b/components/esp_local_ctrl/src/esp_local_ctrl_handler.c @@ -1,22 +1,15 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include #include #include #include +#include "esp_compiler.h" #include "esp_local_ctrl.h" #include "esp_local_ctrl_priv.h" #include "esp_local_ctrl.pb-c.h" @@ -127,11 +120,13 @@ static esp_err_t cmd_get_prop_vals_handler(LocalCtrlMessage *req, if (ret == ESP_OK) { resp_payload->n_props = 0; for (size_t i = 0; i < req->cmd_get_prop_vals->n_indices; i++) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") // False-positive detection. TODO GCC-366 resp_payload->props[i] = malloc(sizeof(PropertyInfo)); if (!resp_payload->props[i]) { resp_payload->status = STATUS__InternalError; break; } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") resp_payload->n_props++; property_info__init(resp_payload->props[i]); resp_payload->props[i]->name = descs[i].name; diff --git a/components/esp_mm/esp_cache.c b/components/esp_mm/esp_cache.c index 84a265a2197f..b87925bb7de5 100644 --- a/components/esp_mm/esp_cache.c +++ b/components/esp_mm/esp_cache.c @@ -17,6 +17,7 @@ #include "hal/cache_hal.h" #include "hal/cache_ll.h" #include "esp_cache.h" +#include "esp_compiler.h" #include "esp_private/esp_cache_private.h" #include "esp_private/critical_section.h" @@ -147,7 +148,7 @@ esp_err_t esp_cache_aligned_malloc_prefer(size_t size, void **out_ptr, size_t *a *out_ptr = NULL; while (flag_nums--) { - flags = va_arg(argp, uint32_t); + flags = va_arg(argp, int); ret = esp_cache_aligned_malloc_internal(size, flags, out_ptr, actual_size); if (ret == ESP_OK) { break; @@ -199,10 +200,10 @@ esp_err_t esp_cache_aligned_calloc_prefer(size_t n, size_t size, void **out_ptr, arg = va_arg(argp, int); ret = esp_cache_aligned_malloc_internal(size_bytes, arg, &ptr, actual_size); if (ret == ESP_OK) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-null-argument") memset(ptr, 0, size_bytes); *out_ptr = ptr; - - arg = va_arg(argp, int); + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-null-argument") break; } diff --git a/components/esp_mm/esp_mmu_map.c b/components/esp_mm/esp_mmu_map.c index 226ec38e0c9a..498497a4ce4e 100644 --- a/components/esp_mm/esp_mmu_map.c +++ b/components/esp_mm/esp_mmu_map.c @@ -14,6 +14,7 @@ #include "esp_log.h" #include "esp_check.h" #include "esp_heap_caps.h" +#include "esp_compiler.h" #include "soc/soc_caps.h" #include "hal/cache_types.h" @@ -630,9 +631,11 @@ esp_err_t esp_mmu_unmap(void *ptr) size_t slot_len = 0; for (int i = 0; i < s_mmu_ctx.num_regions; i++) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-out-of-bounds") if (ptr_laddr >= s_mmu_ctx.mem_regions[i].free_head && ptr_laddr < s_mmu_ctx.mem_regions[i].end) { region = &s_mmu_ctx.mem_regions[i]; } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-out-of-bounds") } ESP_RETURN_ON_FALSE(region, ESP_ERR_NOT_FOUND, TAG, "munmap target pointer is outside external memory regions"); diff --git a/components/esp_netif/lwip/esp_netif_lwip.c b/components/esp_netif/lwip/esp_netif_lwip.c index 11f377f957dd..e0cd05c6f0f9 100644 --- a/components/esp_netif/lwip/esp_netif_lwip.c +++ b/components/esp_netif/lwip/esp_netif_lwip.c @@ -9,6 +9,7 @@ #include #include +#include "esp_compiler.h" #include "esp_check.h" #include "esp_netif_lwip_internal.h" #include "lwip/esp_netif_net_stack.h" @@ -859,12 +860,15 @@ static void esp_netif_lwip_remove(esp_netif_t *esp_netif) static esp_err_t esp_netif_lwip_add(esp_netif_t *esp_netif) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak"); // False-positive detection. TODO GCC-366 if (esp_netif->lwip_netif == NULL) { esp_netif->lwip_netif = calloc(1, sizeof(struct netif)); if (esp_netif->lwip_netif == NULL) { return ESP_ERR_NO_MEM; } } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak"); + if (esp_netif->flags & ESP_NETIF_FLAG_IS_PPP) { #if CONFIG_PPP_SUPPORT err_t err = esp_netif->lwip_init_fn(NULL); @@ -2537,7 +2541,7 @@ static esp_err_t esp_netif_napt_control_api(esp_netif_api_msg_t *msg) /* Disable napt on all other interface */ esp_netif_t *netif = esp_netif_next_unsafe(NULL); while (netif) { - if (netif != esp_netif) { + if (netif != esp_netif && netif->lwip_netif->napt == 1) { ip_napt_enable_netif(netif->lwip_netif, 0); // Fails only if netif is down ESP_LOGW(TAG, "napt disabled on esp_netif:%p", esp_netif); } diff --git a/components/esp_phy/lib b/components/esp_phy/lib index 792ba5917ee8..06e7625de197 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit 792ba5917ee8191e7264143e69f9e6f8c1c0eacc +Subproject commit 06e7625de197bc12797dd701d6762229bca01826 diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index d56e8d6e34c9..34316de51831 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -873,8 +873,7 @@ void esp_phy_load_cal_and_init(void) ESP_LOGW(TAG, "saving new calibration data because of checksum failure, mode(%d)", calibration_mode); } - if ((calibration_mode != PHY_RF_CAL_NONE && err != ESP_OK) || - (calibration_mode != PHY_RF_CAL_FULL && ret == ESP_CAL_DATA_CHECK_FAIL)) { + if ((calibration_mode != PHY_RF_CAL_NONE) && ((err != ESP_OK) || (ret == ESP_CAL_DATA_CHECK_FAIL))) { err = esp_phy_store_cal_data_to_nvs(cal_data); } else { err = ESP_OK; diff --git a/components/esp_ringbuf/ringbuf.c b/components/esp_ringbuf/ringbuf.c index 18ff802a3ca6..aa877f38d24b 100644 --- a/components/esp_ringbuf/ringbuf.c +++ b/components/esp_ringbuf/ringbuf.c @@ -822,12 +822,7 @@ static BaseType_t prvReceiveGeneric(Ringbuffer_t *pxRingbuffer, BaseType_t xEntryTimeSet = pdFALSE; TimeOut_t xTimeOut; -#ifdef __clang_analyzer__ - // Teach clang-tidy that if NULL pointers are provided, this function will never dereference them - if (!pvItem1 || !pvItem2 || !xItemSize1 || !xItemSize2) { - return pdFALSE; - } -#endif /*__clang_analyzer__ */ + ESP_STATIC_ANALYZER_CHECK(!pvItem1 || !pvItem2 || !xItemSize1 || !xItemSize2, pdFALSE); while (xExitLoop == pdFALSE) { portENTER_CRITICAL(&pxRingbuffer->mux); @@ -888,12 +883,7 @@ static BaseType_t prvReceiveGenericFromISR(Ringbuffer_t *pxRingbuffer, { BaseType_t xReturn = pdFALSE; -#ifdef __clang_analyzer__ - // Teach clang-tidy that if NULL pointers are provided, this function will never dereference them - if (!pvItem1 || !pvItem2 || !xItemSize1 || !xItemSize2) { - return pdFALSE; - } -#endif /*__clang_analyzer__ */ + ESP_STATIC_ANALYZER_CHECK(!pvItem1 || !pvItem2 || !xItemSize1 || !xItemSize2, pdFALSE); portENTER_CRITICAL_ISR(&pxRingbuffer->mux); if (prvCheckItemAvail(pxRingbuffer) == pdTRUE) { diff --git a/components/esp_rom/patches/esp_rom_print.c b/components/esp_rom/patches/esp_rom_print.c index ce9505a1b10f..f92f0e3dd7fe 100644 --- a/components/esp_rom/patches/esp_rom_print.c +++ b/components/esp_rom/patches/esp_rom_print.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "esp_rom_caps.h" #include "esp_rom_sys.h" #include "rom/ets_sys.h" @@ -54,7 +55,7 @@ static int ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap) islong, islonglong; long long val = 0; int res = 0, length = 0; - + // %[flags][left_prec][.right_prec][sub_type]type while ((c = *fmt++) != '\0') { if (c == '%') { c = *fmt++; @@ -75,13 +76,11 @@ static int ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap) } if (c == '.') { c = *fmt++; - zero_fill++; + zero_fill = false; while (is_digit(c)) { right_prec = (right_prec * 10) + (c - '0'); c = *fmt++; } - } else { - right_prec = left_prec; } sign = '\0'; if (c == 'l') { @@ -168,10 +167,14 @@ static int ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap) case 'S': cp = va_arg(ap, char *); if (cp == NULL) { - cp = (char *)""; + cp = (char *)""; } length = 0; while (cp[length] != '\0') length++; + if (right_prec) { + length = MIN(right_prec, length); + right_prec = 0; + } break; case 'c': case 'C': @@ -206,6 +209,10 @@ static int ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap) res += 2; } pad = left_prec - length; + right_prec = right_prec - length; + if (right_prec > 0) { + pad -= right_prec; + } if (sign != '\0') { pad--; } @@ -229,6 +236,10 @@ static int ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap) (*putc)(sign); res++; } + while (right_prec-- > 0) { + (*putc)('0'); + res++; + } while (length-- > 0) { c = *cp++; (*putc)(c); diff --git a/components/esp_rom/test_apps/.build-test-rules.yml b/components/esp_rom/test_apps/.build-test-rules.yml index 7d6745313d3c..4f7be9378812 100644 --- a/components/esp_rom/test_apps/.build-test-rules.yml +++ b/components/esp_rom/test_apps/.build-test-rules.yml @@ -7,6 +7,9 @@ components/esp_rom/test_apps/linux_rom_apis: components/esp_rom/test_apps/rom_impl_components: disable: # For ROM impl build tests, disable them if none of the tested features are supported in the ROM + - if: CONFIG_NAME == "no_rom_impl_components" and IDF_TARGET == "esp32c5" + temporary: true + reason: build failed. track in IDFCI-2204 - if: CONFIG_NAME == "rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: CONFIG_NAME == "no_rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: SOC_WDT_SUPPORTED != 1 diff --git a/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt b/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt index baaac731700a..e43a09c3263d 100644 --- a/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt +++ b/components/esp_rom/test_apps/linux_rom_apis/main/CMakeLists.txt @@ -1,4 +1,5 @@ idf_component_register(SRCS "rom_test.cpp" + "rom_printf_test.cpp" INCLUDE_DIRS "." REQUIRES esp_rom WHOLE_ARCHIVE) diff --git a/components/esp_rom/test_apps/linux_rom_apis/main/rom_printf_test.cpp b/components/esp_rom/test_apps/linux_rom_apis/main/rom_printf_test.cpp new file mode 100644 index 000000000000..5561cf6c673d --- /dev/null +++ b/components/esp_rom/test_apps/linux_rom_apis/main/rom_printf_test.cpp @@ -0,0 +1,104 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include "esp_rom_sys.h" +#include "esp_err.h" + +#include + +using namespace std; + +#define BUFFER_SIZE (128) +static char s_print_buffer[BUFFER_SIZE]; +static unsigned s_counter = 0; + +static void reset_buffer(void) +{ + s_counter = 0; + memset(s_print_buffer, 0, BUFFER_SIZE); +} + +void putc_to_buffer(char c) +{ + s_print_buffer[s_counter++] = c; +} + +static esp_err_t test_printf(const char *format, ...) +{ + esp_err_t error = ESP_OK; + va_list list1, list2; + char expected_str[BUFFER_SIZE]; + char *tested_str = s_print_buffer; + + va_start(list1, format); + va_copy(list2, list1); + reset_buffer(); + int len1 = esp_rom_vprintf(format, list1); + int len2 = vsnprintf(expected_str, BUFFER_SIZE, format, list2); + va_end(list2); + va_end(list1); + + if (len1 != len2) { + error = ESP_FAIL; + } + if (strcmp(tested_str, expected_str) != 0) { + error = ESP_FAIL; + } + if (error) { + printf("BAD: "); + } else { + printf("OK : "); + } + printf("'%s' -> %s", format, tested_str); + if (error) { + printf(" != "); + } else { + printf(" == "); + } + printf("%s\n", expected_str); + + return error; +} + +TEST_CASE("Test precisions attrs of esp_rom_vprintf") +{ + esp_rom_install_channel_putc(1, putc_to_buffer); + esp_err_t error = ESP_OK; + error |= test_printf("[%d|%3d|%6d|%03d|%06d|%0d]", 1, 2, 3, 4, 5, 6); + error |= test_printf("[%d|%3d|%6d|%03d|%06d|%0d]", -1, -2, -3, -4, -5, -6); + error |= test_printf("[%d|%3d|%6d|%03d|%06d|%0d]", 10, 11, 12, 13, 14, 15); + error |= test_printf("[%d|%3d|%6d|%03d|%06d|%0d]", -10, -11, -12, -13, -14, -15); + error |= test_printf("[%d|%3d|%6d|%03d|%06d|%0d]", 12345, 12346, 12347, 12348, 12349, 12350); + error |= test_printf("[%d|%3d|%6d|%03d|%06d|%0d]", -12345, -12346, -12347, -12348, -12349, -12350); + + error |= test_printf("[%.3d|%.1d|%.0d|%0.0d|%0.3d|%0.1d|%03.3d]", 1, 2, 3, 4, 5, 6, 7); + error |= test_printf("[%.3d|%.1d|%.0d|%0.0d|%0.3d|%0.1d|%03.3d]", -1, -2, -3, -4, -5, -6, -7); + error |= test_printf("[%.3d|%.1d|%.0d|%0.0d|%0.3d|%0.1d|%03.3d]", 10, 11, 12, 13, 14, 15, 16); + error |= test_printf("[%.3d|%.1d|%.0d|%0.0d|%0.3d|%0.1d|%03.3d]", -10, -11, -12, -13, -14, -15, -16); + error |= test_printf("[%.3d|%.1d|%.0d|%0.0d|%0.3d|%0.1d|%03.3d]", 12345, 12346, 12347, 12348, 12349, 12350, 123451); + error |= test_printf("[%.3d|%.1d|%.0d|%0.0d|%0.3d|%0.1d|%03.3d]", -12345, -12346, -12347, -12348, -12349, -12350, 123451); + + error |= test_printf("[%6.4d|%06.4d|%04.6d|%4.6d|%8.4d|%08.4d]", 1, 2, 3, 4, 5, 6); + error |= test_printf("[%6.4d|%06.4d|%04.6d|%4.6d|%8.4d|%08.4d]", -1, -2, -3, -4, -5, -6); + error |= test_printf("[%6.4d|%06.4d|%04.6d|%4.6d|%8.4d|%08.4d]", 10, 11, 12, 13, 14, 15); + error |= test_printf("[%6.4d|%06.4d|%04.6d|%4.6d|%8.4d|%08.4d]", -10, -11, -12, -13, -14, -15); + error |= test_printf("[%6.4d|%06.4d|%04.6d|%4.6d|%8.4d|%08.4d]", 12340, 12341, 12342, 12343, 12344, 12345); + error |= test_printf("[%6.4d|%06.4d|%04.6d|%4.6d|%8.4d|%08.4d]", -12340, -12341, -12342, -12343, -12344, -12345); + + error |= test_printf("[%-20s]", "1TEST_STR"); + error |= test_printf("[%-20.5s]", "8TEST_STR"); + error |= test_printf("[%20s]", "2TEST_STR"); + error |= test_printf("[%3s]", "3TEST_STR"); + error |= test_printf("[%.3s]", "4TEST_STR"); + error |= test_printf("[%.20s]", "5TEST_STR"); + error |= test_printf("[%6.3s]", "6TEST_STR"); + error |= test_printf("[%06.3s]", "7TEST_STR"); + esp_rom_install_uart_printf(); + CHECK(error == ESP_OK); +} diff --git a/components/esp_system/fpga_overrides_clk.c b/components/esp_system/fpga_overrides_clk.c index a3b4b43de590..1b1f9efad2f1 100644 --- a/components/esp_system/fpga_overrides_clk.c +++ b/components/esp_system/fpga_overrides_clk.c @@ -62,14 +62,18 @@ void bootloader_clock_configure(void) REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16)); } -void esp_clk_init(void) +void esp_rtc_init(void) { - s_warn(); #if SOC_PMU_SUPPORTED pmu_init(); #endif } +void esp_clk_init(void) +{ + s_warn(); +} + void esp_perip_clk_init(void) { } diff --git a/components/esp_system/panic.c b/components/esp_system/panic.c index fd28c7695cb0..20851d554c3e 100644 --- a/components/esp_system/panic.c +++ b/components/esp_system/panic.c @@ -8,6 +8,7 @@ #include "esp_err.h" #include "esp_attr.h" +#include "esp_compiler.h" #include "esp_private/system_internal.h" #include "esp_private/usb_console.h" @@ -221,7 +222,7 @@ static inline void disable_all_wdts(void) wdt_hal_write_protect_enable(&wdt0_context); #if SOC_TIMER_GROUPS >= 2 - //Interupt WDT is the Main Watchdog Timer of Timer Group 1 + //Interrupt WDT is the Main Watchdog Timer of Timer Group 1 wdt_hal_write_protect_disable(&wdt1_context); wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); @@ -460,7 +461,9 @@ void IRAM_ATTR __attribute__((noreturn, no_sanitize_undefined)) panic_abort(cons #endif #endif + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-null-dereference") *((volatile int *) 0) = 0; // NOLINT(clang-analyzer-core.NullDereference) should be an invalid operation on targets + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-null-dereference") while (1); } diff --git a/components/esp_system/port/brownout.c b/components/esp_system/port/brownout.c index cce5f65deff1..d90dcc911ad3 100644 --- a/components/esp_system/port/brownout.c +++ b/components/esp_system/port/brownout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,7 @@ #include "soc/soc.h" #include "soc/rtc_periph.h" #include "esp_attr.h" +#include "esp_rom_sys.h" #include "bootloader_flash.h" #include "esp_intr_alloc.h" #include "hal/brownout_hal.h" @@ -56,7 +57,10 @@ IRAM_ATTR static void rtc_brownout_isr_handler(void *arg) ESP_DRAM_LOGI(TAG, "Brownout detector was triggered\r\n\r\n"); } - esp_restart_noos(); + esp_rom_software_reset_system(); + while (true) { + ; + } } #endif // CONFIG_ESP_SYSTEM_BROWNOUT_INTR diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 2469b3150687..798cd5e97df2 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -541,6 +541,10 @@ void IRAM_ATTR call_start_cpu0(void) // For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors. // So we have to read it here in SPI mode, before entering the OPI mode. bootloader_flash_update_id(); + + // Configure the power related stuff. After this the MSPI timing tuning can be done. + esp_rtc_init(); + /** * This function initialise the Flash chip to the user-defined settings. * @@ -549,14 +553,9 @@ void IRAM_ATTR call_start_cpu0(void) * In this stage, we re-configure the Flash (and MSPI) to required configuration */ spi_flash_init_chip_state(); - - // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough. - // Do calibration again here so that we can use better clock for the timing tuning. -#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB - rtc_clk_recalib_bbpll(); -#endif #if SOC_MEMSPI_SRC_FREQ_120M - // This function needs to be called when PLL is enabled + // This function needs to be called when PLL is enabled. Needs to be called after spi_flash_init_chip_state in case + // some state of flash is modified. mspi_timing_flash_tuning(); #endif diff --git a/components/esp_system/port/include/esp_clk_internal.h b/components/esp_system/port/include/esp_clk_internal.h index 358002e2a197..a3829368b326 100644 --- a/components/esp_system/port/include/esp_clk_internal.h +++ b/components/esp_system/port/include/esp_clk_internal.h @@ -18,6 +18,15 @@ extern "C" { * Private clock-related functions */ +/** + * @brief Initialize rtc-related settings + * + * Called from cpu_start.c, not intended to be called from other places. + * This function configures the power related stuff. + * After this the MSPI timing tuning can be done. + */ +void esp_rtc_init(void); + /** * @brief Initialize clock-related settings * diff --git a/components/esp_system/port/soc/esp32/clk.c b/components/esp_system/port/soc/esp32/clk.c index 0de819e687e6..88f72ff94733 100644 --- a/components/esp_system/port/soc/esp32/clk.c +++ b/components/esp_system/port/soc/esp32/clk.c @@ -106,11 +106,14 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) esp_clk_slowclk_cal_set(cal_val); } -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_init(cfg); +} +__attribute__((weak)) void esp_clk_init(void) +{ #if (CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS || CONFIG_APP_INIT_CLK) /* Check the bootloader set the XTAL frequency. diff --git a/components/esp_system/port/soc/esp32c2/clk.c b/components/esp_system/port/soc/esp32c2/clk.c index ef75764dacbb..6cc267ea6c88 100644 --- a/components/esp_system/port/soc/esp32c2/clk.c +++ b/components/esp_system/port/soc/esp32c2/clk.c @@ -51,11 +51,18 @@ typedef enum { } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); +static __attribute__((unused)) void recalib_bbpll(void); static const char *TAG = "clk"; -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { +#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB + // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough. + // Do calibration again here so that we can use better clock for the timing tuning. + recalib_bbpll(); +#endif + #if !CONFIG_IDF_ENV_FPGA rtc_config_t cfg = RTC_CONFIG_DEFAULT(); soc_reset_reason_t rst_reas; @@ -64,7 +71,12 @@ __attribute__((weak)) void esp_clk_init(void) cfg.cali_ocode = 1; } rtc_init(cfg); +#endif +} +__attribute__((weak)) void esp_clk_init(void) +{ +#if !CONFIG_IDF_ENV_FPGA #ifndef CONFIG_XTAL_FREQ_AUTO assert(rtc_clk_xtal_freq_get() == CONFIG_XTAL_FREQ); #endif @@ -265,3 +277,21 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } + +// Workaround for bootloader not calibrated well issue. +// Placed in IRAM because disabling BBPLL may influence the cache +static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void) +{ + rtc_cpu_freq_config_t old_config; + rtc_clk_cpu_freq_get_config(&old_config); + + // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. + // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. + // Turn off the BBPLL and do calibration again to fix the issue. + // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's + // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. + if (old_config.source == SOC_CPU_CLK_SRC_PLL) { + rtc_clk_cpu_freq_set_xtal(); + rtc_clk_cpu_freq_set_config(&old_config); + } +} diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c index 972dc75d1ba2..ece3d4c732fc 100644 --- a/components/esp_system/port/soc/esp32c3/clk.c +++ b/components/esp_system/port/soc/esp32c3/clk.c @@ -56,7 +56,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); static const char *TAG = "clk"; -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { #if !CONFIG_IDF_ENV_FPGA rtc_config_t cfg = RTC_CONFIG_DEFAULT(); @@ -70,7 +70,10 @@ __attribute__((weak)) void esp_clk_init(void) cfg.cali_ocode = 1; } rtc_init(cfg); +} +__attribute__((weak)) void esp_clk_init(void) +{ assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M); bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled(); diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index c1dab5b04119..7242255e4d4e 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -45,7 +45,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src); static const char *TAG = "clk"; // TODO: [ESP32C5] IDF-8642 -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { #if !CONFIG_IDF_ENV_FPGA #if SOC_PMU_SUPPORTED @@ -54,7 +54,13 @@ __attribute__((weak)) void esp_clk_init(void) if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) { esp_ocode_calib_init(); } +#endif +} +// TODO: [ESP32C5] IDF-8642 +__attribute__((weak)) void esp_clk_init(void) +{ +#if !CONFIG_IDF_ENV_FPGA assert((rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_48M) || (rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M)); rtc_clk_8m_enable(true); diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index e2b1e8d20e82..42a2f8f00a30 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -58,17 +58,29 @@ #define MHZ (1000000) static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src); +static __attribute__((unused)) void recalib_bbpll(void); static const char *TAG = "clk"; -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { +#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB + // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough. + // Do calibration again here so that we can use better clock for the timing tuning. + recalib_bbpll(); +#endif + #if !CONFIG_IDF_ENV_FPGA pmu_init(); if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) { esp_ocode_calib_init(); } +#endif +} +__attribute__((weak)) void esp_clk_init(void) +{ +#if !CONFIG_IDF_ENV_FPGA assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M); rtc_clk_8m_enable(true); @@ -302,3 +314,21 @@ __attribute__((weak)) void esp_perip_clk_init(void) WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0); } } + +// Workaround for bootloader not calibrated well issue. +// Placed in IRAM because disabling BBPLL may influence the cache +static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void) +{ + rtc_cpu_freq_config_t old_config; + rtc_clk_cpu_freq_get_config(&old_config); + + // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. + // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. + // Turn off the BBPLL and do calibration again to fix the issue. + // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's + // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. + if (old_config.source == SOC_CPU_CLK_SRC_PLL) { + rtc_clk_cpu_freq_set_xtal(); + rtc_clk_cpu_freq_set_config(&old_config); + } +} diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 9eabae25939e..9a82793f6f73 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -41,14 +41,19 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src); static const char *TAG = "clk"; -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { #if !CONFIG_IDF_ENV_FPGA pmu_init(); if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) { esp_ocode_calib_init(); } +#endif +} +__attribute__((weak)) void esp_clk_init(void) +{ +#if !CONFIG_IDF_ENV_FPGA assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M); rtc_clk_8m_enable(true); diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 0523bd8c92b4..87e2140cf3e6 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -58,14 +58,26 @@ #define MHZ (1000000) static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src); +static __attribute__((unused)) void recalib_bbpll(void); static const char *TAG = "clk"; -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { +#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB + // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough. + // Do calibration again here so that we can use better clock for the timing tuning. + recalib_bbpll(); +#endif + #if !CONFIG_IDF_ENV_FPGA pmu_init(); +#endif +} +__attribute__((weak)) void esp_clk_init(void) +{ +#if !CONFIG_IDF_ENV_FPGA assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_32M); rtc_clk_8m_enable(true); @@ -290,3 +302,21 @@ __attribute__((weak)) void esp_perip_clk_init(void) WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0); } } + +// Workaround for bootloader not calibrated well issue. +// Placed in IRAM because disabling BBPLL may influence the cache +static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void) +{ + rtc_cpu_freq_config_t old_config; + rtc_clk_cpu_freq_get_config(&old_config); + + // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. + // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. + // Turn off the BBPLL and do calibration again to fix the issue. Flash_PLL comes from the same source as PLL. + // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's + // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. + if (old_config.source == SOC_CPU_CLK_SRC_PLL || old_config.source == SOC_CPU_CLK_SRC_FLASH_PLL) { + rtc_clk_cpu_freq_set_xtal(); + rtc_clk_cpu_freq_set_config(&old_config); + } +} diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index c00287e5a10c..85332e67ae98 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -41,12 +41,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src); static const char *TAG = "clk"; -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { #if SOC_PMU_SUPPORTED pmu_init(); #endif //SOC_PMU_SUPPORTED +} +__attribute__((weak)) void esp_clk_init(void) +{ assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M); rtc_clk_8m_enable(true); diff --git a/components/esp_system/port/soc/esp32p4/reset_reason.c b/components/esp_system/port/soc/esp32p4/reset_reason.c index afcb6184df11..b9cea8ddfeef 100644 --- a/components/esp_system/port/soc/esp32p4/reset_reason.c +++ b/components/esp_system/port/soc/esp32p4/reset_reason.c @@ -8,6 +8,8 @@ #include "esp_rom_sys.h" #include "esp_private/system_internal.h" #include "soc/rtc_periph.h" +#include "soc/chip_revision.h" +#include "hal/efuse_hal.h" #include "esp32p4/rom/rtc.h" static void esp_reset_reason_clear_hint(void); @@ -57,7 +59,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, case RESET_REASON_CORE_EFUSE_CRC: #if CONFIG_IDF_TARGET_ESP32P4 - return ESP_RST_DEEPSLEEP; // TODO: IDF-9564 + if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { + return ESP_RST_DEEPSLEEP; + } #endif return ESP_RST_EFUSE; diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c index 7da508fde773..45d932ba5205 100644 --- a/components/esp_system/port/soc/esp32s2/clk.c +++ b/components/esp_system/port/soc/esp32s2/clk.c @@ -59,7 +59,7 @@ typedef enum { static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { rtc_config_t cfg = RTC_CONFIG_DEFAULT(); soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0); @@ -73,7 +73,10 @@ __attribute__((weak)) void esp_clk_init(void) } } rtc_init(cfg); +} +__attribute__((weak)) void esp_clk_init(void) +{ bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled(); rtc_clk_8m_enable(true, rc_fast_d256_is_enabled); rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c index 4589d5e4f941..fac148fb41a5 100644 --- a/components/esp_system/port/soc/esp32s3/clk.c +++ b/components/esp_system/port/soc/esp32s3/clk.c @@ -54,9 +54,16 @@ typedef enum { } slow_clk_sel_t; static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); +static __attribute__((unused)) void recalib_bbpll(void); -__attribute__((weak)) void esp_clk_init(void) +void esp_rtc_init(void) { +#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB + // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough. + // Do calibration again here so that we can use better clock for the timing tuning. + recalib_bbpll(); +#endif + rtc_config_t cfg = RTC_CONFIG_DEFAULT(); soc_reset_reason_t rst_reas; rst_reas = esp_rom_get_reset_reason(0); @@ -65,7 +72,10 @@ __attribute__((weak)) void esp_clk_init(void) cfg.cali_ocode = 1; } rtc_init(cfg); +} +__attribute__((weak)) void esp_clk_init(void) +{ assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M); bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled(); @@ -325,3 +335,21 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } + +// Workaround for bootloader not calibrated well issue. +// Placed in IRAM because disabling BBPLL may influence the cache +static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void) +{ + rtc_cpu_freq_config_t old_config; + rtc_clk_cpu_freq_get_config(&old_config); + + // There are two paths we arrive here: 1. CPU reset. 2. Other reset reasons. + // - For other reasons, the bootloader will set CPU source to BBPLL and enable it. But there are calibration issues. + // Turn off the BBPLL and do calibration again to fix the issue. + // - For CPU reset, the CPU source will be set to XTAL, while the BBPLL is kept to meet USB Serial JTAG's + // requirements. In this case, we don't touch BBPLL to avoid USJ disconnection. + if (old_config.source == SOC_CPU_CLK_SRC_PLL) { + rtc_clk_cpu_freq_set_xtal(); + rtc_clk_cpu_freq_set_config(&old_config); + } +} diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index e9af973ff2db..f242a2db7743 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -9,6 +9,7 @@ #include "esp_attr.h" #include "esp_err.h" +#include "esp_compiler.h" #include "esp_system.h" #include "esp_log.h" @@ -21,7 +22,7 @@ #include "esp_private/startup_internal.h" // Ensure that system configuration matches the underlying number of cores. -// This should enable us to avoid checking for both everytime. +// This should enable us to avoid checking for both every time. #if !(SOC_CPU_CORES_NUM > 1) && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #error "System has been configured to run on multiple cores, but target SoC only has a single core." #endif @@ -96,10 +97,13 @@ static void do_global_ctors(void) } #endif + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-out-of-bounds") for (p = &__init_array_end - 1; p >= &__init_array_start; --p) { ESP_LOGD(TAG, "calling init function: %p", *p); (*p)(); } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-out-of-bounds") + } /** diff --git a/components/esp_timer/src/esp_timer.c b/components/esp_timer/src/esp_timer.c index 5c0ec368cc8c..71698b335e8c 100644 --- a/components/esp_timer/src/esp_timer.c +++ b/components/esp_timer/src/esp_timer.c @@ -18,6 +18,7 @@ #include "esp_ipc.h" #include "esp_timer.h" #include "esp_timer_impl.h" +#include "esp_compiler.h" #include "esp_private/startup_internal.h" #include "esp_private/esp_timer_private.h" @@ -215,7 +216,7 @@ esp_err_t IRAM_ATTR esp_timer_start_once(esp_timer_handle_t timer, uint64_t time timer_list_lock(dispatch_method); /* Check if the timer is armed once the list is locked. - * Otherwise another task may arm the timer inbetween the check + * Otherwise another task may arm the timer between the checks * and us locking the list, resulting in us inserting the * timer to s_timers a second time. This will create a loop * in s_timers. */ @@ -418,9 +419,11 @@ static bool timer_process_alarm(esp_timer_dispatch_t dispatch_method) while (1) { it = LIST_FIRST(&s_timers[dispatch_method]); int64_t now = esp_timer_impl_get_time(); + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-use-after-free") // False-positive detection. TODO GCC-366 if (it == NULL || it->alarm > now) { break; } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-use-after-free") processed = true; LIST_REMOVE(it, list_entry); if (it->event_id == EVENT_ID_DELETE_TIMER) { diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index fda241ceff83..eacd07f165fe 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit fda241ceff83a34609c9fc132d3e19916969f2c8 +Subproject commit eacd07f165fee254b37ee5819208e1185549ec59 diff --git a/components/freertos/CMakeLists.txt b/components/freertos/CMakeLists.txt index f64041477014..79e11d0c4549 100644 --- a/components/freertos/CMakeLists.txt +++ b/components/freertos/CMakeLists.txt @@ -248,4 +248,12 @@ else() idf_component_optional_requires(PRIVATE esp_pm) endif() + if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_FREERTOS_SMP AND + CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # suppress false-positive warning + set_source_files_properties( + "${kernel_impl}/queue.c" + PROPERTIES COMPILE_OPTIONS + "-Wno-analyzer-null-argument" + ) + endif() endif() diff --git a/components/freertos/esp_additions/freertos_tasks_c_additions.h b/components/freertos/esp_additions/freertos_tasks_c_additions.h index ec2236b87aca..8c9ce93d7867 100644 --- a/components/freertos/esp_additions/freertos_tasks_c_additions.h +++ b/components/freertos/esp_additions/freertos_tasks_c_additions.h @@ -7,6 +7,7 @@ #include "sdkconfig.h" #include "esp_assert.h" #include "esp_heap_caps.h" +#include "esp_compiler.h" #include "freertos/idf_additions.h" #if CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT #include "esp_private/freertos_debug.h" @@ -1041,6 +1042,8 @@ int xTaskGetNext( TaskIterator_t * xIterator ) BaseType_t vTaskGetSnapshot( TaskHandle_t pxTask, TaskSnapshot_t * pxTaskSnapshot ) { + ESP_STATIC_ANALYZER_CHECK(!pxTask, pdFALSE); + if( ( portVALID_TCB_MEM( pxTask ) == false ) || ( pxTaskSnapshot == NULL ) ) { return pdFALSE; diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 2cc5191546de..6cc4319dc2ce 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -326,3 +326,8 @@ if(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 1) elseif(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 2) target_link_libraries(${COMPONENT_LIB} INTERFACE "-u __assert_func") endif() + +if((CONFIG_IDF_TARGET_ESP32H2 OR CONFIG_IDF_TARGET_ESP32S2 OR CONFIG_IDF_TARGET_ESP32S3) AND + CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10234 + target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer") +endif() diff --git a/components/hal/esp32/include/hal/mwdt_ll.h b/components/hal/esp32/include/hal/mwdt_ll.h index 48a468f5acc5..28167fa17a40 100644 --- a/components/hal/esp32/include/hal/mwdt_ll.h +++ b/components/hal/esp32/include/hal/mwdt_ll.h @@ -17,7 +17,7 @@ extern "C" { #include #include "hal/misc.h" #include "hal/assert.h" -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "hal/wdt_types.h" #include "esp_attr.h" diff --git a/components/hal/esp32/include/hal/sdio_slave_ll.h b/components/hal/esp32/include/hal/sdio_slave_ll.h index 2c94f217e78d..aa0a001ca648 100644 --- a/components/hal/esp32/include/hal/sdio_slave_ll.h +++ b/components/hal/esp32/include/hal/sdio_slave_ll.h @@ -17,6 +17,7 @@ #pragma once #include "hal/sdio_slave_types.h" +#include "hal/misc.h" #include "soc/slc_struct.h" #include "soc/slc_reg.h" #include "soc/host_struct.h" @@ -514,7 +515,7 @@ static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_ { //use registers in SLC to trigger, rather than write HOST registers directly //other interrupts than tohost interrupts are not supported yet - slc->intvec_tohost.slc0_intvec = (*mask); + HAL_FORCE_MODIFY_U32_REG_FIELD(slc->intvec_tohost, slc0_intvec, *mask); } /** diff --git a/components/hal/esp32c2/include/hal/ecc_ll.h b/components/hal/esp32c2/include/hal/ecc_ll.h index 2fcca34ea0f8..58ddd82dd002 100644 --- a/components/hal/esp32c2/include/hal/ecc_ll.h +++ b/components/hal/esp32c2/include/hal/ecc_ll.h @@ -49,6 +49,9 @@ static inline void ecc_ll_reset_register(void) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define ecc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_reset_register(__VA_ARGS__) +static inline void ecc_ll_power_up(void) {} +static inline void ecc_ll_power_down(void) {} + static inline void ecc_ll_enable_interrupt(void) { REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); diff --git a/components/hal/esp32c2/include/hal/mwdt_ll.h b/components/hal/esp32c2/include/hal/mwdt_ll.h index cb3649497b90..11eeaa64626d 100644 --- a/components/hal/esp32c2/include/hal/mwdt_ll.h +++ b/components/hal/esp32c2/include/hal/mwdt_ll.h @@ -15,7 +15,7 @@ extern "C" { #include #include -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "hal/wdt_types.h" #include "esp_attr.h" diff --git a/components/hal/esp32c3/include/hal/mwdt_ll.h b/components/hal/esp32c3/include/hal/mwdt_ll.h index 24fd44803e95..711b437590d3 100644 --- a/components/hal/esp32c3/include/hal/mwdt_ll.h +++ b/components/hal/esp32c3/include/hal/mwdt_ll.h @@ -15,7 +15,7 @@ extern "C" { #include #include -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "hal/wdt_types.h" #include "hal/assert.h" diff --git a/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h index f57b378e7f45..7a5b4ed23e31 100644 --- a/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h @@ -12,6 +12,7 @@ #include "soc/usb_serial_jtag_struct.h" #include "soc/system_struct.h" #include "hal/usb_serial_jtag_types.h" +#include "hal/misc.h" /* ----------------------------- Macros & Types ----------------------------- */ @@ -116,7 +117,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); } return i; } @@ -135,7 +136,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); } return i; } diff --git a/components/hal/esp32c5/include/hal/ecc_ll.h b/components/hal/esp32c5/include/hal/ecc_ll.h index 45c4e66071c6..b9f04d7a8a98 100644 --- a/components/hal/esp32c5/include/hal/ecc_ll.h +++ b/components/hal/esp32c5/include/hal/ecc_ll.h @@ -11,6 +11,7 @@ #include "hal/ecc_types.h" #include "soc/ecc_mult_reg.h" #include "soc/pcr_struct.h" +#include "soc/pcr_reg.h" #ifdef __cplusplus extern "C" { @@ -46,6 +47,20 @@ static inline void ecc_ll_reset_register(void) PCR.ecdsa_conf.ecdsa_rst_en = 0; } +static inline void ecc_ll_power_up(void) +{ + /* Power up the ECC peripheral (default state is power-down) */ + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD); +} + +static inline void ecc_ll_power_down(void) +{ + /* Power down the ECC peripheral */ + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU); + REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); +} + static inline void ecc_ll_enable_interrupt(void) { REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); diff --git a/components/hal/esp32c5/include/hal/i2c_ll.h b/components/hal/esp32c5/include/hal/i2c_ll.h index 5bff9a330237..5c6547f29270 100644 --- a/components/hal/esp32c5/include/hal/i2c_ll.h +++ b/components/hal/esp32c5/include/hal/i2c_ll.h @@ -611,7 +611,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h * * @param hw Beginning address of the peripheral registers * @param ptr Pointer to data buffer - * @param len Amount of data needs to be writen + * @param len Amount of data needs to be written * * @return None. */ @@ -646,7 +646,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * @param hw Beginning address of the peripheral registers * @param ram_offset Offset value of I2C RAM. * @param ptr Pointer to data buffer - * @param len Amount of data needs to be writen + * @param len Amount of data needs to be written */ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) { @@ -718,7 +718,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) } /** - * @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM + * @brief Reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * * @param hw Beginning address of the peripheral registers * @@ -746,7 +746,7 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_en = 1; hw->ctr.conf_upgate = 1; - // hardward will clear scl_rst_slv_en after sending SCL pulses, + // hardware will clear scl_rst_slv_en after sending SCL pulses, // and we should set conf_upgate bit to synchronize register value. while (hw->scl_sp_conf.scl_rst_slv_en); hw->ctr.conf_upgate = 1; @@ -853,6 +853,20 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev) dev->scl_stretch_conf.slave_scl_stretch_clr = 1; } +/** + * @brief Check if i2c command is done. + * + * @param hw Beginning address of the peripheral registers + * @param cmd_idx The index of the command register, must be less than 8 + * + * @return True if the `cmd_idx` command is done. Otherwise false. + */ +__attribute__((always_inline)) +static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx) +{ + return hw->command[cmd_idx].command_done; +} + /** * @brief Calculate SCL timeout us to reg value * @@ -902,7 +916,7 @@ typedef enum { * @brief Configure I2C SCL timing * * @param hw Beginning address of the peripheral registers - * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) + * @param high_period The I2C SCL height period (in core clock cycle, height_period > 2) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param wait_high_period The I2C SCL wait rising edge period. * @@ -1090,16 +1104,16 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) * @brief Configure I2C SCL timing * * @param hw Beginning address of the peripheral registers - * @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) + * @param height_period The I2C SCL height period (in core clock cycle, height_period > 2) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * * @return None. */ -static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period) +static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int height_period, int low_period) { hw->scl_low_period.scl_low_period = low_period - 1; - hw->scl_high_period.scl_high_period = hight_period - 10; - hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.scl_high_period; + hw->scl_high_period.scl_high_period = height_period - 10; + hw->scl_high_period.scl_wait_high_period = height_period - hw->scl_high_period.scl_high_period; } /** diff --git a/components/hal/esp32c5/include/hal/lp_core_ll.h b/components/hal/esp32c5/include/hal/lp_core_ll.h index c1e5baeae6b1..59cb13c44179 100644 --- a/components/hal/esp32c5/include/hal/lp_core_ll.h +++ b/components/hal/esp32c5/include/hal/lp_core_ll.h @@ -120,6 +120,16 @@ static inline void lp_core_ll_request_sleep(void) PMU.lp_ext.pwr1.sleep_req = 1; } +/** + * @brief Get which interrupts have triggered on the LP core + * + * @return uint8_t bit mask of triggered LP interrupt sources + */ +static inline uint8_t lp_core_ll_get_triggered_interrupt_srcs(void) +{ + return LPPERI.interrupt_source.lp_interrupt_source; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/lp_timer_ll.h b/components/hal/esp32c5/include/hal/lp_timer_ll.h index 7878c91d7d0f..cac0a289b55a 100644 --- a/components/hal/esp32c5/include/hal/lp_timer_ll.h +++ b/components/hal/esp32c5/include/hal/lp_timer_ll.h @@ -9,11 +9,11 @@ #pragma once #include +#include #include "soc/soc.h" -#include "soc/rtc.h" #include "soc/lp_timer_struct.h" +#include "soc/lp_timer_reg.h" #include "soc/lp_aon_reg.h" -#include "hal/assert.h" #include "hal/lp_timer_types.h" #include "hal/misc.h" #include "esp_attr.h" @@ -22,121 +22,55 @@ extern "C" { #endif -/** - * @brief Set lp_timer alarm target - * - * @param dev lp_timer source - * @param timer_id lp_timer target num - * @param value next alarm value - * - * @return None - */ FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value) { - HAL_ASSERT(false && "lp_timer not supported yet"); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high0, (value >> 32) & 0xFFFF); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low0, value & 0xFFFFFFFF); } -/** - * @brief Enable lp_timer alarm - * - * @param dev lp_timer source - * @param timer_id lp_timer target num - * @param en enable bit - * - * @return None - */ FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en) { - HAL_ASSERT(false && "lp_timer not supported yet"); + dev->target[timer_id].hi.main_timer_tar_en0 = en; } -/** - * @brief Get lp_timer low bits value of counter - * - * @param dev lp_timer source - * @param buffer_id lp_timer counter buffer num - * - * @return The lp_timer low bits value of counter - */ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id) { - HAL_ASSERT(false && "lp_timer not supported yet"); - return 0; + return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf0_low); } -/** - * @brief Get lp_timer high bits value of counter - * - * @param dev lp_timer source - * @param buffer_id lp_timer counter buffer num - * - * @return The lp_timer high bits value of counter - */ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id) { - HAL_ASSERT(false && "lp_timer not supported yet"); - return 0; + return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf0_high); } -/** - * @brief Update lp_timer counter - * - * @param dev lp_timer source - * - * @return None - */ FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev) { - HAL_ASSERT(false && "lp_timer not supported yet"); + dev->update.main_timer_update = 1; } -/** - * @brief Clear lp_timer alarm intr status - * - * @param dev lp_timer source - * - * @return None - */ FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev) { - HAL_ASSERT(false && "lp_timer not supported yet"); + dev->int_clr.soc_wakeup_int_clr = 1; } -/** - * @brief Clear lp_timer overflow intr status - * - * @param dev lp_timer source - * - * @return None - */ FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev) { - HAL_ASSERT(false && "lp_timer not supported yet"); + dev->int_clr.overflow_clr = 1; } -/** - * @brief Clear lp_timer lp_alarm intr status - * - * @param dev lp_timer source - * - * @return None - */ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev) { - HAL_ASSERT(false && "lp_timer not supported yet"); + dev->lp_int_clr.main_timer_lp_int_clr = 1; } -/** - * @brief Convert lp_timer time to count - * - * @param time_in_us time in us - * - * @return lp_timer count - */ -FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us) +FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev) +{ + return dev->lp_int_raw.val; +} + +FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask) { - HAL_ASSERT(false && "lp_timer not supported yet"); - return 0; + dev->lp_int_clr.val = mask; } #ifdef __cplusplus diff --git a/components/hal/esp32c5/include/hal/modem_lpcon_ll.h b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h index 1d8b72af5a4a..91bd12b7c135 100644 --- a/components/hal/esp32c5/include/hal/modem_lpcon_ll.h +++ b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h @@ -12,11 +12,311 @@ #include #include "soc/soc.h" #include "hal/assert.h" +#include "modem/modem_lpcon_struct.h" +#include "hal/modem_clock_types.h" #ifdef __cplusplus extern "C" { #endif +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->lp_timer_conf.clk_lp_timer_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->lp_timer_conf.clk_lp_timer_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->coex_lp_clk_conf.clk_coex_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->coex_lp_clk_conf.clk_coex_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en) +{ + // ESP32C5 Not Support +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_modem_pwr_clk_src_fo(modem_lpcon_dev_t *hw, bool value) +{ + hw->modem_src_clk_conf.modem_pwr_clk_src_fo = value; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_clk_modem_aon_force(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->modem_src_clk_conf.clk_modem_aon_force = value; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src) +{ + hw->modem_32k_clk_conf.clk_modem_32k_sel = src; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_wifipwr_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_coex_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_i2c_mst_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_lp_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifipwr_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_coex_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_i2c_mst_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_lp_timer_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_wifipwr_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifipwr_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_coex_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_coex_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_i2c_mst_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_i2c_mst_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_lp_apb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_lp_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_wifipwr(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_wifipwr = 1; + hw->rst_conf.rst_wifipwr = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_coex = 1; + hw->rst_conf.rst_coex = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_i2c_mst = 1; + hw->rst_conf.rst_i2c_mst = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_lp_timer = 1; + hw->rst_conf.rst_lp_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.val = 0xf; + hw->rst_conf.val = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_pwr_tick_target(modem_lpcon_dev_t *hw, uint32_t val) +{ + hw->tick_conf.modem_pwr_tick_target = val; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw) +{ + return hw->date.val; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_chan_freq_mem(modem_lpcon_dev_t *hw, bool en) +{ + hw->apb_mem_sel.chan_freq_mem_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_pbus_mem(modem_lpcon_dev_t *hw, bool en) +{ + hw->apb_mem_sel.pbus_mem_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_agc_mem(modem_lpcon_dev_t *hw, bool en) +{ + hw->apb_mem_sel.agc_mem_en = en; +} #ifdef __cplusplus } diff --git a/components/hal/esp32c5/include/hal/modem_syscon_ll.h b/components/hal/esp32c5/include/hal/modem_syscon_ll.h index 6f237998aeac..c1fdfafa71b9 100644 --- a/components/hal/esp32c5/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32c5/include/hal/modem_syscon_ll.h @@ -12,11 +12,675 @@ #include #include "soc/soc.h" #include "hal/assert.h" +#include "modem/modem_syscon_struct.h" +#include "hal/modem_clock_types.h" #ifdef __cplusplus extern "C" { #endif +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_pwdet_sar_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.pwdet_sar_clock_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_pwdet_clk_div_num(modem_syscon_dev_t *hw, uint32_t div) +{ + hw->clk_conf.pwdet_clk_div_num = div; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_tx_dac_inv(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_tx_dac_inv_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_rx_dac_inv(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_rx_adc_inv_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_pwdet_adc_inv(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_pwdet_adc_inv_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_i2c_mst_sel_160m(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_i2c_mst_sel_160m = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_mux = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_etm_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zb_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zbmac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_modem_sec_en = en; + hw->clk_conf.clk_modem_sec_ecb_en = en; + hw->clk_conf.clk_modem_sec_ccm_en = en; + hw->clk_conf.clk_modem_sec_bah_en = en; + hw->clk_conf.clk_modem_sec_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_ble_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_etm_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zbmac_apb_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zbmac_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_modem_sec_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_ble_timer_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_data_dump_fo = 1; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_ieee802154_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_zb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_ieee802154_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_zb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_fe_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_fe_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_fe_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_fe_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_bt_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_bt_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_bt_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_bt_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_wifi_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_wifi_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_wifi_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifi_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_modem_periph_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_modem_peri_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_periph_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_peri_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_modem_apb_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_modem_apb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_apb_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifibb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifibb = 1; + hw->modem_rst_conf.rst_wifibb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifimac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifimac = 1; + hw->modem_rst_conf.rst_wifimac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_fe = 1; + hw->modem_rst_conf.rst_fe = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac_apb = 1; + hw->modem_rst_conf.rst_btmac_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac = 1; + hw->modem_rst_conf.rst_btmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb_apb = 1; + hw->modem_rst_conf.rst_btbb_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb = 1; + hw->modem_rst_conf.rst_btbb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_etm = 1; + hw->modem_rst_conf.rst_etm = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_zbmac_apb = 1; + hw->modem_rst_conf.rst_zbmac_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_zbmac = 1; + hw->modem_rst_conf.rst_zbmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_ecb = 1; + hw->modem_rst_conf.rst_modem_ccm = 1; + hw->modem_rst_conf.rst_modem_bah = 1; + hw->modem_rst_conf.rst_modem_sec = 1; + hw->modem_rst_conf.rst_modem_ecb = 0; + hw->modem_rst_conf.rst_modem_ccm = 0; + hw->modem_rst_conf.rst_modem_bah = 0; + hw->modem_rst_conf.rst_modem_sec = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_ble_timer = 1; + hw->modem_rst_conf.rst_ble_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_data_dump = 1; + hw->modem_rst_conf.rst_data_dump = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.val = 0xffffffff; + hw->modem_rst_conf.val = 0; +} + + +__attribute__((always_inline)) +static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) +{ + if(en){ + hw->clk_conf1.val = hw->clk_conf1.val | mask; + } else { + hw->clk_conf1.val = hw->clk_conf1.val & ~mask; + } +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en) +{ + /* Configure + clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_44m / clk_wifibb_80m + clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1 + clk_wifibb_160x1 + */ + modem_syscon_ll_clk_conf1_configure(hw, en, 0x1ff); +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_22m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_44m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_160x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_wifibb_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifimac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifi_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_20m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_apb_en = en; +} + +// The modem_syscon of esp32c5 adds the enablement of the adc clock on the analog front end compared to esp32h2 and esp32c6. +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_adc_en = en; +} + +// The modem_syscon of esp32c5 adds the enablement of the dac clock on the analog front end compared to esp32h2 and esp32c6. +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_dac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_dac_en = en; +} + +// The modem_syscon of esp32c5 adds the enablement of the analog power detect clock on the analog front end compared to esp32h2 and esp32c6. +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_pwdet_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_pwdet_adc_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_bt_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_btmac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_btbb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_22m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_44m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_160x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifimac_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifi_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_20m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_cal_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_cal_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_bt_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_bt_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_480m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_160m_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw) +{ + return hw->date.val; +} #ifdef __cplusplus } diff --git a/components/hal/esp32c5/include/hal/mpi_ll.h b/components/hal/esp32c5/include/hal/mpi_ll.h index ccc0598e4cbd..6bd9fc771c0d 100644 --- a/components/hal/esp32c5/include/hal/mpi_ll.h +++ b/components/hal/esp32c5/include/hal/mpi_ll.h @@ -51,11 +51,15 @@ static inline size_t mpi_ll_calculate_hardware_words(size_t words) static inline void mpi_ll_clear_power_control_bit(void) { + /* Power up the MPI peripheral (default is power-down state) */ REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD); + REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD); } static inline void mpi_ll_set_power_control_bit(void) { + /* Power down the MPI peripheral */ + REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU); REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD); } diff --git a/components/hal/esp32c5/include/hal/mwdt_ll.h b/components/hal/esp32c5/include/hal/mwdt_ll.h index 2a335affcb6d..c4e386a6646f 100644 --- a/components/hal/esp32c5/include/hal/mwdt_ll.h +++ b/components/hal/esp32c5/include/hal/mwdt_ll.h @@ -15,7 +15,7 @@ extern "C" { #include #include -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "hal/wdt_types.h" diff --git a/components/hal/esp32c5/include/hal/parlio_ll.h b/components/hal/esp32c5/include/hal/parlio_ll.h new file mode 100644 index 000000000000..5f6d7b024295 --- /dev/null +++ b/components/hal/esp32c5/include/hal/parlio_ll.h @@ -0,0 +1,672 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/hal_utils.h" +#include "soc/pcr_struct.h" +#include "soc/parl_io_struct.h" +#include "hal/parlio_types.h" + +#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF +#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x10000 +#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider +#define PARLIO_LL_RX_MAX_TIMEOUT 0xFFFF + +#define PARLIO_LL_TX_MAX_BITS_PER_FRAME 0x7FFFF +#define PARLIO_LL_TX_MAX_CLK_INT_DIV 0x10000 +#define PARLIO_LL_TX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider + +#define PARLIO_LL_EVENT_TX_FIFO_EMPTY (1 << 0) +#define PARLIO_LL_EVENT_RX_FIFO_FULL (1 << 1) +#define PARLIO_LL_EVENT_TX_EOF (1 << 2) +#define PARLIO_LL_EVENT_TX_MASK (PARLIO_LL_EVENT_TX_FIFO_EMPTY | PARLIO_LL_EVENT_TX_EOF) +#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL) + +#define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 7 // TXD[7] can be used a valid signal +#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal + +#define PARLIO_LL_CLK_DIVIDER_MAX (0) // Not support fractional divider + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PARLIO_LL_RX_EOF_COND_RX_FULL, /*!< RX unit generates EOF event when it receives enough data */ + PARLIO_LL_RX_EOF_COND_EN_INACTIVE, /*!< RX unit generates EOF event when the external enable signal becomes inactive */ +} parlio_ll_rx_eof_cond_t; + +typedef enum { + PARLIO_LL_TX_EOF_COND_DATA_LEN, /*!< TX unit generates EOF event when it transmits particular data bit length that specified in `tx_bitlen`. */ + PARLIO_LL_TX_EOF_COND_DMA_EOF, /*!< TX unit generates EOF event when the DMA EOF takes place */ +} parlio_ll_tx_eof_cond_t; + +/** + * @brief Enable or disable the parlio peripheral APB clock + * + * @param group_id The group id of the parlio module + * @param enable Set true to enable, false to disable + */ +static inline void parlio_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.parl_io_conf.parl_clk_en = enable; +} + +/** + * @brief Reset the parlio module + * + * @param group_id The group id of the parlio module + */ +static inline void parlio_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.parl_io_conf.parl_rst_en = 1; + PCR.parl_io_conf.parl_rst_en = 0; +} + +///////////////////////////////////////RX Unit/////////////////////////////////////// + +/** + * @brief Set the clock source for the RX unit + * + * @param dev Parallel IO register base address + * @param src Clock source + */ +static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src) +{ + (void)dev; + uint32_t clk_sel = 0; + switch (src) { + case PARLIO_CLK_SRC_XTAL: + clk_sel = 0; + break; + case PARLIO_CLK_SRC_RC_FAST: + clk_sel = 1; + break; + case PARLIO_CLK_SRC_PLL_F240M: + clk_sel = 2; + break; + case PARLIO_CLK_SRC_EXTERNAL: + clk_sel = 3; + break; + + default: // unsupported clock source + HAL_ASSERT(false); + break; + } + PCR.parl_clk_rx_conf.parl_clk_rx_sel = clk_sel; +} + +/** + * @brief Set the clock divider for the RX unit + * + * @param dev Parallel IO register base address + * @param clk_div Clock division with integral part, no fractional part on C5 + */ +static inline void parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div) +{ + (void)dev; + HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_rx_conf, parl_clk_rx_div_num, clk_div->integer - 1); +} + +/** + * @brief Reset the RX unit Core clock domain + * + * @param dev Parallel IO register base address + */ +static inline void parlio_ll_rx_reset_clock(parl_io_dev_t *dev) +{ + (void)dev; + PCR.parl_clk_rx_conf.parl_rx_rst_en = 1; + PCR.parl_clk_rx_conf.parl_rx_rst_en = 0; +} + +/** + * @brief Enable the RX unit Core clock domain + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en) +{ + (void)dev; + PCR.parl_clk_rx_conf.parl_clk_rx_en = en; +} + +/** + * @brief Set the condition to generate the RX EOF event + * + * @param dev Parallel IO register base address + * @param cond RX EOF condition + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_rx_eof_cond_t cond) +{ + dev->rx_genrl_cfg.rx_eof_gen_sel = cond; +} + +/** + * @brief Start RX unit to sample the input data + * + * @param dev Parallel IO register base address + * @param en True to start, False to stop + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_start(parl_io_dev_t *dev, bool en) +{ + dev->rx_start_cfg.rx_start = en; +} + +/** + * @brief Set the receive length + * + * @note The receive length can be used to generate DMA EOF signal, or to work as a frame end delimiter + * + * @param dev Parallel IO register base address + * @param bitlen Number of bits to receive in the next transaction, bitlen must be a multiple of 8 + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bitlen) +{ + dev->rx_data_cfg.rx_bitlen = bitlen; +} + +/** + * @brief Set the sub mode of the level controlled receive mode + * + * @param dev Parallel IO register base address + * @param active_low_en Level of the external enable signal, true for active low, false for active high + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_low_en) +{ + dev->rx_mode_cfg.rx_smp_mode_sel = 0; + dev->rx_mode_cfg.rx_ext_en_inv = active_low_en; +} + +/** + * @brief Set the sub mode of the pulse controlled receive mode + * + * @param dev Parallel IO register base address + * @param start_inc Whether the start pulse is counted + * @param end_inc Whether the end pulse is counted + * @param end_by_len Whether to use the frame length to determine the end of the frame + * @param pulse_inv Whether the pulse is inverted + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_pulse_recv_mode(parl_io_dev_t *dev, bool start_inc, bool end_inc, bool end_by_len, bool pulse_inv) +{ + uint32_t submode = 0; + uint32_t step = 1; + if (end_by_len) { + submode += 4; + } else { // end by pulse + step = 2; + if (!end_inc) { + submode += 1; + } + } + if (!start_inc) { + submode += step; + } + dev->rx_mode_cfg.rx_smp_mode_sel = 1; + dev->rx_mode_cfg.rx_pulse_submode_sel = submode; + dev->rx_mode_cfg.rx_ext_en_inv = pulse_inv; +} + +/** + * @brief Set the receive mode to software controlled receive mode + * + * @param dev Parallel IO register base address + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_soft_recv_mode(parl_io_dev_t *dev) +{ + dev->rx_mode_cfg.rx_smp_mode_sel = 2; +} + +/** + * @brief Whether to start the software controlled receive mode + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en) +{ + dev->rx_mode_cfg.rx_sw_en = en; +} + +/** + * @brief Set the sample clock edge + * + * @param dev Parallel IO register base address + * @param edge Sample clock edge + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) +{ + dev->rx_clk_cfg.rx_clk_i_inv = edge; + dev->rx_clk_cfg.rx_clk_o_inv = edge; +} + +/** + * @brief Set the order to pack bits into one byte + * + * @param dev Parallel IO register base address + * @param order Packing order + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order) +{ + dev->rx_data_cfg.rx_data_order_inv = order; +} + +/** + * @brief Set the bus width of the RX unit + * + * @param dev Parallel IO register base address + * @param width Bus width + */ +static inline void parlio_ll_rx_set_bus_width(parl_io_dev_t *dev, uint32_t width) +{ + uint32_t width_sel = 0; + switch (width) { + case 8: + width_sel = 3; + break; + case 4: + width_sel = 2; + break; + case 2: + width_sel = 1; + break; + case 1: + width_sel = 0; + break; + default: + HAL_ASSERT(false); + } + dev->rx_data_cfg.rx_bus_wid_sel = width_sel; +} + +/** + * @brief Reset RX Async FIFO + * + * @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain. + * The reset synchronization must be performed two clock cycles in advance. + * @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock, + * and then switch to the actual clock after the reset is completed. + * + * @param dev Parallel IO register base address + */ +static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev) +{ + dev->fifo_cfg.rx_fifo_srst = 1; + dev->fifo_cfg.rx_fifo_srst = 0; +} + +/** + * @brief Set which data line as the enable signal + * + * @param dev Parallel IO register base address + * @param line_num Data line number (0-15) + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num) +{ + dev->rx_mode_cfg.rx_ext_en_sel = line_num; +} + +/** + * @brief Whether to enable the RX clock gating + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +static inline void parlio_ll_rx_enable_clock_gating(parl_io_dev_t *dev, bool en) +{ + dev->rx_genrl_cfg.rx_gating_en = en; +} + +/** + * @brief Enable RX timeout feature + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_enable_timeout(parl_io_dev_t *dev, bool en) +{ + dev->rx_genrl_cfg.rx_timeout_en = en; +} + +/** + * @brief Set the threshold of RX timeout + * + * @param dev Parallel IO register base address + * @param thres Threshold of RX timeout + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_set_timeout_thres(parl_io_dev_t *dev, uint32_t thres) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_genrl_cfg, rx_timeout_thres, thres); +} + +/** + * @brief Update the RX configuration, to make the new configuration take effect + * + * @param dev Parallel IO register base address + */ +__attribute__((always_inline)) +static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev) +{ + dev->reg_update.rx_reg_update = 1; + while (dev->reg_update.rx_reg_update); +} + +///////////////////////////////////TX Unit/////////////////////////////////////// + +/** + * @brief Set the clock source for the TX unit + * + * @param dev Parallel IO register base address + * @param src Clock source + */ +static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src) +{ + (void)dev; + uint32_t clk_sel = 0; + switch (src) { + case PARLIO_CLK_SRC_XTAL: + clk_sel = 0; + break; + case PARLIO_CLK_SRC_RC_FAST: + clk_sel = 1; + break; + case PARLIO_CLK_SRC_PLL_F240M: + clk_sel = 2; + break; + case PARLIO_CLK_SRC_EXTERNAL: + clk_sel = 3; + break; + + default: // unsupported clock source + HAL_ASSERT(false); + break; + } + PCR.parl_clk_tx_conf.parl_clk_tx_sel = clk_sel; +} + +/** + * @brief Set the clock divider for the TX unit + * + * @param dev Parallel IO register base address + * @param clk_div Clock division with integral part, no fractional part on C5 + */ +static inline void parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div) +{ + (void)dev; + HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_tx_conf, parl_clk_tx_div_num, clk_div->integer - 1); +} + +/** + * @brief Reset the TX unit Core clock domain + * + * @param dev Parallel IO register base address + */ +__attribute__((always_inline)) +static inline void parlio_ll_tx_reset_clock(parl_io_dev_t *dev) +{ + (void)dev; + PCR.parl_clk_tx_conf.parl_tx_rst_en = 1; + PCR.parl_clk_tx_conf.parl_tx_rst_en = 0; +} + +/** + * @brief Enable the TX unit Core clock domain + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en) +{ + (void)dev; + PCR.parl_clk_tx_conf.parl_clk_tx_en = en; +} + +/** + * @brief Set the data length to be transmitted + * + * @param dev Parallel IO register base address + * @param bitlen Data length in bits, must be a multiple of 8 + */ +__attribute__((always_inline)) +static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t bitlen) +{ + dev->tx_data_cfg.tx_bitlen = bitlen; +} + +/** + * @brief Set the condition to generate the TX EOF event + * + * @param dev Parallel IO register base address + * @param cond TX EOF condition + */ +static inline void parlio_ll_tx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_tx_eof_cond_t cond) +{ + dev->tx_genrl_cfg.tx_eof_gen_sel = cond; +} + +/** + * @brief Whether to enable the TX clock gating + * + * @note The MSB of TXD will be taken as the gating enable signal + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en) +{ + dev->tx_genrl_cfg.tx_gating_en = en; +} + +/** + * @brief Start TX unit to transmit data + * + * @param dev Parallel IO register base address + * @param en True to start, False to stop + */ +__attribute__((always_inline)) +static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en) +{ + dev->tx_start_cfg.tx_start = en; +} + +/** + * @brief Whether to treat the MSB of TXD as the valid signal + * + * @note If enabled, TXD[7] will work as valid signal, which stay high during data transmission. + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en) +{ + dev->tx_genrl_cfg.tx_valid_output_en = en; +} + +/** + * @brief Set the sample clock edge + * + * @param dev Parallel IO register base address + * @param edge Sample clock edge + */ +static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) +{ + dev->tx_clk_cfg.tx_clk_i_inv = edge; + dev->tx_clk_cfg.tx_clk_o_inv = edge; +} + +/** + * @brief Set the order to unpack bits from a byte + * + * @param dev Parallel IO register base address + * @param order Packing order + */ +static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order) +{ + dev->tx_data_cfg.tx_data_order_inv = order; +} + +/** + * @brief Set the bus width of the TX unit + * + * @param dev Parallel IO register base address + * @param width Bus width + */ +static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width) +{ + uint32_t width_sel = 0; + switch (width) { + case 8: + width_sel = 3; + break; + case 4: + width_sel = 2; + break; + case 2: + width_sel = 1; + break; + case 1: + width_sel = 0; + break; + default: + HAL_ASSERT(false); + } + dev->tx_data_cfg.tx_bus_wid_sel = width_sel; +} + +/** + * @brief Reset TX Async FIFO + * + * @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain. + * The reset synchronization must be performed two clock cycles in advance. + * @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock, + * and then switch to the actual clock after the reset is completed. + * + * @param dev Parallel IO register base address + */ +__attribute__((always_inline)) +static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev) +{ + dev->fifo_cfg.tx_fifo_srst = 1; + dev->fifo_cfg.tx_fifo_srst = 0; +} + +/** + * @brief Set the value to output on the TXD when the TX unit is in IDLE state + * + * @param dev Parallel IO register base address + * @param value Value to output + */ +__attribute__((always_inline)) +static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value); +} + +/** + * @brief Check whether the TX unit is ready + * + * @param dev Parallel IO register base address + * @return true: ready, false: busy + */ +__attribute__((always_inline)) +static inline bool parlio_ll_tx_is_ready(parl_io_dev_t *dev) +{ + return dev->st.tx_ready; +} + +////////////////////////////////////Interrupt//////////////////////////////////////////////// + +/** + * @brief Enable Parallel IO interrupt for specific event mask + * + * @param dev Parallel IO register base address + * @param mask Event mask + * @param enable True to enable, False to disable + */ +static inline void parlio_ll_enable_interrupt(parl_io_dev_t *dev, uint32_t mask, bool enable) +{ + if (enable) { + dev->int_ena.val |= mask; + } else { + dev->int_ena.val &= ~mask; + } +} + +/** + * @brief Get interrupt status for TX unit + * + * @param dev Parallel IO register base address + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t parlio_ll_tx_get_interrupt_status(parl_io_dev_t *dev) +{ + return dev->int_st.val & PARLIO_LL_EVENT_TX_MASK; +} + +/** + * @brief Get interrupt status for RX unit + * + * @param dev Parallel IO register base address + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t parlio_ll_rx_get_interrupt_status(parl_io_dev_t *dev) +{ + return dev->int_st.val & PARLIO_LL_EVENT_RX_MASK; +} + +/** + * @brief Clear Parallel IO interrupt status by mask + * + * @param dev Parallel IO register base address + * @param mask Interrupt status mask + */ +__attribute__((always_inline)) +static inline void parlio_ll_clear_interrupt_status(parl_io_dev_t *dev, uint32_t mask) +{ + dev->int_clr.val = mask; +} + +/** + * @brief Get interrupt status register address + * + * @param dev Parallel IO register base address + * @return Register address + */ +static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *dev) +{ + return &dev->int_st; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/pmu_ll.h b/components/hal/esp32c5/include/hal/pmu_ll.h index 83793ed62d62..97a15793daa8 100644 --- a/components/hal/esp32c5/include/hal/pmu_ll.h +++ b/components/hal/esp32c5/include/hal/pmu_ll.h @@ -683,6 +683,16 @@ FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask) hw->lp_ext.int_clr.val = mask; } +FORCE_INLINE_ATTR void pmu_ll_lp_clear_sw_intr_status(pmu_dev_t *hw) +{ + hw->lp_ext.int_clr.sw_trigger = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_enable_sw_intr(pmu_dev_t *hw, bool enable) +{ + hw->lp_ext.int_ena.sw_trigger = enable; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/hal/esp32c5/include/hal/rtc_io_ll.h index 89c8c9a37cfd..ef2eb7bcf634 100644 --- a/components/hal/esp32c5/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c5/include/hal/rtc_io_ll.h @@ -44,6 +44,15 @@ typedef enum { RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */ } rtcio_ll_out_mode_t; +typedef enum { + RTCIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ + RTCIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */ + RTCIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */ + RTCIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling edge */ + RTCIO_INTR_LOW_LEVEL = 4, /*!< GPIO interrupt type : input low level trigger */ + RTCIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */ +} rtcio_ll_intr_type_t; + /** * @brief Select a RTC IOMUX function for the RTC IO * @@ -451,6 +460,18 @@ static inline void rtcio_ll_clear_interrupt_status(void) abort(); } +/** + * Enable interrupt function and set interrupt type + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Interrupt type on high level or low level. + */ +static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type) +{ + // TODO: [ESP32C5] IDF-8719 + //LP_GPIO.pin[rtcio_num].int_type = type; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h new file mode 100644 index 000000000000..b217e71dbbc5 --- /dev/null +++ b/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h @@ -0,0 +1,334 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_attr.h" +#include "soc/pcr_struct.h" +#include "soc/usb_serial_jtag_reg.h" +#include "soc/usb_serial_jtag_struct.h" +#include "hal/usb_serial_jtag_types.h" +#include "hal/misc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ----------------------------- Macros & Types ----------------------------- */ + +#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) // All interrupts mask +#define USB_SERIAL_JTAG_LL_PHY_DEPENDS_ON_BBPLL (1) + +// Define USB_SERIAL_JTAG interrupts +// Note the hardware has more interrupts, but they're only useful for debugging +// the hardware. +typedef enum { + USB_SERIAL_JTAG_INTR_SOF = (1 << 1), + USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2), + USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3), + USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8), + USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9), + USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10), +} usb_serial_jtag_ll_intr_t; + +/* ----------------------------- USJ Peripheral ----------------------------- */ + +/** + * @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask. + * + * @param mask The bitmap of the interrupts need to be enabled. + * + * @return None + */ +static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_ena.val |= mask; +} + +/** + * @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask. + * + * @param mask The bitmap of the interrupts need to be disabled. + * + * @return None + */ +static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_ena.val &= (~mask); +} + +/** + * @brief Get the USB_SERIAL_JTAG interrupt status. + * + * @return The USB_SERIAL_JTAG interrupt status. + */ +static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void) +{ + return USB_SERIAL_JTAG.int_st.val; +} + +/** + * @brief Get the USB_SERIAL_JTAG raw interrupt status. + * + * @return The USB_SERIAL_JTAG raw interrupt status. + */ +static inline __attribute__((always_inline)) uint32_t usb_serial_jtag_ll_get_intraw_mask(void) +{ + return USB_SERIAL_JTAG.int_raw.val; +} + +/** + * @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask. + * + * @param mask The bitmap of the interrupts need to be cleared. + * + * @return None + */ +static inline __attribute__((always_inline)) void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_clr.val = mask; +} + +/** + * @brief Get status of enabled interrupt. + * + * @return interrupt enable value + */ +static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void) +{ + return USB_SERIAL_JTAG.int_ena.val; +} + +/** + * @brief Read the bytes from the USB_SERIAL_JTAG rxfifo. + * + * @param buf The data buffer. + * @param rd_len The data length needs to be read. + * + * @return amount of bytes read + */ +static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) +{ + int i; + for (i = 0; i < (int)rd_len; i++) { + if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); + } + return i; +} + +/** + * @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there + * is room in the buffer. + * + * @param buf The data buffer. + * @param wr_len The data length needs to be written. + * + * @return Amount of bytes actually written. May be less than wr_len. + */ +static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len) +{ + int i; + for (i = 0; i < (int)wr_len; i++) { + if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; + HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); + } + return i; +} + +/** + * @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available. + * + * @return 0 if no data available, 1 if data available + */ +static inline int usb_serial_jtag_ll_rxfifo_data_available(void) +{ + return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail; +} + +/** + * @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room. + * + * @return 0 if no data available, 1 if data available + */ +static inline int usb_serial_jtag_ll_txfifo_writable(void) +{ + return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free; +} + +/** + * @brief Flushes the TX buffer, that is, make it available for the + * host to pick up. + * + * @note When fifo is full (with 64 byte), HW will flush the buffer automatically, + * if this function is called directly after, this effectively turns into a + * no-op. Because a 64-byte packet will be interpreted as a not-complete USB + * transaction, you need to transfer either more data or a zero-length packet + * for the data to actually end up at the program listening to the CDC-ACM + * serial port. To send a zero-length packet, call + * usb_serial_jtag_ll_txfifo_flush() again when + * usb_serial_jtag_ll_txfifo_writable() returns true. + * + * @return na + */ +static inline void usb_serial_jtag_ll_txfifo_flush(void) +{ + USB_SERIAL_JTAG.ep1_conf.wr_done=1; +} + +/** + * @brief Enable USJ JTAG bridge + * + * If enabled, USJ is disconnected from internal JTAG interface. JTAG interface + * is routed through GPIO matrix instead. + * + * @param enable Enable USJ JTAG bridge + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_jtag_bridge(bool enable) +{ + USB_SERIAL_JTAG.conf0.usb_jtag_bridge_en = enable; +} + +/* ---------------------------- USB PHY Control ---------------------------- */ + +/** + * @brief Sets PHY defaults + * + * Some PHY register fields/features of the USJ are redundant on the ESP32-C5. + * This function those fields are set to the appropriate default values. + * + * @param hw Start address of the USB Wrap registers + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_defaults(void) +{ + // External FSLS PHY is not supported + USB_SERIAL_JTAG.conf0.phy_sel = 0; + USB_SERIAL_JTAG.conf0.usb_pad_enable = 1; +} + +/** + * @brief Enables/disables exchanging of the D+/D- pins USB PHY + * + * @param enable Enables pin exchange, disabled otherwise + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pin_exchg(bool enable) +{ + if (enable) { + USB_SERIAL_JTAG.conf0.exchg_pins = 1; + USB_SERIAL_JTAG.conf0.exchg_pins_override = 1; + } else { + USB_SERIAL_JTAG.conf0.exchg_pins_override = 0; + USB_SERIAL_JTAG.conf0.exchg_pins = 0; + } +} + +/** + * @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs + * + * @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V. + * @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V. + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_vref_override(unsigned int vrefh_step, unsigned int vrefl_step) +{ + USB_SERIAL_JTAG.conf0.vrefh = vrefh_step; + USB_SERIAL_JTAG.conf0.vrefl = vrefl_step; + USB_SERIAL_JTAG.conf0.vref_override = 1; +} + +/** + * @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_vref_override(void) +{ + USB_SERIAL_JTAG.conf0.vref_override = 0; +} + +/** + * @brief Enable override of USB FSLS PHY's pull up/down resistors + * + * @param vals Override values to set + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pull_override(const usb_serial_jtag_pull_override_vals_t *vals) +{ + USB_SERIAL_JTAG.conf0.dp_pullup = vals->dp_pu; + USB_SERIAL_JTAG.conf0.dp_pulldown = vals->dp_pd; + USB_SERIAL_JTAG.conf0.dm_pullup = vals->dm_pu; + USB_SERIAL_JTAG.conf0.dm_pulldown = vals->dm_pd; + USB_SERIAL_JTAG.conf0.pad_pull_override = 1; +} + +/** + * @brief Disable override of USB FSLS PHY pull up/down resistors + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_pull_override(void) +{ + USB_SERIAL_JTAG.conf0.pad_pull_override = 0; +} + +/** + * @brief Sets the strength of the pullup resistor + * + * @param strong True is a ~1.4K pullup, false is a ~2.4K pullup + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_pullup_strength(bool strong) +{ + USB_SERIAL_JTAG.conf0.pullup_value = strong; +} + +/** + * @brief Check if USB FSLS PHY pads are enabled + * + * @return True if enabled, false otherwise + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_phy_is_pad_enabled(void) +{ + return USB_SERIAL_JTAG.conf0.usb_pad_enable; +} + +/** + * @brief Enable the USB FSLS PHY pads + * + * @param enable Whether to enable the USB FSLS PHY pads + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable) +{ + USB_SERIAL_JTAG.conf0.usb_pad_enable = enable; +} + +/* ----------------------------- RCC Functions ----------------------------- */ + +/** + * @brief Enable the bus clock for USJ module + * @param clk_en True if enable the clock of USJ module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en) +{ + PCR.usb_device_conf.usb_device_clk_en = clk_en; +} + +/** + * @brief Reset the USJ module + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void) +{ + PCR.usb_device_conf.usb_device_rst_en = 1; + PCR.usb_device_conf.usb_device_rst_en = 0; +} + +/** + * Get the enable status of the USJ module + * + * @return Return true if USJ module is enabled + */ +FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void) +{ + return (PCR.usb_device_conf.usb_device_clk_en && !PCR.usb_device_conf.usb_device_rst_en); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/ecc_ll.h b/components/hal/esp32c6/include/hal/ecc_ll.h index c5e8799dcfb3..cb8b4ca2cd28 100644 --- a/components/hal/esp32c6/include/hal/ecc_ll.h +++ b/components/hal/esp32c6/include/hal/ecc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include "hal/ecc_types.h" #include "soc/ecc_mult_reg.h" #include "soc/pcr_struct.h" +#include "soc/pcr_reg.h" #ifdef __cplusplus extern "C" { @@ -41,6 +42,18 @@ static inline void ecc_ll_reset_register(void) PCR.ecc_conf.ecc_rst_en = 0; } +static inline void ecc_ll_power_up(void) +{ + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD); +} + +static inline void ecc_ll_power_down(void) +{ + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU); + REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); +} + static inline void ecc_ll_enable_interrupt(void) { REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); diff --git a/components/hal/esp32c6/include/hal/etm_ll.h b/components/hal/esp32c6/include/hal/etm_ll.h index a40dd68b1250..9a46f46a1daf 100644 --- a/components/hal/esp32c6/include/hal/etm_ll.h +++ b/components/hal/esp32c6/include/hal/etm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -98,7 +98,7 @@ static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) */ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) { - hw->channel[chan].evt_id.evt_id = event; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, evt_id, event); } /** @@ -110,10 +110,10 @@ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, ui */ static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) { - hw->channel[chan].task_id.task_id = task; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, task_id, task); } -#define etm_ll_is_lpcore_wakeup_triggered() lp_aon_ll_get_lpcore_etm_wakeup_flag() +#define etm_ll_is_lpcore_wakeup_triggered() lp_aon_ll_get_lpcore_etm_wakeup_flag() #define etm_ll_clear_lpcore_wakeup_status() lp_aon_ll_clear_lpcore_etm_wakeup_flag() diff --git a/components/hal/esp32c6/include/hal/modem_syscon_ll.h b/components/hal/esp32c6/include/hal/modem_syscon_ll.h index 169f8b4022f3..27ad9187fef0 100644 --- a/components/hal/esp32c6/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32c6/include/hal/modem_syscon_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -242,6 +242,12 @@ static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) hw->modem_rst_conf.rst_zbmac = 0; } +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw) +{ + // ESP32C6 Not Support +} + __attribute__((always_inline)) static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) { diff --git a/components/hal/esp32c6/include/hal/mpi_ll.h b/components/hal/esp32c6/include/hal/mpi_ll.h index f8deda1658cd..a45616564c97 100644 --- a/components/hal/esp32c6/include/hal/mpi_ll.h +++ b/components/hal/esp32c6/include/hal/mpi_ll.h @@ -49,11 +49,15 @@ static inline size_t mpi_ll_calculate_hardware_words(size_t words) static inline void mpi_ll_clear_power_control_bit(void) { + /* Power up the MPI peripheral */ REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD); + REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD); } static inline void mpi_ll_set_power_control_bit(void) { + /* Power down the MPI peripheral */ + REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU); REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD); } diff --git a/components/hal/esp32c6/include/hal/mwdt_ll.h b/components/hal/esp32c6/include/hal/mwdt_ll.h index 28a34eb88a26..21e15e209fc0 100644 --- a/components/hal/esp32c6/include/hal/mwdt_ll.h +++ b/components/hal/esp32c6/include/hal/mwdt_ll.h @@ -15,7 +15,7 @@ extern "C" { #include #include -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "hal/wdt_types.h" diff --git a/components/hal/esp32c6/include/hal/sdio_slave_ll.h b/components/hal/esp32c6/include/hal/sdio_slave_ll.h index 97c4b544100d..2831edd57bce 100644 --- a/components/hal/esp32c6/include/hal/sdio_slave_ll.h +++ b/components/hal/esp32c6/include/hal/sdio_slave_ll.h @@ -17,6 +17,7 @@ #pragma once #include "hal/sdio_slave_types.h" +#include "hal/misc.h" #include "soc/slc_struct.h" #include "soc/slc_reg.h" #include "soc/host_struct.h" @@ -503,7 +504,7 @@ static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_ { //use registers in SLC to trigger, rather than write HOST registers directly //other interrupts than tohost interrupts are not supported yet - slc->slcintvec_tohost.slc0_tohost_intvec = (*mask); + HAL_FORCE_MODIFY_U32_REG_FIELD(slc->slcintvec_tohost, slc0_tohost_intvec, *mask); } /** diff --git a/components/hal/esp32c6/include/hal/timer_ll.h b/components/hal/esp32c6/include/hal/timer_ll.h index bc507a38771a..a12488a2857a 100644 --- a/components/hal/esp32c6/include/hal/timer_ll.h +++ b/components/hal/esp32c6/include/hal/timer_ll.h @@ -24,6 +24,7 @@ extern "C" { // Get timer group register base address with giving group number #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) +#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER) #define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \ diff --git a/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h index d9aa7e58fa1b..803a1e3e2d71 100644 --- a/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h @@ -12,6 +12,7 @@ #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" #include "hal/usb_serial_jtag_types.h" +#include "hal/misc.h" /* ----------------------------- Macros & Types ----------------------------- */ @@ -116,7 +117,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); } return i; } @@ -135,7 +136,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); } return i; } diff --git a/components/hal/esp32c61/include/hal/mwdt_ll.h b/components/hal/esp32c61/include/hal/mwdt_ll.h index 8f3829ed4d81..39431442eea6 100644 --- a/components/hal/esp32c61/include/hal/mwdt_ll.h +++ b/components/hal/esp32c61/include/hal/mwdt_ll.h @@ -15,7 +15,7 @@ extern "C" { #include #include -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "hal/wdt_types.h" diff --git a/components/hal/esp32h2/include/hal/ecc_ll.h b/components/hal/esp32h2/include/hal/ecc_ll.h index 47d4e8b9e6a5..46667692a700 100644 --- a/components/hal/esp32h2/include/hal/ecc_ll.h +++ b/components/hal/esp32h2/include/hal/ecc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include "hal/ecc_types.h" #include "soc/ecc_mult_reg.h" #include "soc/pcr_struct.h" +#include "soc/pcr_reg.h" #ifdef __cplusplus extern "C" { @@ -47,6 +48,18 @@ static inline void ecc_ll_reset_register(void) PCR.ecdsa_conf.ecdsa_rst_en = 0; } +static inline void ecc_ll_power_up(void) +{ + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD); +} + +static inline void ecc_ll_power_down(void) +{ + REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU); + REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD); +} + static inline void ecc_ll_enable_interrupt(void) { REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); diff --git a/components/hal/esp32h2/include/hal/etm_ll.h b/components/hal/esp32h2/include/hal/etm_ll.h index 9d341ae2ed76..210933eaba00 100644 --- a/components/hal/esp32h2/include/hal/etm_ll.h +++ b/components/hal/esp32h2/include/hal/etm_ll.h @@ -97,7 +97,7 @@ static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) */ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) { - hw->channel[chan].evt_id.evt_id = event; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, evt_id, event); } /** @@ -109,7 +109,7 @@ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, ui */ static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) { - hw->channel[chan].task_id.task_id = task; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, task_id, task); } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/hal/modem_syscon_ll.h b/components/hal/esp32h2/include/hal/modem_syscon_ll.h index 9f214db8eee7..9d6f3e8bbe23 100644 --- a/components/hal/esp32h2/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32h2/include/hal/modem_syscon_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -151,6 +151,12 @@ static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) hw->modem_rst_conf.rst_zbmac = 0; } +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw) +{ + // ESP32H2 Not Support +} + __attribute__((always_inline)) static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) { diff --git a/components/hal/esp32h2/include/hal/mpi_ll.h b/components/hal/esp32h2/include/hal/mpi_ll.h index aa740dcf7171..869cfe34c8eb 100644 --- a/components/hal/esp32h2/include/hal/mpi_ll.h +++ b/components/hal/esp32h2/include/hal/mpi_ll.h @@ -50,11 +50,15 @@ static inline size_t mpi_ll_calculate_hardware_words(size_t words) static inline void mpi_ll_clear_power_control_bit(void) { + /* Power up the MPI peripheral */ REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD); + REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD); } static inline void mpi_ll_set_power_control_bit(void) { + /* Power down the MPI peripheral */ + REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU); REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD); } diff --git a/components/hal/esp32h2/include/hal/mwdt_ll.h b/components/hal/esp32h2/include/hal/mwdt_ll.h index 8b2f01e2d50f..b3b4cf1ef9ec 100644 --- a/components/hal/esp32h2/include/hal/mwdt_ll.h +++ b/components/hal/esp32h2/include/hal/mwdt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,7 +15,7 @@ extern "C" { #include #include -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "soc/pcr_struct.h" #include "hal/wdt_types.h" diff --git a/components/hal/esp32h2/include/hal/parlio_ll.h b/components/hal/esp32h2/include/hal/parlio_ll.h index e0236e0f8a7d..ac3f5d747060 100644 --- a/components/hal/esp32h2/include/hal/parlio_ll.h +++ b/components/hal/esp32h2/include/hal/parlio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -326,7 +326,7 @@ static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32 } /** - * @brief Wether to enable the RX clock gating + * @brief Whether to enable the RX clock gating * * @param dev Parallel IO register base address * @param en True to enable, False to disable @@ -457,7 +457,7 @@ static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t b } /** - * @brief Wether to enable the TX clock gating + * @brief Whether to enable the TX clock gating * * @note The MSB of TXD will be taken as the gating enable signal * @@ -571,7 +571,7 @@ static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev) __attribute__((always_inline)) static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value) { - dev->tx_genrl_cfg.tx_idle_value = value; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value); } /** diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/hal/esp32h2/include/hal/timer_ll.h index b62bdb4db803..982d42e500f8 100644 --- a/components/hal/esp32h2/include/hal/timer_ll.h +++ b/components/hal/esp32h2/include/hal/timer_ll.h @@ -24,6 +24,7 @@ extern "C" { // Get timer group register base address with giving group number #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) +#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER) #define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \ diff --git a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h index 289f0adf18bf..42795580d50a 100644 --- a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h @@ -12,6 +12,7 @@ #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" #include "hal/usb_serial_jtag_types.h" +#include "hal/misc.h" /* ----------------------------- Macros & Types ----------------------------- */ @@ -116,7 +117,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); } return i; } @@ -135,7 +136,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); } return i; } diff --git a/components/hal/esp32p4/include/hal/cpu_utility_ll.h b/components/hal/esp32p4/include/hal/cpu_utility_ll.h index 5c6b606488be..38a21cfc3c24 100644 --- a/components/hal/esp32p4/include/hal/cpu_utility_ll.h +++ b/components/hal/esp32p4/include/hal/cpu_utility_ll.h @@ -11,6 +11,7 @@ #include "soc/pmu_struct.h" #include "soc/hp_system_reg.h" #include "esp_attr.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -29,18 +30,18 @@ FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no) FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no) { if (cpu_no == 0) { - PMU.cpu_sw_stall.hpcore0_stall_code = 0x86; + HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0x86); } else { - PMU.cpu_sw_stall.hpcore1_stall_code = 0x86; + HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0x86); } } FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no) { if (cpu_no == 0) { - PMU.cpu_sw_stall.hpcore0_stall_code = 0xFF; + HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0xFF); } else { - PMU.cpu_sw_stall.hpcore1_stall_code = 0xFF; + HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0xFF); } } #endif // SOC_CPU_CORES_NUM > 1 diff --git a/components/hal/esp32p4/include/hal/dw_gdma_ll.h b/components/hal/esp32p4/include/hal/dw_gdma_ll.h index 6afcca79b359..efe817b8e37d 100644 --- a/components/hal/esp32p4/include/hal/dw_gdma_ll.h +++ b/components/hal/esp32p4/include/hal/dw_gdma_ll.h @@ -1112,7 +1112,7 @@ __attribute__((always_inline)) static inline void dw_gdma_ll_lli_set_src_burst_len(dw_gdma_link_list_item_t *lli, uint8_t len) { lli->ctrl_hi.arlen_en = len > 0; - lli->ctrl_hi.arlen = len; + HAL_FORCE_MODIFY_U32_REG_FIELD(lli->ctrl_hi, arlen, len); } /** @@ -1125,7 +1125,7 @@ __attribute__((always_inline)) static inline void dw_gdma_ll_lli_set_dst_burst_len(dw_gdma_link_list_item_t *lli, uint8_t len) { lli->ctrl_hi.awlen_en = len > 0; - lli->ctrl_hi.awlen = len; + HAL_FORCE_MODIFY_U32_REG_FIELD(lli->ctrl_hi, awlen, len); } /** diff --git a/components/hal/esp32p4/include/hal/ecc_ll.h b/components/hal/esp32p4/include/hal/ecc_ll.h index 879a438acd54..92d747afbc42 100644 --- a/components/hal/esp32p4/include/hal/ecc_ll.h +++ b/components/hal/esp32p4/include/hal/ecc_ll.h @@ -56,6 +56,9 @@ static inline void ecc_ll_reset_register(void) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define ecc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_reset_register(__VA_ARGS__) +static inline void ecc_ll_power_up(void) {} +static inline void ecc_ll_power_down(void) {} + static inline void ecc_ll_enable_interrupt(void) { REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); diff --git a/components/hal/esp32p4/include/hal/emac_ll.h b/components/hal/esp32p4/include/hal/emac_ll.h index 6f7e484edf17..33a5ed8a5c9c 100644 --- a/components/hal/esp32p4/include/hal/emac_ll.h +++ b/components/hal/esp32p4/include/hal/emac_ll.h @@ -628,11 +628,11 @@ static inline void emac_ll_clock_enable_mii(void *ext_regs) HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_src_sel = 1; // 0-pad_emac_txrx_clk, 1-pad_emac_rx_clk - HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = 0; // 25MHz + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_rx_clk_div_num, 0); // 25MHz HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_src_sel = 1; // 0-pad_emac_txrx_clk, 1-pad_emac_tx_clk - HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_div_num = 0; // 25MHz + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_tx_clk_div_num, 0); // 25MHz LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_tx_clk_en = 1; LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_rx_clk_en = 1; @@ -653,11 +653,11 @@ static inline void emac_ll_clock_enable_rmii_input(void *ext_regs) HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_src_sel = 0; // 0-pad_emac_txrx_clk, 1-pad_emac_rx_clk - HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = 1; // set default divider + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_rx_clk_div_num, 1); // set default divider HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_src_sel = 0; // 0-pad_emac_txrx_clk, 1-pad_emac_tx_clk - HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_div_num = 1; // set default divider + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_tx_clk_div_num, 1); // set default divider LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_tx_clk_en = 0; LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_rx_clk_en = 0; @@ -670,8 +670,8 @@ static inline void emac_ll_clock_enable_rmii_input(void *ext_regs) static inline void emac_ll_clock_rmii_rx_tx_div(void *ext_regs, int div) { - HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = div; - HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_div_num = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_rx_clk_div_num, div); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_tx_clk_div_num, div); } /// use a macro to wrap the function, force the caller to use it in a critical section diff --git a/components/hal/esp32p4/include/hal/etm_ll.h b/components/hal/esp32p4/include/hal/etm_ll.h index 6904d170ac74..12e11d64323c 100644 --- a/components/hal/esp32p4/include/hal/etm_ll.h +++ b/components/hal/esp32p4/include/hal/etm_ll.h @@ -106,7 +106,7 @@ static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) */ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) { - hw->channel[chan].evt_id.evt_id = event; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, evt_id, event); } /** @@ -118,7 +118,7 @@ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, ui */ static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) { - hw->channel[chan].task_id.task_id = task; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, task_id, task); } /** diff --git a/components/hal/esp32p4/include/hal/huk_ll.h b/components/hal/esp32p4/include/hal/huk_ll.h index 6fa5b98f2aa8..6b5a50a64fd8 100644 --- a/components/hal/esp32p4/include/hal/huk_ll.h +++ b/components/hal/esp32p4/include/hal/huk_ll.h @@ -58,30 +58,36 @@ static inline void huk_ll_continue(void) /* @bried Enable or Disable the HUK interrupts */ static inline void huk_ll_configure_interrupt(const esp_huk_interrupt_type_t intr, const bool en) { - switch(intr) { - case ESP_HUK_INT_PREP_DONE: - REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en); - case ESP_HUK_INT_PROC_DONE: - REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en); - case ESP_HUK_INT_POST_DONE: - REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en); - default: - return; + switch (intr) { + case ESP_HUK_INT_PREP_DONE: + REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en); + break; + case ESP_HUK_INT_PROC_DONE: + REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en); + break; + case ESP_HUK_INT_POST_DONE: + REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en); + break; + default: + return; } } /* @bried Clear the HUK interrupts */ static inline void huk_ll_clear_int(const esp_huk_interrupt_type_t intr) { - switch(intr) { - case ESP_HUK_INT_PREP_DONE: - REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1); - case ESP_HUK_INT_PROC_DONE: - REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1); - case ESP_HUK_INT_POST_DONE: - REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1); - default: - return; + switch (intr) { + case ESP_HUK_INT_PREP_DONE: + REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1); + break; + case ESP_HUK_INT_PROC_DONE: + REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1); + break; + case ESP_HUK_INT_POST_DONE: + REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1); + break; + default: + return; } } @@ -108,7 +114,7 @@ static inline esp_huk_gen_status_t huk_ll_get_gen_status(void) */ static inline uint32_t huk_ll_get_date_info(void) { - // Only the least siginificant 28 bits have desired information + // Only the least significant 28 bits have desired information return (uint32_t)(0x0FFFFFFF & REG_READ(HUK_DATE_REG)); } diff --git a/components/hal/esp32p4/include/hal/lp_i2s_ll.h b/components/hal/esp32p4/include/hal/lp_i2s_ll.h index 17f3aba185f5..c25e3c57dfdf 100644 --- a/components/hal/esp32p4/include/hal/lp_i2s_ll.h +++ b/components/hal/esp32p4/include/hal/lp_i2s_ll.h @@ -23,7 +23,7 @@ extern "C" { #endif -#define I2S_LL_GET_HW(num) (((num) == 0)? (&LP_I2S) : NULL) +#define LP_I2S_LL_GET_HW(num) (((num) == 0)? (&LP_I2S) : NULL) #define LP_I2S_LL_EVENT_RX_DONE_INT (1<<0) #define LP_I2S_LL_EVENT_RX_HUNG_INT_INT (1<<1) @@ -146,7 +146,7 @@ static inline void lp_i2s_ll_clk_source_div_num(int id, uint32_t val) * @param a div a * @param b div b */ -static inline void i2s_ll_tx_set_raw_clk_div(int id, uint32_t a, uint32_t b) +static inline void lp_i2s_ll_tx_set_raw_clk_div(int id, uint32_t a, uint32_t b) { if (b <= a / 2) { LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_yn1 = 0; @@ -297,7 +297,7 @@ static inline void lp_i2s_ll_rx_enable_pdm(lp_i2s_dev_t *hw) /** * @brief Configure LP I2S rx channel bits and bits mode */ -static inline void i2s_ll_rx_set_sample_bit(lp_i2s_dev_t *hw, int chan_bits, int bits_mode) +static inline void lp_i2s_ll_rx_set_sample_bit(lp_i2s_dev_t *hw, int chan_bits, int bits_mode) { hw->rx_conf1.rx_tdm_chan_bits = chan_bits - 1; hw->rx_conf1.rx_bits_mod = bits_mode - 1; diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h index 999f7d3226d8..e88ea9e7a51c 100644 --- a/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h @@ -114,11 +114,11 @@ static inline void mipi_dsi_host_ll_set_timeout_count(dsi_host_dev_t *dev, uint3 { HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, hstx_to_cnt, hs_tx); HAL_FORCE_MODIFY_U32_REG_FIELD(dev->to_cnt_cfg, lprx_to_cnt, lp_rx); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_rd_to_cnt, hs_rd_to_cnt, hs_rd); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_rd_to_cnt, lp_rd_to_cnt, lp_rd); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_wr_to_cnt, hs_wr_to_cnt, hs_wr); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_wr_to_cnt, lp_wr_to_cnt, lp_wr); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->bta_to_cnt, bta_to_cnt, bta); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_rd_timeout_cnt, hs_rd_to_cnt, hs_rd); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_rd_timeout_cnt, lp_rd_to_cnt, lp_rd); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->hs_wr_timeout_cnt, hs_wr_to_cnt, hs_wr); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lp_wr_timeout_cnt, lp_wr_to_cnt, lp_wr); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->bta_timeout_cnt, bta_to_cnt, bta); } /** diff --git a/components/hal/esp32p4/include/hal/mwdt_ll.h b/components/hal/esp32p4/include/hal/mwdt_ll.h index fb0091c50f7f..2879b9916ac4 100644 --- a/components/hal/esp32p4/include/hal/mwdt_ll.h +++ b/components/hal/esp32p4/include/hal/mwdt_ll.h @@ -15,7 +15,7 @@ extern "C" { #include #include -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "soc/hp_sys_clkrst_struct.h" #include "hal/wdt_types.h" diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h index b7cc5558d515..f863acf27718 100644 --- a/components/hal/esp32p4/include/hal/parlio_ll.h +++ b/components/hal/esp32p4/include/hal/parlio_ll.h @@ -636,7 +636,7 @@ static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev) __attribute__((always_inline)) static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value) { - dev->tx_genrl_cfg.tx_idle_value = value; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value); } /** diff --git a/components/hal/esp32p4/include/hal/ppa_ll.h b/components/hal/esp32p4/include/hal/ppa_ll.h index 687e63c5ef2d..60facd94fec5 100644 --- a/components/hal/esp32p4/include/hal/ppa_ll.h +++ b/components/hal/esp32p4/include/hal/ppa_ll.h @@ -660,9 +660,9 @@ static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, color_pi */ static inline void ppa_ll_blend_set_rx_fg_fix_rgb(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb) { - dev->blend_rgb.blend1_rx_b = rgb->b; - dev->blend_rgb.blend1_rx_g = rgb->g; - dev->blend_rgb.blend1_rx_r = rgb->r; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_rgb, blend1_rx_b, rgb->b); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_rgb, blend1_rx_g, rgb->g); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_rgb, blend1_rx_r, rgb->r); } /* @@ -682,13 +682,13 @@ static inline void ppa_ll_blend_set_rx_fg_fix_rgb(ppa_dev_t *dev, color_pixel_rg */ static inline void ppa_ll_blend_configure_rx_bg_ck_range(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb_thres_low, color_pixel_rgb888_data_t *rgb_thres_high) { - dev->ck_bg_low.colorkey_bg_b_low = rgb_thres_low->b; - dev->ck_bg_low.colorkey_bg_g_low = rgb_thres_low->g; - dev->ck_bg_low.colorkey_bg_r_low = rgb_thres_low->r; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_low, colorkey_bg_b_low, rgb_thres_low->b); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_low, colorkey_bg_g_low, rgb_thres_low->g); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_low, colorkey_bg_r_low, rgb_thres_low->r); - dev->ck_bg_high.colorkey_bg_b_high = rgb_thres_high->b; - dev->ck_bg_high.colorkey_bg_g_high = rgb_thres_high->g; - dev->ck_bg_high.colorkey_bg_r_high = rgb_thres_high->r; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_high, colorkey_bg_b_high, rgb_thres_high->b); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_high, colorkey_bg_g_high, rgb_thres_high->g); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_high, colorkey_bg_r_high, rgb_thres_high->r); } /** @@ -700,13 +700,13 @@ static inline void ppa_ll_blend_configure_rx_bg_ck_range(ppa_dev_t *dev, color_p */ static inline void ppa_ll_blend_configure_rx_fg_ck_range(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb_thres_low, color_pixel_rgb888_data_t *rgb_thres_high) { - dev->ck_fg_low.colorkey_fg_b_low = rgb_thres_low->b; - dev->ck_fg_low.colorkey_fg_g_low = rgb_thres_low->g; - dev->ck_fg_low.colorkey_fg_r_low = rgb_thres_low->r; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_low, colorkey_fg_b_low, rgb_thres_low->b); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_low, colorkey_fg_g_low, rgb_thres_low->g); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_low, colorkey_fg_r_low, rgb_thres_low->r); - dev->ck_fg_high.colorkey_fg_b_high = rgb_thres_high->b; - dev->ck_fg_high.colorkey_fg_g_high = rgb_thres_high->g; - dev->ck_fg_high.colorkey_fg_r_high = rgb_thres_high->r; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_high, colorkey_fg_b_high, rgb_thres_high->b); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_high, colorkey_fg_g_high, rgb_thres_high->g); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_high, colorkey_fg_r_high, rgb_thres_high->r); } /** @@ -717,9 +717,9 @@ static inline void ppa_ll_blend_configure_rx_fg_ck_range(ppa_dev_t *dev, color_p */ static inline void ppa_ll_blend_set_ck_default_rgb(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb) { - dev->ck_default.colorkey_default_b = rgb->b; - dev->ck_default.colorkey_default_g = rgb->g; - dev->ck_default.colorkey_default_r = rgb->r; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_default, colorkey_default_b, rgb->b); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_default, colorkey_default_g, rgb->g); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_default, colorkey_default_r, rgb->r); } /** diff --git a/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h b/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h index 438f474d524e..822a4759be4f 100644 --- a/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h +++ b/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -53,7 +53,7 @@ static inline void psram_ctrlr_ll_set_wr_cmd(uint32_t mspi_id, uint32_t cmd_bitl HAL_ASSERT(cmd_bitlen > 0); SPIMEM2.mem_cache_sctrl.mem_cache_sram_usr_wcmd = 1; SPIMEM2.mem_sram_dwr_cmd.mem_cache_sram_usr_wr_cmd_bitlen = cmd_bitlen - 1; - SPIMEM2.mem_sram_dwr_cmd.mem_cache_sram_usr_wr_cmd_value = cmd_val; + HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM2.mem_sram_dwr_cmd, mem_cache_sram_usr_wr_cmd_value, cmd_val); } /** @@ -70,7 +70,7 @@ static inline void psram_ctrlr_ll_set_rd_cmd(uint32_t mspi_id, uint32_t cmd_bitl HAL_ASSERT(cmd_bitlen > 0); SPIMEM2.mem_cache_sctrl.mem_cache_sram_usr_rcmd = 1; SPIMEM2.mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_bitlen = cmd_bitlen - 1; - SPIMEM2.mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_value = cmd_val; + HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM2.mem_sram_drd_cmd, mem_cache_sram_usr_rd_cmd_value, cmd_val); } /** @@ -501,7 +501,7 @@ static inline void psram_ctrlr_ll_enable_skip_page_corner(uint32_t mspi_id, bool } /** - * @brief Enable spliting transactions + * @brief Enable splitting transactions * * @param mspi_id mspi_id * @param en enable / disable diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h index 23de80140b84..2fc156aaa2d6 100644 --- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h @@ -570,7 +570,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr) { dev->cache_fctrl.cache_usr_addr_4byte = 0; - dev->rd_status.wb_mode = extra_addr; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr); } /** diff --git a/components/hal/esp32p4/include/hal/timer_ll.h b/components/hal/esp32p4/include/hal/timer_ll.h index 9dc5f1cef06d..e8c678e88e6e 100644 --- a/components/hal/esp32p4/include/hal/timer_ll.h +++ b/components/hal/esp32p4/include/hal/timer_ll.h @@ -24,6 +24,7 @@ extern "C" { // Get timer group register base address with giving group number #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) +#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER) #define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ (uint32_t[2][2][GPTIMER_ETM_TASK_MAX]){ \ diff --git a/components/hal/esp32p4/include/hal/touch_sensor_ll.h b/components/hal/esp32p4/include/hal/touch_sensor_ll.h index 1bb9286bf3d8..e63fb9d465fa 100644 --- a/components/hal/esp32p4/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32p4/include/hal/touch_sensor_ll.h @@ -695,39 +695,23 @@ static inline void touch_ll_filter_set_debounce(uint32_t dbc_cnt) } /** - * Set the positive noise threshold coefficient. Higher = More noise resistance. - * The benchmark will update to the new value if the touch data is within (benchmark + active_threshold * pos_coeff) + * Set the denoise coefficient regarding the denoise level. * - * - * @param pos_noise_thresh Range [-1 ~ 3]. The coefficient is -1: always; 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; - * -1: the benchmark will always update to the new touch data without considering the positive noise threshold + * @param denoise_lvl Range [0 ~ 4]. 0 = no noise resistance, otherwise higher denoise_lvl means more noise resistance. */ -static inline void touch_ll_filter_set_pos_noise_thresh(int pos_noise_thresh) +static inline void touch_ll_filter_set_denoise_level(int denoise_lvl) { - bool always_update = pos_noise_thresh < 0; + HAL_ASSERT(denoise_lvl >= 0 && denoise_lvl <= 4); + bool always_update = denoise_lvl == 0; + // Map denoise level to actual noise threshold coefficients + uint32_t noise_thresh = denoise_lvl == 4 ? 3 : 3 - denoise_lvl; + LP_ANA_PERI.touch_filter2.touch_bypass_noise_thres = always_update; - LP_ANA_PERI.touch_filter1.touch_noise_thres = always_update ? 0 : pos_noise_thresh; -} + LP_ANA_PERI.touch_filter1.touch_noise_thres = always_update ? 0 : noise_thresh; -/** - * Set the negative noise threshold coefficient. Higher = More noise resistance. - * The benchmark will update to the new value if the touch data is greater than (benchmark - active_threshold * neg_coeff) - * - * @param neg_noise_thresh Range [-2 ~ 3]. The coefficient is -2: never; -1: always; 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; - * -1: the benchmark will always update to the new touch data without considering the negative noise threshold - * -2: the benchmark will never update to the new touch data with negative growth - * @param neg_noise_limit Only when neg_noise_thresh >= 0, if the touch data keep blow the negative threshold for mare than neg_noise_limit ticks, - * the benchmark will still update to the new value. - * It is normally used for updating the benchmark at the first scanning - */ -static inline void touch_ll_filter_set_neg_noise_thresh(int neg_noise_thresh, uint8_t neg_noise_limit) -{ - bool always_update = neg_noise_thresh == -1; - bool stop_update = neg_noise_thresh == -2; - LP_ANA_PERI.touch_filter2.touch_bypass_neg_noise_thres = always_update; - LP_ANA_PERI.touch_filter1.touch_neg_noise_disupdate_baseline_en = stop_update; - LP_ANA_PERI.touch_filter1.touch_neg_noise_thres = always_update || stop_update ? 0 : neg_noise_thresh; - LP_ANA_PERI.touch_filter1.touch_neg_noise_limit = always_update || stop_update ? 5 : neg_noise_limit; // 5 is the default value + LP_ANA_PERI.touch_filter2.touch_bypass_nn_thres = always_update; + LP_ANA_PERI.touch_filter1.touch_nn_thres = always_update ? 0 : noise_thresh; + LP_ANA_PERI.touch_filter1.touch_nn_limit = 5; // 5 is the default value } /** diff --git a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h index f6b13b9a797c..bffbd877426c 100644 --- a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h @@ -13,6 +13,7 @@ #include "soc/hp_sys_clkrst_struct.h" #include "soc/usb_serial_jtag_struct.h" #include "hal/usb_serial_jtag_types.h" +#include "hal/misc.h" #if SOC_USB_SERIAL_JTAG_SUPPORTED @@ -119,7 +120,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); } return i; } @@ -138,7 +139,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); } return i; } diff --git a/components/hal/esp32s2/include/hal/mwdt_ll.h b/components/hal/esp32s2/include/hal/mwdt_ll.h index 5f425bada27a..45952c4384cb 100644 --- a/components/hal/esp32s2/include/hal/mwdt_ll.h +++ b/components/hal/esp32s2/include/hal/mwdt_ll.h @@ -16,7 +16,7 @@ extern "C" { #include #include #include "esp_assert.h" -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "hal/wdt_types.h" #include "hal/assert.h" diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index 67adaefd0b62..efb690877c36 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -19,6 +19,7 @@ #include "esp_types.h" #include "esp_attr.h" #include "esp_bit_defs.h" +#include "esp_compiler.h" #include "soc/spi_periph.h" #include "soc/spi_struct.h" #include "soc/spi_reg.h" @@ -1336,6 +1337,7 @@ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32 __attribute__((always_inline)) static inline uint32_t spi_dma_ll_get_in_suc_eof_desc_addr(spi_dma_dev_t *dma_in, uint32_t channel) { + ESP_STATIC_ANALYZER_CHECK(!dma_in, -1); return dma_in->dma_in_suc_eof_des_addr; } @@ -1437,6 +1439,7 @@ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uin __attribute__((always_inline)) static inline uint32_t spi_dma_ll_get_out_eof_desc_addr(spi_dma_dev_t *dma_out, uint32_t channel) { + ESP_STATIC_ANALYZER_CHECK(!dma_out, -1); return dma_out->dma_out_eof_des_addr; } diff --git a/components/hal/esp32s3/include/hal/mwdt_ll.h b/components/hal/esp32s3/include/hal/mwdt_ll.h index c3cc7b062bce..f91a4ec68254 100644 --- a/components/hal/esp32s3/include/hal/mwdt_ll.h +++ b/components/hal/esp32s3/include/hal/mwdt_ll.h @@ -16,7 +16,7 @@ extern "C" { #include #include #include "hal/misc.h" -#include "soc/timer_periph.h" +#include "soc/wdt_periph.h" #include "soc/timer_group_struct.h" #include "hal/wdt_types.h" #include "hal/assert.h" diff --git a/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h index 8a1addeb11ed..0b6f6d5a3497 100644 --- a/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h @@ -13,6 +13,7 @@ #include "soc/usb_serial_jtag_reg.h" #include "soc/usb_serial_jtag_struct.h" #include "hal/usb_serial_jtag_types.h" +#include "hal/misc.h" /* ----------------------------- Macros & Types ----------------------------- */ @@ -118,7 +119,7 @@ static inline uint32_t usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_ uint32_t i; for (i = 0; i < rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); } return i; } @@ -137,7 +138,7 @@ static inline uint32_t usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint3 uint32_t i; for (i = 0; i < wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); } return i; } diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h index 3bed2c72b35f..dfc5009741b2 100644 --- a/components/hal/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -19,12 +19,10 @@ extern "C" { #endif -#if !CONFIG_IDF_TARGET_ESP32C5 typedef struct { modem_syscon_dev_t *syscon_dev; modem_lpcon_dev_t *lpcon_dev; } modem_clock_hal_context_t; -#endif #if !CONFIG_IDF_TARGET_ESP32H2 //TODO: PM-92 void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); diff --git a/components/hal/test_apps/crypto/main/ecc/test_ecc.c b/components/hal/test_apps/crypto/main/ecc/test_ecc.c index a6bc8c3fdcb5..fcf72814f24a 100644 --- a/components/hal/test_apps/crypto/main/ecc/test_ecc.c +++ b/components/hal/test_apps/crypto/main/ecc/test_ecc.c @@ -46,6 +46,7 @@ static void ecc_enable_and_reset(void) { ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(true); + ecc_ll_power_up(); ecc_ll_reset_register(); } } @@ -54,6 +55,7 @@ static void ecc_disable(void) { ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(false); + ecc_ll_power_down(); } } diff --git a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c index d0777dc817bd..2a7e1d4239bf 100644 --- a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c +++ b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c @@ -34,6 +34,7 @@ static void ecdsa_enable_and_reset(void) ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(true); + ecc_ll_power_up(); ecc_ll_reset_register(); } @@ -55,6 +56,7 @@ static void ecdsa_disable(void) ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(false); + ecc_ll_power_down(); } ECDSA_RCC_ATOMIC() { diff --git a/components/hal/test_apps/hal_i2c/README.md b/components/hal/test_apps/hal_i2c/README.md index e5485b5d19a8..2d5b6a950ae5 100644 --- a/components/hal/test_apps/hal_i2c/README.md +++ b/components/hal/test_apps/hal_i2c/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # HAL I2C test diff --git a/components/hal/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c b/components/hal/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c index 91adc7f3c6d6..7fa64df7884b 100644 --- a/components/hal/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c +++ b/components/hal/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c @@ -92,7 +92,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg) // 2. Set both SCL and SDA open-drain // 3. Set both SCL and SDA pullup enable and pulldown disable. (If you use external pullup, this can be ignored) // 4. io mux function select - // 5. We connect out/in signal. As I2C master, out/in signal is necessary fpr both SCL and SDA according to esp hardware. + // 5. We connect out/in signal. As I2C master, out/in signal is necessary for both SCL and SDA according to esp hardware. // SDA pin configurations if (sda_io != -1) { @@ -101,7 +101,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg) gpio_ll_od_enable(&GPIO, sda_io); gpio_ll_pullup_en(&GPIO, sda_io); gpio_ll_pulldown_dis(&GPIO, sda_io); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[sda_io], PIN_FUNC_GPIO); + gpio_ll_func_sel(&GPIO, sda_io, PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(sda_io, i2c_periph_signal[cfg->i2c_port].sda_out_sig, 0, 0); esp_rom_gpio_connect_in_signal(sda_io, i2c_periph_signal[cfg->i2c_port].sda_in_sig, 0); } @@ -112,7 +112,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg) gpio_ll_od_enable(&GPIO, scl_io); gpio_ll_pullup_en(&GPIO, scl_io); gpio_ll_pulldown_dis(&GPIO, scl_io); - gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[scl_io], PIN_FUNC_GPIO); + gpio_ll_func_sel(&GPIO, scl_io, PIN_FUNC_GPIO); esp_rom_gpio_connect_out_signal(scl_io, i2c_periph_signal[cfg->i2c_port].scl_out_sig, 0, 0); esp_rom_gpio_connect_in_signal(scl_io, i2c_periph_signal[cfg->i2c_port].scl_out_sig, 0); } diff --git a/components/heap/heap_caps_init.c b/components/heap/heap_caps_init.c index a096471e6c67..22e0b2436dd7 100644 --- a/components/heap/heap_caps_init.c +++ b/components/heap/heap_caps_init.c @@ -101,6 +101,7 @@ void heap_caps_init(void) const soc_memory_type_desc_t *type = &soc_memory_types[region->type]; heap_t *heap = &temp_heaps[heap_idx]; if (region->type == -1) { + memset(heap, 0, sizeof(*heap)); continue; } heap_idx++; diff --git a/components/lwip/lwip b/components/lwip/lwip index 4297782bf9e6..aa4f6e780f37 160000 --- a/components/lwip/lwip +++ b/components/lwip/lwip @@ -1 +1 @@ -Subproject commit 4297782bf9e614be1bb8605f30d46af8697fab17 +Subproject commit aa4f6e780f374af5e10730960fe0262a916166d1 diff --git a/components/lwip/port/freertos/include/arch/sys_arch.h b/components/lwip/port/freertos/include/arch/sys_arch.h index f945a14c0c78..408f9e799037 100644 --- a/components/lwip/port/freertos/include/arch/sys_arch.h +++ b/components/lwip/port/freertos/include/arch/sys_arch.h @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * SPDX-FileContributor: 2018-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD */ #ifndef __SYS_ARCH_H__ #define __SYS_ARCH_H__ @@ -24,7 +24,6 @@ typedef TaskHandle_t sys_thread_t; typedef struct sys_mbox_s { QueueHandle_t os_mbox; - void *owner; }* sys_mbox_t; /** This is returned by _fromisr() sys functions to tell the outermost function @@ -38,33 +37,17 @@ void sys_delay_ms(uint32_t ms); #define LWIP_COMPAT_MUTEX 0 #if !LWIP_COMPAT_MUTEX -#define sys_mutex_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) -#define sys_mutex_set_invalid( x ) ( ( *x ) = NULL ) +#define sys_mutex_valid_val(mutex) ((mutex) != NULL) +#define sys_mutex_valid(mutex) (((mutex) != NULL) && sys_mutex_valid_val(*(mutex))) +#define sys_mutex_set_invalid(mutex) ((*(mutex)) = NULL) #endif -#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) +#define sys_mbox_valid(mbox) (*(mbox) != NULL) +#define sys_mbox_set_invalid(mbox) (*(mbox) = NULL) -/* Define the sys_mbox_set_invalid() to empty to support lock-free mbox in ESP LWIP. - * - * The basic idea about the lock-free mbox is that the mbox should always be valid unless - * no socket APIs are using the socket and the socket is closed. ESP LWIP achieves this by - * following two changes to official LWIP: - * 1. Postpone the deallocation of mbox to netconn_free(), in other words, free the mbox when - * no one is using the socket. - * 2. Define the sys_mbox_set_invalid() to empty if the mbox is not actually freed. - - * The second change is necessary. Consider a common scenario: the application task calls - * recv() to receive packets from the socket, the sys_mbox_valid() returns true. Because there - * is no lock for the mbox, the LWIP CORE can call sys_mbox_set_invalid() to set the mbox at - * anytime and the thread-safe issue may happen. - * - * However, if the sys_mbox_set_invalid() is not called after sys_mbox_free(), e.g. in netconn_alloc(), - * we need to initialize the mbox to invalid explicitly since sys_mbox_set_invalid() now is empty. - */ -#define sys_mbox_set_invalid( x ) *x = NULL - -#define sys_sem_valid( x ) ( ( (x) == NULL ) ? pdFALSE : ( ( *x ) == NULL ? pdFALSE : pdTRUE ) ) -#define sys_sem_set_invalid( x ) ( ( *x ) = NULL ) +#define sys_sem_valid_val(sema) ((sema) != NULL) +#define sys_sem_valid(sema) (((sema) != NULL) && sys_sem_valid_val(*(sema))) +#define sys_sem_set_invalid(sema) ((*(sema)) = NULL) void sys_delay_ms(uint32_t ms); sys_sem_t* sys_thread_sem_init(void); diff --git a/components/lwip/port/freertos/sys_arch.c b/components/lwip/port/freertos/sys_arch.c index 0f8cb26376e3..a7a48d08b773 100644 --- a/components/lwip/port/freertos/sys_arch.c +++ b/components/lwip/port/freertos/sys_arch.c @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * SPDX-FileContributor: 2018-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD */ /* lwIP includes. */ @@ -219,10 +219,6 @@ sys_mbox_new(sys_mbox_t *mbox, int size) return ERR_MEM; } -#if ESP_THREAD_SAFE - (*mbox)->owner = NULL; -#endif - LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("new *mbox ok mbox=%p os_mbox=%p\n", *mbox, (*mbox)->os_mbox)); return ERR_OK; } @@ -352,15 +348,6 @@ sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) return 0; } -void -sys_mbox_set_owner(sys_mbox_t *mbox, void* owner) -{ - if (mbox && *mbox) { - (*mbox)->owner = owner; - LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("set mbox=%p owner=%p", *mbox, owner)); - } -} - /** * @brief Delete a mailbox * @@ -444,7 +431,7 @@ sys_jiffies(void) } /** - * @brief Get current time, in miliseconds + * @brief Get current time, in milliseconds * * @return current time */ diff --git a/components/lwip/port/include/lwipopts.h b/components/lwip/port/include/lwipopts.h index e95d6470298d..48feeb16c38e 100644 --- a/components/lwip/port/include/lwipopts.h +++ b/components/lwip/port/include/lwipopts.h @@ -1592,7 +1592,7 @@ static inline uint32_t timeout_from_offered(uint32_t lease, uint32_t min) #define ESP_LWIP 1 #define ESP_LWIP_ARP 1 #define ESP_PER_SOC_TCP_WND 0 -#define ESP_THREAD_SAFE 1 +#define ESP_THREAD_SAFE 1 /* Not used (to be removed in v6.x) */ #define ESP_THREAD_SAFE_DEBUG LWIP_DBG_OFF #define ESP_DHCP 1 #define ESP_DNS 1 @@ -1630,12 +1630,10 @@ static inline uint32_t timeout_from_offered(uint32_t lease, uint32_t min) #if LWIP_NETCONN_SEM_PER_THREAD -#if ESP_THREAD_SAFE #define LWIP_NETCONN_THREAD_SEM_GET() sys_thread_sem_get() #define LWIP_NETCONN_THREAD_SEM_ALLOC() sys_thread_sem_init() #define LWIP_NETCONN_THREAD_SEM_FREE() sys_thread_sem_deinit() #endif -#endif /** * If CONFIG_ALLOC_MEMORY_IN_SPIRAM_FIRST is enabled, Try to diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt index ad0ca7151dab..6791015b81f4 100644 --- a/components/mbedtls/CMakeLists.txt +++ b/components/mbedtls/CMakeLists.txt @@ -293,6 +293,9 @@ endif() foreach(target ${mbedtls_targets}) target_compile_definitions(${target} PUBLIC -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h") + if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10087 + target_compile_options(${target} PRIVATE "-fno-analyzer") + endif() endforeach() if(CONFIG_MBEDTLS_DYNAMIC_BUFFER) diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c index 1808abe9d6c5..928252cc2041 100644 --- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c +++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c @@ -8,7 +8,6 @@ #include "esp_attr.h" #include "esp_cache.h" #include "esp_check.h" -#include "esp_dma_utils.h" #include "esp_err.h" #include "esp_heap_caps.h" #include "esp_intr_alloc.h" @@ -323,13 +322,7 @@ static inline void dma_desc_append(crypto_dma_desc_t **head, crypto_dma_desc_t * static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size) { - void *ptr = NULL; - esp_dma_mem_info_t dma_mem_info = { - .extra_heap_caps = caps, - .dma_alignment_bytes = DMA_DESC_MEM_ALIGN_SIZE, - }; - esp_dma_capable_calloc(num, size, &dma_mem_info, &ptr, actual_size); - return ptr; + return heap_caps_aligned_calloc(DMA_DESC_MEM_ALIGN_SIZE, num, size, caps | MALLOC_CAP_DMA | MALLOC_CAP_8BIT); } static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_dma_desc_num, size_t cache_line_size) diff --git a/components/mbedtls/port/ecc/esp_ecc.c b/components/mbedtls/port/ecc/esp_ecc.c index b9fe0a8871ac..0cb4e72e9cb0 100644 --- a/components/mbedtls/port/ecc/esp_ecc.c +++ b/components/mbedtls/port/ecc/esp_ecc.c @@ -19,6 +19,7 @@ static void esp_ecc_acquire_hardware(void) ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(true); + ecc_ll_power_up(); ecc_ll_reset_register(); } } @@ -27,6 +28,7 @@ static void esp_ecc_release_hardware(void) { ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(false); + ecc_ll_power_down(); } esp_crypto_ecc_lock_release(); diff --git a/components/mbedtls/port/ecdsa/ecdsa_alt.c b/components/mbedtls/port/ecdsa/ecdsa_alt.c index 2e6e0a6dd4ae..e28ee3aada8c 100644 --- a/components/mbedtls/port/ecdsa/ecdsa_alt.c +++ b/components/mbedtls/port/ecdsa/ecdsa_alt.c @@ -35,6 +35,7 @@ static void esp_ecdsa_acquire_hardware(void) ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(true); + ecc_ll_power_up(); ecc_ll_reset_register(); } @@ -57,6 +58,7 @@ static void esp_ecdsa_release_hardware(void) ECC_RCC_ATOMIC() { ecc_ll_enable_bus_clock(false); + ecc_ll_power_down(); } #ifdef SOC_ECDSA_USES_MPI diff --git a/components/mbedtls/port/sha/dma/sha.c b/components/mbedtls/port/sha/dma/sha.c index 14c352a6deb4..f3c6b17a937f 100644 --- a/components/mbedtls/port/sha/dma/sha.c +++ b/components/mbedtls/port/sha/dma/sha.c @@ -29,7 +29,6 @@ #include #include -#include "esp_dma_utils.h" #include "esp_private/esp_crypto_lock_internal.h" #include "esp_private/esp_cache_private.h" #include "esp_log.h" diff --git a/components/newlib/scandir.c b/components/newlib/scandir.c index cf5d85e73874..d4db252cbbbd 100644 --- a/components/newlib/scandir.c +++ b/components/newlib/scandir.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,8 +71,11 @@ int scandir(const char *dirname, struct dirent ***out_dirlist, } free(entries); } + + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") // Ignore intended return of allocated *out_dirlist if (dir_ptr) { closedir(dir_ptr); } return ret; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } diff --git a/components/nvs_flash/CMakeLists.txt b/components/nvs_flash/CMakeLists.txt index 1d03a68a19ce..6e7c6544b448 100644 --- a/components/nvs_flash/CMakeLists.txt +++ b/components/nvs_flash/CMakeLists.txt @@ -41,3 +41,7 @@ else() target_sources(${COMPONENT_LIB} PRIVATE "src/nvs_encrypted_partition.cpp") target_link_libraries(${COMPONENT_LIB} PRIVATE idf::mbedtls) endif() + +if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10088 + target_compile_options(${COMPONENT_LIB} PUBLIC "-fno-analyzer") +endif() diff --git a/components/openthread/src/port/esp_openthread_uart.c b/components/openthread/src/port/esp_openthread_uart.c index fc33cd1f93ba..19070a7a228b 100644 --- a/components/openthread/src/port/esp_openthread_uart.c +++ b/components/openthread/src/port/esp_openthread_uart.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ #include "esp_openthread_common_macro.h" #include "esp_openthread_platform.h" #include "esp_openthread_types.h" +#include "esp_vfs.h" #include "esp_vfs_dev.h" #include "common/logging.hpp" #include "driver/uart.h" @@ -62,6 +63,17 @@ otError otPlatUartSend(const uint8_t *buf, uint16_t buf_length) esp_err_t esp_openthread_uart_init_port(const esp_openthread_uart_config_t *config) { +#ifndef CONFIG_ESP_CONSOLE_UART + // If UART console is used, UART vfs devices should be registered during startup. + // Otherwise we need to register them here. + DIR *uart_dir = opendir("/dev/uart"); + if (!uart_dir) { + // If UART vfs devices are registered, we will failed to open the directory + uart_vfs_dev_register(); + } else { + closedir(uart_dir); + } +#endif ESP_RETURN_ON_ERROR(uart_param_config(config->port, &config->uart_config), OT_PLAT_LOG_TAG, "uart_param_config failed"); ESP_RETURN_ON_ERROR( @@ -91,7 +103,6 @@ esp_err_t esp_openthread_host_cli_usb_init(const esp_openthread_platform_config_ ret = usb_serial_jtag_driver_install((usb_serial_jtag_driver_config_t *)&config->host_config.host_usb_config); usb_serial_jtag_vfs_use_driver(); - uart_vfs_dev_register(); return ret; } #endif diff --git a/components/partition_table/parttool.py b/components/partition_table/parttool.py index 2b6920cb5988..85167f3af140 100755 --- a/components/partition_table/parttool.py +++ b/components/partition_table/parttool.py @@ -3,10 +3,8 @@ # parttool is used to perform partition level operations - reading, # writing, erasing and getting info about the partition. # -# SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 -from __future__ import division, print_function - import argparse import os import re @@ -158,11 +156,11 @@ def read_partition(self, partition_id, output): partition = self.get_partition_info(partition_id) self._call_esptool(['read_flash', str(partition.offset), str(partition.size), output] + self.esptool_read_args) - def write_partition(self, partition_id, input): + def write_partition(self, partition_id, input, ignore_readonly=False): partition = self.get_partition_info(partition_id) - if partition.readonly: - raise Exception(f'"{partition.name}" partition is read-only') + if partition.readonly and not ignore_readonly: + raise SystemExit(f'"{partition.name}" partition is read-only, (use the --ignore-readonly flag to skip it)') self.erase_partition(partition_id) @@ -175,8 +173,8 @@ def write_partition(self, partition_id, input): self._call_esptool(['write_flash', str(partition.offset), input] + self.esptool_write_args) -def _write_partition(target, partition_id, input): - target.write_partition(partition_id, input) +def _write_partition(target, partition_id, input, ignore_readonly=False): + target.write_partition(partition_id, input, ignore_readonly) partition = target.get_partition_info(partition_id) status("Written contents of file '{}' at offset 0x{:x}".format(input, partition.offset)) @@ -268,6 +266,7 @@ def main(): write_part_subparser = subparsers.add_parser('write_partition', help='write contents of a binary file to partition on device', parents=[partition_selection_parser]) write_part_subparser.add_argument('--input', help='file whose contents are to be written to the partition offset') + write_part_subparser.add_argument('--ignore-readonly', help='Ignore read-only attribute', action='store_true') subparsers.add_parser('erase_partition', help='erase the contents of a partition on the device', parents=[partition_selection_parser]) @@ -336,7 +335,7 @@ def main(): parttool_ops = { 'erase_partition': (_erase_partition, []), 'read_partition': (_read_partition, ['output']), - 'write_partition': (_write_partition, ['input']), + 'write_partition': (_write_partition, ['input', 'ignore_readonly']), 'get_partition_info': (_get_partition_info, ['info']) } diff --git a/components/pthread/pthread.c b/components/pthread/pthread.c index 3fbda1219572..c0a6f10db677 100644 --- a/components/pthread/pthread.c +++ b/components/pthread/pthread.c @@ -25,6 +25,7 @@ #include "pthread_internal.h" #include "esp_pthread.h" +#include "esp_compiler.h" #include "esp_log.h" const static char *TAG = "pthread"; @@ -165,7 +166,10 @@ esp_err_t esp_pthread_set_cfg(const esp_pthread_cfg_t *cfg) *p = *cfg; p->stack_alloc_caps = heap_caps; pthread_setspecific(s_pthread_cfg_key, p); + + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-malloc-leak") // ignore leak of 'p' return 0; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-malloc-leak") } esp_err_t esp_pthread_get_cfg(esp_pthread_cfg_t *p) diff --git a/components/sdmmc/sdmmc_io.c b/components/sdmmc/sdmmc_io.c index 86f471b8ac21..ae0225b260fd 100644 --- a/components/sdmmc/sdmmc_io.c +++ b/components/sdmmc/sdmmc_io.c @@ -327,7 +327,9 @@ esp_err_t sdmmc_io_rw_extended(sdmmc_card_t* card, int func, return ESP_ERR_INVALID_ARG; } memset(card->host.dma_aligned_buffer, 0xcc, SDMMC_IO_BLOCK_SIZE); - memcpy(card->host.dma_aligned_buffer, datap, datalen); + if (arg & SD_ARG_CMD53_WRITE) { + memcpy(card->host.dma_aligned_buffer, datap, datalen); + } cmd.data = card->host.dma_aligned_buffer; cmd.buflen = SDMMC_IO_BLOCK_SIZE; } @@ -362,7 +364,8 @@ esp_err_t sdmmc_io_rw_extended(sdmmc_card_t* card, int func, err = sdmmc_send_cmd(card, &cmd); - if (datalen > 0 && cmd.data == card->host.dma_aligned_buffer) { + if (arg & SD_ARG_CMD53_READ && + datalen > 0 && cmd.data == card->host.dma_aligned_buffer) { assert(datalen <= SDMMC_IO_BLOCK_SIZE); memcpy(datap, card->host.dma_aligned_buffer, datalen); } diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 54b293aeea28..42f8128835f4 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -121,6 +121,10 @@ if(CONFIG_SOC_TWAI_SUPPORTED) list(APPEND srcs "${target_folder}/twai_periph.c") endif() +if(CONFIG_SOC_WDT_SUPPORTED) + list(APPEND srcs "${target_folder}/wdt_periph.c") +endif() + if(CONFIG_SOC_IEEE802154_SUPPORTED) if(NOT target STREQUAL "esp32h4") list(APPEND srcs "${target_folder}/ieee802154_periph.c") diff --git a/components/soc/esp32/wdt_periph.c b/components/soc/esp32/wdt_periph.c new file mode 100644 index 000000000000..58f1349d3d24 --- /dev/null +++ b/components/soc/esp32/wdt_periph.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/wdt_periph.h" diff --git a/components/soc/esp32c2/wdt_periph.c b/components/soc/esp32c2/wdt_periph.c new file mode 100644 index 000000000000..58f1349d3d24 --- /dev/null +++ b/components/soc/esp32c2/wdt_periph.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/wdt_periph.h" diff --git a/components/soc/esp32c3/wdt_periph.c b/components/soc/esp32c3/wdt_periph.c new file mode 100644 index 000000000000..58f1349d3d24 --- /dev/null +++ b/components/soc/esp32c3/wdt_periph.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/wdt_periph.h" diff --git a/components/soc/esp32c5/i2c_periph.c b/components/soc/esp32c5/i2c_periph.c new file mode 100644 index 000000000000..4e87d0c44fcb --- /dev/null +++ b/components/soc/esp32c5/i2c_periph.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2c_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { + { + .sda_out_sig = I2CEXT0_SDA_OUT_IDX, + .sda_in_sig = I2CEXT0_SDA_IN_IDX, + .scl_out_sig = I2CEXT0_SCL_OUT_IDX, + .scl_in_sig = I2CEXT0_SCL_IN_IDX, + .irq = ETS_I2C_EXT0_INTR_SOURCE, + .module = PERIPH_I2C0_MODULE, + }, +}; diff --git a/components/soc/esp32c5/include/modem/modem_lpcon_struct.h b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h index cb8e4ff8a594..8ce1a6ab1513 100644 --- a/components/soc/esp32c5/include/modem/modem_lpcon_struct.h +++ b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h @@ -13,7 +13,7 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t reg_clk_en : 1; + uint32_t clk_en : 1; uint32_t reserved1 : 1; uint32_t reserved2 : 30; }; @@ -21,58 +21,58 @@ typedef volatile struct { } test_conf; union { struct { - uint32_t reg_clk_lp_timer_sel_osc_slow : 1; - uint32_t reg_clk_lp_timer_sel_osc_fast : 1; - uint32_t reg_clk_lp_timer_sel_xtal : 1; - uint32_t reg_clk_lp_timer_sel_xtal32k : 1; - uint32_t reg_clk_lp_timer_div_num : 12; + uint32_t clk_lp_timer_sel_osc_slow : 1; + uint32_t clk_lp_timer_sel_osc_fast : 1; + uint32_t clk_lp_timer_sel_xtal : 1; + uint32_t clk_lp_timer_sel_xtal32k : 1; + uint32_t clk_lp_timer_div_num : 12; uint32_t reserved16 : 16; }; uint32_t val; } lp_timer_conf; union { struct { - uint32_t reg_clk_coex_lp_sel_osc_slow : 1; - uint32_t reg_clk_coex_lp_sel_osc_fast : 1; - uint32_t reg_clk_coex_lp_sel_xtal : 1; - uint32_t reg_clk_coex_lp_sel_xtal32k : 1; - uint32_t reg_clk_coex_lp_div_num : 12; + uint32_t clk_coex_lp_sel_osc_slow : 1; + uint32_t clk_coex_lp_sel_osc_fast : 1; + uint32_t clk_coex_lp_sel_xtal : 1; + uint32_t clk_coex_lp_sel_xtal32k : 1; + uint32_t clk_coex_lp_div_num : 12; uint32_t reserved16 : 16; }; uint32_t val; } coex_lp_clk_conf; union { struct { - uint32_t reg_clk_wifipwr_lp_sel_osc_slow: 1; - uint32_t reg_clk_wifipwr_lp_sel_osc_fast: 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal : 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal32k: 1; - uint32_t reg_clk_wifipwr_lp_div_num : 12; + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal : 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num : 12; uint32_t reserved16 : 16; }; uint32_t val; } wifi_lp_clk_conf; union { struct { - uint32_t reg_clk_modem_aon_force : 2; - uint32_t reg_modem_pwr_clk_src_fo : 1; + uint32_t clk_modem_aon_force : 2; + uint32_t modem_pwr_clk_src_fo : 1; uint32_t reserved3 : 29; }; uint32_t val; } modem_src_clk_conf; union { struct { - uint32_t reg_clk_modem_32k_sel : 2; - uint32_t reserved2 : 30; + uint32_t clk_modem_32k_sel : 2; + uint32_t reserved2 : 30; }; uint32_t val; } modem_32k_clk_conf; union { struct { - uint32_t reg_clk_wifipwr_en : 1; - uint32_t reg_clk_coex_en : 1; - uint32_t reg_clk_i2c_mst_en : 1; - uint32_t reg_clk_lp_timer_en : 1; + uint32_t clk_wifipwr_en : 1; + uint32_t clk_coex_en : 1; + uint32_t clk_i2c_mst_en : 1; + uint32_t clk_lp_timer_en : 1; uint32_t reserved4 : 1; uint32_t reserved5 : 1; uint32_t reserved6 : 1; @@ -106,11 +106,11 @@ typedef volatile struct { } clk_conf; union { struct { - uint32_t reg_clk_wifipwr_fo : 1; - uint32_t reg_clk_coex_fo : 1; - uint32_t reg_clk_i2c_mst_fo : 1; - uint32_t reg_clk_lp_timer_fo : 1; - uint32_t reg_clk_fe_mem_fo : 1; + uint32_t clk_wifipwr_fo : 1; + uint32_t clk_coex_fo : 1; + uint32_t clk_i2c_mst_fo : 1; + uint32_t clk_lp_timer_fo : 1; + uint32_t clk_fe_mem_fo : 1; uint32_t reserved5 : 1; uint32_t reserved6 : 1; uint32_t reserved7 : 1; @@ -144,19 +144,19 @@ typedef volatile struct { union { struct { uint32_t reserved0 : 16; - uint32_t reg_clk_wifipwr_st_map : 4; - uint32_t reg_clk_coex_st_map : 4; - uint32_t reg_clk_i2c_mst_st_map : 4; - uint32_t reg_clk_lp_apb_st_map : 4; + uint32_t clk_wifipwr_st_map : 4; + uint32_t clk_coex_st_map : 4; + uint32_t clk_i2c_mst_st_map : 4; + uint32_t clk_lp_apb_st_map : 4; }; uint32_t val; } clk_conf_power_st; union { struct { - uint32_t reg_rst_wifipwr : 1; - uint32_t reg_rst_coex : 1; - uint32_t reg_rst_i2c_mst : 1; - uint32_t reg_rst_lp_timer : 1; + uint32_t rst_wifipwr : 1; + uint32_t rst_coex : 1; + uint32_t rst_i2c_mst : 1; + uint32_t rst_lp_timer : 1; uint32_t reserved4 : 1; uint32_t reserved5 : 1; uint32_t reserved6 : 1; @@ -190,33 +190,33 @@ typedef volatile struct { } rst_conf; union { struct { - uint32_t reg_modem_pwr_tick_target : 6; + uint32_t modem_pwr_tick_target : 6; uint32_t reserved6 : 26; }; uint32_t val; } tick_conf; union { struct { - uint32_t reg_dc_mem_mode : 3; - uint32_t reg_dc_mem_force : 1; - uint32_t reg_agc_mem_mode : 3; - uint32_t reg_agc_mem_force : 1; - uint32_t reg_pbus_mem_mode : 3; - uint32_t reg_pbus_mem_force : 1; - uint32_t reg_bc_mem_mode : 3; - uint32_t reg_bc_mem_force : 1; - uint32_t reg_i2c_mst_mem_mode : 3; - uint32_t reg_i2c_mst_mem_force : 1; - uint32_t reg_chan_freq_mem_mode : 3; - uint32_t reg_chan_freq_mem_force : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; + uint32_t dc_mem_mode : 3; + uint32_t dc_mem_force : 1; + uint32_t agc_mem_mode : 3; + uint32_t agc_mem_force : 1; + uint32_t pbus_mem_mode : 3; + uint32_t pbus_mem_force : 1; + uint32_t bc_mem_mode : 3; + uint32_t bc_mem_force : 1; + uint32_t i2c_mst_mem_mode : 3; + uint32_t i2c_mst_mem_force : 1; + uint32_t chan_freq_mem_mode : 3; + uint32_t chan_freq_mem_force : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; }; uint32_t val; } mem_conf; @@ -224,16 +224,16 @@ typedef volatile struct { uint32_t mem_rf2_aux_ctrl; union { struct { - uint32_t reg_chan_freq_mem_en : 1; - uint32_t reg_pbus_mem_en : 1; - uint32_t reg_agc_mem_en : 1; + uint32_t chan_freq_mem_en : 1; + uint32_t pbus_mem_en : 1; + uint32_t agc_mem_en : 1; uint32_t reserved3 : 29; }; uint32_t val; } apb_mem_sel; union { struct { - uint32_t reg_date : 28; + uint32_t date : 28; uint32_t reserved28 : 4; }; uint32_t val; diff --git a/components/soc/esp32c5/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/include/modem/modem_syscon_struct.h index b7086ad37a2e..3e42205e609d 100644 --- a/components/soc/esp32c5/include/modem/modem_syscon_struct.h +++ b/components/soc/esp32c5/include/modem/modem_syscon_struct.h @@ -13,76 +13,76 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t reg_clk_en : 1; - uint32_t reg_modem_ant_force_sel_bt : 1; - uint32_t reg_modem_ant_force_sel_wifi : 1; - uint32_t reg_fpga_debug_clkswitch : 1; - uint32_t reg_fpga_debug_clk80 : 1; - uint32_t reg_fpga_debug_clk40 : 1; - uint32_t reg_fpga_debug_clk20 : 1; - uint32_t reg_fpga_debug_clk10 : 1; - uint32_t reg_modem_mem_mode_force : 1; - uint32_t reserved9 : 23; + uint32_t clk_en : 1; + uint32_t modem_ant_force_sel_bt : 1; + uint32_t modem_ant_force_sel_wifi : 1; + uint32_t fpga_debug_clkswitch : 1; + uint32_t fpga_debug_clk80 : 1; + uint32_t fpga_debug_clk40 : 1; + uint32_t fpga_debug_clk20 : 1; + uint32_t fpga_debug_clk10 : 1; + uint32_t modem_mem_mode_force : 1; + uint32_t reserved9 : 23; }; uint32_t val; } test_conf; union { struct { - uint32_t reg_pwdet_sar_clock_ena : 1; - uint32_t reg_pwdet_clk_div_num : 8; - uint32_t reg_clk_tx_dac_inv_ena : 1; - uint32_t reg_clk_rx_adc_inv_ena : 1; - uint32_t reg_clk_pwdet_adc_inv_ena : 1; - uint32_t reg_clk_i2c_mst_sel_160m : 1; - uint32_t reserved13 : 8; - uint32_t reg_clk_data_dump_mux : 1; - uint32_t reg_clk_etm_en : 1; - uint32_t reg_clk_zb_apb_en : 1; - uint32_t reg_clk_zbmac_en : 1; - uint32_t reg_clk_modem_sec_ecb_en : 1; - uint32_t reg_clk_modem_sec_ccm_en : 1; - uint32_t reg_clk_modem_sec_bah_en : 1; - uint32_t reg_clk_modem_sec_apb_en : 1; - uint32_t reg_clk_modem_sec_en : 1; - uint32_t reg_clk_ble_timer_en : 1; - uint32_t reg_clk_data_dump_en : 1; + uint32_t pwdet_sar_clock_ena : 1; + uint32_t pwdet_clk_div_num : 8; + uint32_t clk_tx_dac_inv_ena : 1; + uint32_t clk_rx_adc_inv_ena : 1; + uint32_t clk_pwdet_adc_inv_ena : 1; + uint32_t clk_i2c_mst_sel_160m : 1; + uint32_t reserved13 : 8; + uint32_t clk_data_dump_mux : 1; + uint32_t clk_etm_en : 1; + uint32_t clk_zb_apb_en : 1; + uint32_t clk_zbmac_en : 1; + uint32_t clk_modem_sec_ecb_en : 1; + uint32_t clk_modem_sec_ccm_en : 1; + uint32_t clk_modem_sec_bah_en : 1; + uint32_t clk_modem_sec_apb_en : 1; + uint32_t clk_modem_sec_en : 1; + uint32_t clk_ble_timer_en : 1; + uint32_t clk_data_dump_en : 1; }; uint32_t val; } clk_conf; union { struct { - uint32_t reg_clk_wifibb_fo : 1; - uint32_t reg_clk_wifimac_fo : 1; - uint32_t reg_clk_wifi_apb_fo : 1; - uint32_t reg_clk_fe_fo : 1; - uint32_t reg_clk_fe_apb_fo : 1; - uint32_t reg_clk_btbb_fo : 1; - uint32_t reg_clk_btmac_fo : 1; - uint32_t reg_clk_bt_apb_fo : 1; - uint32_t reg_clk_zbmac_fo : 1; - uint32_t reg_clk_zbmac_apb_fo : 1; + uint32_t clk_wifibb_fo : 1; + uint32_t clk_wifimac_fo : 1; + uint32_t clk_wifi_apb_fo : 1; + uint32_t clk_fe_fo : 1; + uint32_t clk_fe_apb_fo : 1; + uint32_t clk_btbb_fo : 1; + uint32_t clk_btmac_fo : 1; + uint32_t clk_bt_apb_fo : 1; + uint32_t clk_zbmac_fo : 1; + uint32_t clk_zbmac_apb_fo : 1; uint32_t reserved10 : 13; uint32_t reserved23 : 1; uint32_t reserved24 : 1; uint32_t reserved25 : 1; uint32_t reserved26 : 1; uint32_t reserved27 : 1; - uint32_t reg_clk_etm_fo : 1; - uint32_t reg_clk_modem_sec_fo : 1; - uint32_t reg_clk_ble_timer_fo : 1; - uint32_t reg_clk_data_dump_fo : 1; + uint32_t clk_etm_fo : 1; + uint32_t clk_modem_sec_fo : 1; + uint32_t clk_ble_timer_fo : 1; + uint32_t clk_data_dump_fo : 1; }; uint32_t val; } clk_conf_force_on; union { struct { uint32_t reserved0 : 8; - uint32_t reg_clk_zb_st_map : 4; - uint32_t reg_clk_fe_st_map : 4; - uint32_t reg_clk_bt_st_map : 4; - uint32_t reg_clk_wifi_st_map : 4; - uint32_t reg_clk_modem_peri_st_map : 4; - uint32_t reg_clk_modem_apb_st_map : 4; + uint32_t clk_zb_st_map : 4; + uint32_t clk_fe_st_map : 4; + uint32_t clk_bt_st_map : 4; + uint32_t clk_wifi_st_map : 4; + uint32_t clk_modem_peri_st_map : 4; + uint32_t clk_modem_apb_st_map : 4; }; uint32_t val; } clk_conf_power_st; @@ -96,58 +96,58 @@ typedef volatile struct { uint32_t reserved5 : 1; uint32_t reserved6 : 1; uint32_t reserved7 : 1; - uint32_t reg_rst_wifibb : 1; - uint32_t reg_rst_wifimac : 1; - uint32_t reg_rst_fe_pwdet_adc : 1; - uint32_t reg_rst_fe_dac : 1; - uint32_t reg_rst_fe_adc : 1; - uint32_t reg_rst_fe_ahb : 1; - uint32_t reg_rst_fe : 1; - uint32_t reg_rst_btmac_apb : 1; - uint32_t reg_rst_btmac : 1; - uint32_t reg_rst_btbb_apb : 1; - uint32_t reg_rst_btbb : 1; + uint32_t rst_wifibb : 1; + uint32_t rst_wifimac : 1; + uint32_t rst_fe_pwdet_adc : 1; + uint32_t rst_fe_dac : 1; + uint32_t rst_fe_adc : 1; + uint32_t rst_fe_ahb : 1; + uint32_t rst_fe : 1; + uint32_t rst_btmac_apb : 1; + uint32_t rst_btmac : 1; + uint32_t rst_btbb_apb : 1; + uint32_t rst_btbb : 1; uint32_t reserved19 : 3; - uint32_t reg_rst_etm : 1; - uint32_t reg_rst_zbmac_apb : 1; - uint32_t reg_rst_zbmac : 1; - uint32_t reg_rst_modem_ecb : 1; - uint32_t reg_rst_modem_ccm : 1; - uint32_t reg_rst_modem_bah : 1; + uint32_t rst_etm : 1; + uint32_t rst_zbmac_apb : 1; + uint32_t rst_zbmac : 1; + uint32_t rst_modem_ecb : 1; + uint32_t rst_modem_ccm : 1; + uint32_t rst_modem_bah : 1; uint32_t reserved28 : 1; - uint32_t reg_rst_modem_sec : 1; - uint32_t reg_rst_ble_timer : 1; - uint32_t reg_rst_data_dump : 1; + uint32_t rst_modem_sec : 1; + uint32_t rst_ble_timer : 1; + uint32_t rst_data_dump : 1; }; uint32_t val; } modem_rst_conf; union { struct { - uint32_t reg_clk_wifibb_22m_en : 1; - uint32_t reg_clk_wifibb_40m_en : 1; - uint32_t reg_clk_wifibb_44m_en : 1; - uint32_t reg_clk_wifibb_80m_en : 1; - uint32_t reg_clk_wifibb_40x_en : 1; - uint32_t reg_clk_wifibb_80x_en : 1; - uint32_t reg_clk_wifibb_40x1_en : 1; - uint32_t reg_clk_wifibb_80x1_en : 1; - uint32_t reg_clk_wifibb_160x1_en : 1; - uint32_t reg_clk_wifimac_en : 1; - uint32_t reg_clk_wifi_apb_en : 1; - uint32_t reg_clk_fe_20m_en : 1; - uint32_t reg_clk_fe_40m_en : 1; - uint32_t reg_clk_fe_80m_en : 1; - uint32_t reg_clk_fe_160m_en : 1; - uint32_t reg_clk_fe_apb_en : 1; - uint32_t reg_clk_bt_apb_en : 1; - uint32_t reg_clk_btbb_en : 1; - uint32_t reg_clk_btmac_en : 1; - uint32_t reg_clk_fe_pwdet_adc_en : 1; - uint32_t reg_clk_fe_adc_en : 1; - uint32_t reg_clk_fe_dac_en : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 8; + uint32_t clk_wifibb_22m_en : 1; + uint32_t clk_wifibb_40m_en : 1; + uint32_t clk_wifibb_44m_en : 1; + uint32_t clk_wifibb_80m_en : 1; + uint32_t clk_wifibb_40x_en : 1; + uint32_t clk_wifibb_80x_en : 1; + uint32_t clk_wifibb_40x1_en : 1; + uint32_t clk_wifibb_80x1_en : 1; + uint32_t clk_wifibb_160x1_en : 1; + uint32_t clk_wifimac_en : 1; + uint32_t clk_wifi_apb_en : 1; + uint32_t clk_fe_20m_en : 1; + uint32_t clk_fe_40m_en : 1; + uint32_t clk_fe_80m_en : 1; + uint32_t clk_fe_160m_en : 1; + uint32_t clk_fe_apb_en : 1; + uint32_t clk_bt_apb_en : 1; + uint32_t clk_btbb_en : 1; + uint32_t clk_btmac_en : 1; + uint32_t clk_fe_pwdet_adc_en : 1; + uint32_t clk_fe_adc_en : 1; + uint32_t clk_fe_dac_en : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 8; }; uint32_t val; } clk_conf1; @@ -156,7 +156,7 @@ typedef volatile struct { uint32_t mem_rf2_conf; union { struct { - uint32_t reg_date : 28; + uint32_t date : 28; uint32_t reserved28 : 4; }; uint32_t val; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index e36ec0f749b1..a9d6abc8e664 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -27,14 +27,30 @@ config SOC_MCPWM_SUPPORTED bool default y +config SOC_PARLIO_SUPPORTED + bool + default y + config SOC_ASYNC_MEMCPY_SUPPORTED bool default y +config SOC_USB_SERIAL_JTAG_SUPPORTED + bool + default y + config SOC_SUPPORTS_SECURE_DL_MODE bool default y +config SOC_LP_CORE_SUPPORTED + bool + default y + +config SOC_ULP_SUPPORTED + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y @@ -67,6 +83,10 @@ config SOC_LEDC_SUPPORTED bool default y +config SOC_I2C_SUPPORTED + bool + default y + config SOC_SYSTIMER_SUPPORTED bool default y @@ -111,6 +131,14 @@ config SOC_SECURE_BOOT_SUPPORTED bool default y +config SOC_LP_TIMER_SUPPORTED + bool + default y + +config SOC_LP_PERIPHERALS_SUPPORTED + bool + default y + config SOC_SPI_FLASH_SUPPORTED bool default y @@ -119,6 +147,10 @@ config SOC_ECDSA_SUPPORTED bool default y +config SOC_MODEM_CLOCK_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y @@ -287,6 +319,50 @@ config SOC_HP_I2C_NUM int default 1 +config SOC_I2C_FIFO_LEN + int + default 32 + +config SOC_I2C_CMD_REG_NUM + int + default 8 + +config SOC_I2C_SUPPORT_SLAVE + bool + default y + +config SOC_I2C_SUPPORT_HW_FSM_RST + bool + default y + +config SOC_I2C_SUPPORT_XTAL + bool + default y + +config SOC_I2C_SUPPORT_RTC + bool + default y + +config SOC_I2C_SUPPORT_10BIT_ADDR + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_BROADCAST + bool + default y + +config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS + bool + default y + +config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH + bool + default y + config SOC_I2S_NUM int default 1 @@ -511,6 +587,46 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP bool default y +config SOC_PARLIO_GROUPS + int + default 1 + +config SOC_PARLIO_TX_UNITS_PER_GROUP + int + default 1 + +config SOC_PARLIO_RX_UNITS_PER_GROUP + int + default 1 + +config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH + int + default 8 + +config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH + int + default 8 + +config SOC_PARLIO_TX_CLK_SUPPORT_GATING + bool + default y + +config SOC_PARLIO_RX_CLK_SUPPORT_GATING + bool + default y + +config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT + bool + default y + +config SOC_PARLIO_TRANS_BIT_ALIGN + bool + default y + +config SOC_PARLIO_TX_SIZE_BY_DMA + bool + default y + config SOC_MPI_MEM_BLOCKS_NUM int default 4 @@ -643,6 +759,14 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE bool default y +config SOC_LP_TIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_LP_TIMER_BIT_WIDTH_HI + int + default 16 + config SOC_TIMER_GROUPS int default 2 @@ -719,10 +843,26 @@ config SOC_LP_UART_FIFO_LEN int default 16 +config SOC_UART_BITRATE_MAX + int + default 5000000 + config SOC_UART_SUPPORT_XTAL_CLK bool default y +config SOC_UART_SUPPORT_WAKEUP_INT + bool + default y + +config SOC_UART_HAS_LP_UART + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + config SOC_PM_SUPPORT_MODEM_PD bool default y @@ -774,3 +914,7 @@ config SOC_CLK_RC32K_SUPPORTED config SOC_RCC_IS_INDEPENDENT bool default y + +config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR + bool + default y diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index e0c3c6f16636..ee7437c0e57b 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -520,10 +520,16 @@ typedef enum { /** * @brief PARLIO clock source */ -typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6) - PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ - PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ +typedef enum { + PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ + PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */ +#if SOC_CLK_TREE_SUPPORTED // TODO: [ESP32C5] IDF-8642 remove when clock tree is supported + PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ +#else + PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +#endif } soc_periph_parlio_clk_src_t; //////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/include/soc/i2c_struct.h b/components/soc/esp32c5/include/soc/i2c_struct.h index 81044ebc1970..438c849ee478 100644 --- a/components/soc/esp32c5/include/soc/i2c_struct.h +++ b/components/soc/esp32c5/include/soc/i2c_struct.h @@ -992,180 +992,37 @@ typedef union { uint32_t val; } i2c_int_status_reg_t; - /** Group: Command registers */ -/** Type of comd0 register - * I2C command register 0 +/** Type of comd register + * I2C command register n */ typedef union { struct { /** command0 : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. \\ - * It consists of three parts:\\ - * op_code is the command\\ - * 1: WRITE\\ - * 2: STOP\\ - * 3: READ\\ - * 4: END\\ - * 6: RSTART\\ - * Byte_num represents the number of bytes that need to be sent or received.\\ + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure link for more information. - * \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" + * structure for more information. */ - uint32_t command0:14; + uint32_t command:14; uint32_t reserved_14:17; - /** command0_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + /** command_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done */ - uint32_t command0_done:1; + uint32_t command_done:1; }; uint32_t val; -} i2c_comd0_reg_t; - -/** Type of comd1 register - * I2C command register 1 - */ -typedef union { - struct { - /** command1 : R/W; bitpos: [13:0]; default: 0; - * Configures command 1.\\ - * See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command1:14; - uint32_t reserved_14:17; - /** command1_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 1 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ - */ - uint32_t command1_done:1; - }; - uint32_t val; -} i2c_comd1_reg_t; - -/** Type of comd2 register - * I2C command register 2 - */ -typedef union { - struct { - /** command2 : R/W; bitpos: [13:0]; default: 0; - * Configures command 2. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command2:14; - uint32_t reserved_14:17; - /** command2_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 2 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ - */ - uint32_t command2_done:1; - }; - uint32_t val; -} i2c_comd2_reg_t; - -/** Type of comd3 register - * I2C command register 3 - */ -typedef union { - struct { - /** command3 : R/W; bitpos: [13:0]; default: 0; - * Configures command 3. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command3:14; - uint32_t reserved_14:17; - /** command3_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 3 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ - */ - uint32_t command3_done:1; - }; - uint32_t val; -} i2c_comd3_reg_t; - -/** Type of comd4 register - * I2C command register 4 - */ -typedef union { - struct { - /** command4 : R/W; bitpos: [13:0]; default: 0; - * Configures command 4. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command4:14; - uint32_t reserved_14:17; - /** command4_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 4 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ - */ - uint32_t command4_done:1; - }; - uint32_t val; -} i2c_comd4_reg_t; - -/** Type of comd5 register - * I2C command register 5 - */ -typedef union { - struct { - /** command5 : R/W; bitpos: [13:0]; default: 0; - * Configures command 5. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command5:14; - uint32_t reserved_14:17; - /** command5_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 5 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ - */ - uint32_t command5_done:1; - }; - uint32_t val; -} i2c_comd5_reg_t; - -/** Type of comd6 register - * I2C command register 6 - */ -typedef union { - struct { - /** command6 : R/W; bitpos: [13:0]; default: 0; - * Configures command 6. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command6:14; - uint32_t reserved_14:17; - /** command6_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 6 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ - */ - uint32_t command6_done:1; - }; - uint32_t val; -} i2c_comd6_reg_t; - -/** Type of comd7 register - * I2C command register 7 - */ -typedef union { - struct { - /** command7 : R/W; bitpos: [13:0]; default: 0; - * Configures command 7. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command7:14; - uint32_t reserved_14:17; - /** command7_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 7 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ - */ - uint32_t command7_done:1; - }; - uint32_t val; -} i2c_comd7_reg_t; - +} i2c_comd_reg_t; /** Group: Version register */ /** Type of date register @@ -1233,14 +1090,7 @@ typedef struct { volatile i2c_scl_stop_setup_reg_t scl_stop_setup; volatile i2c_filter_cfg_reg_t filter_cfg; volatile i2c_clk_conf_reg_t clk_conf; - volatile i2c_comd0_reg_t comd0; - volatile i2c_comd1_reg_t comd1; - volatile i2c_comd2_reg_t comd2; - volatile i2c_comd3_reg_t comd3; - volatile i2c_comd4_reg_t comd4; - volatile i2c_comd5_reg_t comd5; - volatile i2c_comd6_reg_t comd6; - volatile i2c_comd7_reg_t comd7; + volatile i2c_comd_reg_t command[8]; volatile i2c_scl_st_time_out_reg_t scl_st_time_out; volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; volatile i2c_scl_sp_conf_reg_t scl_sp_conf; @@ -1248,15 +1098,14 @@ typedef struct { uint32_t reserved_088[28]; volatile i2c_date_reg_t date; uint32_t reserved_0fc; - volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; - uint32_t reserved_104[31]; - volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; + volatile uint32_t txfifo_mem[32]; + volatile uint32_t rxfifo_mem[32]; } i2c_dev_t; -extern i2c_dev_t I2C; +extern i2c_dev_t I2C0; #ifndef __cplusplus -_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/include/soc/lp_i2c_reg.h index fc23269e71d7..d529feb426b1 100644 --- a/components/soc/esp32c5/include/soc/lp_i2c_reg.h +++ b/components/soc/esp32c5/include/soc/lp_i2c_reg.h @@ -11,1197 +11,1197 @@ extern "C" { #endif -/** I2C_SCL_LOW_PERIOD_REG register +/** LP_I2C_SCL_LOW_PERIOD_REG register * Configures the low level width of the SCL * Clock */ -#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) -/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) +/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL remains low in master mode, in * I2C module clock cycles. */ -#define I2C_SCL_LOW_PERIOD 0x000001FFU -#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) -#define I2C_SCL_LOW_PERIOD_V 0x000001FFU -#define I2C_SCL_LOW_PERIOD_S 0 +#define LP_I2C_SCL_LOW_PERIOD 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) +#define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_S 0 -/** I2C_CTR_REG register +/** LP_I2C_CTR_REG register * Transmission setting */ -#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) -/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; +#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) +/** LP_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; * 1: direct output, 0: open drain output. */ -#define I2C_SDA_FORCE_OUT (BIT(0)) -#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) -#define I2C_SDA_FORCE_OUT_V 0x00000001U -#define I2C_SDA_FORCE_OUT_S 0 -/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; +#define LP_I2C_SDA_FORCE_OUT (BIT(0)) +#define LP_I2C_SDA_FORCE_OUT_M (LP_I2C_SDA_FORCE_OUT_V << LP_I2C_SDA_FORCE_OUT_S) +#define LP_I2C_SDA_FORCE_OUT_V 0x00000001U +#define LP_I2C_SDA_FORCE_OUT_S 0 +/** LP_I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; * 1: direct output, 0: open drain output. */ -#define I2C_SCL_FORCE_OUT (BIT(1)) -#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) -#define I2C_SCL_FORCE_OUT_V 0x00000001U -#define I2C_SCL_FORCE_OUT_S 1 -/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; +#define LP_I2C_SCL_FORCE_OUT (BIT(1)) +#define LP_I2C_SCL_FORCE_OUT_M (LP_I2C_SCL_FORCE_OUT_V << LP_I2C_SCL_FORCE_OUT_S) +#define LP_I2C_SCL_FORCE_OUT_V 0x00000001U +#define LP_I2C_SCL_FORCE_OUT_S 1 +/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; * This register is used to select the sample mode.1: sample SDA data on the SCL low * level.0: sample SDA data on the SCL high level. */ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) -#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; +#define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) +#define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define LP_I2C_SAMPLE_SCL_LEVEL_S 2 +/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; * This register is used to configure the ACK value that need to sent by master when * the rx_fifo_cnt has reached the threshold. */ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) -#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U -#define I2C_RX_FULL_ACK_LEVEL_S 3 -/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; +#define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) +#define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define LP_I2C_RX_FULL_ACK_LEVEL_S 3 +/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; * Set this bit to start sending the data in txfifo. */ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) -#define I2C_TRANS_START_V 0x00000001U -#define I2C_TRANS_START_S 5 -/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; +#define LP_I2C_TRANS_START (BIT(5)) +#define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) +#define LP_I2C_TRANS_START_V 0x00000001U +#define LP_I2C_TRANS_START_S 5 +/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; * This bit is used to control the sending mode for data needing to be sent. 1: send * data from the least significant bit,0: send data from the most significant bit. */ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) -#define I2C_TX_LSB_FIRST_V 0x00000001U -#define I2C_TX_LSB_FIRST_S 6 -/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; +#define LP_I2C_TX_LSB_FIRST (BIT(6)) +#define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) +#define LP_I2C_TX_LSB_FIRST_V 0x00000001U +#define LP_I2C_TX_LSB_FIRST_S 6 +/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; * This bit is used to control the storage mode for received data.1: receive data from * the least significant bit,0: receive data from the most significant bit. */ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) -#define I2C_RX_LSB_FIRST_V 0x00000001U -#define I2C_RX_LSB_FIRST_S 7 -/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; +#define LP_I2C_RX_LSB_FIRST (BIT(7)) +#define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) +#define LP_I2C_RX_LSB_FIRST_V 0x00000001U +#define LP_I2C_RX_LSB_FIRST_S 7 +/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; * Reserved */ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) -#define I2C_CLK_EN_V 0x00000001U -#define I2C_CLK_EN_S 8 -/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_CLK_EN (BIT(8)) +#define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) +#define LP_I2C_CLK_EN_V 0x00000001U +#define LP_I2C_CLK_EN_S 8 +/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; * This is the enable bit for arbitration_lost. */ -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) -#define I2C_ARBITRATION_EN_V 0x00000001U -#define I2C_ARBITRATION_EN_S 9 -/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; +#define LP_I2C_ARBITRATION_EN (BIT(9)) +#define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) +#define LP_I2C_ARBITRATION_EN_V 0x00000001U +#define LP_I2C_ARBITRATION_EN_S 9 +/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; * This register is used to reset the scl FMS. */ -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) -#define I2C_FSM_RST_V 0x00000001U -#define I2C_FSM_RST_S 10 -/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; +#define LP_I2C_FSM_RST (BIT(10)) +#define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) +#define LP_I2C_FSM_RST_V 0x00000001U +#define LP_I2C_FSM_RST_S 10 +/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; * synchronization bit */ -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) -#define I2C_CONF_UPGATE_V 0x00000001U -#define I2C_CONF_UPGATE_S 11 +#define LP_I2C_CONF_UPGATE (BIT(11)) +#define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) +#define LP_I2C_CONF_UPGATE_V 0x00000001U +#define LP_I2C_CONF_UPGATE_S 11 -/** I2C_SR_REG register +/** LP_I2C_SR_REG register * Describe I2C work status. */ -#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) -/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; +#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) +/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. */ -#define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) -#define I2C_RESP_REC_V 0x00000001U -#define I2C_RESP_REC_S 0 -/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; +#define LP_I2C_RESP_REC (BIT(0)) +#define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) +#define LP_I2C_RESP_REC_V 0x00000001U +#define LP_I2C_RESP_REC_S 0 +/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; * When the I2C controller loses control of SCL line, this register changes to 1. */ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) -#define I2C_ARB_LOST_V 0x00000001U -#define I2C_ARB_LOST_S 3 -/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; +#define LP_I2C_ARB_LOST (BIT(3)) +#define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) +#define LP_I2C_ARB_LOST_V 0x00000001U +#define LP_I2C_ARB_LOST_S 3 +/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. */ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) -#define I2C_BUS_BUSY_V 0x00000001U -#define I2C_BUS_BUSY_S 4 -/** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; +#define LP_I2C_BUS_BUSY (BIT(4)) +#define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) +#define LP_I2C_BUS_BUSY_V 0x00000001U +#define LP_I2C_BUS_BUSY_S 4 +/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; * This field represents the amount of data needed to be sent. */ -#define I2C_RXFIFO_CNT 0x0000001FU -#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) -#define I2C_RXFIFO_CNT_V 0x0000001FU -#define I2C_RXFIFO_CNT_S 8 -/** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; +#define LP_I2C_RXFIFO_CNT 0x0000001FU +#define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) +#define LP_I2C_RXFIFO_CNT_V 0x0000001FU +#define LP_I2C_RXFIFO_CNT_S 8 +/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; * This field stores the amount of received data in RAM. */ -#define I2C_TXFIFO_CNT 0x0000001FU -#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) -#define I2C_TXFIFO_CNT_V 0x0000001FU -#define I2C_TXFIFO_CNT_S 18 -/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; +#define LP_I2C_TXFIFO_CNT 0x0000001FU +#define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) +#define LP_I2C_TXFIFO_CNT_V 0x0000001FU +#define LP_I2C_TXFIFO_CNT_S 18 +/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; * This field indicates the states of the I2C module state machine. 0: Idle, 1: * Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK */ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) -#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; +#define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) +#define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_S 24 +/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; * This field indicates the states of the state machine used to produce SCL.0: Idle, * 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop */ -#define I2C_SCL_STATE_LAST 0x00000007U -#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) -#define I2C_SCL_STATE_LAST_V 0x00000007U -#define I2C_SCL_STATE_LAST_S 28 +#define LP_I2C_SCL_STATE_LAST 0x00000007U +#define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) +#define LP_I2C_SCL_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_STATE_LAST_S 28 -/** I2C_TO_REG register +/** LP_I2C_TO_REG register * Setting time out control for receiving data. */ -#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) -/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) +/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; * This register is used to configure the timeout for receiving a data bit in APBclock * cycles. */ -#define I2C_TIME_OUT_VALUE 0x0000001FU -#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) -#define I2C_TIME_OUT_VALUE_V 0x0000001FU -#define I2C_TIME_OUT_VALUE_S 0 -/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; +#define LP_I2C_TIME_OUT_VALUE 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) +#define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_S 0 +/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; * This is the enable bit for time out control. */ -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) -#define I2C_TIME_OUT_EN_V 0x00000001U -#define I2C_TIME_OUT_EN_S 5 +#define LP_I2C_TIME_OUT_EN (BIT(5)) +#define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) +#define LP_I2C_TIME_OUT_EN_V 0x00000001U +#define LP_I2C_TIME_OUT_EN_S 5 -/** I2C_FIFO_ST_REG register +/** LP_I2C_FIFO_ST_REG register * FIFO status register. */ -#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) -/** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; +#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) +/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; * This is the offset address of the APB reading from rxfifo */ -#define I2C_RXFIFO_RADDR 0x0000000FU -#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) -#define I2C_RXFIFO_RADDR_V 0x0000000FU -#define I2C_RXFIFO_RADDR_S 0 -/** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; +#define LP_I2C_RXFIFO_RADDR 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) +#define LP_I2C_RXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_S 0 +/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; * This is the offset address of i2c module receiving data and writing to rxfifo. */ -#define I2C_RXFIFO_WADDR 0x0000000FU -#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) -#define I2C_RXFIFO_WADDR_V 0x0000000FU -#define I2C_RXFIFO_WADDR_S 5 -/** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; +#define LP_I2C_RXFIFO_WADDR 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) +#define LP_I2C_RXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_S 5 +/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; * This is the offset address of i2c module reading from txfifo. */ -#define I2C_TXFIFO_RADDR 0x0000000FU -#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) -#define I2C_TXFIFO_RADDR_V 0x0000000FU -#define I2C_TXFIFO_RADDR_S 10 -/** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; +#define LP_I2C_TXFIFO_RADDR 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) +#define LP_I2C_TXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_S 10 +/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; * This is the offset address of APB bus writing to txfifo. */ -#define I2C_TXFIFO_WADDR 0x0000000FU -#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) -#define I2C_TXFIFO_WADDR_V 0x0000000FU -#define I2C_TXFIFO_WADDR_S 15 +#define LP_I2C_TXFIFO_WADDR 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) +#define LP_I2C_TXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_S 15 -/** I2C_FIFO_CONF_REG register +/** LP_I2C_FIFO_CONF_REG register * FIFO configuration register. */ -#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) -/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; +#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) +/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; * The water mark threshold of rx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. */ -#define I2C_RXFIFO_WM_THRHD 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) -#define I2C_RXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_S 0 -/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; +#define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) +#define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_S 0 +/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; * The water mark threshold of tx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. */ -#define I2C_TXFIFO_WM_THRHD 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) -#define I2C_TXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_S 5 -/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; +#define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) +#define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_S 5 +/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; * Set this bit to enable APB nonfifo access. */ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) -#define I2C_NONFIFO_EN_V 0x00000001U -#define I2C_NONFIFO_EN_S 10 -/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; +#define LP_I2C_NONFIFO_EN (BIT(10)) +#define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) +#define LP_I2C_NONFIFO_EN_V 0x00000001U +#define LP_I2C_NONFIFO_EN_S 10 +/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; * Set this bit to reset rx-fifo. */ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) -#define I2C_RX_FIFO_RST_V 0x00000001U -#define I2C_RX_FIFO_RST_S 12 -/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; +#define LP_I2C_RX_FIFO_RST (BIT(12)) +#define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) +#define LP_I2C_RX_FIFO_RST_V 0x00000001U +#define LP_I2C_RX_FIFO_RST_S 12 +/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; * Set this bit to reset tx-fifo. */ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) -#define I2C_TX_FIFO_RST_V 0x00000001U -#define I2C_TX_FIFO_RST_S 13 -/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; +#define LP_I2C_TX_FIFO_RST (BIT(13)) +#define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) +#define LP_I2C_TX_FIFO_RST_V 0x00000001U +#define LP_I2C_TX_FIFO_RST_S 13 +/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. */ -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) -#define I2C_FIFO_PRT_EN_V 0x00000001U -#define I2C_FIFO_PRT_EN_S 14 +#define LP_I2C_FIFO_PRT_EN (BIT(14)) +#define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) +#define LP_I2C_FIFO_PRT_EN_V 0x00000001U +#define LP_I2C_FIFO_PRT_EN_S 14 -/** I2C_DATA_REG register +/** LP_I2C_DATA_REG register * Rx FIFO read data. */ -#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) -/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; +#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) +/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; * The value of rx FIFO read data. */ -#define I2C_FIFO_RDATA 0x000000FFU -#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) -#define I2C_FIFO_RDATA_V 0x000000FFU -#define I2C_FIFO_RDATA_S 0 +#define LP_I2C_FIFO_RDATA 0x000000FFU +#define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) +#define LP_I2C_FIFO_RDATA_V 0x000000FFU +#define LP_I2C_FIFO_RDATA_S 0 -/** I2C_INT_RAW_REG register +/** LP_I2C_INT_RAW_REG register * Raw interrupt status */ -#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) -/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) -#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_WM_INT_RAW_S 0 -/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) -#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_WM_INT_RAW_S 1 -/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) -#define I2C_END_DETECT_INT_RAW_V 0x00000001U -#define I2C_END_DETECT_INT_RAW_S 3 -/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 -/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 -/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) -#define I2C_TIME_OUT_INT_RAW_V 0x00000001U -#define I2C_TIME_OUT_INT_RAW_S 8 -/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) -#define I2C_TRANS_START_INT_RAW_V 0x00000001U -#define I2C_TRANS_START_INT_RAW_S 9 -/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) -#define I2C_NACK_INT_RAW_V 0x00000001U -#define I2C_NACK_INT_RAW_S 10 -/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_RAW_S 11 -/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_RAW_S 12 -/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) -#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_ST_TO_INT_RAW_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 -/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt bit for I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) -#define I2C_DET_START_INT_RAW_V 0x00000001U -#define I2C_DET_START_INT_RAW_S 15 +#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) +/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) +#define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_RAW_S 0 +/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) +#define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_RAW_S 1 +/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) +#define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 +/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_RAW (BIT(3)) +#define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) +#define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U +#define LP_I2C_END_DETECT_INT_RAW_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) +#define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) +#define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_RAW_S 8 +/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_RAW (BIT(9)) +#define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) +#define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_START_INT_RAW_S 9 +/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_RAW (BIT(10)) +#define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) +#define LP_I2C_NACK_INT_RAW_V 0x00000001U +#define LP_I2C_NACK_INT_RAW_S 10 +/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) +#define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 +/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) +#define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 +/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_RAW_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_RAW (BIT(15)) +#define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) +#define LP_I2C_DET_START_INT_RAW_V 0x00000001U +#define LP_I2C_DET_START_INT_RAW_S 15 -/** I2C_INT_CLR_REG register +/** LP_I2C_INT_CLR_REG register * Interrupt clear bits */ -#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) -/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) -#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_WM_INT_CLR_S 0 -/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) -#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_WM_INT_CLR_S 1 -/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) -#define I2C_END_DETECT_INT_CLR_V 0x00000001U -#define I2C_END_DETECT_INT_CLR_S 3 -/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 -/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 -/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) -#define I2C_TIME_OUT_INT_CLR_V 0x00000001U -#define I2C_TIME_OUT_INT_CLR_S 8 -/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) -#define I2C_TRANS_START_INT_CLR_V 0x00000001U -#define I2C_TRANS_START_INT_CLR_S 9 -/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) -#define I2C_NACK_INT_CLR_V 0x00000001U -#define I2C_NACK_INT_CLR_S 10 -/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_CLR_S 11 -/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_CLR_S 12 -/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) -#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_ST_TO_INT_CLR_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 -/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) -#define I2C_DET_START_INT_CLR_V 0x00000001U -#define I2C_DET_START_INT_CLR_S 15 +#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) +/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) +#define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_CLR_S 0 +/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) +#define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_CLR_S 1 +/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) +#define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 +/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_CLR (BIT(3)) +#define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) +#define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U +#define LP_I2C_END_DETECT_INT_CLR_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) +#define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) +#define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_CLR_S 8 +/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_CLR (BIT(9)) +#define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) +#define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_START_INT_CLR_S 9 +/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_CLR (BIT(10)) +#define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) +#define LP_I2C_NACK_INT_CLR_V 0x00000001U +#define LP_I2C_NACK_INT_CLR_S 10 +/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) +#define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 +/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) +#define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 +/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_CLR_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_CLR (BIT(15)) +#define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) +#define LP_I2C_DET_START_INT_CLR_V 0x00000001U +#define LP_I2C_DET_START_INT_CLR_S 15 -/** I2C_INT_ENA_REG register +/** LP_I2C_INT_ENA_REG register * Interrupt enable bits */ -#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) -/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) -#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ENA_S 0 -/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) -#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ENA_S 1 -/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) -#define I2C_END_DETECT_INT_ENA_V 0x00000001U -#define I2C_END_DETECT_INT_ENA_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 -/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 -/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) -#define I2C_TIME_OUT_INT_ENA_V 0x00000001U -#define I2C_TIME_OUT_INT_ENA_S 8 -/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) -#define I2C_TRANS_START_INT_ENA_V 0x00000001U -#define I2C_TRANS_START_INT_ENA_S 9 -/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) -#define I2C_NACK_INT_ENA_V 0x00000001U -#define I2C_NACK_INT_ENA_S 10 -/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ENA_S 11 -/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ENA_S 12 -/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) -#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ENA_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 -/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) -#define I2C_DET_START_INT_ENA_V 0x00000001U -#define I2C_DET_START_INT_ENA_S 15 +#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) +/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) +#define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ENA_S 0 +/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) +#define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ENA_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) +#define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 +/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ENA (BIT(3)) +#define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) +#define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ENA_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) +#define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ENA_S 8 +/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ENA (BIT(9)) +#define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) +#define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ENA_S 9 +/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ENA (BIT(10)) +#define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) +#define LP_I2C_NACK_INT_ENA_V 0x00000001U +#define LP_I2C_NACK_INT_ENA_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) +#define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) +#define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 +/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ENA_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ENA (BIT(15)) +#define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) +#define LP_I2C_DET_START_INT_ENA_V 0x00000001U +#define LP_I2C_DET_START_INT_ENA_S 15 -/** I2C_INT_STATUS_REG register +/** LP_I2C_INT_STATUS_REG register * Status of captured I2C communication events */ -#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) -/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) -#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ST_S 0 -/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) -#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ST_S 1 -/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) -#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) -#define I2C_END_DETECT_INT_ST_V 0x00000001U -#define I2C_END_DETECT_INT_ST_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 -/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 -/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; - * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) -#define I2C_TIME_OUT_INT_ST_V 0x00000001U -#define I2C_TIME_OUT_INT_ST_S 8 -/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) -#define I2C_TRANS_START_INT_ST_V 0x00000001U -#define I2C_TRANS_START_INT_ST_S 9 -/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) -#define I2C_NACK_INT_ST_V 0x00000001U -#define I2C_NACK_INT_ST_S 10 -/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) -#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ST_S 11 -/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) -#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ST_S 12 -/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; - * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) -#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ST_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; - * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 -/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; - * The masked interrupt status bit for I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) -#define I2C_DET_START_INT_ST_V 0x00000001U -#define I2C_DET_START_INT_ST_S 15 +#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) +/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) +#define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ST_S 0 +/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) +#define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ST_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) +#define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ST_S 2 +/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ST (BIT(3)) +#define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) +#define LP_I2C_END_DETECT_INT_ST_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ST_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) +#define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) +#define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 +/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ST (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) +#define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ST_S 8 +/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ST (BIT(9)) +#define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) +#define LP_I2C_TRANS_START_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ST_S 9 +/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ST (BIT(10)) +#define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) +#define LP_I2C_NACK_INT_ST_V 0x00000001U +#define LP_I2C_NACK_INT_ST_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) +#define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ST_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) +#define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ST_S 12 +/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) +#define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ST_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ST (BIT(15)) +#define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) +#define LP_I2C_DET_START_INT_ST_V 0x00000001U +#define LP_I2C_DET_START_INT_ST_S 15 -/** I2C_SDA_HOLD_REG register +/** LP_I2C_SDA_HOLD_REG register * Configures the hold time after a negative SCL edge. */ -#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) -/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) +/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure the time to hold the data after the negativeedge * of SCL, in I2C module clock cycles. */ -#define I2C_SDA_HOLD_TIME 0x000001FFU -#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) -#define I2C_SDA_HOLD_TIME_V 0x000001FFU -#define I2C_SDA_HOLD_TIME_S 0 +#define LP_I2C_SDA_HOLD_TIME 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) +#define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_S 0 -/** I2C_SDA_SAMPLE_REG register +/** LP_I2C_SDA_SAMPLE_REG register * Configures the sample time after a positive SCL edge. */ -#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) -/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) +/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SDA is sampled, in I2C module clock * cycles. */ -#define I2C_SDA_SAMPLE_TIME 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) -#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_S 0 +#define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) +#define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_S 0 -/** I2C_SCL_HIGH_PERIOD_REG register +/** LP_I2C_SCL_HIGH_PERIOD_REG register * Configures the high level width of SCL */ -#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) -/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) +/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL setup to high level and remains * high in master mode, in I2C module clock cycles. */ -#define I2C_SCL_HIGH_PERIOD 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) -#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_S 0 -/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) +#define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_S 0 +/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; * This register is used to configure for the SCL_FSM's waiting period for SCL high * level in master mode, in I2C module clock cycles. */ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 +#define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 -/** I2C_SCL_START_HOLD_REG register +/** LP_I2C_SCL_START_HOLD_REG register * Configures the delay between the SDA and SCL negative edge for a start condition */ -#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) -/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) +/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the negative edgeof SDA and the * negative edge of SCL for a START condition, in I2C module clock cycles. */ -#define I2C_SCL_START_HOLD_TIME 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) -#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_S 0 +#define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) +#define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_S 0 -/** I2C_SCL_RSTART_SETUP_REG register +/** LP_I2C_SCL_RSTART_SETUP_REG register * Configures the delay between the positive * edge of SCL and the negative edge of SDA */ -#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) -/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) +/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positiveedge of SCL and the * negative edge of SDA for a RESTART condition, in I2C module clock cycles. */ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_S 0 +#define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) +#define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 -/** I2C_SCL_STOP_HOLD_REG register +/** LP_I2C_SCL_STOP_HOLD_REG register * Configures the delay after the SCL clock * edge for a stop condition */ -#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) -/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) +/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the delay after the STOP condition,in I2C module * clock cycles. */ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) -#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_S 0 +#define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) +#define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_S 0 -/** I2C_SCL_STOP_SETUP_REG register +/** LP_I2C_SCL_STOP_SETUP_REG register * Configures the delay between the SDA and * SCL positive edge for a stop condition */ -#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) -/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) +/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positive edgeof SCL and the * positive edge of SDA, in I2C module clock cycles. */ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) -#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_S 0 +#define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) +#define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_S 0 -/** I2C_FILTER_CFG_REG register +/** LP_I2C_FILTER_CFG_REG register * SCL and SDA filter configuration register */ -#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) -/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; +#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) +/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; * When a pulse on the SCL input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SCL_FILTER_THRES 0x0000000FU -#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) -#define I2C_SCL_FILTER_THRES_V 0x0000000FU -#define I2C_SCL_FILTER_THRES_S 0 -/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; +#define LP_I2C_SCL_FILTER_THRES 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) +#define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_S 0 +/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; * When a pulse on the SDA input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SDA_FILTER_THRES 0x0000000FU -#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) -#define I2C_SDA_FILTER_THRES_V 0x0000000FU -#define I2C_SDA_FILTER_THRES_S 4 -/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; +#define LP_I2C_SDA_FILTER_THRES 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) +#define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_S 4 +/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; * This is the filter enable bit for SCL. */ -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) -#define I2C_SCL_FILTER_EN_V 0x00000001U -#define I2C_SCL_FILTER_EN_S 8 -/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_SCL_FILTER_EN (BIT(8)) +#define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) +#define LP_I2C_SCL_FILTER_EN_V 0x00000001U +#define LP_I2C_SCL_FILTER_EN_S 8 +/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; * This is the filter enable bit for SDA. */ -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) -#define I2C_SDA_FILTER_EN_V 0x00000001U -#define I2C_SDA_FILTER_EN_S 9 +#define LP_I2C_SDA_FILTER_EN (BIT(9)) +#define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) +#define LP_I2C_SDA_FILTER_EN_V 0x00000001U +#define LP_I2C_SDA_FILTER_EN_S 9 -/** I2C_CLK_CONF_REG register +/** LP_I2C_CLK_CONF_REG register * I2C CLK configuration register */ -#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) -/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; +#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) +/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * the integral part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_NUM 0x000000FFU -#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FFU -#define I2C_SCLK_DIV_NUM_S 0 -/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; +#define LP_I2C_SCLK_DIV_NUM 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) +#define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_S 0 +/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; * the numerator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_A 0x0000003FU -#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003FU -#define I2C_SCLK_DIV_A_S 8 -/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; +#define LP_I2C_SCLK_DIV_A 0x0000003FU +#define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) +#define LP_I2C_SCLK_DIV_A_V 0x0000003FU +#define LP_I2C_SCLK_DIV_A_S 8 +/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; * the denominator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_B 0x0000003FU -#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003FU -#define I2C_SCLK_DIV_B_S 14 -/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; +#define LP_I2C_SCLK_DIV_B 0x0000003FU +#define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) +#define LP_I2C_SCLK_DIV_B_V 0x0000003FU +#define LP_I2C_SCLK_DIV_B_S 14 +/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001U -#define I2C_SCLK_SEL_S 20 -/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; +#define LP_I2C_SCLK_SEL (BIT(20)) +#define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) +#define LP_I2C_SCLK_SEL_V 0x00000001U +#define LP_I2C_SCLK_SEL_S 20 +/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; * The clock switch for i2c module */ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001U -#define I2C_SCLK_ACTIVE_S 21 +#define LP_I2C_SCLK_ACTIVE (BIT(21)) +#define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) +#define LP_I2C_SCLK_ACTIVE_V 0x00000001U +#define LP_I2C_SCLK_ACTIVE_S 21 -/** I2C_COMD0_REG register +/** LP_I2C_COMD0_REG register * I2C command register 0 */ -#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) -/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) +/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 0. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND0 0x00003FFFU -#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) -#define I2C_COMMAND0_V 0x00003FFFU -#define I2C_COMMAND0_S 0 -/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND0 0x00003FFFU +#define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) +#define LP_I2C_COMMAND0_V 0x00003FFFU +#define LP_I2C_COMMAND0_S 0 +/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 0 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) -#define I2C_COMMAND0_DONE_V 0x00000001U -#define I2C_COMMAND0_DONE_S 31 +#define LP_I2C_COMMAND0_DONE (BIT(31)) +#define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) +#define LP_I2C_COMMAND0_DONE_V 0x00000001U +#define LP_I2C_COMMAND0_DONE_S 31 -/** I2C_COMD1_REG register +/** LP_I2C_COMD1_REG register * I2C command register 1 */ -#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) -/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) +/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 1. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND1 0x00003FFFU -#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) -#define I2C_COMMAND1_V 0x00003FFFU -#define I2C_COMMAND1_S 0 -/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND1 0x00003FFFU +#define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) +#define LP_I2C_COMMAND1_V 0x00003FFFU +#define LP_I2C_COMMAND1_S 0 +/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 1 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) -#define I2C_COMMAND1_DONE_V 0x00000001U -#define I2C_COMMAND1_DONE_S 31 +#define LP_I2C_COMMAND1_DONE (BIT(31)) +#define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) +#define LP_I2C_COMMAND1_DONE_V 0x00000001U +#define LP_I2C_COMMAND1_DONE_S 31 -/** I2C_COMD2_REG register +/** LP_I2C_COMD2_REG register * I2C command register 2 */ -#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) -/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) +/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 2. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND2 0x00003FFFU -#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) -#define I2C_COMMAND2_V 0x00003FFFU -#define I2C_COMMAND2_S 0 -/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND2 0x00003FFFU +#define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) +#define LP_I2C_COMMAND2_V 0x00003FFFU +#define LP_I2C_COMMAND2_S 0 +/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 2 is done in I2C Master mode, this bit changes to highLevel. */ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) -#define I2C_COMMAND2_DONE_V 0x00000001U -#define I2C_COMMAND2_DONE_S 31 +#define LP_I2C_COMMAND2_DONE (BIT(31)) +#define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) +#define LP_I2C_COMMAND2_DONE_V 0x00000001U +#define LP_I2C_COMMAND2_DONE_S 31 -/** I2C_COMD3_REG register +/** LP_I2C_COMD3_REG register * I2C command register 3 */ -#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) -/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) +/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 3. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND3 0x00003FFFU -#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) -#define I2C_COMMAND3_V 0x00003FFFU -#define I2C_COMMAND3_S 0 -/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND3 0x00003FFFU +#define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) +#define LP_I2C_COMMAND3_V 0x00003FFFU +#define LP_I2C_COMMAND3_S 0 +/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 3 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) -#define I2C_COMMAND3_DONE_V 0x00000001U -#define I2C_COMMAND3_DONE_S 31 +#define LP_I2C_COMMAND3_DONE (BIT(31)) +#define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) +#define LP_I2C_COMMAND3_DONE_V 0x00000001U +#define LP_I2C_COMMAND3_DONE_S 31 -/** I2C_COMD4_REG register +/** LP_I2C_COMD4_REG register * I2C command register 4 */ -#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) -/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) +/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 4. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND4 0x00003FFFU -#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) -#define I2C_COMMAND4_V 0x00003FFFU -#define I2C_COMMAND4_S 0 -/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND4 0x00003FFFU +#define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) +#define LP_I2C_COMMAND4_V 0x00003FFFU +#define LP_I2C_COMMAND4_S 0 +/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 4 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) -#define I2C_COMMAND4_DONE_V 0x00000001U -#define I2C_COMMAND4_DONE_S 31 +#define LP_I2C_COMMAND4_DONE (BIT(31)) +#define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) +#define LP_I2C_COMMAND4_DONE_V 0x00000001U +#define LP_I2C_COMMAND4_DONE_S 31 -/** I2C_COMD5_REG register +/** LP_I2C_COMD5_REG register * I2C command register 5 */ -#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) -/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) +/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 5. It consists of three parts:op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND5 0x00003FFFU -#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) -#define I2C_COMMAND5_V 0x00003FFFU -#define I2C_COMMAND5_S 0 -/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND5 0x00003FFFU +#define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) +#define LP_I2C_COMMAND5_V 0x00003FFFU +#define LP_I2C_COMMAND5_S 0 +/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 5 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) -#define I2C_COMMAND5_DONE_V 0x00000001U -#define I2C_COMMAND5_DONE_S 31 +#define LP_I2C_COMMAND5_DONE (BIT(31)) +#define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) +#define LP_I2C_COMMAND5_DONE_V 0x00000001U +#define LP_I2C_COMMAND5_DONE_S 31 -/** I2C_COMD6_REG register +/** LP_I2C_COMD6_REG register * I2C command register 6 */ -#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) -/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) +/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 6. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND6 0x00003FFFU -#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) -#define I2C_COMMAND6_V 0x00003FFFU -#define I2C_COMMAND6_S 0 -/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND6 0x00003FFFU +#define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) +#define LP_I2C_COMMAND6_V 0x00003FFFU +#define LP_I2C_COMMAND6_S 0 +/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 6 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) -#define I2C_COMMAND6_DONE_V 0x00000001U -#define I2C_COMMAND6_DONE_S 31 +#define LP_I2C_COMMAND6_DONE (BIT(31)) +#define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) +#define LP_I2C_COMMAND6_DONE_V 0x00000001U +#define LP_I2C_COMMAND6_DONE_S 31 -/** I2C_COMD7_REG register +/** LP_I2C_COMD7_REG register * I2C command register 7 */ -#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) -/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) +/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 7. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND7 0x00003FFFU -#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) -#define I2C_COMMAND7_V 0x00003FFFU -#define I2C_COMMAND7_S 0 -/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND7 0x00003FFFU +#define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) +#define LP_I2C_COMMAND7_V 0x00003FFFU +#define LP_I2C_COMMAND7_S 0 +/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 7 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) -#define I2C_COMMAND7_DONE_V 0x00000001U -#define I2C_COMMAND7_DONE_S 31 +#define LP_I2C_COMMAND7_DONE (BIT(31)) +#define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) +#define LP_I2C_COMMAND7_DONE_V 0x00000001U +#define LP_I2C_COMMAND7_DONE_S 31 -/** I2C_SCL_ST_TIME_OUT_REG register +/** LP_I2C_SCL_ST_TIME_OUT_REG register * SCL status time out register */ -#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) -/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) +/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 */ -#define I2C_SCL_ST_TO_I2C 0x0000001FU -#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) -#define I2C_SCL_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_ST_TO_I2C_S 0 +#define LP_I2C_SCL_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_M (LP_I2C_SCL_ST_TO_LP_I2C_V << LP_I2C_SCL_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_S 0 -/** I2C_SCL_MAIN_ST_TIME_OUT_REG register +/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register * SCL main status time out register */ -#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) -/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) +/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more * than 23 */ -#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) -#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_S 0 +#define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_M (LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V << LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S 0 -/** I2C_SCL_SP_CONF_REG register +/** LP_I2C_SCL_SP_CONF_REG register * Power configuration register */ -#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) -/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; +#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) +/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses * equals to reg_scl_rst_slv_num[4:0]. */ -#define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) -#define I2C_SCL_RST_SLV_EN_V 0x00000001U -#define I2C_SCL_RST_SLV_EN_S 0 -/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; +#define LP_I2C_SCL_RST_SLV_EN (BIT(0)) +#define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) +#define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U +#define LP_I2C_SCL_RST_SLV_EN_S 0 +/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; * Configure the pulses of SCL generated in I2C master mode. Valid when * reg_scl_rst_slv_en is 1. */ -#define I2C_SCL_RST_SLV_NUM 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) -#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_S 1 -/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; +#define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) +#define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_S 1 +/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. */ -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) -#define I2C_SCL_PD_EN_V 0x00000001U -#define I2C_SCL_PD_EN_S 6 -/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; +#define LP_I2C_SCL_PD_EN (BIT(6)) +#define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) +#define LP_I2C_SCL_PD_EN_V 0x00000001U +#define LP_I2C_SCL_PD_EN_S 6 +/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. */ -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) -#define I2C_SDA_PD_EN_V 0x00000001U -#define I2C_SDA_PD_EN_S 7 +#define LP_I2C_SDA_PD_EN (BIT(7)) +#define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) +#define LP_I2C_SDA_PD_EN_V 0x00000001U +#define LP_I2C_SDA_PD_EN_S 7 -/** I2C_DATE_REG register +/** LP_I2C_DATE_REG register * Version register */ -#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) -/** I2C_DATE : R/W; bitpos: [31:0]; default: 37752896; +#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) +/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 37752896; * This is the the version register. */ -#define I2C_DATE 0xFFFFFFFFU -#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) -#define I2C_DATE_V 0xFFFFFFFFU -#define I2C_DATE_S 0 +#define LP_I2C_DATE 0xFFFFFFFFU +#define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) +#define LP_I2C_DATE_V 0xFFFFFFFFU +#define LP_I2C_DATE_S 0 -/** I2C_TXFIFO_START_ADDR_REG register +/** LP_I2C_TXFIFO_START_ADDR_REG register * I2C TXFIFO base address register */ -#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) -/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) +/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C txfifo first address. */ -#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) -#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_S 0 +#define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) +#define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_S 0 -/** I2C_RXFIFO_START_ADDR_REG register +/** LP_I2C_RXFIFO_START_ADDR_REG register * I2C RXFIFO base address register */ -#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) -/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) +/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C rxfifo first address. */ -#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) -#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_S 0 +#define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) +#define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32c5/include/soc/parl_io_struct.h b/components/soc/esp32c5/include/soc/parl_io_struct.h index 4c3e326433df..786e68043a49 100644 --- a/components/soc/esp32c5/include/soc/parl_io_struct.h +++ b/components/soc/esp32c5/include/soc/parl_io_struct.h @@ -468,7 +468,7 @@ typedef union { } parl_io_version_reg_t; -typedef struct { +typedef struct parl_io_dev_t { volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg; volatile parl_io_rx_data_cfg_reg_t rx_data_cfg; volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg; diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/include/soc/pcr_struct.h index 6ffbbb0ba77a..db621a0671ed 100644 --- a/components/soc/esp32c5/include/soc/pcr_struct.h +++ b/components/soc/esp32c5/include/soc/pcr_struct.h @@ -2329,6 +2329,13 @@ typedef union { uint32_t val; } pcr_date_reg_t; +/** + * @brief The struct of I2C configuration registers + */ +typedef struct { + pcr_i2c_conf_reg_t i2c_conf; + pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; +} pcr_i2c_reg_t; typedef struct { volatile pcr_uart0_conf_reg_t uart0_conf; @@ -2339,8 +2346,7 @@ typedef struct { volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; volatile pcr_mspi_conf_reg_t mspi_conf; volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; - volatile pcr_i2c_conf_reg_t i2c_conf; - volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; + volatile pcr_i2c_reg_t i2c[1]; volatile pcr_twai0_conf_reg_t twai0_conf; volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; volatile pcr_twai1_conf_reg_t twai1_conf; diff --git a/components/soc/esp32c5/include/soc/periph_defs.h b/components/soc/esp32c5/include/soc/periph_defs.h index b438aee3f3e0..04f5b92e4989 100644 --- a/components/soc/esp32c5/include/soc/periph_defs.h +++ b/components/soc/esp32c5/include/soc/periph_defs.h @@ -20,7 +20,7 @@ typedef enum { PERIPH_UART0_MODULE, PERIPH_UART1_MODULE, PERIPH_USB_DEVICE_MODULE, // USB Serial Jtag - PERIPH_I2C_MODULE, + PERIPH_I2C0_MODULE, PERIPH_I2S_MODULE, PERIPH_TIMG0_MODULE, PERIPH_TIMG1_MODULE, diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/include/soc/pmu_struct.h index bdb33425cfb7..ef9f62e81be3 100644 --- a/components/soc/esp32c5/include/soc/pmu_struct.h +++ b/components/soc/esp32c5/include/soc/pmu_struct.h @@ -376,6 +376,16 @@ typedef union { uint32_t val; } pmu_power_wait_timer1_reg_t; +typedef union { + struct { + uint32_t reserved0 : 9; + uint32_t powerdown_timer: 7; + uint32_t powerup_timer : 7; + uint32_t wait_timer : 9; + }; + uint32_t val; +} pmu_power_wait_timer2_reg_t; + typedef union { struct { uint32_t force_reset : 1; @@ -445,6 +455,7 @@ typedef union { typedef struct pmu_power_hw_regmap_t{ pmu_power_wait_timer0_reg_t wait_timer0; pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_wait_timer2_reg_t wait_timer2; pmu_power_domain_cntl_reg_t hp_pd[5]; pmu_power_domain_cntl_reg_t lp_peri; pmu_power_memory_cntl_reg_t mem_cntl; @@ -731,8 +742,6 @@ typedef struct pmu_dev_t{ volatile uint32_t val; } vdd_spi_status; - uint32_t reserved[150]; - union { struct { volatile uint32_t pmu_date: 31; @@ -745,9 +754,8 @@ typedef struct pmu_dev_t{ extern pmu_dev_t PMU; #ifndef __cplusplus -_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); -//_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); +//_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); TODO IDF-8643 #endif diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 9f2762b06992..155000b197b9 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -19,7 +19,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ // #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701 // #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725 -#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722 +#define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 @@ -27,13 +27,14 @@ #define SOC_MCPWM_SUPPORTED 1 // #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 // #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693 -// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686 +#define SOC_PARLIO_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 -// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721 +#define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727 // #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851 #define SOC_SUPPORTS_SECURE_DL_MODE 1 -// #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8637 +#define SOC_LP_CORE_SUPPORTED 1 +#define SOC_ULP_SUPPORTED 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 @@ -43,7 +44,7 @@ // #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687 #define SOC_GPSPI_SUPPORTED 1 #define SOC_LEDC_SUPPORTED 1 -// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696 +#define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 #define SOC_AES_SUPPORTED 1 #define SOC_MPI_SUPPORTED 1 @@ -59,9 +60,9 @@ // #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615 // #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 // #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638 -// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 +#define SOC_LP_TIMER_SUPPORTED 1 // #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638 -// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719 +#define SOC_LP_PERIPHERALS_SUPPORTED 1 // #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634 // #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633 // #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8642 @@ -72,7 +73,7 @@ #define SOC_ECDSA_SUPPORTED 1 // #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 // #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 -// #define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 +#define SOC_MODEM_CLOCK_SUPPORTED 1 // #define SOC_PM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8643 /*-------------------------- XTAL CAPS ---------------------------------------*/ @@ -235,20 +236,18 @@ #define SOC_I2C_NUM (1U) #define SOC_HP_I2C_NUM (1U) -// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ -// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */ -// #define SOC_I2C_SUPPORT_SLAVE (1) +#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ +#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */ +#define SOC_I2C_SUPPORT_SLAVE (1) -// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined. -// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) - -// #define SOC_I2C_SUPPORT_XTAL (1) -// #define SOC_I2C_SUPPORT_RTC (1) -// #define SOC_I2C_SUPPORT_10BIT_ADDR (1) -// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1) -// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1) -// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1) -// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1) +#define SOC_I2C_SUPPORT_HW_FSM_RST (1) +#define SOC_I2C_SUPPORT_XTAL (1) +#define SOC_I2C_SUPPORT_RTC (1) +#define SOC_I2C_SUPPORT_10BIT_ADDR (1) +#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1) +#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1) +#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1) +#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1) // #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693 @@ -343,12 +342,16 @@ // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 /*-------------------------- PARLIO CAPS --------------------------------------*/ -// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ -// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ -// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ -// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ -// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ -// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */ +#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ +#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ +#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ +#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */ +#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */ +#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */ +#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */ +#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */ +#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */ +#define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */ /*--------------------------- MPI CAPS ---------------------------------------*/ #define SOC_MPI_MEM_BLOCKS_NUM (4) @@ -435,8 +438,8 @@ // #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ -// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part -// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part +#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) @@ -489,14 +492,15 @@ #define SOC_UART_LP_NUM (1U) #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ -// #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ // #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ -// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ // TODO: [ESP32C5] IDF-8642 #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ -// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ +#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ +#define SOC_UART_HAS_LP_UART (1) /*!< Support LP UART */ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled -// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ // #define SOC_COEX_HW_PTI (1) @@ -579,3 +583,6 @@ /*------------------------------------- PHY CAPS -------------------------------------*/ // #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/ + +/*------------------------------------- ULP CAPS -------------------------------------*/ +#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */ diff --git a/components/soc/esp32c5/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld index 56be2b14fd37..bb5488358c93 100644 --- a/components/soc/esp32c5/ld/esp32c5.peripherals.ld +++ b/components/soc/esp32c5/ld/esp32c5.peripherals.ld @@ -8,7 +8,7 @@ PROVIDE ( UART0 = 0x60000000 ); PROVIDE ( UART1 = 0x60001000 ); PROVIDE ( SPIMEM0 = 0x60002000 ); PROVIDE ( SPIMEM1 = 0x60003000 ); -PROVIDE ( I2C = 0x60004000 ); +PROVIDE ( I2C0 = 0x60004000 ); PROVIDE ( UHCI = 0x60005000 ); PROVIDE ( RMT = 0x60006000 ); PROVIDE ( RMTMEM = 0x60006400 ); diff --git a/components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h b/components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h deleted file mode 100644 index 2e16b2e54c39..000000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "modem/reg_base.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) -/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_EN (BIT(0)) -#define MODEM_LPCON_CLK_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_EN_V 0x1 -#define MODEM_LPCON_CLK_EN_S 0 - -#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) -/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 - -#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) -/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 - -#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) -/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 - -#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) -/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1 -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 -/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003 -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S)) -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3 -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0 - -#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) -/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 -#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) -#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 -#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 - -#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) -/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 -/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_V 0x1 -#define MODEM_LPCON_CLK_COEX_EN_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 - -#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) -/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 -/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 -/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_V 0x1 -#define MODEM_LPCON_CLK_COEX_FO_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 - -#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) -/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 -/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) -#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 -/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 - -#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) -/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_V 0x1 -#define MODEM_LPCON_RST_LP_TIMER_S 3 -/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_I2C_MST (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_V 0x1 -#define MODEM_LPCON_RST_I2C_MST_S 2 -/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_COEX (BIT(1)) -#define MODEM_LPCON_RST_COEX_M (BIT(1)) -#define MODEM_LPCON_RST_COEX_V 0x1 -#define MODEM_LPCON_RST_COEX_S 1 -/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_WIFIPWR (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_V 0x1 -#define MODEM_LPCON_RST_WIFIPWR_S 0 - -#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) -/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)) -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0 - -#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 -/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)) -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 -/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1 -#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 -/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007 -#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S)) -#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7 -#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 -/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_BC_MEM_FORCE_S 15 -/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_MODE 0x00000007 -#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S)) -#define MODEM_LPCON_BC_MEM_MODE_V 0x7 -#define MODEM_LPCON_BC_MEM_MODE_S 12 -/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1 -#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 -/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007 -#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S)) -#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7 -#define MODEM_LPCON_PBUS_MEM_MODE_S 8 -/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_AGC_MEM_FORCE_S 7 -/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_MODE 0x00000007 -#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S)) -#define MODEM_LPCON_AGC_MEM_MODE_V 0x7 -#define MODEM_LPCON_AGC_MEM_MODE_S 4 -/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_DC_MEM_FORCE_S 3 -/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_MODE 0x00000007 -#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S)) -#define MODEM_LPCON_DC_MEM_MODE_V 0x7 -#define MODEM_LPCON_DC_MEM_MODE_S 0 - -#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) -/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0 - -#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) -/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0 - -#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) -/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_V 0x1 -#define MODEM_LPCON_AGC_MEM_EN_S 2 -/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_V 0x1 -#define MODEM_LPCON_PBUS_MEM_EN_S 1 -/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0 - -#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C) -/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */ -/*description: .*/ -#define MODEM_LPCON_DATE 0x0FFFFFFF -#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) -#define MODEM_LPCON_DATE_V 0xFFFFFFF -#define MODEM_LPCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h b/components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h deleted file mode 100644 index cb8e4ff8a594..000000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t reg_clk_en : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 30; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t reg_clk_lp_timer_sel_osc_slow : 1; - uint32_t reg_clk_lp_timer_sel_osc_fast : 1; - uint32_t reg_clk_lp_timer_sel_xtal : 1; - uint32_t reg_clk_lp_timer_sel_xtal32k : 1; - uint32_t reg_clk_lp_timer_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } lp_timer_conf; - union { - struct { - uint32_t reg_clk_coex_lp_sel_osc_slow : 1; - uint32_t reg_clk_coex_lp_sel_osc_fast : 1; - uint32_t reg_clk_coex_lp_sel_xtal : 1; - uint32_t reg_clk_coex_lp_sel_xtal32k : 1; - uint32_t reg_clk_coex_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } coex_lp_clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_lp_sel_osc_slow: 1; - uint32_t reg_clk_wifipwr_lp_sel_osc_fast: 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal : 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal32k: 1; - uint32_t reg_clk_wifipwr_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } wifi_lp_clk_conf; - union { - struct { - uint32_t reg_clk_modem_aon_force : 2; - uint32_t reg_modem_pwr_clk_src_fo : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } modem_src_clk_conf; - union { - struct { - uint32_t reg_clk_modem_32k_sel : 2; - uint32_t reserved2 : 30; - }; - uint32_t val; - } modem_32k_clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_en : 1; - uint32_t reg_clk_coex_en : 1; - uint32_t reg_clk_i2c_mst_en : 1; - uint32_t reg_clk_lp_timer_en : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_fo : 1; - uint32_t reg_clk_coex_fo : 1; - uint32_t reg_clk_i2c_mst_fo : 1; - uint32_t reg_clk_lp_timer_fo : 1; - uint32_t reg_clk_fe_mem_fo : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 16; - uint32_t reg_clk_wifipwr_st_map : 4; - uint32_t reg_clk_coex_st_map : 4; - uint32_t reg_clk_i2c_mst_st_map : 4; - uint32_t reg_clk_lp_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t reg_rst_wifipwr : 1; - uint32_t reg_rst_coex : 1; - uint32_t reg_rst_i2c_mst : 1; - uint32_t reg_rst_lp_timer : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } rst_conf; - union { - struct { - uint32_t reg_modem_pwr_tick_target : 6; - uint32_t reserved6 : 26; - }; - uint32_t val; - } tick_conf; - union { - struct { - uint32_t reg_dc_mem_mode : 3; - uint32_t reg_dc_mem_force : 1; - uint32_t reg_agc_mem_mode : 3; - uint32_t reg_agc_mem_force : 1; - uint32_t reg_pbus_mem_mode : 3; - uint32_t reg_pbus_mem_force : 1; - uint32_t reg_bc_mem_mode : 3; - uint32_t reg_bc_mem_force : 1; - uint32_t reg_i2c_mst_mem_mode : 3; - uint32_t reg_i2c_mst_mem_force : 1; - uint32_t reg_chan_freq_mem_mode : 3; - uint32_t reg_chan_freq_mem_force : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } mem_conf; - uint32_t mem_rf1_aux_ctrl; - uint32_t mem_rf2_aux_ctrl; - union { - struct { - uint32_t reg_chan_freq_mem_en : 1; - uint32_t reg_pbus_mem_en : 1; - uint32_t reg_agc_mem_en : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } apb_mem_sel; - union { - struct { - uint32_t reg_date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; -} modem_lpcon_dev_t; - -extern modem_lpcon_dev_t MODEM_LPCON; - -#ifndef __cplusplus -_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h b/components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h deleted file mode 100644 index 765cb3a00c74..000000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "modem/reg_base.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) -/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x1 -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 -/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 -/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 -/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 -/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 -/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 -/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_EN (BIT(0)) -#define MODEM_SYSCON_CLK_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_EN_V 0x1 -#define MODEM_SYSCON_CLK_EN_S 0 - -#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) -/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 -/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 -/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 -/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 -/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 -/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 -/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 -/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 -#define MODEM_SYSCON_CLK_ETM_EN_S 22 -/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 -/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x1 -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 -/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 -/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 -/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 -/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */ -/*description: .*/ -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S)) -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0xFF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 -/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x1 -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S 0 - -#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) -/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 -/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 -#define MODEM_SYSCON_CLK_ETM_FO_S 28 -/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 -/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 -/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 -/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 -/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_FO_S 5 -/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 -/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_FO_S 3 -/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 -/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_FO_S 0 - -#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) -/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 -/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 -/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 -/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S)) -#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 -/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S)) -#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 -/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 - -#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) -/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 -#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 -#define MODEM_SYSCON_RST_BLE_TIMER_S 30 -/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 -#define MODEM_SYSCON_RST_MODEM_SEC_S 29 -/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 -#define MODEM_SYSCON_RST_MODEM_BAH_S 27 -/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 -#define MODEM_SYSCON_RST_MODEM_CCM_S 26 -/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 -#define MODEM_SYSCON_RST_MODEM_ECB_S 25 -/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_S 24 -/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_M (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 -/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ETM (BIT(22)) -#define MODEM_SYSCON_RST_ETM_M (BIT(22)) -#define MODEM_SYSCON_RST_ETM_V 0x1 -#define MODEM_SYSCON_RST_ETM_S 22 -/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_S 18 -/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_APB_S 17 -/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_S 16 -/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_APB_S 15 -/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE (BIT(14)) -#define MODEM_SYSCON_RST_FE_M (BIT(14)) -#define MODEM_SYSCON_RST_FE_V 0x1 -#define MODEM_SYSCON_RST_FE_S 14 -/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_V 0x1 -#define MODEM_SYSCON_RST_FE_AHB_S 13 -/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_ADC_S 12 -/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_V 0x1 -#define MODEM_SYSCON_RST_FE_DAC_S 11 -/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 -/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_V 0x1 -#define MODEM_SYSCON_RST_WIFIMAC_S 9 -/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_WIFIBB (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_V 0x1 -#define MODEM_SYSCON_RST_WIFIBB_S 8 - -#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) -/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 -/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 -/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 -/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 -/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_EN_S 17 -/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 -/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 -/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 -/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 -/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 -/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 -/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 -/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 -/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 -/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 -/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 -/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 -/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 -/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 -/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 -/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 - -#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) -/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF -#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S)) -#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF -#define MODEM_SYSCON_WIFI_BB_CFG_S 0 - -#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) -/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0 - -#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) -/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0 - -#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) -/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2312050 ; */ -/*description: .*/ -#define MODEM_SYSCON_DATE 0x0FFFFFFF -#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) -#define MODEM_SYSCON_DATE_V 0xFFFFFFF -#define MODEM_SYSCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h deleted file mode 100644 index b7086ad37a2e..000000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t reg_clk_en : 1; - uint32_t reg_modem_ant_force_sel_bt : 1; - uint32_t reg_modem_ant_force_sel_wifi : 1; - uint32_t reg_fpga_debug_clkswitch : 1; - uint32_t reg_fpga_debug_clk80 : 1; - uint32_t reg_fpga_debug_clk40 : 1; - uint32_t reg_fpga_debug_clk20 : 1; - uint32_t reg_fpga_debug_clk10 : 1; - uint32_t reg_modem_mem_mode_force : 1; - uint32_t reserved9 : 23; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t reg_pwdet_sar_clock_ena : 1; - uint32_t reg_pwdet_clk_div_num : 8; - uint32_t reg_clk_tx_dac_inv_ena : 1; - uint32_t reg_clk_rx_adc_inv_ena : 1; - uint32_t reg_clk_pwdet_adc_inv_ena : 1; - uint32_t reg_clk_i2c_mst_sel_160m : 1; - uint32_t reserved13 : 8; - uint32_t reg_clk_data_dump_mux : 1; - uint32_t reg_clk_etm_en : 1; - uint32_t reg_clk_zb_apb_en : 1; - uint32_t reg_clk_zbmac_en : 1; - uint32_t reg_clk_modem_sec_ecb_en : 1; - uint32_t reg_clk_modem_sec_ccm_en : 1; - uint32_t reg_clk_modem_sec_bah_en : 1; - uint32_t reg_clk_modem_sec_apb_en : 1; - uint32_t reg_clk_modem_sec_en : 1; - uint32_t reg_clk_ble_timer_en : 1; - uint32_t reg_clk_data_dump_en : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t reg_clk_wifibb_fo : 1; - uint32_t reg_clk_wifimac_fo : 1; - uint32_t reg_clk_wifi_apb_fo : 1; - uint32_t reg_clk_fe_fo : 1; - uint32_t reg_clk_fe_apb_fo : 1; - uint32_t reg_clk_btbb_fo : 1; - uint32_t reg_clk_btmac_fo : 1; - uint32_t reg_clk_bt_apb_fo : 1; - uint32_t reg_clk_zbmac_fo : 1; - uint32_t reg_clk_zbmac_apb_fo : 1; - uint32_t reserved10 : 13; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reg_clk_etm_fo : 1; - uint32_t reg_clk_modem_sec_fo : 1; - uint32_t reg_clk_ble_timer_fo : 1; - uint32_t reg_clk_data_dump_fo : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 8; - uint32_t reg_clk_zb_st_map : 4; - uint32_t reg_clk_fe_st_map : 4; - uint32_t reg_clk_bt_st_map : 4; - uint32_t reg_clk_wifi_st_map : 4; - uint32_t reg_clk_modem_peri_st_map : 4; - uint32_t reg_clk_modem_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 1; - uint32_t reserved3 : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reg_rst_wifibb : 1; - uint32_t reg_rst_wifimac : 1; - uint32_t reg_rst_fe_pwdet_adc : 1; - uint32_t reg_rst_fe_dac : 1; - uint32_t reg_rst_fe_adc : 1; - uint32_t reg_rst_fe_ahb : 1; - uint32_t reg_rst_fe : 1; - uint32_t reg_rst_btmac_apb : 1; - uint32_t reg_rst_btmac : 1; - uint32_t reg_rst_btbb_apb : 1; - uint32_t reg_rst_btbb : 1; - uint32_t reserved19 : 3; - uint32_t reg_rst_etm : 1; - uint32_t reg_rst_zbmac_apb : 1; - uint32_t reg_rst_zbmac : 1; - uint32_t reg_rst_modem_ecb : 1; - uint32_t reg_rst_modem_ccm : 1; - uint32_t reg_rst_modem_bah : 1; - uint32_t reserved28 : 1; - uint32_t reg_rst_modem_sec : 1; - uint32_t reg_rst_ble_timer : 1; - uint32_t reg_rst_data_dump : 1; - }; - uint32_t val; - } modem_rst_conf; - union { - struct { - uint32_t reg_clk_wifibb_22m_en : 1; - uint32_t reg_clk_wifibb_40m_en : 1; - uint32_t reg_clk_wifibb_44m_en : 1; - uint32_t reg_clk_wifibb_80m_en : 1; - uint32_t reg_clk_wifibb_40x_en : 1; - uint32_t reg_clk_wifibb_80x_en : 1; - uint32_t reg_clk_wifibb_40x1_en : 1; - uint32_t reg_clk_wifibb_80x1_en : 1; - uint32_t reg_clk_wifibb_160x1_en : 1; - uint32_t reg_clk_wifimac_en : 1; - uint32_t reg_clk_wifi_apb_en : 1; - uint32_t reg_clk_fe_20m_en : 1; - uint32_t reg_clk_fe_40m_en : 1; - uint32_t reg_clk_fe_80m_en : 1; - uint32_t reg_clk_fe_160m_en : 1; - uint32_t reg_clk_fe_apb_en : 1; - uint32_t reg_clk_bt_apb_en : 1; - uint32_t reg_clk_btbb_en : 1; - uint32_t reg_clk_btmac_en : 1; - uint32_t reg_clk_fe_pwdet_adc_en : 1; - uint32_t reg_clk_fe_adc_en : 1; - uint32_t reg_clk_fe_dac_en : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 8; - }; - uint32_t val; - } clk_conf1; - uint32_t wifi_bb_cfg; - uint32_t mem_rf1_conf; - uint32_t mem_rf2_conf; - union { - struct { - uint32_t reg_date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; -} modem_syscon_dev_t; - -extern modem_syscon_dev_t MODEM_SYSCON; - -#ifndef __cplusplus -_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/reg_base.h b/components/soc/esp32c5/mp/include/modem/reg_base.h deleted file mode 100644 index 37b441740c28..000000000000 --- a/components/soc/esp32c5/mp/include/modem/reg_base.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once -#define DR_REG_MODEM_SYSCON_BASE 0x600A9C00 -#define DR_REG_MODEM_LPCON_BASE 0x600AF000 diff --git a/components/soc/esp32c5/parlio_periph.c b/components/soc/esp32c5/parlio_periph.c new file mode 100644 index 000000000000..142e461cf17b --- /dev/null +++ b/components/soc/esp32c5/parlio_periph.c @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/parlio_periph.h" +#include "soc/gpio_sig_map.h" + +const parlio_signal_conn_t parlio_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_PARLIO_MODULE, + .tx_irq_id = ETS_PARL_IO_TX_INTR_SOURCE, + .rx_irq_id = ETS_PARL_IO_RX_INTR_SOURCE, + .tx_units = { + [0] = { + .data_sigs = { + PARL_TX_DATA0_IDX, + PARL_TX_DATA1_IDX, + PARL_TX_DATA2_IDX, + PARL_TX_DATA3_IDX, + PARL_TX_DATA4_IDX, + PARL_TX_DATA5_IDX, + PARL_TX_DATA6_IDX, + PARL_TX_DATA7_IDX, + }, + .clk_out_sig = PARL_TX_CLK_OUT_IDX, + .clk_in_sig = PARL_TX_CLK_IN_IDX, + } + }, + .rx_units = { + [0] = { + .data_sigs = { + PARL_RX_DATA0_IDX, + PARL_RX_DATA1_IDX, + PARL_RX_DATA2_IDX, + PARL_RX_DATA3_IDX, + PARL_RX_DATA4_IDX, + PARL_RX_DATA5_IDX, + PARL_RX_DATA6_IDX, + PARL_RX_DATA7_IDX, + }, + .clk_out_sig = PARL_RX_CLK_OUT_IDX, + .clk_in_sig = PARL_RX_CLK_IN_IDX, + } + } + }, + }, +}; diff --git a/components/soc/esp32c5/wdt_periph.c b/components/soc/esp32c5/wdt_periph.c new file mode 100644 index 000000000000..58f1349d3d24 --- /dev/null +++ b/components/soc/esp32c5/wdt_periph.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/wdt_periph.h" diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 092fb261eb40..14916f9cabb5 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1131,6 +1131,10 @@ config SOC_MWDT_SUPPORT_XTAL bool default y +config SOC_MWDT_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_TWAI_CONTROLLER_NUM int default 2 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 31bc9530ec35..6f32679bf462 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -447,6 +447,7 @@ /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ #define SOC_MWDT_SUPPORT_XTAL (1) +#define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- TWAI CAPS ---------------------------------------*/ #define SOC_TWAI_CONTROLLER_NUM 2 diff --git a/components/soc/esp32c6/include/soc/soc_etm_struct.h b/components/soc/esp32c6/include/soc/soc_etm_struct.h index 5e8f2dea6bba..3c62027ae5a4 100644 --- a/components/soc/esp32c6/include/soc/soc_etm_struct.h +++ b/components/soc/esp32c6/include/soc/soc_etm_struct.h @@ -735,8 +735,8 @@ typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; volatile struct { - soc_etm_chn_evt_id_reg_t evt_id; - soc_etm_chn_task_id_reg_t task_id; + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; } channel[50]; volatile soc_etm_clk_en_reg_t clk_en; volatile soc_etm_date_reg_t date; diff --git a/components/soc/esp32c6/timer_periph.c b/components/soc/esp32c6/timer_periph.c index 422b536f37a4..58750906fd8f 100644 --- a/components/soc/esp32c6/timer_periph.c +++ b/components/soc/esp32c6/timer_periph.c @@ -23,68 +23,111 @@ const timer_group_signal_conn_t timer_group_periph_signals = { } }; -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - /*Timer group backup. should get of write project firstly. wdt used by RTOS.*/ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - /*Timer group0 backup. T0_wdt should get of write project firstly. wdt used by RTOS.*/ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - /* Registers in retention context: * TIMG_T0CONFIG_REG * TIMG_T0ALARMLO_REG * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG * TIMG_INT_ENA_TIMERS_REG * TIMG_REGCLK_REG */ -#define N_REGS_TG_TIMER_CFG 5 -static const uint32_t tg_timer_regs_map[4] = {0x10000031, 0x80000000, 0, 0}; +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; -const regdma_entries_config_t tg0_timer_regs_retention[] = { +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x00), TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), N_REGS_TG_TIMER_CFG, 0, 0, \ - tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [5] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x05), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x01), TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02), TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03), TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x04), TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05), TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; -const regdma_entries_config_t tg1_timer_regs_retention[] = { +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x00), TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), N_REGS_TG_TIMER_CFG, 0, 0, \ - tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [5] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x05), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x01), TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02), TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03), TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x04), TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, }; -const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = { - [0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)}, - [1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)}, +const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = { + [0] = { + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + }, + [1] = { + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + }, }; diff --git a/components/soc/esp32c6/wdt_periph.c b/components/soc/esp32c6/wdt_periph.c new file mode 100644 index 000000000000..f615401cfa8f --- /dev/null +++ b/components/soc/esp32c6/wdt_periph.c @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/wdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; + +const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 10b4001d212f..45fc5a8cb945 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -503,30 +503,6 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP bool default y -config SOC_PARLIO_GROUPS - int - default 1 - -config SOC_PARLIO_TX_UNITS_PER_GROUP - int - default 1 - -config SOC_PARLIO_RX_UNITS_PER_GROUP - int - default 1 - -config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH - int - default 16 - -config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH - int - default 16 - -config SOC_PARLIO_TX_RX_SHARE_INTERRUPT - bool - default y - config SOC_MPI_MEM_BLOCKS_NUM int default 4 diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h index df78d1d90729..4ae064433475 100644 --- a/components/soc/esp32c61/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -20,7 +20,7 @@ extern "C" { * * 2) External 40MHz Crystal Clock: XTAL * - * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) + * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description) * * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock * can be computed in runtime through calibration. @@ -468,24 +468,6 @@ typedef enum { LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ } soc_periph_ledc_clk_src_legacy_t; -//////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of PARLIO - */ -#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M} - -/** - * @brief PARLIO clock source - */ -typedef enum { - PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ - PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */ - PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ -} soc_periph_parlio_clk_src_t; - //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// typedef enum { CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index f947825157ef..d0dbd4d01ef1 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -66,7 +66,6 @@ // \#define SOC_MCPWM_SUPPORTED 0 //TODO: [ESP32C61] IDF-9338 // \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336 // \#define SOC_ETM_SUPPORTED 0 -// \#define SOC_PARLIO_SUPPORTED 0 //TODO: [ESP32C61] IDF-9333, 9334 // \#define SOC_LP_CORE_SUPPORTED 0 //TODO: [ESP32C61] IDF-9331 // \#define SOC_RMT_SUPPORTED 0 //TODO: [ESP32C61] IDF-9343 // \#define SOC_AES_SUPPORTED 0 //TODO: [ESP32C61] IDF-9328 @@ -329,14 +328,6 @@ /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/ // \#define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 -/*-------------------------- PARLIO CAPS --------------------------------------*/ -#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ -#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ -#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ -#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ -#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ -#define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */ - /*--------------------------- MPI CAPS ---------------------------------------*/ #define SOC_MPI_MEM_BLOCKS_NUM (4) #define SOC_MPI_OPERATIONS_NUM (3) diff --git a/components/soc/esp32c61/wdt_periph.c b/components/soc/esp32c61/wdt_periph.c new file mode 100644 index 000000000000..58f1349d3d24 --- /dev/null +++ b/components/soc/esp32c61/wdt_periph.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/wdt_periph.h" diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 05ae236a59df..de6392554628 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1135,6 +1135,10 @@ config SOC_MWDT_SUPPORT_XTAL bool default y +config SOC_MWDT_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_TWAI_CONTROLLER_NUM int default 1 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 16c4b71bac47..79b8323a75e1 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -445,6 +445,7 @@ /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ #define SOC_MWDT_SUPPORT_XTAL (1) +#define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- TWAI CAPS ---------------------------------------*/ #define SOC_TWAI_CONTROLLER_NUM 1UL diff --git a/components/soc/esp32h2/include/soc/soc_etm_struct.h b/components/soc/esp32h2/include/soc/soc_etm_struct.h index 5e8f2dea6bba..3c62027ae5a4 100644 --- a/components/soc/esp32h2/include/soc/soc_etm_struct.h +++ b/components/soc/esp32h2/include/soc/soc_etm_struct.h @@ -735,8 +735,8 @@ typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; volatile struct { - soc_etm_chn_evt_id_reg_t evt_id; - soc_etm_chn_task_id_reg_t task_id; + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; } channel[50]; volatile soc_etm_clk_en_reg_t clk_en; volatile soc_etm_date_reg_t date; diff --git a/components/soc/esp32h2/timer_periph.c b/components/soc/esp32h2/timer_periph.c index 422b536f37a4..58750906fd8f 100644 --- a/components/soc/esp32h2/timer_periph.c +++ b/components/soc/esp32h2/timer_periph.c @@ -23,68 +23,111 @@ const timer_group_signal_conn_t timer_group_periph_signals = { } }; -#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG - -static const regdma_entries_config_t tg0_wdt_regs_retention[] = { - /*Timer group backup. should get of write project firstly. wdt used by RTOS.*/ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -static const regdma_entries_config_t tg1_wdt_regs_retention[] = { - /*Timer group0 backup. T0_wdt should get of write project firstly. wdt used by RTOS.*/ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - /* Registers in retention context: * TIMG_T0CONFIG_REG * TIMG_T0ALARMLO_REG * TIMG_T0ALARMHI_REG + * TIMG_T0LOADLO_REG + * TIMG_T0LOADHI_REG * TIMG_INT_ENA_TIMERS_REG * TIMG_REGCLK_REG */ -#define N_REGS_TG_TIMER_CFG 5 -static const uint32_t tg_timer_regs_map[4] = {0x10000031, 0x80000000, 0, 0}; +#define TG_TIMER_RETENTION_REGS_CNT 7 +static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0}; -const regdma_entries_config_t tg0_timer_regs_retention[] = { +const regdma_entries_config_t tg0_timer_regdma_entries[] = { + // backup stage: trigger a soft capture [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x00), TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), N_REGS_TG_TIMER_CFG, 0, 0, \ - tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02), + TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03), + TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x04), + TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [5] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x05), + TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x01), TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02), TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03), TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x04), TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05), TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; -const regdma_entries_config_t tg1_timer_regs_retention[] = { +const regdma_entries_config_t tg1_timer_regdma_entries[] = { + // backup stage: trigger a soft capture [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x00), TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), N_REGS_TG_TIMER_CFG, 0, 0, \ - tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]), .owner = ENTRY(0) | ENTRY(2) + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00), + TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: wait for the capture done + [1] = { + .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01), + TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save the captured counter value + // restore stage: store the captured counter value to the loader register + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02), + TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [3] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03), + TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a soft reload, so the timer can continue from where it was backed up + [4] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x04), + TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + // backup stage: save other configuration and status registers + // restore stage: restore the configuration and status registers + [5] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x05), + TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), + TG_TIMER_RETENTION_REGS_CNT, 0, 0, + tg_timer_regs_map[0], tg_timer_regs_map[1], + tg_timer_regs_map[2], tg_timer_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x01), TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02), TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, - [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03), TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x04), TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, -}; - -const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { - [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, - [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, }; -const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = { - [0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)}, - [1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)}, +const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = { + [0] = { + .regdma_entry_array = tg0_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg0_timer_regdma_entries) + }, + [1] = { + .regdma_entry_array = tg1_timer_regdma_entries, + .array_size = ARRAY_SIZE(tg1_timer_regdma_entries) + }, }; diff --git a/components/soc/esp32h2/wdt_periph.c b/components/soc/esp32h2/wdt_periph.c new file mode 100644 index 000000000000..f615401cfa8f --- /dev/null +++ b/components/soc/esp32h2/wdt_periph.c @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/wdt_periph.h" + +#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG + +static const regdma_entries_config_t tg0_wdt_regs_retention[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; + +static const regdma_entries_config_t tg1_wdt_regs_retention[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; + +const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = { + [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)}, + [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)}, +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index c73776ac9806..624c2d2c3cb8 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1095,10 +1095,22 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH int default 16 +config SOC_PARLIO_TX_CLK_SUPPORT_GATING + bool + default y + +config SOC_PARLIO_RX_CLK_SUPPORT_GATING + bool + default y + config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT bool default y +config SOC_PARLIO_TRANS_BIT_ALIGN + bool + default y + config SOC_PARLIO_TX_SIZE_BY_DMA bool default y @@ -1399,6 +1411,10 @@ config SOC_MWDT_SUPPORT_XTAL bool default y +config SOC_MWDT_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_TOUCH_SENSOR_VERSION int default 3 @@ -1627,6 +1643,10 @@ config SOC_PM_SUPPORT_CNNT_PD bool default y +config SOC_PM_SUPPORT_RTC_PERIPH_PD + bool + default y + config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY bool default y diff --git a/components/soc/esp32p4/include/soc/lp_analog_peri_reg.h b/components/soc/esp32p4/include/soc/lp_analog_peri_reg.h index 68fcde9d0d31..cfd26fd01649 100644 --- a/components/soc/esp32p4/include/soc/lp_analog_peri_reg.h +++ b/components/soc/esp32p4/include/soc/lp_analog_peri_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -619,13 +619,13 @@ extern "C" { * need_des */ #define LP_ANALOG_PERI_TOUCH_FILTER1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x110) -/** LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN : R/W; bitpos: [0]; default: 0; +/** LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN : R/W; bitpos: [0]; default: 0; * Reserved */ -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN (BIT(0)) -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_M (LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_V << LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_S) -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_V 0x00000001U -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_S 0 +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN (BIT(0)) +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_M (LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_V << LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_S) +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BASELINE_EN_S 0 /** LP_ANALOG_PERI_TOUCH_HYSTERESIS : R/W; bitpos: [2:1]; default: 0; * need_des */ @@ -633,13 +633,13 @@ extern "C" { #define LP_ANALOG_PERI_TOUCH_HYSTERESIS_M (LP_ANALOG_PERI_TOUCH_HYSTERESIS_V << LP_ANALOG_PERI_TOUCH_HYSTERESIS_S) #define LP_ANALOG_PERI_TOUCH_HYSTERESIS_V 0x00000003U #define LP_ANALOG_PERI_TOUCH_HYSTERESIS_S 1 -/** LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [4:3]; default: 0; +/** LP_ANALOG_PERI_TOUCH_NN_THRES : R/W; bitpos: [4:3]; default: 0; * need_des */ -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES 0x00000003U -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_M (LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_S) -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_V 0x00000003U -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_S 3 +#define LP_ANALOG_PERI_TOUCH_NN_THRES 0x00000003U +#define LP_ANALOG_PERI_TOUCH_NN_THRES_M (LP_ANALOG_PERI_TOUCH_NN_THRES_V << LP_ANALOG_PERI_TOUCH_NN_THRES_S) +#define LP_ANALOG_PERI_TOUCH_NN_THRES_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_NN_THRES_S 3 /** LP_ANALOG_PERI_TOUCH_NOISE_THRES : R/W; bitpos: [6:5]; default: 0; * need_des */ @@ -675,13 +675,13 @@ extern "C" { #define LP_ANALOG_PERI_TOUCH_FILTER_EN_M (LP_ANALOG_PERI_TOUCH_FILTER_EN_V << LP_ANALOG_PERI_TOUCH_FILTER_EN_S) #define LP_ANALOG_PERI_TOUCH_FILTER_EN_V 0x00000001U #define LP_ANALOG_PERI_TOUCH_FILTER_EN_S 16 -/** LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [20:17]; default: 5; +/** LP_ANALOG_PERI_TOUCH_NN_LIMIT : R/W; bitpos: [20:17]; default: 5; * need_des */ -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT 0x0000000FU -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_M (LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_V << LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_S) -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_V 0x0000000FU -#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_S 17 +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_M (LP_ANALOG_PERI_TOUCH_NN_LIMIT_V << LP_ANALOG_PERI_TOUCH_NN_LIMIT_S) +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_S 17 /** LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT : R/W; bitpos: [28:21]; default: 80; * need_des */ @@ -715,13 +715,13 @@ extern "C" { #define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_M (LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S) #define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V 0x00000001U #define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S 30 -/** LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES : R/W; bitpos: [31]; default: 0; +/** LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES : R/W; bitpos: [31]; default: 0; * need_des */ -#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(31)) -#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_M (LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_S) -#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_V 0x00000001U -#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_S 31 +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES (BIT(31)) +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_M (LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_S) +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_S 31 /** LP_ANALOG_PERI_TOUCH_FILTER3_REG register * need_des diff --git a/components/soc/esp32p4/include/soc/lp_analog_peri_struct.h b/components/soc/esp32p4/include/soc/lp_analog_peri_struct.h index e50534067c7a..2819658d26e8 100644 --- a/components/soc/esp32p4/include/soc/lp_analog_peri_struct.h +++ b/components/soc/esp32p4/include/soc/lp_analog_peri_struct.h @@ -510,18 +510,18 @@ typedef union { */ typedef union { struct { - /** touch_neg_noise_disupdate_baseline_en : R/W; bitpos: [0]; default: 0; + /** touch_nn_disupdate_baseline_en : R/W; bitpos: [0]; default: 0; * Reserved */ - uint32_t touch_neg_noise_disupdate_baseline_en:1; + uint32_t touch_nn_disupdate_baseline_en:1; /** touch_hysteresis : R/W; bitpos: [2:1]; default: 0; * need_des */ uint32_t touch_hysteresis:2; - /** touch_neg_noise_thres : R/W; bitpos: [4:3]; default: 0; + /** touch_nn_thres : R/W; bitpos: [4:3]; default: 0; * need_des */ - uint32_t touch_neg_noise_thres:2; + uint32_t touch_nn_thres:2; /** touch_noise_thres : R/W; bitpos: [6:5]; default: 0; * need_des */ @@ -542,10 +542,10 @@ typedef union { * need_des */ uint32_t touch_filter_en:1; - /** touch_neg_noise_limit : R/W; bitpos: [20:17]; default: 5; + /** touch_nn_limit : R/W; bitpos: [20:17]; default: 5; * need_des */ - uint32_t touch_neg_noise_limit:4; + uint32_t touch_nn_limit:4; /** touch_approach_limit : R/W; bitpos: [28:21]; default: 80; * need_des */ @@ -572,10 +572,10 @@ typedef union { * need_des */ uint32_t touch_bypass_noise_thres:1; - /** touch_bypass_neg_noise_thres : R/W; bitpos: [31]; default: 0; + /** touch_bypass_nn_thres : R/W; bitpos: [31]; default: 0; * need_des */ - uint32_t touch_bypass_neg_noise_thres:1; + uint32_t touch_bypass_nn_thres:1; }; uint32_t val; } lp_analog_peri_touch_filter2_reg_t; diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h b/components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h index 8cd55877c26c..2eaeaecdae1c 100644 --- a/components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h +++ b/components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1943,11 +1943,11 @@ typedef struct dsi_host_dev_t { volatile dsi_host_gen_pld_data_reg_t gen_pld_data; volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status; volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg; - volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_to_cnt; - volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_to_cnt; - volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_to_cnt; - volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_to_cnt; - volatile dsi_host_bta_to_cnt_reg_t bta_to_cnt; + volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_timeout_cnt; + volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_timeout_cnt; + volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_timeout_cnt; + volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_timeout_cnt; + volatile dsi_host_bta_to_cnt_reg_t bta_timeout_cnt; volatile dsi_host_sdf_3d_reg_t sdf_3d; volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl; volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg; diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 72d13459779e..a9e10dca9b49 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -417,7 +417,10 @@ #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ +#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */ +#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */ #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */ +#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */ #define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */ /*--------------------------- MPI CAPS ---------------------------------------*/ @@ -546,6 +549,7 @@ /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ #define SOC_MWDT_SUPPORT_XTAL (1) +#define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ #define SOC_TOUCH_SENSOR_VERSION (3) /*!< Hardware version of touch sensor */ @@ -634,6 +638,7 @@ #define SOC_PM_SUPPORT_VDDSDIO_PD (1) #define SOC_PM_SUPPORT_TOP_PD (1) #define SOC_PM_SUPPORT_CNNT_PD (1) +#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*! +#include "soc/timer_group_reg.h" +#include "soc/timer_group_struct.h" +#include "soc/soc_caps.h" +#include "soc/periph_defs.h" +#include "soc/regdma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +#if SOC_MWDT_SUPPORT_SLEEP_RETENTION +typedef struct { + const regdma_entries_config_t *link_list; + uint32_t link_num; +} tg_reg_ctx_link_t; + +extern const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS]; +#endif // SOC_MWDT_SUPPORT_SLEEP_RETENTION + +#ifdef __cplusplus +} +#endif diff --git a/components/tcp_transport/transport.c b/components/tcp_transport/transport.c index 5ec219512572..de1924e4af2a 100644 --- a/components/tcp_transport/transport.c +++ b/components/tcp_transport/transport.c @@ -271,6 +271,9 @@ int esp_transport_get_errno(esp_transport_handle_t t) void capture_tcp_transport_error(esp_transport_handle_t t, enum esp_tcp_transport_err_t error) { esp_tls_last_error_t *err_handle = esp_transport_get_error_handle(t); + if (err_handle == NULL) { + return; + } switch (error) { case ERR_TCP_TRANSPORT_CONNECTION_CLOSED_BY_FIN: err_handle->last_error = ESP_ERR_ESP_TLS_TCP_CLOSED_FIN; diff --git a/components/tcp_transport/transport_ssl.c b/components/tcp_transport/transport_ssl.c index 7f0a4d78f386..a11f160fbcff 100644 --- a/components/tcp_transport/transport_ssl.c +++ b/components/tcp_transport/transport_ssl.c @@ -61,6 +61,8 @@ static inline transport_esp_tls_t *ssl_get_context_data(esp_transport_handle_t t static int esp_tls_connect_async(esp_transport_handle_t t, const char *host, int port, int timeout_ms, bool is_plain_tcp) { transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); + if (ssl->conn_state == TRANS_SSL_INIT) { ssl->cfg.timeout_ms = timeout_ms; ssl->cfg.is_plain_tcp = is_plain_tcp; @@ -101,6 +103,7 @@ static inline int tcp_connect_async(esp_transport_handle_t t, const char *host, static int ssl_connect(esp_transport_handle_t t, const char *host, int port, int timeout_ms) { transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); ssl->cfg.timeout_ms = timeout_ms; @@ -139,6 +142,7 @@ static int tcp_connect(esp_transport_handle_t t, const char *host, int port, int { transport_esp_tls_t *ssl = ssl_get_context_data(t); esp_tls_last_error_t *err_handle = esp_transport_get_error_handle(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); ssl->cfg.timeout_ms = timeout_ms; esp_err_t err = esp_tls_plain_tcp_connect(host, strlen(host), port, &ssl->cfg, err_handle, &ssl->sockfd); @@ -154,6 +158,7 @@ static int tcp_connect(esp_transport_handle_t t, const char *host, int port, int static int base_poll_read(esp_transport_handle_t t, int timeout_ms) { transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); int ret = -1; int remain = 0; struct timeval timeout; @@ -185,6 +190,7 @@ static int base_poll_read(esp_transport_handle_t t, int timeout_ms) static int base_poll_write(esp_transport_handle_t t, int timeout_ms) { transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); int ret = -1; struct timeval timeout; fd_set writeset; @@ -211,6 +217,7 @@ static int ssl_write(esp_transport_handle_t t, const char *buffer, int len, int { int poll; transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); if ((poll = esp_transport_poll_write(t, timeout_ms)) <= 0) { ESP_LOGW(TAG, "Poll timeout or error, errno=%s, fd=%d, timeout_ms=%d", strerror(errno), ssl->sockfd, timeout_ms); @@ -233,6 +240,7 @@ static int tcp_write(esp_transport_handle_t t, const char *buffer, int len, int { int poll; transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); if ((poll = esp_transport_poll_write(t, timeout_ms)) <= 0) { ESP_LOGW(TAG, "Poll timeout or error, errno=%s, fd=%d, timeout_ms=%d", strerror(errno), ssl->sockfd, timeout_ms); @@ -249,6 +257,7 @@ static int tcp_write(esp_transport_handle_t t, const char *buffer, int len, int static int ssl_read(esp_transport_handle_t t, char *buffer, int len, int timeout_ms) { transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); int poll = esp_transport_poll_read(t, timeout_ms); if (poll == -1) { @@ -284,6 +293,7 @@ static int ssl_read(esp_transport_handle_t t, char *buffer, int len, int timeout static int tcp_read(esp_transport_handle_t t, char *buffer, int len, int timeout_ms) { transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); int poll = esp_transport_poll_read(t, timeout_ms); if (poll == -1) { @@ -316,6 +326,8 @@ static int base_close(esp_transport_handle_t t) { int ret = -1; transport_esp_tls_t *ssl = ssl_get_context_data(t); + ESP_STATIC_ANALYZER_CHECK(ssl == NULL, -1); + if (ssl && ssl->ssl_initialized) { ret = esp_tls_conn_destroy(ssl->tls); ssl->tls = NULL; diff --git a/components/tcp_transport/transport_ws.c b/components/tcp_transport/transport_ws.c index 529494ca09da..f7434aa02fba 100644 --- a/components/tcp_transport/transport_ws.c +++ b/components/tcp_transport/transport_ws.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -104,6 +104,8 @@ static esp_transport_handle_t ws_get_payload_transport_handle(esp_transport_hand static int esp_transport_read_internal(transport_ws_t *ws, char *buffer, int len, int timeout_ms) { + ESP_STATIC_ANALYZER_CHECK(buffer == NULL, 0); + // No buffered data to read from, directly attempt to read from the transport. if (ws->buffer_len == 0) { return esp_transport_read(ws->parent, buffer, len, timeout_ms); diff --git a/components/ulp/cmake/CMakeLists.txt b/components/ulp/cmake/CMakeLists.txt index 05bddaa68d12..f08c3ab0a0e8 100644 --- a/components/ulp/cmake/CMakeLists.txt +++ b/components/ulp/cmake/CMakeLists.txt @@ -121,11 +121,7 @@ elseif(ULP_COCPU_IS_LP_CORE) target_link_options(${ULP_APP_NAME} PRIVATE -Wl,--gc-sections) target_link_options(${ULP_APP_NAME} PRIVATE -Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.map) - if(${IDF_TARGET} STREQUAL "esp32c5") - set(target_folder "esp32c5/mp") - else() - set(target_folder ${IDF_TARGET}) - endif() + set(target_folder ${IDF_TARGET}) target_link_options(${ULP_APP_NAME} PRIVATE SHELL:-T ${IDF_PATH}/components/soc/${target_folder}/ld/${IDF_TARGET}.peripherals.ld) diff --git a/components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h b/components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h index f75771197435..8d20d1f43c0d 100644 --- a/components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h +++ b/components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h @@ -7,13 +7,14 @@ #pragma once #include "sdkconfig.h" +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { #endif -#if CONFIG_IDF_TARGET_ESP32C6 -#define LP_CORE_ISR_ATTR // On C6 registers are saved by us before calling the ISR +#if SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR +#define LP_CORE_ISR_ATTR // On chips with just a single interrupt entry point registers are saved by us before calling the ISR #else #define LP_CORE_ISR_ATTR __attribute__((interrupt)) #endif diff --git a/components/ulp/lp_core/lp_core/lp_core_interrupt.c b/components/ulp/lp_core/lp_core/lp_core_interrupt.c index a24b7953e13e..63de987f52f3 100644 --- a/components/ulp/lp_core/lp_core/lp_core_interrupt.c +++ b/components/ulp/lp_core/lp_core/lp_core_interrupt.c @@ -7,11 +7,12 @@ #include #include "sdkconfig.h" +#include "soc/soc_caps.h" #include "hal/lp_core_ll.h" #include "riscv/rv_utils.h" #include "riscv/rvruntime-frames.h" -#if CONFIG_IDF_TARGET_ESP32C6 +#if SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR /* Enable interrupt 30, which all external interrupts are routed to*/ #define MIE_ALL_INTS_MASK (1 << 30) #else @@ -66,7 +67,7 @@ void __attribute__((weak, alias("ulp_lp_core_default_intr_handler"))) ulp_lp_cor void __attribute__((weak, alias("ulp_lp_core_default_intr_handler"))) ulp_lp_core_lp_rtc_intr_handler(void); void __attribute__((weak, alias("ulp_lp_core_default_intr_handler"))) ulp_lp_core_sw_intr_handler(void); -#if CONFIG_IDF_TARGET_ESP32C6 +#if SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR static void* s_intr_handlers[] = { ulp_lp_core_lp_io_intr_handler, @@ -90,4 +91,4 @@ void __attribute__((weak)) ulp_lp_core_intr_handler(void) } } -#endif +#endif //SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR diff --git a/components/ulp/lp_core/lp_core/port/esp32c5/vector_table.S b/components/ulp/lp_core/lp_core/port/esp32c5/vector_table.S new file mode 100644 index 000000000000..a1309e3cf817 --- /dev/null +++ b/components/ulp/lp_core/lp_core/port/esp32c5/vector_table.S @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + .section .init.vector,"ax" + + .global _vector_table + .type _vector_table, @function +_vector_table: + .option push + .option norvc + + .rept 30 + j _panic_handler + .endr + j _interrupt_handler // All interrupts are routed to mtvec + 4*30, i.e. the 31st entry + j _panic_handler + + .option pop + .size _vector_table, .-_vector_table diff --git a/components/ulp/test_apps/lp_core/README.md b/components/ulp/test_apps/lp_core/README.md index b38644435588..59db987a228b 100644 --- a/components/ulp/test_apps/lp_core/README.md +++ b/components/ulp/test_apps/lp_core/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | diff --git a/components/ulp/test_apps/lp_core/main/test_lp_core.c b/components/ulp/test_apps/lp_core/main/test_lp_core.c index 2545d4a3ac7a..bc1102c75fe3 100644 --- a/components/ulp/test_apps/lp_core/main/test_lp_core.c +++ b/components/ulp/test_apps/lp_core/main/test_lp_core.c @@ -8,7 +8,6 @@ #include #include #include "soc/soc_caps.h" -#include "soc/gpio_num.h" #include "esp_rom_caps.h" #include "lp_core_test_app.h" #include "lp_core_test_app_counter.h" @@ -321,6 +320,7 @@ TEST_CASE("LP core can schedule next wake-up time by itself", "[ulp]") TEST_ASSERT_INT_WITHIN_MESSAGE(5, expected_run_count, ulp_set_timer_wakeup_counter, "LP Core did not wake up the expected number of times"); } +#if SOC_RTCIO_PIN_COUNT > 0 TEST_CASE("LP core gpio tests", "[ulp]") { /* Load ULP firmware and start the coprocessor */ @@ -337,19 +337,15 @@ TEST_CASE("LP core gpio tests", "[ulp]") TEST_ASSERT_TRUE(ulp_gpio_test_succeeded); } +#endif //SOC_RTCIO_PIN_COUNT > 0 #endif //SOC_LP_TIMER_SUPPORTED #define ISR_TEST_ITERATIONS 100 #define IO_TEST_PIN 0 -#include "lp_core_uart.h" TEST_CASE("LP core ISR tests", "[ulp]") { - lp_core_uart_cfg_t ucfg = LP_CORE_UART_DEFAULT_CONFIG(); - - ESP_ERROR_CHECK(lp_core_uart_init(&ucfg)); - /* Load ULP firmware and start the coprocessor */ ulp_lp_core_cfg_t cfg = { .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU, @@ -368,6 +364,7 @@ TEST_CASE("LP core ISR tests", "[ulp]") printf("ULP PMU ISR triggered %"PRIu32" times\n", ulp_pmu_isr_counter); TEST_ASSERT_EQUAL(ISR_TEST_ITERATIONS, ulp_pmu_isr_counter); +#if SOC_RTCIO_PIN_COUNT > 0 /* Test LP IO interrupt */ rtc_gpio_init(IO_TEST_PIN); rtc_gpio_set_direction(IO_TEST_PIN, RTC_GPIO_MODE_INPUT_ONLY); @@ -384,4 +381,6 @@ TEST_CASE("LP core ISR tests", "[ulp]") printf("ULP LP IO ISR triggered %"PRIu32" times\n", ulp_io_isr_counter); TEST_ASSERT_EQUAL(ISR_TEST_ITERATIONS, ulp_io_isr_counter); +#endif //SOC_RTCIO_PIN_COUNT > 0 + } diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h index 11e486c2f6d2..504b2e0c9138 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h @@ -109,7 +109,7 @@ static inline uint8_t ulp_riscv_gpio_get_level(gpio_num_t gpio_num) static inline void ulp_riscv_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode) { - REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_DRV, mode); + REG_SET_FIELD(RTC_GPIO_PIN0_REG + gpio_num * 4, RTC_GPIO_PIN0_PAD_DRIVER, mode); } static inline void ulp_riscv_gpio_pullup(gpio_num_t gpio_num) diff --git a/components/ulp/ulp_riscv/ulp_riscv_i2c.c b/components/ulp/ulp_riscv/ulp_riscv_i2c.c index a56be4c1bd26..3d73b22e376d 100644 --- a/components/ulp/ulp_riscv/ulp_riscv_i2c.c +++ b/components/ulp/ulp_riscv/ulp_riscv_i2c.c @@ -47,6 +47,9 @@ rtc_io_dev_t *rtc_io_dev = &RTCIO; /* Read/Write timeout (number of iterations)*/ #define ULP_RISCV_I2C_RW_TIMEOUT CONFIG_ULP_RISCV_I2C_RW_TIMEOUT +/* RTC I2C lock */ +static portMUX_TYPE rtc_i2c_lock = portMUX_INITIALIZER_UNLOCKED; + static esp_err_t i2c_gpio_is_cfg_valid(gpio_num_t sda_io_num, gpio_num_t scl_io_num) { /* Verify that the SDA and SCL GPIOs are valid RTC I2C io pins */ @@ -348,6 +351,8 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size) SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); + portENTER_CRITICAL(&rtc_i2c_lock); + for (i = 0; i < size; i++) { /* Poll for RTC I2C Rx Data interrupt bit to be set */ ret = ulp_riscv_i2c_wait_for_interrupt(ULP_RISCV_I2C_RW_TIMEOUT); @@ -368,15 +373,17 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size) /* Clear the Rx data interrupt bit */ SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_RX_DATA_INT_CLR); } else { - ESP_LOGE(RTCI2C_TAG, "Read Failed!"); + ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Read Failed!"); uint32_t status = READ_PERI_REG(RTC_I2C_INT_RAW_REG); - ESP_LOGE(RTCI2C_TAG, "RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status); - ESP_LOGE(RTCI2C_TAG, "RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG)); + ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status); + ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG)); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status); break; } } + portEXIT_CRITICAL(&rtc_i2c_lock); + /* Clear the RTC I2C transmission bits */ CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); @@ -422,6 +429,8 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size) /* Configure the RTC I2C controller in write mode */ SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0x1, 1, 27); + portENTER_CRITICAL(&rtc_i2c_lock); + for (i = 0; i < size; i++) { /* Write the data to be transmitted */ CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, I2C_CTRL_MASTER_TX_DATA_MASK); @@ -440,15 +449,17 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size) /* Clear the Tx data interrupt bit */ SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR); } else { - ESP_LOGE(RTCI2C_TAG, "Write Failed!"); + ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Write Failed!"); uint32_t status = READ_PERI_REG(RTC_I2C_INT_RAW_REG); - ESP_LOGE(RTCI2C_TAG, "RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status); - ESP_LOGE(RTCI2C_TAG, "RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG)); + ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status); + ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG)); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status); break; } } + portEXIT_CRITICAL(&rtc_i2c_lock); + /* Clear the RTC I2C transmission bits */ CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); @@ -505,7 +516,7 @@ esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg) i2c_dev->i2c_ctrl.i2c_i2c_ctrl_clk_gate_en = 1; #endif // CONFIG_IDF_TARGET_ESP32S2 - /* Configure RTC I2C timing paramters */ + /* Configure RTC I2C timing parameters */ ESP_RETURN_ON_ERROR(i2c_set_timing(cfg), RTCI2C_TAG, "Failed to configure RTC I2C timing"); /* Enable RTC I2C interrupts */ diff --git a/components/usb/CMakeLists.txt b/components/usb/CMakeLists.txt index ce87157e50e5..8eca16596fea 100644 --- a/components/usb/CMakeLists.txt +++ b/components/usb/CMakeLists.txt @@ -34,3 +34,7 @@ idf_component_register(SRCS ${srcs} PRIV_INCLUDE_DIRS ${priv_includes} PRIV_REQUIRES ${priv_requires} ) + +if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO GCC-366 (segfault) + set_property(SOURCE usb_host.c PROPERTY COMPILE_FLAGS -fno-analyzer) +endif() diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c index ebfd2c8e79c6..8187eea96703 100644 --- a/components/usb/hcd_dwc.c +++ b/components/usb/hcd_dwc.c @@ -1593,9 +1593,12 @@ static dma_buffer_block_t *buffer_block_alloc(usb_transfer_type_t type) break; } dma_buffer_block_t *buffer = calloc(1, sizeof(dma_buffer_block_t)); + if (buffer == NULL) { + return NULL; + } size_t real_len = 0; void *xfer_desc_list = transfer_descriptor_list_alloc(desc_list_len, &real_len); - if (buffer == NULL || xfer_desc_list == NULL) { + if (xfer_desc_list == NULL) { free(buffer); heap_caps_free(xfer_desc_list); return NULL; diff --git a/components/usb/include/usb/usb_host.h b/components/usb/include/usb/usb_host.h index ba44c584d17b..823a42b1585f 100644 --- a/components/usb/include/usb/usb_host.h +++ b/components/usb/include/usb/usb_host.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -346,6 +346,35 @@ esp_err_t usb_host_get_device_descriptor(usb_device_handle_t dev_hdl, const usb_ */ esp_err_t usb_host_get_active_config_descriptor(usb_device_handle_t dev_hdl, const usb_config_desc_t **config_desc); +/** + * @brief Get get device's configuration descriptor + * + * - The USB Host library only caches a device's active configuration descriptor. + * - This function reads any configuration descriptor of a particular device (specified by bConfigurationValue). + * - This function will read the specified configuration descriptor via control transfers, and allocate memory to store that descriptor. + * - Users can call usb_host_get_config_desc_free() to free the descriptor's memory afterwards. + * + * @note This function can block + * @note A client must call usb_host_device_open() on the device first + * @param[in] client_hdl Client handle - usb_host_client_handle_events() should be called repeatedly in a separate task to handle client events + * @param[in] dev_hdl Device handle + * @param[out] config_desc_ret Returned configuration descriptor + * @param[in] bConfigurationValue Index of device's configuration descriptor to be read + * @note bConfigurationValue starts from index 1 + * @return esp_err_t + */ +esp_err_t usb_host_get_config_desc(usb_host_client_handle_t client_hdl, usb_device_handle_t dev_hdl, uint8_t bConfigurationValue, const usb_config_desc_t **config_desc_ret); + +/** + * @brief Free a configuration descriptor + * + * This function frees a configuration descriptor that was returned by usb_host_get_config_desc() + * + * @param[out] config_desc Configuration descriptor + * @return esp_err_t + */ +esp_err_t usb_host_get_config_desc_free(const usb_config_desc_t *config_desc); + // ----------------------------------------------- Interface Functions ------------------------------------------------- /** diff --git a/components/usb/test_apps/usb_host/main/multiconf_client.h b/components/usb/test_apps/usb_host/main/multiconf_client.h new file mode 100644 index 000000000000..b5af74db74ff --- /dev/null +++ b/components/usb/test_apps/usb_host/main/multiconf_client.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +typedef struct { + SemaphoreHandle_t dev_open_smp; + uint8_t bConfigurationValue; +} multiconf_client_test_param_t; + +/** + * @brief Multiconfiguration client task + */ +void multiconf_client_async_task(void *arg); + +/** + * @brief Get configuration descriptor + */ +void multiconf_client_get_conf_desc(void); diff --git a/components/usb/test_apps/usb_host/main/multiconf_client_async.c b/components/usb/test_apps/usb_host/main/multiconf_client_async.c new file mode 100644 index 000000000000..26e67069a9ae --- /dev/null +++ b/components/usb/test_apps/usb_host/main/multiconf_client_async.c @@ -0,0 +1,179 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "esp_err.h" +#include "esp_log.h" +#include "test_usb_common.h" +#include "multiconf_client.h" +#include "mock_msc.h" +#include "dev_msc.h" +#include "usb/usb_host.h" +#include "unity.h" + +/* +Implementation of a multi-configuration client used for USB Host Tests. + +- The multi-configuration client will: + - Register itself as a client + - Receive USB_HOST_CLIENT_EVENT_NEW_DEV event message, and open the device + - Get active configuration descriptor + - Start handling client events + - Wait for a request from main task to read a configuration descriptor + - Compare the obtained configuration descriptor with the active configuration descriptor + - Free the memory used for storing the configuration descriptor + - Close the device + - Deregister control client +*/ + +const char *MULTICONF_CLIENT_TAG = "Multi config Client"; + +#define CLIENT_NUM_EVENT_MSG 5 + +typedef enum { + TEST_STAGE_WAIT_CONN, + TEST_STAGE_DEV_OPEN, + TEST_STAGE_WAIT, + TEST_STAGE_CHECK_CONFIG_DESC, + TEST_STAGE_DEV_CLOSE, +} test_stage_t; + +typedef struct { + // Test parameters + multiconf_client_test_param_t test_param; + // device info + uint8_t dev_addr; + usb_speed_t dev_speed; + // Client variables + usb_host_client_handle_t client_hdl; + usb_device_handle_t dev_hdl; + // Test state + test_stage_t cur_stage; + test_stage_t next_stage; + const usb_config_desc_t *config_desc_cached; +} multiconf_client_obj_t; + +static multiconf_client_obj_t *s_multiconf_obj; + +static void multiconf_client_event_cb(const usb_host_client_event_msg_t *event_msg, void *arg) +{ + multiconf_client_obj_t *multiconf_obj = (multiconf_client_obj_t *)arg; + switch (event_msg->event) { + case USB_HOST_CLIENT_EVENT_NEW_DEV: + TEST_ASSERT_EQUAL(TEST_STAGE_WAIT_CONN, multiconf_obj->cur_stage); + multiconf_obj->next_stage = TEST_STAGE_DEV_OPEN; + multiconf_obj->dev_addr = event_msg->new_dev.address; + break; + default: + abort(); // Should never occur in this test + break; + } +} + +void multiconf_client_async_task(void *arg) +{ + multiconf_client_obj_t multiconf_obj; + // Initialize test params + memcpy(&multiconf_obj.test_param, arg, sizeof(multiconf_client_test_param_t)); + // Initialize client variables + multiconf_obj.client_hdl = NULL; + multiconf_obj.dev_hdl = NULL; + // Initialize test stage + multiconf_obj.cur_stage = TEST_STAGE_WAIT_CONN; + multiconf_obj.next_stage = TEST_STAGE_WAIT_CONN; + multiconf_obj.dev_addr = 0; + + // Register client + usb_host_client_config_t client_config = { + .is_synchronous = false, + .max_num_event_msg = CLIENT_NUM_EVENT_MSG, + .async = { + .client_event_callback = multiconf_client_event_cb, + .callback_arg = (void *) &multiconf_obj, + }, + }; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_client_register(&client_config, &multiconf_obj.client_hdl)); + s_multiconf_obj = &multiconf_obj; + + // Wait to be started by main thread + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + ESP_LOGD(MULTICONF_CLIENT_TAG, "Starting"); + + bool exit_loop = false; + bool skip_event_handling = false; + while (!exit_loop) { + if (!skip_event_handling) { + TEST_ASSERT_EQUAL(ESP_OK, usb_host_client_handle_events(multiconf_obj.client_hdl, portMAX_DELAY)); + } + skip_event_handling = false; + if (multiconf_obj.cur_stage == multiconf_obj.next_stage) { + continue; + } + multiconf_obj.cur_stage = multiconf_obj.next_stage; + + switch (multiconf_obj.next_stage) { + case TEST_STAGE_DEV_OPEN: { + ESP_LOGD(MULTICONF_CLIENT_TAG, "Open"); + // Open the device + TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, usb_host_device_open(multiconf_obj.client_hdl, multiconf_obj.dev_addr, &multiconf_obj.dev_hdl), "Failed to open the device"); + + // Get device info to get it's speed + usb_device_info_t dev_info; + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_info(multiconf_obj.dev_hdl, &dev_info)); + multiconf_obj.dev_speed = dev_info.speed; + + multiconf_obj.next_stage = TEST_STAGE_WAIT; + skip_event_handling = true; + break; + } + case TEST_STAGE_WAIT: { + // Give semaphore signalizing that the device has been opened + xSemaphoreGive(multiconf_obj.test_param.dev_open_smp); + break; + } + case TEST_STAGE_CHECK_CONFIG_DESC: { + ESP_LOGD(MULTICONF_CLIENT_TAG, "Check config descriptors"); + // Get mocked config descriptor + const usb_config_desc_t *config_desc_ref = dev_msc_get_config_desc(multiconf_obj.dev_speed); + TEST_ASSERT_EQUAL_MESSAGE(multiconf_obj.config_desc_cached->wTotalLength, config_desc_ref->wTotalLength, "Incorrect length of CFG descriptor"); + TEST_ASSERT_EQUAL_MEMORY_MESSAGE(config_desc_ref, multiconf_obj.config_desc_cached, sizeof(usb_config_desc_t), "Configuration descriptors do not match"); + + // Free the memory used to store the config descriptor + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_config_desc_free(multiconf_obj.config_desc_cached)); + multiconf_obj.next_stage = TEST_STAGE_DEV_CLOSE; + skip_event_handling = true; + break; + } + case TEST_STAGE_DEV_CLOSE: { + ESP_LOGD(MULTICONF_CLIENT_TAG, "Close"); + vTaskDelay(10); // Give USB Host Lib some time to process all transfers + TEST_ASSERT_EQUAL(ESP_OK, usb_host_device_close(multiconf_obj.client_hdl, multiconf_obj.dev_hdl)); + exit_loop = true; + break; + } + default: + abort(); + break; + } + } + TEST_ASSERT_EQUAL(ESP_OK, usb_host_client_deregister(multiconf_obj.client_hdl)); + ESP_LOGD(MULTICONF_CLIENT_TAG, "Done"); + vTaskDelete(NULL); +} + +void multiconf_client_get_conf_desc(void) +{ + // Get configuration descriptor, ctrl transfer is sent to the device to get the config descriptor + TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_config_desc(s_multiconf_obj->client_hdl, s_multiconf_obj->dev_hdl, s_multiconf_obj->test_param.bConfigurationValue, &s_multiconf_obj->config_desc_cached)); + + // Go to next stage + s_multiconf_obj->next_stage = TEST_STAGE_CHECK_CONFIG_DESC; + ESP_ERROR_CHECK(usb_host_client_unblock(s_multiconf_obj->client_hdl)); +} diff --git a/components/usb/test_apps/usb_host/main/test_app_main.c b/components/usb/test_apps/usb_host/main/test_app_main.c index 93e2510374c7..de47f0b0f3f8 100644 --- a/components/usb/test_apps/usb_host/main/test_app_main.c +++ b/components/usb/test_apps/usb_host/main/test_app_main.c @@ -33,6 +33,8 @@ void tearDown(void) vTaskDelay(10); // Clean up USB Host ESP_ERROR_CHECK(usb_host_uninstall()); + // Short delay to allow task to be cleaned up after client uninstall + vTaskDelay(10); test_usb_deinit_phy(); // Deinitialize the internal USB PHY after testing unity_utils_evaluate_leaks(); } diff --git a/components/usb/test_apps/usb_host/main/test_usb_host_async.c b/components/usb/test_apps/usb_host/main/test_usb_host_async.c index c7329d91fa1c..0dac7076f5b3 100644 --- a/components/usb/test_apps/usb_host/main/test_usb_host_async.c +++ b/components/usb/test_apps/usb_host/main/test_usb_host_async.c @@ -14,6 +14,7 @@ #include "dev_msc.h" #include "msc_client.h" #include "ctrl_client.h" +#include "multiconf_client.h" #include "usb/usb_host.h" #include "unity.h" @@ -21,6 +22,7 @@ #define TEST_MSC_NUM_SECTORS_PER_XFER 2 #define TEST_MSC_SCSI_TAG 0xDEADBEEF #define TEST_CTRL_NUM_TRANSFERS 30 +#define B_CONFIGURATION_VALUE 1 // --------------------------------------------------- Test Cases ------------------------------------------------------ @@ -275,3 +277,66 @@ TEST_CASE("Test USB Host async API", "[usb_host][full_speed][low_speed]") vTaskDelay(10); } } + +/* +Test USB Host Asynchronous API single client + +Purpose: + - Test that client can read configuration descriptor by request + +Procedure: + - Install USB Host Library + - Create a task to run a multiconfig client + - Create a task to handle system events + - Start the MSC client task. It will open the device and start handling client events + - Wait for the main task requests client to read configuration descriptor + - Compare the requested configuration descriptor with the active configuration descriptor + - Wait for the host library event handler to report a USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS event + - Free all devices + - Uninstall USB Host Library +*/ +static void host_lib_task(void *arg) +{ + while (1) { + // Start handling system events + uint32_t event_flags; + usb_host_lib_handle_events(portMAX_DELAY, &event_flags); + if (event_flags & USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS) { + printf("No more clients\n"); + TEST_ASSERT_EQUAL(ESP_ERR_NOT_FINISHED, usb_host_device_free_all()); + } + if (event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) { + break; + } + } + + printf("Deleting host_lib_task\n"); + vTaskDelete(NULL); +} + +TEST_CASE("Test USB Host multiconfig client (single client)", "[usb_host][full_speed][high_speed]") +{ + SemaphoreHandle_t dev_open_smp = xSemaphoreCreateBinary(); + TaskHandle_t client_task; + + multiconf_client_test_param_t multiconf_params = { + .dev_open_smp = dev_open_smp, + .bConfigurationValue = B_CONFIGURATION_VALUE, + }; + + xTaskCreatePinnedToCore(multiconf_client_async_task, "async client", 4096, (void*)&multiconf_params, 2, &client_task, 0); + TEST_ASSERT_NOT_NULL_MESSAGE(client_task, "Failed to create async client task"); + // Start the task + xTaskNotifyGive(client_task); + + TaskHandle_t host_lib_task_hdl; + xTaskCreatePinnedToCore(host_lib_task, "host lib", 4096, NULL, 2, &host_lib_task_hdl, 0); + TEST_ASSERT_NOT_NULL_MESSAGE(host_lib_task_hdl, "Failed to create host lib task"); + + // Wait for the device to be open + xSemaphoreTake(dev_open_smp, portMAX_DELAY); + multiconf_client_get_conf_desc(); + + // Cleanup + vSemaphoreDelete(dev_open_smp); +} diff --git a/components/usb/usb_host.c b/components/usb/usb_host.c index 743a48639b86..1e1ca4c16f2d 100644 --- a/components/usb/usb_host.c +++ b/components/usb/usb_host.c @@ -10,6 +10,7 @@ Warning: The USB Host Library API is still a beta version and may be subject to #include #include +#include #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -50,6 +51,9 @@ static portMUX_TYPE host_lock = portMUX_INITIALIZER_UNLOCKED; #define PROCESS_REQUEST_PENDING_FLAG_HUB (1 << 1) #define PROCESS_REQUEST_PENDING_FLAG_ENUM (1 << 2) +#define SHORT_DESC_REQ_LEN 8 +#define CTRL_TRANSFER_MAX_DATA_LEN CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE + typedef struct ep_wrapper_s ep_wrapper_t; typedef struct interface_s interface_t; typedef struct client_s client_t; @@ -408,6 +412,12 @@ static bool endpoint_callback(usbh_ep_handle_t ep_hdl, usbh_ep_event_t ep_event, return yield; } +static void get_config_desc_transfer_cb(usb_transfer_t *transfer) +{ + SemaphoreHandle_t transfer_done = (SemaphoreHandle_t)transfer->context; + xSemaphoreGive(transfer_done); +} + // ------------------------------------------------ Library Functions -------------------------------------------------- // ----------------------- Public -------------------------- @@ -1022,6 +1032,135 @@ esp_err_t usb_host_get_active_config_descriptor(usb_device_handle_t dev_hdl, con return usbh_dev_get_config_desc(dev_hdl, config_desc); } +// ----------------- Descriptors Transfer Requests -------------------- + +static usb_transfer_status_t wait_for_transmission_done(usb_transfer_t *transfer) +{ + SemaphoreHandle_t transfer_done = (SemaphoreHandle_t)transfer->context; + xSemaphoreTake(transfer_done, portMAX_DELAY); + usb_transfer_status_t status = transfer->status; + + // EP0 halt->flush->clear is managed by USBH and lower layers + return status; +} + +static esp_err_t get_config_desc_transfer(usb_host_client_handle_t client_hdl, usb_transfer_t *ctrl_transfer, const int bConfigurationValue, const int num_bytes) +{ + const usb_device_desc_t *dev_desc; + ESP_ERROR_CHECK(usbh_dev_get_desc(ctrl_transfer->device_handle, &dev_desc)); + + usb_setup_packet_t *setup_pkt = (usb_setup_packet_t *)ctrl_transfer->data_buffer; + USB_SETUP_PACKET_INIT_GET_CONFIG_DESC(setup_pkt, bConfigurationValue - 1, num_bytes); + ctrl_transfer->num_bytes = sizeof(usb_setup_packet_t) + usb_round_up_to_mps(num_bytes, dev_desc->bMaxPacketSize0); + + // IN data stage should return exactly num_bytes (SHORT_DESC_REQ_LEN or wTotalLength) bytes + const int expect_num_bytes = sizeof(usb_setup_packet_t) + num_bytes; + + // Submit control transfer + esp_err_t ret = usb_host_transfer_submit_control(client_hdl, ctrl_transfer); + if (ret != ESP_OK) { + ESP_LOGE(USB_HOST_TAG, "Submit ctrl transfer failed"); + return ret; + } + + // Wait for transfer to finish + const usb_transfer_status_t status_short_desc = wait_for_transmission_done(ctrl_transfer); + if (status_short_desc != USB_TRANSFER_STATUS_COMPLETED) { + ESP_LOGE(USB_HOST_TAG, "Get config descriptor transfer status: %d", status_short_desc); + ret = ESP_ERR_INVALID_STATE; + return ret; + } + + // Check IN transfer returned the expected correct number of bytes + if ((expect_num_bytes != 0) && (ctrl_transfer->actual_num_bytes != expect_num_bytes)) { + if (ctrl_transfer->actual_num_bytes > expect_num_bytes) { + // The device returned more bytes than requested. + // This violates the USB specs chapter 9.3.5, but we can continue + ESP_LOGW(USB_HOST_TAG, "Incorrect number of bytes returned %d", ctrl_transfer->actual_num_bytes); + return ESP_OK; + } else { + // The device returned less bytes than requested. We cannot continue. + ESP_LOGE(USB_HOST_TAG, "Incorrect number of bytes returned %d", ctrl_transfer->actual_num_bytes); + return ESP_ERR_INVALID_RESPONSE; + } + } + return ESP_OK; +} + +esp_err_t usb_host_get_config_desc(usb_host_client_handle_t client_hdl, usb_device_handle_t dev_hdl, uint8_t bConfigurationValue, const usb_config_desc_t **config_desc_ret) +{ + esp_err_t ret = ESP_OK; + HOST_CHECK(client_hdl != NULL && dev_hdl != NULL && config_desc_ret != NULL, ESP_ERR_INVALID_ARG); + + // Get number of configurations + const usb_device_desc_t *dev_desc; + ESP_ERROR_CHECK(usbh_dev_get_desc(dev_hdl, &dev_desc)); + + HOST_CHECK(bConfigurationValue != 0, ESP_ERR_INVALID_ARG); + HOST_CHECK(bConfigurationValue <= dev_desc->bNumConfigurations, ESP_ERR_NOT_SUPPORTED); + + // Initialize transfer + usb_transfer_t *ctrl_transfer; + if (usb_host_transfer_alloc(sizeof(usb_setup_packet_t) + CTRL_TRANSFER_MAX_DATA_LEN, 0, &ctrl_transfer)) { + return ESP_ERR_NO_MEM; + } + + SemaphoreHandle_t transfer_done = xSemaphoreCreateBinary(); + if (transfer_done == NULL) { + ret = ESP_ERR_NO_MEM; + goto exit; + } + + ctrl_transfer->device_handle = dev_hdl; + ctrl_transfer->bEndpointAddress = 0; + ctrl_transfer->callback = get_config_desc_transfer_cb; + ctrl_transfer->context = (void *)transfer_done; + + // Initiate control transfer for short config descriptor + ret = get_config_desc_transfer(client_hdl, ctrl_transfer, bConfigurationValue, SHORT_DESC_REQ_LEN); + if (ret != ESP_OK) { + goto exit; + } + + // Get length of full config descriptor + const usb_config_desc_t *config_desc_short = (usb_config_desc_t *)(ctrl_transfer->data_buffer + sizeof(usb_setup_packet_t)); + + // Initiate control transfer for full config descriptor + ret = get_config_desc_transfer(client_hdl, ctrl_transfer, bConfigurationValue, config_desc_short->wTotalLength); + if (ret != ESP_OK) { + goto exit; + } + + // Allocate memory to store the configuration descriptor + const usb_config_desc_t *config_desc_full = (usb_config_desc_t *)(ctrl_transfer->data_buffer + sizeof(usb_setup_packet_t)); + usb_config_desc_t *config_desc = heap_caps_malloc(config_desc_full->wTotalLength, MALLOC_CAP_DEFAULT); + if (config_desc == NULL) { + ret = ESP_ERR_NO_MEM; + goto exit; + } + + // Copy the configuration descriptor + memcpy(config_desc, config_desc_full, config_desc_full->wTotalLength); + *config_desc_ret = config_desc; + ret = ESP_OK; + +exit: + if (ctrl_transfer) { + usb_host_transfer_free(ctrl_transfer); + } + if (transfer_done != NULL) { + vSemaphoreDelete(transfer_done); + } + return ret; +} + +esp_err_t usb_host_get_config_desc_free(const usb_config_desc_t *config_desc) +{ + HOST_CHECK(config_desc != NULL, ESP_ERR_INVALID_ARG); + heap_caps_free((usb_config_desc_t*)config_desc); + return ESP_OK; +} + // ----------------------------------------------- Interface Functions ------------------------------------------------- // ----------------------- Private ------------------------- diff --git a/components/usb/usb_phy.c b/components/usb/usb_phy.c index cfaf90abd255..7ae5e5f3826b 100644 --- a/components/usb/usb_phy.c +++ b/components/usb/usb_phy.c @@ -340,8 +340,10 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r return ESP_OK; cleanup: - free(phy_context->iopins); - free(phy_context); + if (phy_context) { + free(phy_context->iopins); + free(phy_context); + } if (p_phy_ctrl_obj->ref_count == 0) { free(p_phy_ctrl_obj); p_phy_ctrl_obj = NULL; diff --git a/components/vfs/vfs_eventfd.c b/components/vfs/vfs_eventfd.c index a9a979cf9c04..a8ae79d1b955 100644 --- a/components/vfs/vfs_eventfd.c +++ b/components/vfs/vfs_eventfd.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -107,12 +107,16 @@ static esp_err_t event_start_select(int nfds, for (int i = 0; i < nfds; i++) { _lock_acquire_recursive(&s_events[i].lock); if (s_events[i].fd == i && (FD_ISSET(i, readfds) || FD_ISSET(i, writefds) || FD_ISSET(i, exceptfds))) { + event_select_args_t *event_select_args = + (event_select_args_t *)malloc(sizeof(event_select_args_t)); + if (!event_select_args) { + _lock_release_recursive(&s_events[i].lock); + return ESP_ERR_NO_MEM; + } if (s_events[i].support_isr) { portENTER_CRITICAL(&s_events[i].data_spin_lock); } - event_select_args_t *event_select_args = - (event_select_args_t *)malloc(sizeof(event_select_args_t)); event_select_args->fd = i; event_select_args->signal_sem = signal_sem; diff --git a/components/wear_levelling/CMakeLists.txt b/components/wear_levelling/CMakeLists.txt index 2ca00a42b383..28e98bbb2f1b 100644 --- a/components/wear_levelling/CMakeLists.txt +++ b/components/wear_levelling/CMakeLists.txt @@ -9,3 +9,7 @@ idf_component_register(SRCS "Partition.cpp" PRIV_INCLUDE_DIRS private_include REQUIRES esp_partition PRIV_REQUIRES spi_flash) + +if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10089 + target_compile_options(${COMPONENT_LIB} PUBLIC -fno-analyzer) +endif() diff --git a/components/wpa_supplicant/CMakeLists.txt b/components/wpa_supplicant/CMakeLists.txt index ebbe874f2fda..f0a67dbceb2b 100644 --- a/components/wpa_supplicant/CMakeLists.txt +++ b/components/wpa_supplicant/CMakeLists.txt @@ -231,6 +231,10 @@ idf_component_register(SRCS "${srcs}" "${esp_srcs}" "${tls_src}" "${roaming_src} PRIV_REQUIRES mbedtls esp_timer esp_wifi) target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-strict-aliasing -Wno-write-strings -Werror) +if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10090 + target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer") +endif() + target_compile_definitions(${COMPONENT_LIB} PRIVATE __ets__ ESP_SUPPLICANT diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c b/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c index 32f8efec0e1b..5d1281f6d8d6 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c @@ -294,7 +294,6 @@ static void wpa_sta_disconnected_cb(uint8_t reason_code) case WIFI_REASON_ASSOC_FAIL: case WIFI_REASON_CONNECTION_FAIL: case WIFI_REASON_HANDSHAKE_TIMEOUT: - esp_wpa3_free_sae_data(); wpa_sta_clear_curr_pmksa(); wpa_sm_notify_disassoc(&gWpaSm); break; @@ -308,6 +307,7 @@ static void wpa_sta_disconnected_cb(uint8_t reason_code) owe_deinit(); #endif /* CONFIG_OWE_STA */ + esp_wpa3_free_sae_data(); supplicant_sta_disconn_handler(reason_code); } diff --git a/components/wpa_supplicant/src/ap/ieee802_1x.c b/components/wpa_supplicant/src/ap/ieee802_1x.c index 5e3c078baf49..eb623cecab7e 100644 --- a/components/wpa_supplicant/src/ap/ieee802_1x.c +++ b/components/wpa_supplicant/src/ap/ieee802_1x.c @@ -433,6 +433,8 @@ int ieee802_1x_init(struct hostapd_data *hapd) os_memset(&conf, 0, sizeof(conf)); eap_cfg = os_zalloc(sizeof(struct eap_config)); + if (!eap_cfg) + return -1; eap_cfg->max_auth_rounds = 100; eap_cfg->max_auth_rounds_short = 50; //eap_cfg->backend_auth = 1; diff --git a/components/wpa_supplicant/src/common/ieee802_11_common.c b/components/wpa_supplicant/src/common/ieee802_11_common.c index ed44d3532ef2..61a753f442d2 100644 --- a/components/wpa_supplicant/src/common/ieee802_11_common.c +++ b/components/wpa_supplicant/src/common/ieee802_11_common.c @@ -202,6 +202,10 @@ static int ieee802_11_parse_vendor_specific(struct wpa_supplicant *wpa_s, const case SAE_PK_OUI_TYPE: wpa_s->sae_pk_elems.sae_pk_len = elem->datalen - 4; wpa_s->sae_pk_elems.sae_pk = (u8*)os_zalloc(sizeof(u8)*(elem->datalen-4)); + if (!wpa_s->sae_pk_elems.sae_pk) { + wpa_printf(MSG_EXCESSIVE, "Can not allocate memory for sae_pk"); + return -1; + } os_memcpy(wpa_s->sae_pk_elems.sae_pk, pos+4, elem->datalen-4); break; default: diff --git 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-api-guides/usb-serial-jtag-console.rst api-guides/wifi.rst api-guides/usb-otg-console.rst api-guides/bluetooth.rst @@ -107,8 +106,6 @@ api-reference/peripherals/sdm.rst api-reference/peripherals/touch_pad.rst api-reference/peripherals/adc_calibration.rst api-reference/peripherals/spi_slave_hd.rst -api-reference/peripherals/parlio.rst -api-reference/peripherals/i2c.rst api-reference/peripherals/dedic_gpio.rst api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/spi_master.rst diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt index dacc365bc102..828989eb3914 100644 --- a/docs/docs_not_updated/esp32p4.txt +++ b/docs/docs_not_updated/esp32p4.txt @@ -9,18 +9,6 @@ api-guides/esp-wifi-mesh.rst api-guides/dfu.rst api-guides/current-consumption-measurement-modules.rst api-guides/wifi-security.rst -api-reference/storage/vfs.rst -api-reference/storage/spiffs.rst -api-reference/storage/nvs_encryption.rst -api-reference/storage/wear-levelling.rst -api-reference/storage/fatfs.rst -api-reference/storage/nvs_partition_gen.rst -api-reference/storage/nvs_flash.rst -api-reference/storage/partition.rst -api-reference/storage/mass_mfg.rst -api-reference/storage/fatfsgen.rst -api-reference/storage/index.rst -api-reference/storage/nvs_partition_parse.rst api-reference/peripherals/adc_continuous.rst api-reference/peripherals/adc_oneshot.rst api-reference/peripherals/usb_host.rst diff --git a/docs/doxygen/Doxyfile_esp32c5 b/docs/doxygen/Doxyfile_esp32c5 index c97591d32c22..234f39a672a0 100644 --- a/docs/doxygen/Doxyfile_esp32c5 +++ b/docs/doxygen/Doxyfile_esp32c5 @@ -7,4 +7,5 @@ INPUT += \ $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_print.h \ $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h \ $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h \ + $(PROJECT_PATH)/components/ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h \ $(PROJECT_PATH)/components/ulp/ulp_common/include/ulp_common.h \ diff --git a/docs/en/_templates/layout.html b/docs/en/_templates/layout.html index ad7da75e6578..efcb5029c1bd 100644 --- a/docs/en/_templates/layout.html +++ b/docs/en/_templates/layout.html @@ -1,4 +1,66 @@ {% extends '!layout.html' %} {% block comments %} -

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+ {% endblock %} diff --git a/docs/en/api-guides/bootloader.rst b/docs/en/api-guides/bootloader.rst index b8167b462574..f2b4d6277c93 100644 --- a/docs/en/api-guides/bootloader.rst +++ b/docs/en/api-guides/bootloader.rst @@ -163,12 +163,18 @@ Options to work around this are: When Secure Boot V2 is enabled, there is also an absolute binary size limit of {IDF_TARGET_MAX_BOOTLOADER_SIZE} (excluding the 4 KB signature), because the bootloader is first loaded into a fixed size buffer for verification. +Fast Boot from Deep-Sleep +------------------------- + +The bootloader has the :ref:`CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` option which allows the wake-up time from Deep-sleep to be reduced (useful for reducing power consumption). This option is available when the :ref:`CONFIG_SECURE_BOOT` option is disabled or :ref:`CONFIG_SECURE_BOOT_INSECURE` is enabled along with Secure Boot. The reduction in time is achieved by ignoring image verification. + .. only:: SOC_RTC_FAST_MEM_SUPPORTED - Fast Boot from Deep-Sleep - ------------------------- + During the first boot, the bootloader stores the address of the application being launched in the RTC FAST memory. After waking up from deep sleep, this address is used to boot the application again without any checks, resulting in a significantly faster load. + +.. only:: not SOC_RTC_FAST_MEM_SUPPORTED - The bootloader has the :ref:`CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` option which allows the wake-up time from Deep-sleep to be reduced (useful for reducing power consumption). This option is available when :ref:`CONFIG_SECURE_BOOT` option is disabled. Reduction of time is achieved due to the lack of image verification. During the first boot, the bootloader stores the address of the application being launched in the RTC FAST memory. And during the awakening, this address is used for booting without any checks, thus fast loading is achieved. + The {IDF_TARGET_NAME} does not have RTC memory, so a running partition cannot be saved there; instead, the entire partition table is read to select the correct application. During wake-up, the selected application is loaded without any checks, resulting in a significantly faster load. Custom Bootloader ----------------- diff --git a/docs/en/api-guides/code-quality/index.rst b/docs/en/api-guides/code-quality/index.rst new file mode 100644 index 000000000000..527e6b89153d --- /dev/null +++ b/docs/en/api-guides/code-quality/index.rst @@ -0,0 +1,14 @@ +Code Quality +============ + +:link_to_translation:`zh_CN:[中文]` + +Code quality refers to how well-written and maintainable a piece of software code is. It encompasses aspects like readability, efficiency, reliability, and adherence to coding standards. High-quality code is easier to understand, modify, and extend, leading to reduced development time and fewer bugs. + +Guides +------ + +.. toctree:: + :maxdepth: 2 + + static-analyzer diff --git a/docs/en/api-guides/code-quality/static-analyzer.rst b/docs/en/api-guides/code-quality/static-analyzer.rst new file mode 100644 index 000000000000..5bea438423a0 --- /dev/null +++ b/docs/en/api-guides/code-quality/static-analyzer.rst @@ -0,0 +1,31 @@ +Static Analyzer +=============== + +:link_to_translation:`zh_CN:[中文]` + +A static analyzer is a tool that checks source code for errors and vulnerabilities without running it. It helps developers find issues early, improving code quality. + +GNU Static Analyzer +------------------- + +The GNU Static Analyzer is distributed with GCC (refer to `GCC documentation `_). It can be enabled with :ref:`CONFIG_COMPILER_STATIC_ANALYZER` to perform code checks during application builds. + +Suppressing Warnings +^^^^^^^^^^^^^^^^^^^^ + +GNU Static Analyzer is still under development and may give some false-positive warnings. Here is an example of how to suppress unwanted warnings using IDF: + +.. code-block:: c + + #include "esp_compiler.h" + /* .... */ + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-null-dereference") + *((volatile int *) 0) = 0; + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-null-dereference") + /* .... */ + + +Clang Static Analyzer +--------------------- + +See :doc:`IDF Clang-Tidy <../../api-guides/tools/idf-clang-tidy>` diff --git a/docs/en/api-guides/host-apps.rst b/docs/en/api-guides/host-apps.rst index bbef3c21a746..adfc33905b87 100644 --- a/docs/en/api-guides/host-apps.rst +++ b/docs/en/api-guides/host-apps.rst @@ -27,7 +27,7 @@ A large number of ESP-IDF components depend on chip-specific hardware. These har 1. Using the `FreeRTOS POSIX/Linux simulator `_ that simulates FreeRTOS scheduling. On top of this simulation, other APIs are also simulated or implemented when running on host. 2. Using `CMock `_ to mock all dependencies and run the code in complete isolation. -In principle, it is possible to mix both approaches (POSIX/Linux simulator and mocking using CMock), but this has not been done yet in ESP-IDF. Note that despite the name, the FreeRTOS POSIX/Linux simulator currently also works on macOS. Running ESP-IDF applications on host machines is often used for testing. However, simulating the environment and mocking dependencies does not fully represent the target device. Thus, testing on the target device is still necessary, though with a different focus that usually puts more weight on integration and system testing. +Note that despite the name, the FreeRTOS POSIX/Linux simulator currently also works on macOS. Running ESP-IDF applications on host machines is often used for testing. However, simulating the environment and mocking dependencies does not fully represent the target device. Thus, testing on the target device is still necessary, though with a different focus that usually puts more weight on integration and system testing. .. note:: @@ -44,6 +44,18 @@ POSIX/Linux Simulator Approach The `FreeRTOS POSIX/Linux simulator `_ is available on ESP-IDF as a preview target already. This simulator allows ESP-IDF components to be implemented on the host, making them accessible to ESP-IDF applications when running on host. Currently, only a limited number of components are ready to be built on Linux. Furthermore, the functionality of each component ported to Linux may also be limited or different compared to the functionality when building that component for a chip target. For more information about whether the desired components are supported on Linux, please refer to :ref:`component-linux-mock-support`. +Note that this simulator relies heavily on POSIX signals and signal handlers to control and interrupt threads. Hence, it has the following *limitations*: + +.. list:: + - Functions that are not *async-signal-safe*, e.g. ``printf()``, should be avoided. In particular, calling them from different tasks with different priority can lead to crashes and deadlocks. + - Calling any FreeRTOS primitives from threads not created by FreeRTOS API functions is forbidden. + - FreeRTOS tasks using any native blocking/waiting mechanism (e.g., ``select()``), may be perceived as *ready* by the simulated FreeRTOS scheduler and therefore may be scheduled, even though they are actually blocked. This is because the simulated FreeRTOS scheduler only recognizes tasks blocked on any FreeRTOS API as *waiting*. + - APIs that may be interrupted by signals will continually receive the signals simulating FreeRTOS tick interrupts when invoked from a running simulated FreeRTOS task. Consequently, code that calls these APIs should be designed to handle potential interrupting signals or the API needs to be wrapped by the linker. + +Since these limitations are not very practical, in particular for testing and development, we are currently evaluating if we can find a better solution for running ESP-IDF applications on the host machine. + +Note furthermore that if you use the ESP-IDF FreeRTOS mock component (``tools/mocks/freertos``), these limitations do not apply. But that mock component will not do any scheduling, either. + .. only:: not esp32p4 .. note:: diff --git a/docs/en/api-guides/index.rst b/docs/en/api-guides/index.rst index e2d46e436c24..ffc491c00d98 100644 --- a/docs/en/api-guides/index.rst +++ b/docs/en/api-guides/index.rst @@ -14,6 +14,7 @@ API Guides :SOC_SUPPORT_COEXISTENCE: coexist c cplusplus + code-quality/index core_dump current-consumption-measurement-modules :SOC_RTC_MEM_SUPPORTED: deep-sleep-stub diff --git a/docs/en/api-guides/partition-tables.rst b/docs/en/api-guides/partition-tables.rst index e51659bc003a..b9432bb2d865 100644 --- a/docs/en/api-guides/partition-tables.rst +++ b/docs/en/api-guides/partition-tables.rst @@ -328,6 +328,24 @@ The command-line interface of `parttool.py` has the following structure: # Print the size of default boot partition parttool.py --port "/dev/ttyUSB1" get_partition_info --partition-boot-default --info size +.. note:: + If the device has already enabled ``Flash Encryption`` or ``Secure Boot``, attempting to use commands that modify the flash content, such as ``erase_partition`` or ``write_partition``, will result in an error. This error is generated by the erase command of ``esptool.py``, which is called first before writing. This error is done as a safety measure to prevent bricking your device. + + :: + A fatal error occurred: Active security features detected, erasing flash is disabled as a safety measure. Use --force to override, please use with caution, otherwise it may brick your device! + + To work around this, you need use the ``--force`` flag with ``esptool.py``. Specifically, the ``parttool.py`` provides the ``--esptool-erase-args`` argument that help to pass this flag to ``esptool.py``. + + .. code-block:: bash + + # Erase partition with name 'storage' + # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force" + parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force erase_partition --partition-name=storage + + # Write to partition 'factory' the contents of a file named 'factory.bin' + # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force" + parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force write_partition --partition-name=factory --input "factory.bin" + More information can be obtained by specifying `--help` as argument: .. code-block:: bash diff --git a/docs/en/api-guides/performance/size.rst b/docs/en/api-guides/performance/size.rst index d0eae2f06c2e..b38a2b7d1e01 100644 --- a/docs/en/api-guides/performance/size.rst +++ b/docs/en/api-guides/performance/size.rst @@ -382,7 +382,7 @@ The following configuration options reduces the final binary size of almost any - Set :ref:`CONFIG_COMPILER_OPTIMIZATION` to ``Optimize for size (-Os)``. In some cases, ``Optimize for performance (-O2)`` will also reduce the binary size compared to the default. Note that if your code contains C or C++ Undefined Behavior then increasing the compiler optimization level may expose bugs that otherwise do not happen. - Reduce the compiled-in log output by lowering the app :ref:`CONFIG_LOG_DEFAULT_LEVEL`. If the :ref:`CONFIG_LOG_MAXIMUM_LEVEL` is changed from the default then this setting controls the binary size instead. Reducing compiled-in logging reduces the number of strings in the binary, and also the code size of the calls to logging functions. - - If your application doesn't require dynamic log level changes and you do not need to control logs per module using tags, consider disabling :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` and changing :ref:`CONFIG_LOG_TAG_LEVEL_IMPL`. It reduces IRAM usage by approximately 260 bytes, DRAM usage by approximately 264 bytes, and Flash usage by approximately 1K bytes compared to the default option, it also speeds up logging. + - If your application does not require dynamic log level changes and you do not need to control logs per module using tags, consider disabling :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` and changing :ref:`CONFIG_LOG_TAG_LEVEL_IMPL`. It reduces IRAM usage by approximately 260 bytes, DRAM usage by approximately 264 bytes, and flash usage by approximately 1 KB compared to the default option, it also speeds up logging. - Set the :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL` to ``Silent``. This avoids compiling in a dedicated assertion string and source file name for each assert that may fail. It is still possible to find the failed assert in the code by looking at the memory address where the assertion failed. - Besides the :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL`, you can disable or silent the assertion for the HAL component separately by setting :ref:`CONFIG_HAL_DEFAULT_ASSERTION_LEVEL`. It is to notice that ESP-IDF lowers the HAL assertion level in bootloader to be silent even if :ref:`CONFIG_HAL_DEFAULT_ASSERTION_LEVEL` is set to full-assertion level. This is to reduce the bootloader size. - Setting :ref:`CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT` removes specific error messages for particular internal ESP-IDF error check macros. This may make it harder to debug some error conditions by reading the log output. diff --git a/docs/en/api-guides/performance/speed.rst b/docs/en/api-guides/performance/speed.rst index eb8921d18d6e..372ef0fc4241 100644 --- a/docs/en/api-guides/performance/speed.rst +++ b/docs/en/api-guides/performance/speed.rst @@ -128,7 +128,7 @@ Although standard output is buffered, it is possible for an application to be li - Reduce the volume of log output by lowering the app :ref:`CONFIG_LOG_DEFAULT_LEVEL` (the equivalent bootloader setting is :ref:`CONFIG_BOOTLOADER_LOG_LEVEL`). This also reduces the binary size, and saves some CPU time spent on string formatting. :not SOC_USB_OTG_SUPPORTED: - Increase the speed of logging output by increasing the :ref:`CONFIG_ESP_CONSOLE_UART_BAUDRATE`. :SOC_USB_OTG_SUPPORTED: - Increase the speed of logging output by increasing the :ref:`CONFIG_ESP_CONSOLE_UART_BAUDRATE`. However, if you are using internal USB-CDC, the serial throughput is not dependent on the configured baud rate. - - If your application doesn't require dynamic log level changes and you do not need to control logs per module using tags, consider disabling :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` and changing :ref:`CONFIG_LOG_TAG_LEVEL_IMPL`. It helps to reduce memory usage and also contributes to speeding up log operations in your application about 10 times. + - If your application does not require dynamic log level changes and you do not need to control logs per module using tags, consider disabling :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` and changing :ref:`CONFIG_LOG_TAG_LEVEL_IMPL`. It helps to reduce memory usage and also contributes to speeding up log operations in your application about 10 times. Not Recommended ^^^^^^^^^^^^^^^ diff --git a/docs/en/api-guides/usb-serial-jtag-console.rst b/docs/en/api-guides/usb-serial-jtag-console.rst index 4bde079df73c..5121bb85e613 100644 --- a/docs/en/api-guides/usb-serial-jtag-console.rst +++ b/docs/en/api-guides/usb-serial-jtag-console.rst @@ -19,8 +19,8 @@ Generally, ESP chips implement a serial port using UART and can be connected to Hardware Requirements ===================== -{IDF_TARGET_USB_DP_GPIO:default="Not Updated!",esp32c3="19",esp32s3="20", esp32c6="13", esp32h2="27", esp32p4="25/27"} -{IDF_TARGET_USB_DM_GPIO:default="Not Updated!",esp32c3="18",esp32s3="19", esp32c6="12", esp32h2="26", esp32p4="24/26"} +{IDF_TARGET_USB_DP_GPIO:default="Not Updated!",esp32c3="19",esp32s3="20", esp32c6="13", esp32h2="27", esp32p4="25/27", esp32c5="14"} +{IDF_TARGET_USB_DM_GPIO:default="Not Updated!",esp32c3="18",esp32s3="19", esp32c6="12", esp32h2="26", esp32p4="24/26", esp32c5="13"} Connect {IDF_TARGET_NAME} to the USB port as follows: diff --git a/docs/en/api-reference/peripherals/gptimer.rst b/docs/en/api-reference/peripherals/gptimer.rst index b836a05551cc..65140754bdca 100644 --- a/docs/en/api-reference/peripherals/gptimer.rst +++ b/docs/en/api-reference/peripherals/gptimer.rst @@ -43,14 +43,11 @@ A GPTimer instance is represented by :cpp:type:`gptimer_handle_t`. The driver be To install a timer instance, there is a configuration structure that needs to be given in advance: :cpp:type:`gptimer_config_t`: - :cpp:member:`gptimer_config_t::clk_src` selects the source clock for the timer. The available clocks are listed in :cpp:type:`gptimer_clock_source_t`, you can only pick one of them. For the effect on power consumption of different clock source, please refer to Section :ref:`gptimer-power-management`. - - :cpp:member:`gptimer_config_t::direction` sets the counting direction of the timer, supported directions are listed in :cpp:type:`gptimer_count_direction_t`, you can only pick one of them. - - :cpp:member:`gptimer_config_t::resolution_hz` sets the resolution of the internal counter. Each count step is equivalent to **1 / resolution_hz** seconds. - -- :cpp:member:`gptimer_config::intr_priority` sets the priority of the timer interrupt. If it is set to ``0``, the driver will allocate an interrupt with a default priority. Otherwise, the driver will use the given priority. - -- Optional :cpp:member:`gptimer_config_t::intr_shared` sets whether or not mark the timer interrupt source as a shared one. For the pros/cons of a shared interrupt, you can refer to :doc:`Interrupt Handling <../../api-reference/system/intr_alloc>`. +- :cpp:member:`gptimer_config::intr_priority` sets the priority of the timer interrupt. If it is set to ``0``, the driver will allocate an interrupt with a default priority. Otherwise, the driver will use the given priority. +- :cpp:member:`gptimer_config_t::backup_before_sleep` enables the backup of the GPTimer registers before entering sleep mode. This option implies an balance between power consumption and memory usage. If the power consumption is not a concern, you can disable this option to save memory. But if you want to save more power, you should enable this option to backup the GPTimer registers before entering sleep mode, and restore them after waking up. This feature depends on specific hardware module, if you enable this flag on an unsupported chip, you will get an error message like ``register back up is not supported``. +- Optional :cpp:member:`gptimer_config_t::intr_shared` sets whether or not mark the timer interrupt source as a shared one. For the pros/cons of a shared interrupt, you can refer to :doc:`Interrupt Handling <../../api-reference/system/intr_alloc>`. With all the above configurations set in the structure, the structure can be passed to :cpp:func:`gptimer_new_timer` which will instantiate the timer instance and return a handle of the timer. @@ -284,9 +281,13 @@ Alarm value can be updated dynamically inside the ISR handler callback, by chang Power Management ^^^^^^^^^^^^^^^^ -There are some power management strategies, which might turn off or change the frequency of GPTimer's source clock to save power consumption. For example, during DFS, APB clock will be scaled down. If light-sleep is also enabled, PLL and XTAL clocks will be powered off. Both of them can result in an inaccurate time keeping. +When power management is enabled, i.e., :ref:`CONFIG_PM_ENABLE` is on, the system may adjust or disable the clock source before going to sleep. As a result, the time keeping will be inaccurate. + +The driver can prevent the above issue by creating a power management lock. The lock type is set based on different clock sources. The driver will acquire the lock in :cpp:func:`gptimer_enable`, and release it in :cpp:func:`gptimer_disable`. So that the timer can work correctly in between these two functions, because the clock source won't be disabled or adjusted its frequency during this time. + +.. only:: SOC_TIMER_SUPPORT_SLEEP_RETENTION -The driver can prevent the above situation from happening by creating different power management lock according to different clock source. The driver increases the reference count of that power management lock in the :cpp:func:`gptimer_enable` and decrease it in the :cpp:func:`gptimer_disable`. So we can ensure the clock source is stable between :cpp:func:`gptimer_enable` and :cpp:func:`gptimer_disable`. + Besides the potential changes to the clock source, when the power management is enabled, the system can also power down a domain where GPTimer register located. To ensure the GPTimer driver can continue work after sleep, we can either backup the GPTimer registers to the RAM, or just refuse to power down. You can choose what to do in :cpp:member:`gptimer_config_t::backup_before_sleep`. It's a balance between power saving and memory consumption. Set it based on your application requirements. .. _gptimer-iram-safe: diff --git a/docs/en/api-reference/peripherals/i2c.rst b/docs/en/api-reference/peripherals/i2c.rst index 75081b7fcf14..9e28cc92d289 100644 --- a/docs/en/api-reference/peripherals/i2c.rst +++ b/docs/en/api-reference/peripherals/i2c.rst @@ -362,7 +362,7 @@ Some I2C device needs write configurations before reading data from it. Therefor I2C master write to slave and read from slave -Simple example for writing and reading from slave: +Please note that no STOP condition bit is inserted between the write and read operations; therefore, this function is suited to read a register from an I2C device. A simple example for writing and reading from a slave device: .. code:: c @@ -625,6 +625,14 @@ Kconfig Options - :ref:`CONFIG_I2C_ISR_IRAM_SAFE` controls whether the default ISR handler can work when cache is disabled, see also `IRAM Safe <#iram-safe>`__ for more information. - :ref:`CONFIG_I2C_ENABLE_DEBUG_LOG` is used to enable the debug log at the cost of increased firmware binary size. +Application Examples +-------------------- + +.. list:: + + - :example:`peripherals/i2c/i2c_eeprom` demonstrates the basic usage of I2C driver by reading and writing from an I2C connected EEPROM. + - :example:`peripherals/i2c/i2c_tools` implements some basic features of I2C tools based on the ESP32 console component. + API Reference ------------- diff --git a/docs/en/api-reference/storage/nvs_encryption.rst b/docs/en/api-reference/storage/nvs_encryption.rst index e76a446f8177..002b4dc2f225 100644 --- a/docs/en/api-reference/storage/nvs_encryption.rst +++ b/docs/en/api-reference/storage/nvs_encryption.rst @@ -66,6 +66,10 @@ The XTS encryption keys in the :ref:`nvs_encr_key_partition` can be generated in parttool.py --port PORT --partition-table-file=PARTITION_TABLE_FILE --partition-table-offset PARTITION_TABLE_OFFSET erase_partition --partition-type=data --partition-subtype=nvs_keys + # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force" to suppress the error: + # "Active security features detected, erasing flash is disabled as a safety measure. Use --force to override ..." + parttool.py --port PORT --esptool-erase-args=force --partition-table-file=PARTITION_TABLE_FILE --partition-table-offset PARTITION_TABLE_OFFSET erase_partition --partition-type=data --partition-subtype=nvs_keys + **Use a pre-generated NVS key partition** This option will be required by the user when keys in the :ref:`nvs_encr_key_partition` are not generated by the application. The :ref:`nvs_encr_key_partition` containing the XTS encryption keys can be generated with the help of :doc:`NVS Partition Generator Utility `. Then the user can store the pre-generated key partition on the flash with help of the following two commands: @@ -80,12 +84,20 @@ The XTS encryption keys in the :ref:`nvs_encr_key_partition` can be generated in parttool.py --port PORT --partition-table-offset PARTITION_TABLE_OFFSET write_partition --partition-name="name of nvs_key partition" --input NVS_KEY_PARTITION_FILE + # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force" to suppress the error: + # "Active security features detected, erasing flash is disabled as a safety measure. Use --force to override ..." + parttool.py --port PORT --esptool-erase-args=force --partition-table-offset PARTITION_TABLE_OFFSET write_partition --partition-name="name of nvs_key partition" --input NVS_KEY_PARTITION_FILE + .. note:: If the device is encrypted in flash encryption development mode and you want to renew the NVS key partition, you need to tell :component_file:`parttool.py` to encrypt the NVS key partition and you also need to give it a pointer to the unencrypted partition table in your build directory (build/partition_table) since the partition table on the device is encrypted, too. You can use the following command: :: parttool.py --esptool-write-args encrypt --port PORT --partition-table-file=PARTITION_TABLE_FILE --partition-table-offset PARTITION_TABLE_OFFSET write_partition --partition-name="name of nvs_key partition" --input NVS_KEY_PARTITION_FILE + # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force" to suppress the error: + # "Active security features detected, erasing flash is disabled as a safety measure. Use --force to override ..." + parttool.py --esptool-erase-args=force --esptool-write-args encrypt --port PORT --partition-table-file=PARTITION_TABLE_FILE --partition-table-offset PARTITION_TABLE_OFFSET write_partition --partition-name="name of nvs_key partition" --input NVS_KEY_PARTITION_FILE + Since the key partition is marked as ``encrypted`` and :doc:`Flash Encryption <../../security/flash-encryption>` is enabled, the bootloader will encrypt this partition using flash encryption key on the first boot. It is possible for an application to use different keys for different NVS partitions and thereby have multiple key-partitions. However, it is a responsibility of the application to provide the correct key-partition and keys for encryption or decryption. diff --git a/docs/en/api-reference/system/efuse.rst b/docs/en/api-reference/system/efuse.rst index fe3ad9563397..6579a6d82636 100644 --- a/docs/en/api-reference/system/efuse.rst +++ b/docs/en/api-reference/system/efuse.rst @@ -1,123 +1,126 @@ eFuse Manager ============= +:link_to_translation:`zh_CN:[中文]` + {IDF_TARGET_CODING_SCHEMES:default="Reed-Solomon", esp32="3/4 or Repeat"} Introduction ------------ -The eFuse Manager library is designed to structure access to eFuse bits and make using these easy. This library operates eFuse bits by a structure name which is assigned in eFuse table. This sections introduces some concepts used by eFuse Manager. +eFuse (Electronic Fuses) are microscopic one-time programmable fuses that can be "burned" (i.e., programmed) to store data into the {IDF_TARGET_NAME}. eFuse bits are organized into different data fields, and these data fields could be used for system parameters (i.e., data parameters used by ESP-IDF of {IDF_TARGET_NAME}) or user defined parameters. +The eFuse Manager component is a collection of tools and APIs that assist with defining, burning, accessing eFuses parameters. The notable tools and APIs include: -eFuse Manager vs idf.py ------------------------ +* A table format used to define eFuse data fields in CSV file. +* ``efuse_table_gen.py`` tool to generate C structure representation of eFuse data fields specified by the CSV file. +* Collection of C API to read/write eFuse data fields. + +eFuse Manager vs ``idf.py`` +--------------------------- -idf.py provides a subset of the functionality of the eFuse Manager via the ``idf.py efuse-`` commands. In this documentation, mostly ``idf.py`` based commands will be used, although you can still see some ``espefuse.py`` based commands for advanced or rare cases. To see all available commands, run ``idf.py --help`` and search for those prefixed with ``efuse-``. +``idf.py`` provides a subset of the functionality of the eFuse Manager via the ``idf.py efuse-`` commands. In this documentation, mostly ``idf.py`` based commands will be used, although you can still see some ``espefuse.py`` based commands for advanced or rare cases. To see all available commands, run ``idf.py --help`` and search for those prefixed with ``efuse-``. Hardware Description -------------------- -The {IDF_TARGET_NAME} has a number of eFuses which can store system and user parameters. Each eFuse is a one-bit field which can be programmed to 1 after which it cannot be reverted back to 0. -Some of system parameters are using these eFuse bits directly by hardware modules and have special place (for example EFUSE_BLK0). +The {IDF_TARGET_NAME} has a number of eFuses which can store system and user parameters. Each eFuse is a one-bit field which can be programmed to 1 after which it cannot be reverted back to 0. The eFuse bits are grouped into blocks of 256 bits, where each block is further divided into 8 32-bit registers. Some blocks are reserved for system parameters while the remaining blocks can be used for user parameters. -For more details, see **{IDF_TARGET_NAME} Technical Reference Manual** > **eFuse Controller (eFuse)** [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__]. Some eFuse bits are available for user applications. +For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__]. .. only:: esp32 - {IDF_TARGET_NAME} has 4 eFuse blocks each of the size of 256 bits (not all bits are available): + {IDF_TARGET_NAME} has 4 eFuse blocks each containing 256 bits (not all bits can be used for user parameters): - * EFUSE_BLK0 is used entirely for system purposes; - * EFUSE_BLK1 is used for flash encrypt key. If not using that Flash Encryption feature, they can be used for another purpose; - * EFUSE_BLK2 is used for security boot key. If not using that Secure Boot feature, they can be used for another purpose; - * EFUSE_BLK3 can be partially reserved for the custom MAC address, or used entirely for user application. Note that some bits are already used in ESP-IDF. + * EFUSE_BLK0 is used entirely for system purposes + * EFUSE_BLK1 is used for Flash Encryption keys. If the Flash Encryption feature is not used, this block can be used for user parameters. + * EFUSE_BLK2 is used for the Secure Boot key. If the Secure Boot feature is not used, this block can be used for user parameters. + * EFUSE_BLK3 can be partially reserved to store a custom MAC address, or can be used entirely for user parameters. Note that some bits are already used in ESP-IDF. .. only:: not esp32 and not esp32c2 - .. list:: + {IDF_TARGET_NAME} has 11 eFuse blocks each containing 256 bits (not all bits can be used for user parameters): - {IDF_TARGET_NAME} has 11 eFuse blocks each of the size of 256 bits (not all bits are available): + .. list:: - * EFUSE_BLK0 is used entirely for system purposes; - * EFUSE_BLK1 is used entirely for system purposes; - * EFUSE_BLK2 is used entirely for system purposes; - * EFUSE_BLK3 (also named EFUSE_BLK_USER_DATA) can be used for user purposes; - * EFUSE_BLK4 (also named EFUSE_BLK_KEY0) can be used as key (for secure_boot or flash_encryption) or for user purposes; - * EFUSE_BLK5 (also named EFUSE_BLK_KEY1) can be used as key (for secure_boot or flash_encryption) or for user purposes; - * EFUSE_BLK6 (also named EFUSE_BLK_KEY2) can be used as key (for secure_boot or flash_encryption) or for user purposes; - * EFUSE_BLK7 (also named EFUSE_BLK_KEY3) can be used as key (for secure_boot or flash_encryption) or for user purposes; - * EFUSE_BLK8 (also named EFUSE_BLK_KEY4) can be used as key (for secure_boot or flash_encryption) or for user purposes; - :SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and SOC_ECDSA_SUPPORTED: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used for any purpose except for flash encryption or ECDSA (due to a HW bug); - :SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and not SOC_ECDSA_SUPPORTED: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used for any purpose except for flash encryption (due to a HW bug); - :not SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used as key (for secure_boot or flash_encryption) or for user purposes; - * EFUSE_BLK10 (also named EFUSE_BLK_SYS_DATA_PART2) is reserved for system purposes. + * EFUSE_BLK0 is used entirely for system parameters + * EFUSE_BLK1 is used entirely for system parameters + * EFUSE_BLK2 is used entirely for system parameters + * EFUSE_BLK3 (also named EFUSE_BLK_USER_DATA) can be used for user parameters + * EFUSE_BLK4 to EFUSE_BLK8 (also named EFUSE_BLK_KEY0 to EFUSE_BLK_KEY4) can be used to store keys for Secure Boot or Flash Encryption. If both features are unused, these blocks can be used for user parameters. + :SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and SOC_ECDSA_SUPPORTED: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used for any purpose except for Flash Encryption or ECDSA (due to a HW errata); + :SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and not SOC_ECDSA_SUPPORTED: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used for any purpose except for Flash Encryption (due to a HW errata); + :not SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used to store keys for Secure Boot or Flash Encryption. If both features are unused, these blocks can be used for user parameters. + * EFUSE_BLK10 (also named EFUSE_BLK_SYS_DATA_PART2) is reserved for system parameters. .. only:: esp32c2 - {IDF_TARGET_NAME} has 4 eFuse blocks each of the size of 256 bits (not all bits are available): + {IDF_TARGET_NAME} has 4 eFuse blocks each containing 256 bits (not all bits can be used for user parameters): - * EFUSE_BLK0 is used entirely for system purposes; - * EFUSE_BLK1 is used entirely for system purposes; - * EFUSE_BLK2 is used entirely for system purposes; - * EFUSE_BLK3 (also named EFUSE_BLK_KEY0) can be used as key (for secure_boot or flash_encryption) or for user purposes; + * EFUSE_BLK0 is used entirely for system parameters + * EFUSE_BLK1 is used entirely for system parameters + * EFUSE_BLK2 is used entirely for system parameters + * EFUSE_BLK3 (also named EFUSE_BLK_KEY0) can be used to store keys for Secure Boot or Flash Encryption. If both features are unused, these blocks can be used for user parameters. -Each block is divided into 8 32-bits registers. - - -eFuse Manager Component ------------------------ +Defining eFuse Fields +--------------------- -The component has API functions for reading and writing fields. Access to the fields is carried out through the structures that describe the location of the eFuse bits in the blocks. The component provides the ability to form fields of any length and from any number of individual bits. The description of the fields is made in a CSV file in a table form. To generate from a tabular form (CSV file) in the C-source uses the tool ``efuse_table_gen.py``. The tool checks the CSV file for uniqueness of field names and bit intersection, in case of using a `custom` file from the user's project directory, the utility checks with the `common` CSV file. +eFuse fields are defined as a table of records in a CSV file according to a specific format. This record format provides the ability to form eFuse fields of any length and from any number of individual bits. -CSV files: +Moreover, the record format allows structured definition of eFuse fields consisting of sub-fields, meaning that a parent eFuse field may consist of multiple child eFuse fields occupying the same eFuse bits. -* common (`esp_efuse_table.csv`) - contains eFuse fields which are used inside the ESP-IDF. C-source generation should be done manually when changing this file (run command ``idf.py efuse-common-table``). Note that changes in this file can lead to incorrect operation. -* custom - (optional and can be enabled by :ref:`CONFIG_EFUSE_CUSTOM_TABLE`) contains eFuse fields that are used by the user in their application. C-source generation should be done manually when changing this file and running ``idf.py efuse-custom-table``. +Record Format +^^^^^^^^^^^^^ - -Description CSV File --------------------- - -The CSV file contains a description of the eFuse fields. In the simple case, one field has one line of description. -Table header: +In simple cases, each record occupies a single row in the table. Each record contains the following values (i.e., columns): {IDF_TARGET_MAX_EFUSE_BLK:default = "EFUSE_BLK10", esp32 = "EFUSE_BLK3", esp32c2 = "EFUSE_BLK3"} .. code-block:: none - # field_name, efuse_block(EFUSE_BLK0..{IDF_TARGET_MAX_EFUSE_BLK}), bit_start(0..255), bit_count(1..256), comment + # field_name, efuse_block(EFUSE_BLK0..{IDF_TARGET_MAX_EFUSE_BLK}), bit_start(0..255), bit_count(1..256), comment -Individual params in CSV file the following meanings: +- ``field_name`` -field_name + - Name of the eFuse field. + - The prefix ``ESP_EFUSE_`` is automatically added to the name, and this name will be used when referring to the field in C code. + - ``field_name`` unique across all eFuse fields. + - If this value is left empty, then this record is combined with the previous record. This allows you define an eFuse field with arbitrary bit ordering (see ``MAC_FACTORY`` field in the common table). + - Using ``.`` will define a child eFuse field. See :ref:`structured-efuse-fields` for more details. - Name of field. The prefix `ESP_EFUSE_` is added to the name, and this field name is available in the code. This name is used to access the fields. The name must be unique for all fields. If the line has an empty name, then this line is combined with the previous field. This allows you to set an arbitrary order of bits in the field, and expand the field as well (see ``MAC_FACTORY`` field in the common table). The field_name supports structured format using `.` to show that the field belongs to another field (see ``WR_DIS`` and ``RD_DIS`` in the common table). +- ``efuse_block`` -efuse_block + - The eFuse field's block number. E.g., EFUSE_BLK0 to {IDF_TARGET_MAX_EFUSE_BLK}. + - This determines which block the eFuse field is placed. - Block number. It determines where the eFuse bits are placed for this field. Available EFUSE_BLK0..{IDF_TARGET_MAX_EFUSE_BLK}. +- ``bit_start`` -bit_start + - Bit offset (0 to 255) of the eFuse within the block. + - ``bit_start`` is optional and can be omitted. - Start bit number (0..255). The bit_start field can be omitted. In this case, it is set to bit_start + bit_count from the previous record, if it has the same efuse_block. Otherwise (if efuse_block is different, or this is the first entry), an error will be generated. + - In this case, it is set to ``bit_start + bit_count`` from the previous record, given that the previous record is in the same eFuse block. + - If the previous record is in a different eFuse block, an error will be generated. -.. only:: esp32 - - bit_count +- ``bit_count`` - The number of bits to use in this field (1..-). This parameter cannot be omitted. This field also may be ``MAX_BLK_LEN`` in this case, the field length has the maximum block length, taking into account the coding scheme (applicable for ``ESP_EFUSE_SECURE_BOOT_KEY`` and ``ESP_EFUSE_ENCRYPT_FLASH_KEY`` fields). The value ``MAX_BLK_LEN`` depends on :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR`, which will be replaced with "None" - 256, "3/4" - 192, "REPEAT" - 128. + - The size of the eFuse field in bits (1 to N). + - ``bit_count`` cannot be omitted. + - If set to ``MAX_BLK_LEN`` the eFuse field's size will be the maximum allowable eFuse field size in the block. -.. only:: not esp32 + .. only:: esp32 - bit_count + - ``MAX_BLK_LEN`` takes into account the coding scheme of eFuse. + - Depending on the coding scheme selected via :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR`, ``MAX_BLK_LEN`` could be 256 ("None"), 192 ("3/4"), or 128 ("REPEAT"). - The number of bits to use in this field (1..-). This parameter cannot be omitted. This field also may be ``MAX_BLK_LEN`` in this case, the field length has the maximum block length. +- ``comment`` -comment + - Comment describing the eFuse field. + - The comment is copied verbatim into the C header file. - This param is using for comment field, it also move to C-header file. The comment field can be omitted. +If an eFuse field requires non-sequential bit ordering, then the eFuse field will span multiple records (i.e., multiple rows). The first record's ``field_name`` should specify the eFuse field's name, and the following records should leave ``field_name`` blank to indicate that they belong to the same eFuse field. -If a non-sequential bit order is required to describe a field, then the field description in the following lines should be continued without specifying a name, indicating that it belongs to one field. For example two fields ``MAC_FACTORY`` and ``MAC_FACTORY_CRC``: +The following example demonstrates the records to specify the non-sequential eFuse field ``MAC_FACTORY`` followed by a regular eFuse field ``MAC_FACTORY_CRC``: .. code-block:: none @@ -131,13 +134,19 @@ If a non-sequential bit order is required to describe a field, then the field de , EFUSE_BLK0, 32, 8, Factory MAC addr [5] MAC_FACTORY_CRC, EFUSE_BLK0, 80, 8, CRC8 for factory MAC address -This field is available in code as ``ESP_EFUSE_MAC_FACTORY`` and ``ESP_EFUSE_MAC_FACTORY_CRC``. +This eFuse fields will be made available in C code as ``ESP_EFUSE_MAC_FACTORY`` and ``ESP_EFUSE_MAC_FACTORY_CRC``. .. _structured-efuse-fields: Structured eFuse Fields ----------------------- +Typically, an eFuse field represents a particular parameter. However, in some cases where an eFuse field consists of multiple sub-fields, it may be useful to have isolated access to those sub-fields. For example, if an eFuse field contained a floating point parameter, it may be useful to be access the sign, exponent, and mantissa fields of the floating as separate eFuse fields. + +Therefore, it is possible for records to define eFuse fields in a structured manner using the ``.`` operator in ``field_name``. For example, ``XX.YY.ZZ`` defines a eFuse field ``ZZ`` that is a child of eFuse field ``YY`` which in turn is a child field of eFuse field ``XX``. + +The following records demonstrate the definition of eFuse fields in a structured manner: + .. code-block:: none WR_DIS, EFUSE_BLK0, 0, 32, Write protection @@ -150,56 +159,65 @@ Structured eFuse Fields WR_DIS.FIELD_3.ALIAS, EFUSE_BLK0, 5, 1, Write protection for FIELD_3 (just a alias for WR_DIS.FIELD_3) WR_DIS.FIELD_4, EFUSE_BLK0, 7, 1, Write protection for FIELD_4 -The structured eFuse field looks like ``WR_DIS.RD_DIS`` where the dot points that this field belongs to the parent field - ``WR_DIS`` and cannot be out of the parent's range. +Some things to note regarding the example above: -It is possible to use some levels of structured fields as WR_DIS.FIELD_2.B1 and B2. These fields should not be crossed each other and should be in the range of two fields: ``WR_DIS`` and ``WR_DIS.FIELD_2``. +* The ``WR_DIS`` record defines the parent eFuse field. All the other records are child fields of ``WR_DIS`` due to their ``WR_DIS.`` prefix. +* The child fields must utilize the same bits as their parent field. Take note of ``bit_start`` and ``bit_count`` of the child and parent fields: -It is possible to create aliases for fields with the same range, see ``WR_DIS.FIELD_3`` and ``WR_DIS.FIELD_3.ALIAS``. + * The bits of the child fields are always in the range of their parent field. For example, ``WR_DIS.RD_DIS`` and ``WR_DIS.RD_DIS`` occupy the first and second bit of ``WR_DIS``. + * Child fields cannot use overlapping bits (except for when aliasing). -The ESP-IDF names for structured eFuse fields should be unique. The ``efuse_table_gen`` tool generates the final names where the dot is replaced by ``_``. The names for using in ESP-IDF are ESP_EFUSE_WR_DIS, ESP_EFUSE_WR_DIS_RD_DIS, ESP_EFUSE_WR_DIS_FIELD_2_B1, etc. +* It is possible to create aliases as a child field. For example, ``WR_DIS.FIELD_3.ALIAS`` is a child field and alias of ``WR_DIS.FIELD_3`` as they both occupy the same bits. -The ``efuse_table_gen`` tool checks that the fields do not overlap each other and must be within the range of a field if there is a violation, then throws the following error: +All eFuse Fields are eventually converted to C structures via the ``efuse_table_gen.py`` tool. The C structure for each eFuse field will derive their identifier from the ``field_name`` of the eFuse field's record, where all ``.`` are replaced with ``_``. For example, the C symbols for ``WR_DIS.RD_DIS`` and ``WR_DIS.FIELD_2.B1`` will be ``ESP_EFUSE_WR_DIS_RD_DIS`` and ``ESP_EFUSE_WR_DIS_FIELD_2_B1`` respectively. + +The ``efuse_table_gen.py`` tool also checks that the fields do not overlap each other and must be within the range of a field. If there is a violation, then the following error is generated: .. code-block:: none - Field at USER_DATA, EFUSE_BLK3, 0, 256 intersected with SERIAL_NUMBER, EFUSE_BLK3, 0, 32 + Field at USER_DATA, EFUSE_BLK3, 0, 256 intersected with SERIAL_NUMBER, EFUSE_BLK3, 0, 32 -Solution: Describe ``SERIAL_NUMBER`` to be included in ``USER_DATA``. (``USER_DATA.SERIAL_NUMBER``). +In this case, the error can be resolved by making ``SERIAL_NUMBER`` a child field of ``USER_DATA`` via ``USER_DATA.SERIAL_NUMBER``. .. code-block:: none - Field at FIELD, EFUSE_BLK3, 0, 50 out of range FIELD.MAJOR_NUMBER, EFUSE_BLK3, 60, 32 + Field at FIELD, EFUSE_BLK3, 0, 50 out of range FIELD.MAJOR_NUMBER, EFUSE_BLK3, 60, 32 -Solution: Change ``bit_start`` for ``FIELD.MAJOR_NUMBER`` from 60 to 0, so ``MAJOR_NUMBER`` is in the ``FIELD`` range. +In this case, the error can be resolved by changing ``bit_start`` for ``FIELD.MAJOR_NUMBER`` from ``60`` to ``0`` so that ``MAJOR_NUMBER`` overlaps with ``FIELD``. ``efuse_table_gen.py`` Tool --------------------------- -The tool is designed to generate C-source files from CSV file and validate fields. First of all, the check is carried out on the uniqueness of the names and overlaps of the field bits. If an additional `custom` file is used, it will be checked with the existing `common` file (esp_efuse_table.csv). In case of errors, a message will be displayed and the string that caused the error. C-source files contain structures of type `esp_efuse_desc_t`. +The ``efuse_table_gen.py`` tool is designed to generate C source files containing C structures (of type :cpp:type:`esp_efuse_desc_t`) representing the eFuse fields defined in CSV files. Moreover, the tool also runs some checks on the provided CSV files before generation to ensure that: + +- the names of the eFuse fields are unique +- the eFuse fields do not use overlapping bits + +As mentioned previously, eFuse fields can be used to hold either system parameters or user parameters. Given that system parameter eFuse fields are inherently required by ESP-IDF and {IDF_TARGET_NAME}, those eFuse fields are defined in a **common** CSV file (``esp_efuse_table.csv``) and distributed as part of ESP-IDF. For user parameter eFuse fields, users should define those fields in a **custom** CSV file (e.g., ``esp_efuse_custom_table.csv``). -To generate a `common` files, use the following command ``idf.py efuse-common-table`` or: +To generate C source files using the **common** CSV file, use the ``idf.py efuse-common-table`` or the following: .. code-block:: bash cd $IDF_PATH/components/efuse/ ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv -After generation in the folder $IDF_PATH/components/efuse/`{IDF_TARGET_PATH_NAME}` create: +The following C source/header files will be generated by the tool in ``$IDF_PATH/components/efuse/{IDF_TARGET_PATH_NAME}``: -* `esp_efuse_table.c` file. -* In `include` folder `esp_efuse_table.c` file. +* ``esp_efuse_table.c`` file containing the C structures of the system parameter eFuse fields +* ``esp_efuse_table.h`` file in the ``include`` folder. This header can be included by the application to use those C structures. -To generate a `custom` files, use the following command ``idf.py efuse-custom-table`` or: +To generate C source files using a **custom** CSV file, use the command ``idf.py efuse-custom-table`` or the following: .. code-block:: bash cd $IDF_PATH/components/efuse/ ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv PROJECT_PATH/main/esp_efuse_custom_table.csv -After generation in the folder PROJECT_PATH/main create: +The following C source/header files will be generated by the tool in ``PROJECT_PATH/main``: -* `esp_efuse_custom_table.c` file. -* In `include` folder `esp_efuse_custom_table.c` file. +* ``esp_efuse_custom_table.c`` file containing the C structures of the user parameter eFuse fields +* ``esp_efuse_custom_table.h`` file in the ``include`` folder. This header can be included by the application to use those C structures. To use the generated fields, you need to include two files: @@ -209,56 +227,101 @@ To use the generated fields, you need to include two files: #include "esp_efuse_table.h" // or "esp_efuse_custom_table.h" -Supported Coding Scheme ------------------------ +Supported Coding Schemes +------------------------ + +Various coding schemes are supported by eFuses which can protect eFuses against data corruption by detecting and/or correcting for errors. .. only:: esp32 - eFuse have three coding schemes: + {IDF_TARGET_NAME} supports the following eFuse coding schemes: - * ``None`` (value 0). + * ``None`` (value 0), meaning no coding scheme is applied. * ``3/4`` (value 1). - * ``Repeat`` (value 2). + * ``Repeat`` (value 2). It is not entirely supported by IDF, not recommended for use. - The coding scheme affects only EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3 blocks. EUSE_BLK0 block always has a coding scheme ``None``. - Coding changes the number of bits that can be written into a block, the block length is constant 256, some of these bits are used for encoding and not available for the user. + The coding schemes will encode each eFuse block individually. Furthermore, only EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3 will be encoded, meaning EUSE_BLK0 always uses the ``None`` coding scheme. - When using a coding scheme, the length of the payload that can be written is limited (for more details ``20.3.1.3 System Parameter coding_scheme``): + Coding schemes require some bits within an eFuse block to be used as overhead. Thus, by applying a coding scheme, only a subset of the 256 bits within an eFuse block will be usable as eFuse fields. - * None 256 bits. - * 3/4 192 bits. - * Repeat 128 bits. + * ``None``: 256 usable bits + * ``3/4``: 192 usable bits + * ``Repeat``: 128 usable bits + + When using a coding scheme, the length of the payload that can be written is limited. For more details, Please Refer to *{IDF_TARGET_NAME} Technical Reference Manual* > *Chapter 20 eFuse Controller* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__] > *Section 20.3.1.3 System Parameter coding_scheme*. You can find out the coding scheme of your chip: - * run a ``idf.py efuse-summary`` command. + * run the ``idf.py efuse-summary`` command. * from ``esptool`` utility logs (during flashing). - * calling the function in the code :cpp:func:`esp_efuse_get_coding_scheme` for the EFUSE_BLK3 block. + * calling the function :cpp:func:`esp_efuse_get_coding_scheme` in the application for the EFUSE_BLK3 block. + + The eFuse fields specified in the CSV files must always comply with the eFuse coding scheme used by the chip. The :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR` option selects which coding scheme is used by the CSV files. When generating source files, if the records in the CSV files do not adhere to the coding scheme, an error message will be displayed. In that case, you must adjust the ``bit_start`` and ``bit_count`` of the records to comply with the limitations of the selected coding scheme. + + .. note:: - eFuse tables must always comply with the coding scheme in the chip. There is an :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR` option to select the coding type for tables in a Kconfig. When generating source files, if your tables do not follow the coding scheme, an error message will be displayed. Adjust the length or offset fields. - If your program was compiled with ``None`` encoding and ``3/4`` is used in the chip, then the ``ESP_ERR_CODING`` error may occur when calling the eFuse API (the field is outside the block boundaries). If the field matches the new block boundaries, then the API will work without errors. + After changing the coding scheme, run ``efuse_common_table`` and ``efuse_custom_table`` commands to check the tables of the new coding scheme. - Also, 3/4 coding scheme imposes restrictions on writing bits belonging to one coding unit. The whole block with a length of 256 bits is divided into 4 coding units, and in each coding unit there are 6 bytes of useful data and 2 service bytes. These 2 service bytes contain the checksum of the previous 6 data bytes. + If your program was compiled with ``None`` encoding but ``3/4`` is used by the chip, then the ``ESP_ERR_CODING`` error may occur when calling the eFuse API (The field is outside the block boundaries). If the field matches the new block boundaries, then the API will work without errors. - It turns out that only one field can be written into one coding unit. Repeated rewriting in one coding unit is prohibited. But if the record was made in advance or through a :cpp:func:`esp_efuse_write_block` function, then reading the fields belonging to one coding unit is possible. + ``None`` Coding Scheme + ^^^^^^^^^^^^^^^^^^^^^^ - In case ``3/4`` coding scheme, the writing process is divided into the coding units and we cannot use the usual mode of writing some fields. We can prepare all the data for writing and burn it in one time. You can also use this mode for ``None`` coding scheme but it is not necessary. It is important for ``3/4`` coding scheme. - ``The batch writing mode`` blocks ``esp_efuse_read_...`` operations. + The ``None`` coding scheme indicates that no coding scheme is applied, thus all 256 bits of each eFuse block are usable. However, there will be no protection against the corruption of eFuse bits. - After changing the coding scheme, run ``efuse_common_table`` and ``efuse_custom_table`` commands to check the tables of the new coding scheme. + ``3/4`` Coding Scheme + ^^^^^^^^^^^^^^^^^^^^^ + + The ``3/4`` coding scheme imposes restrictions on writing bits belonging to one coding unit. The whole block with a length of 256 bits is divided into 4 coding units. In each coding unit there are 6 bytes of useful data and 2 service bytes. These 2 service bytes contain the checksum of the previous 6 data bytes. + + Due to the calculation of the checksum for each coding unit, the writing process must be divided into the coding units. As such, the normal method (used by the ``None`` coding scheme) of burning eFuse bits separately over multiple write operations will no longer work. The data for the eFuse fields of a particular coding unit and the unit's associated checksum must be burned in one go. This is known as Batch Writing Mode. + + As a result of Batch Writing Mode, a particular coding unit can only be written once (i.e., repeated writing to the same coding unit is prohibited). Thus, any coding unit that is written at run time can only contain one eFuse field. However, if the eFuse fields of a coding unit was specified in advance (via CSV records) or written to via :cpp:func:`esp_efuse_write_block`, then a coding unit can still contain multiple eFuse fields. + + ``Repeat`` Coding Scheme + ^^^^^^^^^^^^^^^^^^^^^^^^ + + The ``Repeat`` coding scheme simply repeats each eFuse bit, thus does not impose the same Batch Writing Mode restrictions as the ``3/4`` coding scheme. However, this comes at the cost of a larger overhead, leaving only 128 usable bits per eFuse block. .. only:: not esp32 - Coding schemes are used to protect against data corruption. {IDF_TARGET_NAME} supports two coding schemes: + {IDF_TARGET_NAME} does not support selection of coding schemes. The following coding schemes are automatically applied to various eFuse blocks: + + * ``None``: Applied to EFUSE_BLK0 + * ``RS``: Applied to EFUSE_BLK1 - {IDF_TARGET_MAX_EFUSE_BLK} + + ``None`` Coding Scheme + ^^^^^^^^^^^^^^^^^^^^^^ + + The ``None`` coding scheme is automatically applied to EFUSE_BLK0. This scheme does not involve any encoding, but simply maintains four backups of EFUSE_BLK0 in hardware, meaning each bit is stored four times. As a result, EFUSE_BLK0 can be written many times. + + This scheme is automatically applied by the hardware and is not visible to software. + + ``RS`` Coding Scheme + ^^^^^^^^^^^^^^^^^^^^^^ + + The ``RS`` coding scheme uses Reed-Solomon encoding and is automatically applied to EFUSE_BLK1 to {IDF_TARGET_MAX_EFUSE_BLK}. The coding scheme supports up to 6 bytes of automatic error correction. + + Software encodes the 32-byte EFUSE_BLKx using ``RS(44, 32)`` to generate a 12-byte check-symbols, and then burn the EFUSE_BLKx and the check-symbols into eFuse at the same time. + + The eFuse Controller automatically decodes the ``RS`` encoding and applies error correction when reading back the eFuse block. Because the ``RS`` check-symbols are generated across the entire 256-bit eFuse block, each block can only be written to one time. As a result of the check-symbols, Batch Writing Mode must be used. - * ``None``. EFUSE_BLK0 is stored with four backups, meaning each bit is stored four times. This backup scheme is automatically applied by the hardware and is not visible to software. EFUSE_BLK0 can be written many times. - * ``RS``. EFUSE_BLK1 - {IDF_TARGET_MAX_EFUSE_BLK} use Reed-Solomon coding scheme that supports up to 5 bytes of automatic error correction. Software encodes the 32-byte EFUSE_BLKx using RS (44, 32) to generate a 12-byte check code, and then burn the EFUSE_BLKx and the check code into eFuse at the same time. The eFuse Controller automatically decodes the RS encoding and applies error correction when reading back the eFuse block. Because the RS check codes are generated across the entire 256-bit eFuse block, each block can only be written to one time. +Batch Writing Mode +^^^^^^^^^^^^^^^^^^ -To write some fields into one block, or different blocks in one time, you need to use ``the batch writing mode``. Firstly set this mode through :cpp:func:`esp_efuse_batch_write_begin` function then write some fields as usual using the ``esp_efuse_write_...`` functions. At the end to burn them, call the :cpp:func:`esp_efuse_batch_write_commit` function. It burns prepared data to the eFuse blocks and disables the ``batch recording mode``. +When writing to eFuse fields at run time, it may be necessary to use the Batch Writing Mode depending on the coding scheme used for eFuse block. Batch writing mode can be used as follows: -.. note:: +#. Enable batch writing mode by calling :cpp:func:`esp_efuse_batch_write_begin` +#. Write to the eFuse fields as usual using various ``esp_efuse_write_...`` functions. +#. Once all writes are complete, call :cpp:func:`esp_efuse_batch_write_commit` which burns prepared data to the eFuse blocks. - If there is already pre-written data in the eFuse block using the ``{IDF_TARGET_CODING_SCHEMES}`` encoding scheme, then it is not possible to write anything extra (even if the required bits are empty) without breaking the previous encoding data. This encoding data will be overwritten with new encoding data and completely destroyed (however, the payload eFuses are not damaged). It can be related to: CUSTOM_MAC, SPI_PAD_CONFIG_HD, SPI_PAD_CONFIG_CS, etc. Please contact Espressif to order the required pre-burnt eFuses. +.. warning:: + + If there is already pre-written data in the eFuse block using the ``{IDF_TARGET_CODING_SCHEMES}`` encoding scheme, then it is not possible to write anything extra (even if the required bits are empty) without breaking the previous data's checksums/check-symbols. + + The checksums/check-symbols will be overwritten with new checksums/check-symbols and be completely destroyed (however, the payload eFuses are not damaged). + + If you happen to find pre-written data in CUSTOM_MAC, SPI_PAD_CONFIG_HD, SPI_PAD_CONFIG_CS, etc., please contact Espressif to obtain the required pre-burnt eFuses. FOR TESTING ONLY (NOT RECOMMENDED): You can ignore or suppress errors that violate encoding scheme data in order to burn the necessary bits in the eFuse block. @@ -277,8 +340,8 @@ Access to the fields is via a pointer to the description structure. API function * :cpp:func:`esp_efuse_read_reg` - returns value of eFuse register. * :cpp:func:`esp_efuse_write_reg` - writes value to eFuse register. * :cpp:func:`esp_efuse_get_coding_scheme` - returns eFuse coding scheme for blocks. -* :cpp:func:`esp_efuse_read_block` - reads key to eFuse block starting at the offset and the required size. -* :cpp:func:`esp_efuse_write_block` - writes key to eFuse block starting at the offset and the required size. +* :cpp:func:`esp_efuse_read_block` - reads a key from an eFuse block starting at the offset with required size. +* :cpp:func:`esp_efuse_write_block` - writes a key to an eFuse block starting at the offset with required size. * :cpp:func:`esp_efuse_batch_write_begin` - set the batch mode of writing fields. * :cpp:func:`esp_efuse_batch_write_commit` - writes all prepared data for batch writing mode and reset the batch writing mode. * :cpp:func:`esp_efuse_batch_write_cancel` - reset the batch writing mode and prepared data. @@ -287,12 +350,12 @@ Access to the fields is via a pointer to the description structure. API function * :cpp:func:`esp_efuse_get_key_dis_write` - Returns a write protection for the key block. * :cpp:func:`esp_efuse_set_key_dis_write` - Sets a write protection for the key block. * :cpp:func:`esp_efuse_get_key_purpose` - Returns the current purpose set for an eFuse key block. -* :cpp:func:`esp_efuse_write_key` - Programs a block of key data to an eFuse block -* :cpp:func:`esp_efuse_write_keys` - Programs keys to unused eFuse blocks +* :cpp:func:`esp_efuse_write_key` - Programs a block of key data to an eFuse block. +* :cpp:func:`esp_efuse_write_keys` - Programs keys to unused eFuse blocks. * :cpp:func:`esp_efuse_find_purpose` - Finds a key block with the particular purpose set. * :cpp:func:`esp_efuse_get_keypurpose_dis_write` - Returns a write protection of the key purpose field for an eFuse key block (for esp32 always true). * :cpp:func:`esp_efuse_key_block_unused` - Returns true if the key block is unused, false otherwise. -* :cpp:func:`esp_efuse_destroy_block` - Destroys the data in this eFuse block. There are two things to do (1) if write protection is not set, then the remaining unset bits are burned, (2) set read protection for this block if it is not locked. +* :cpp:func:`esp_efuse_destroy_block` - Destroys the data in this eFuse block. There are two things to do: (1) if write protection is not set, then the remaining unset bits are burned, (2) set read protection for this block if it is not locked. For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_pkg_ver`. @@ -309,14 +372,14 @@ For frequently used fields, special functions are made, like this :cpp:func:`esp The purposes like ``ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST...`` are used for secure boot. - There are some eFuse APIs useful to work with states of keys. + There are some eFuse APIs useful to work with states of keys: * :cpp:func:`esp_efuse_get_purpose_field` - Returns a pointer to a key purpose for an eFuse key block. * :cpp:func:`esp_efuse_get_key` - Returns a pointer to a key block. * :cpp:func:`esp_efuse_set_key_purpose` - Sets a key purpose for an eFuse key block. * :cpp:func:`esp_efuse_set_keypurpose_dis_write` - Sets a write protection of the key purpose field for an eFuse key block. * :cpp:func:`esp_efuse_find_unused_key_block` - Search for an unused key block and return the first one found. - * :cpp:func:`esp_efuse_count_unused_key_blocks` - Returns the number of unused eFuse key blocks in the range EFUSE_BLK_KEY0..EFUSE_BLK_KEY_MAX + * :cpp:func:`esp_efuse_count_unused_key_blocks` - Returns the number of unused eFuse key blocks in the range EFUSE_BLK_KEY0 to EFUSE_BLK_KEY_MAX .. only:: SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY @@ -329,13 +392,13 @@ For frequently used fields, special functions are made, like this :cpp:func:`esp How to Add a New Field ---------------------- -1. Find a free bits for field. Show `esp_efuse_table.csv` file or run ``idf.py show-efuse-table`` or the next command: +1. Find free bits for field. Refer to the ``esp_efuse_table.csv`` file, running ``idf.py show-efuse-table``, or running the following command: .. include:: inc/show-efuse-table_{IDF_TARGET_NAME}.rst -The number of bits not included in square brackets is free (some bits are reserved for Espressif). All fields are checked for overlapping. +The number of bits not included in square brackets are free (some bits are reserved by Espressif). All fields are checked for overlapping bits. -To add fields to an existing field, use the :ref:`Structured efuse fields ` technique. For example, adding the fields: SERIAL_NUMBER, MODEL_NUMBER and HARDWARE REV to an existing ``USER_DATA`` field. Use ``.`` (dot) to show an attachment in a field. +To add child fields to an existing field, :ref:`structured-efuse-fields` can be used. The following example demonstrates adding of the the fields ``SERIAL_NUMBER``, ``MODEL_NUMBER`` and ``HARDWARE_REV`` to an existing ``USER_DATA`` field by using the ``.`` operator: .. code-block:: none @@ -343,16 +406,18 @@ To add fields to an existing field, use the :ref:`Structured efuse fields ` article. +You may get errors such as ``intersects with`` or ``out of range``. Please see how to solve them in the :ref:`structured-efuse-fields` article. Bit Order --------- -The eFuses bit order is little endian (see the example below), it means that eFuse bits are read and written from LSB to MSB: +The eFuses bit order is little endian (see the example below), meaning that eFuse bits are read and written from LSB to MSB: .. code-block:: none @@ -376,7 +441,7 @@ The eFuses bit order is little endian (see the example below), it means that eFu byte[0] = 0x00, byte[1] = 0x01, ... byte[3] = 0x03, byte[4] = 0x04, ..., byte[31] = 0x1F -For example, csv file describes the ``USER_DATA`` field, which occupies all 256 bits (a whole block). +For example, CSV file describes the ``USER_DATA`` field, which occupies all 256 bits (a whole block). .. code-block:: none @@ -406,7 +471,7 @@ Thus, reading the eFuse ``USER_DATA`` block written as above gives the following uint8_t id = 0; size_t id_size = esp_efuse_get_field_size(ESP_EFUSE_ID); // returns 6 - // size_t id_size = ESP_EFUSE_USER_DATA[0]->bit_count; // cannot be used because it consists of 3 entries. It returns 3 not 6. + // size_t id_size = ESP_EFUSE_USER_DATA[0]->bit_count; // cannot be used because it consists of 3 entries. It returns 3 not 6 esp_efuse_read_field_blob(ESP_EFUSE_ID, &id, id_size); // id = 0x91 // b'100 10 001 @@ -417,15 +482,16 @@ Thus, reading the eFuse ``USER_DATA`` block written as above gives the following // id = 0x01 // b'001 + Get eFuses During Build ----------------------- -There is a way to get the state of eFuses at the build stage of the project. There are two cmake functions for this: +There is a way to get the state of eFuses at the build stage of the project. There are two CMake functions for this: -* ``espefuse_get_json_summary()`` - It calls the ``espefuse.py summary --format json`` command and returns a json string (it is not stored in a file). -* ``espefuse_get_efuse()`` - It finds a given eFuse name in the json string and returns its property. +* ``espefuse_get_json_summary()`` - It calls the ``espefuse.py summary --format json`` command and returns a JSON string (it is not stored in a file). +* ``espefuse_get_efuse()`` - It finds a given eFuse name in the JSON string and returns its property. -The json string has the following properties: +The JSON string has the following properties: .. code-block:: json @@ -472,25 +538,33 @@ Debug eFuse & Unit Tests Virtual eFuses ^^^^^^^^^^^^^^ -The Kconfig option :ref:`CONFIG_EFUSE_VIRTUAL` virtualizes eFuse values inside the eFuse Manager, so writes are emulated and no eFuse values are permanently changed. This can be useful for debugging app and unit tests. +The Kconfig option :ref:`CONFIG_EFUSE_VIRTUAL` virtualizes eFuse values inside the eFuse Manager, so writes are emulated and no eFuse values are permanently changed. This can be useful for debugging and unit testing. + During startup, the eFuses are copied to RAM. All eFuse operations (read and write) are performed with RAM instead of the real eFuse registers. -In addition to the :ref:`CONFIG_EFUSE_VIRTUAL` option there is :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` option that adds a feature to keep eFuses in flash memory. To use this mode the partition_table should have the `efuse` partition. partition.csv: ``"efuse_em, data, efuse, , 0x2000,"``. -During startup, the eFuses are copied from flash or, in case if flash is empty, from real eFuse to RAM and then update flash. This option allows keeping eFuses after reboots (possible to test secure_boot and flash_encryption features with this option). +In addition to the :ref:`CONFIG_EFUSE_VIRTUAL` option, there is the :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` option that adds a feature to keep eFuses in flash memory. To use this mode, the partition_table should have include an ``efuse`` partition in ``partition.csv``: + +.. code-block:: none + + efuse_em, data, efuse, , 0x2000, + +During startup, the eFuses are copied from flash, or in case where flash is empty, copied from real eFuse to RAM and then write flash. This option allows keeping eFuses after reboots, making it possible to test Secure Boot and Flash Encryption features. Flash Encryption Testing """""""""""""""""""""""" -Flash Encryption (FE) is a hardware feature that requires the physical burning of eFuses: key and FLASH_CRYPT_CNT. If FE is not actually enabled then enabling the :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` option just gives testing possibilities and does not encrypt anything in the flash, even though the logs say encryption happens. The :cpp:func:`bootloader_flash_write` is adapted for this purpose. But if FE is already enabled on the chip and you run an application or bootloader created with the :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` option then the flash encryption/decryption operations will work properly (data are encrypted as it is written into an encrypted flash partition and decrypted when they are read from an encrypted partition). +Flash encryption is a hardware feature that requires the physical burning of eFuses ``key`` and ``FLASH_CRYPT_CNT``. If flash encryption is not actually enabled, then enabling the :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` option just provides testing possibilities and does not encrypt anything in the flash, even though the logs indicates that encryption happens. + +The :cpp:func:`bootloader_flash_write` is adapted for this purpose. But if flash encryption is already enabled on the chip when the application is run, or if the bootloader is created with the :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` option, then the flash encryption/decryption operations will work properly. This means that data are encrypted as it is written into an encrypted flash partition and decrypted when they are read from an encrypted partition. ``espefuse.py`` ^^^^^^^^^^^^^^^ esptool includes a useful tool for reading/writing {IDF_TARGET_NAME} eFuse bits - `espefuse.py `_. + Part of the functionality of this tool is also provided directly by ``idf.py`` commands. For example, the ``idf.py efuse-summary`` command is equivalent to ``espefuse.py summary``. .. include:: inc/espefuse_summary_{IDF_TARGET_NAME}.rst - .. include-build-file:: inc/esp_efuse_chip.inc .. include-build-file:: inc/esp_efuse.inc diff --git a/docs/en/api-reference/system/log.rst b/docs/en/api-reference/system/log.rst index 452161ddb146..ecf94d0cee29 100644 --- a/docs/en/api-reference/system/log.rst +++ b/docs/en/api-reference/system/log.rst @@ -96,7 +96,7 @@ The log component provides several options to better adjust the system to your n - (Default) "Cache + Linked List". This option enables the ability to set the log level per tag. This hybrid approach offers a balance between speed and memory usage. The cache stores recently accessed log tags and their corresponding log levels, providing faster lookups for frequently used tags. When the :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` option is enabled, log levels to be changed at runtime via :cpp:func:`esp_log_level_set`. Dynamic log levels increase flexibility but also incurs additional code size. -If your application doesn't require dynamic log level changes and you do not need to control logs per module using tags, consider disabling :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL`. It reduces IRAM usage by approximately 260 bytes, DRAM usage by approximately 264 bytes, and Flash usage by approximately 1K bytes compared to the default option. It is not only streamlines logs for memory efficiency but also contributes to speeding up log operations in your application about 10 times. +If your application does not require dynamic log level changes and you do not need to control logs per module using tags, consider disabling :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL`. It reduces IRAM usage by approximately 260 bytes, DRAM usage by approximately 264 bytes, and flash usage by approximately 1 KB compared to the default option. It is not only streamlines logs for memory efficiency but also contributes to speeding up log operations in your application about 10 times. .. note:: diff --git a/docs/en/api-reference/system/power_management.rst b/docs/en/api-reference/system/power_management.rst index 727c6c56c3f8..216eff12de85 100644 --- a/docs/en/api-reference/system/power_management.rst +++ b/docs/en/api-reference/system/power_management.rst @@ -142,15 +142,14 @@ Light-sleep Peripheral Power Down - INT_MTX - TEE/APM - IO_MUX / GPIO - - UART0 - - TIMG0 + - UART0/1 + - GPTimer - SPI0/1 - SYSTIMER - RMT The following peripherals are not yet supported: - ETM - - TIMG1 - ASSIST_DEBUG - Trace - Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA @@ -164,7 +163,6 @@ Light-sleep Peripheral Power Down - SARADC - SDIO - PARL_IO - - UART1 For peripherals that do not support Light-sleep context retention, if the Power management is enabled, the ``ESP_PM_NO_LIGHT_SLEEP`` lock should be held when the peripheral is working to avoid losing the working context of the peripheral when entering sleep. diff --git a/docs/en/api-reference/system/ulp-lp-core.rst b/docs/en/api-reference/system/ulp-lp-core.rst index cc131a1a801b..70e59eb4054f 100644 --- a/docs/en/api-reference/system/ulp-lp-core.rst +++ b/docs/en/api-reference/system/ulp-lp-core.rst @@ -7,7 +7,7 @@ The ULP LP-Core (Low-power core) coprocessor is a variant of the ULP present in The ULP LP-Core coprocessor has the following features: -* Utilizes a 32-bit processor based on the RISC-V ISA, encompassing the standard extensions integer (I), multiplication/division (M), atomic (A), and compressed (C). +* A RV32I (32-bit RISC-V ISA) processor, with the multiplication/division (M), atomic (A), and compressed (C) extensions. * Interrupt controller. * Includes a debug module that supports external debugging via JTAG. * Can access all of the High-power (HP) SRAM and peripherals when the entire system is active. @@ -22,6 +22,8 @@ The ULP LP-Core code is compiled together with your ESP-IDF project as a separat 2. After registering the component in the CMakeLists.txt file, call the ``ulp_embed_binary`` function. Here is an example: +.. code-block:: cmake + idf_component_register() set(ulp_app_name ulp_${COMPONENT_NAME}) @@ -32,7 +34,7 @@ The ULP LP-Core code is compiled together with your ESP-IDF project as a separat The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The name specified here is also used by other generated artifacts such as the ELF file, map file, header file, and linker export file. The second argument specifies the ULP source files. Finally, the third argument specifies the list of component source files which include the header file to be generated. This list is needed to build the dependencies correctly and ensure that the generated header file is created before any of these files are compiled. See the section below for the concept of generated header files for ULP applications. -1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menucofig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP, and must be set to a value big enough to store both the ULP LP-Core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one. +1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menuconfig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP, and must be set to a value big enough to store both the ULP LP-Core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one. 2. Build the application as usual (e.g., ``idf.py app``). @@ -59,7 +61,7 @@ Accessing the ULP LP-Core Program Variables Global symbols defined in the ULP LP-Core program may be used inside the main program. -For example, the ULP LP-Core program may define a variable ``measurement_count`` which defines the number of GPIO measurements the program needs to make before waking up the chip from deep sleep. +For example, the ULP LP-Core program may define a variable ``measurement_count`` which defines the number of GPIO measurements the program needs to make before waking up the chip from Deep-sleep. .. code-block:: c @@ -83,7 +85,9 @@ The header file contains the declaration of the symbol: Note that all symbols (variables, arrays, functions) are declared as ``uint32_t``. For functions and arrays, take the address of the symbol and cast it to the appropriate type. -The generated linker script file defines the locations of symbols in LP_MEM:: +The generated linker script file defines the locations of symbols in LP_MEM: + +.. code-block:: none PROVIDE ( ulp_measurement_count = 0x50000060 ); @@ -97,6 +101,10 @@ To access the ULP LP-Core program variables from the main program, the generated ulp_measurement_count = 64; } +.. note:: + + Variables declared in the global scope of the LP-Core program reside in either the ``.bss`` or ``.data`` section of the binary. These sections are initialized when the LP-Core binary is loaded and executed. Accessing these variables from the main program on the HP-Core before the first LP-Core run may result in undefined behavior. + Starting the ULP LP-Core Program -------------------------------- @@ -129,7 +137,7 @@ Once the program is loaded into LP memory, the application can be configured and ULP LP-Core Program Flow ------------------------ -How the ULP LP-Core coprocessor is started depends on the wakeup source selected in :cpp:type:`ulp_lp_core_cfg_t`. The most common use-case is for the ULP to periodically wake-up, do some measurements before either waking up the main CPU or going back to sleep again. +How the ULP LP-Core coprocessor is started depends on the wake-up source selected in :cpp:type:`ulp_lp_core_cfg_t`. The most common use-case is for the ULP to periodically wake up, do some measurements before either waking up the main CPU or going back to sleep again. The ULP has the following wake-up sources: * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU` - LP Core can be woken up by the HP CPU. @@ -153,7 +161,7 @@ When the ULP is woken up, it will go through the following steps: ULP LP-Core Peripheral Support ------------------------------ -To enhance the capabilities of the ULP LP-Core coprocessor, it has access to peripherals which operate in the low-power domain. The ULP LP-Core coprocessor can interact with these peripherals when the main CPU is in sleep mode, and can wake up the main CPU once a wakeup condition is reached. The following peripherals are supported: +To enhance the capabilities of the ULP LP-Core coprocessor, it has access to peripherals that operate in the low-power domain. The ULP LP-Core coprocessor can interact with these peripherals when the main CPU is in sleep mode, and can wake up the main CPU once a wake-up condition is reached. The following peripherals are supported: .. list:: @@ -166,7 +174,7 @@ To enhance the capabilities of the ULP LP-Core coprocessor, it has access to per ULP LP-Core ROM --------------- - The ULP LP-Core ROM is a small pre-built piece of code located in LP-ROM, which is not modifiable by users. Similar to the bootloader ROM code ran by the main CPU, this code is executed when the ULP LP-Core coprocessor is started. The ROM code initializes the ULP LP-Core coprocessor and then jumps to the user program. The ROM code also prints boot messages if the LP UART has been initialized. + The ULP LP-Core ROM is a small pre-built piece of code located in LP-ROM, which can't be modified. Similar to the bootloader ROM code ran by the main CPU, this code is executed when the ULP LP-Core coprocessor is started. The ROM code initializes the ULP LP-Core coprocessor and then jumps to the user program. The ROM code also prints boot messages if the LP UART has been initialized. The ROM code is not executed if :cpp:member:`ulp_lp_core_cfg_t::skip_lp_rom_boot` is set to true. This is useful when you need the ULP to wake-up as quickly as possible and the extra overhead of initializing and printing is unwanted. @@ -181,7 +189,7 @@ To enhance the capabilities of the ULP LP-Core coprocessor, it has access to per ULP LP-Core Interrupts ---------------------- -The LP-Core coprocessor can be configured to handle interrupts from various sources. Examples of such interrupts could be LP IO low/high or LP timer interrupts. To register a handler for an interrupt simply override any of the weak handlers provided by IDF. A complete list of handlers can be found in :component_file:`ulp_lp_core_interrupts.h `. For details on which interrupts are available on a specific target, please consult the Low Power CPU chapter in the Technical Reference Manual.` +The LP-Core coprocessor can be configured to handle interrupts from various sources. Examples of such interrupts could be LP IO low/high or LP timer interrupts. To register a handler for an interrupt, simply override any of the weak handlers provided by IDF. A complete list of handlers can be found in :component_file:`ulp_lp_core_interrupts.h `. For details on which interrupts are available on a specific target, please consult **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#ulp>`__]. For example, to override the handler for the LP IO interrupt, you can define the following function in your ULP LP-Core code: @@ -201,26 +209,26 @@ Debugging ULP LP-Core Applications When programming the LP-Core, it can sometimes be challenging to figure out why the program is not behaving as expected. Here are some strategies to help you debug your LP-Core program: - * Use the LP-UART to print: the LP-Core has access to the LP-UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver. +* Use the LP-UART to print: the LP-Core has access to the LP-UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver. - * Share program state through shared variables: as described in :ref:`ulp-lp-core-access-variables`, both the main CPU and the ULP core can easily access global variables in RTC memory. Writing state information to such a variable from the ULP and reading it from the main CPU can help you discern what is happening on the ULP core. The downside of this approach is that it requires the main CPU to be awake, which will not always be the case. Keeping the main CPU awake might even, in some cases, mask problems, as some issues may only occur when certain power domains are powered down. +* Share program state through shared variables: as described in :ref:`ulp-lp-core-access-variables`, both the main CPU and the ULP core can easily access global variables in RTC memory. Writing state information to such a variable from the ULP and reading it from the main CPU can help you discern what is happening on the ULP core. The downside of this approach is that it requires the main CPU to be awake, which will not always be the case. Keeping the main CPU awake might even, in some cases, mask problems, as some issues may only occur when certain power domains are powered down. - * Panic handler: the LP-Core has a panic handler that can dump the state of the LP-Core registers to the LP-UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP-Core application. To recover a backtrace from the panic dump it is possible to use esp-idf-monitor_., e.g.: +* Panic handler: the LP-Core has a panic handler that can dump the state of the LP-Core registers by the LP-UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP-Core application. To recover a backtrace from the panic dump, it is possible to use esp-idf-monitor_., e.g.: -.. code-block:: bash + .. code-block:: bash - python -m esp_idf_monitor --toolchain-prefix riscv32-esp-elf- --target {IDF_TARGET_NAME} --decode-panic backtrace PATH_TO_ULP_ELF_FILE + python -m esp_idf_monitor --toolchain-prefix riscv32-esp-elf- --target {IDF_TARGET_NAME} --decode-panic backtrace PATH_TO_ULP_ELF_FILE Application Examples -------------------- -* :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in deep sleep. +* :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in Deep-sleep. * :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met. * :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core. * :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core. * :example:`system/ulp/lp_core/interrupt` shows how to register an interrupt handler on the LP core to receive an interrupt triggered by the main CPU. -* :example:`system/ulp/lp_core/gpio_intr_pulse_counter` shows how to use GPIO interrupts to count pulses while the main CPU is in deep sleep. +* :example:`system/ulp/lp_core/gpio_intr_pulse_counter` shows how to use GPIO interrupts to count pulses while the main CPU is in Deep-sleep mode. API Reference ------------- diff --git a/docs/en/api-reference/system/ulp-risc-v.rst b/docs/en/api-reference/system/ulp-risc-v.rst index 377ab15150ab..7b78fca49927 100644 --- a/docs/en/api-reference/system/ulp-risc-v.rst +++ b/docs/en/api-reference/system/ulp-risc-v.rst @@ -103,6 +103,11 @@ To access the ULP RISC-V program variables from the main program, the generated ulp_measurement_count = 64; } +.. note:: + + Variables declared in the global scope of the ULP RISC-V program reside in either the ``.bss`` or ``.data`` section of the binary. These sections are initialized when the ULP RISC-V binary is loaded and executed. Accessing these variables from the main program on the main CPU before the first ULP RISC-V run may result in undefined behavior. + + Mutual Exclusion ^^^^^^^^^^^^^^^^ diff --git a/docs/en/contribute/install-pre-commit-hook.rst b/docs/en/contribute/install-pre-commit-hook.rst index 79858ac7b355..98d76a84a367 100644 --- a/docs/en/contribute/install-pre-commit-hook.rst +++ b/docs/en/contribute/install-pre-commit-hook.rst @@ -3,13 +3,6 @@ Install Pre-commit Hook for ESP-IDF Project :link_to_translation:`zh_CN:[中文]` -Required Dependency -------------------- - -Python 3.8.* or above. This is our recommended Python version for ESP-IDF developers. - -If you still have Python versions not compatible, update your Python versions before installing the pre-commit hook. - Install ``pre-commit`` ---------------------- diff --git a/docs/en/get-started/index.rst b/docs/en/get-started/index.rst index 7531a9a261ab..8f4bac790f1d 100644 --- a/docs/en/get-started/index.rst +++ b/docs/en/get-started/index.rst @@ -121,8 +121,8 @@ If you have one of {IDF_TARGET_NAME} official development boards listed below, y :maxdepth: 1 ESP32-S2-Saola-1 <../hw-reference/esp32s2/user-guide-saola-1-v1.2> - ESP32-S2-DevKitM-1 <../hw-reference/esp32s2/user-guide-devkitm-1-v1> - ESP32-S2-DevKitC-1 <../hw-reference/esp32s2/user-guide-s2-devkitc-1> + ESP32-S2-DevKitM-1 + ESP32-S2-DevKitC-1 ESP32-S2-Kaluga-Kit <../hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit> .. only:: esp32c3 diff --git a/docs/en/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst b/docs/en/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst deleted file mode 100644 index 5174afa98ee3..000000000000 --- a/docs/en/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst +++ /dev/null @@ -1,321 +0,0 @@ -================== -ESP32-S2-DevKitM-1 -================== - -:link_to_translation:`zh_CN:[中文]` - -This user guide provides information on Espressif's small-sized development board ESP32-S2-DevKitM-1. - -ESP32-S2-DevKitM-1 is entry-level development board. Most of the I/O pins on the module are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S2-DevKitM-1 on a breadboard. - -+----------------------+-----------------------+ -| |ESP32-S2-DevKitM-1| | |ESP32-S2-DevKitM-1U| | -+----------------------+-----------------------+ -| ESP32-S2-DevKitM-1 | ESP32-S2-DevKitM-1U | -+----------------------+-----------------------+ - -.. |ESP32-S2-DevKitM-1| image:: ../../../_static/esp32-s2-devkitm-1-v1-isometric.png - -.. |ESP32-S2-DevKitM-1U| image:: ../../../_static/esp32-s2-devkitm-1u-v1-isometric.png - -The document consists of the following major sections: - -- `Getting started`_: Provides an overview of the ESP32-S2-DevKitM-1 and hardware/software setup instructions to get started. -- `Hardware reference`_: Provides more detailed information about the ESP32-S2-DevKitM-1's hardware. -- `Hardware Revision Details`_: Revision history, known issues, and links to user guides for previous versions (if any) of ESP32-S2-DevKitM-1. -- `Related Documents`_: Gives links to related documentation. - - -Getting Started -=============== - -This section describes how to get started with ESP32-S2-DevKitM-1. It begins with a few introductory sections about the ESP32-S2-DevKitM-1, then Section `Start Application Development`_ provides instructions on how to get the ESP32-S2-DevKitM-1 ready and flash firmware into it. - - -Contents and Packaging ----------------------- - - -.. _user-guide-s2-devkitm-1-v1-ordering-info: - -Ordering Information -^^^^^^^^^^^^^^^^^^^^ - -The development board has a variety of variants to choose from, as shown in the table below. - -.. list-table:: - :header-rows: 1 - :widths: 41 24 9 8 18 - - * - Ordering Code - - On-board Module [#]_ - - Flash - - PSRAM - - Antenna - * - ESP32-S2-DevKitM-1-N4R2 - - ESP32-S2-MINI-2 - - (Recommended) - - 4 MB - - 2 MB - - PCB on-board antenna - * - ESP32-S2-DevKitM-1U-N4R2 - - ESP32-S2-MINI-2U - - (Recommended) - - 4 MB - - 2 MB - - External antenna connector - * - ESP32-S2-DevKitM-1 - - ESP32-S2-MINI-1 - - 4 MB - - --- - - PCB on-board antenna - * - ESP32-S2-DevKitM-1U - - ESP32-S2-MINI-1U - - 4 MB - - --- - - External antenna connector - * - ESP32-S2-DevKitM-1R - - ESP32-S2-MINI-1 - - 4 MB - - 2 MB - - PCB on-board antenna - * - ESP32-S2-DevKitM-1RU - - ESP32-S2-MINI-1U - - 4 MB - - 2 MB - - External antenna connector - - -.. [#] The ESP32-S2-MINI-2 and ESP32-S2-MINI-2U modules use chip revision v1.0, and the rest use chip revision v0.0. For more information about chip revisions, please refer to `ESP32-S2 Series SoC Errata`_. - - -Retail Orders -^^^^^^^^^^^^^ - -If you order a few samples, each ESP32-S2-DevKitM-1 comes in an individual package in either antistatic bag or any packaging depending on your retailer. - -For retail orders, please go to https://www.espressif.com/en/contact-us/get-samples. - - -Wholesale Orders -^^^^^^^^^^^^^^^^ - -If you order in bulk, the boards come in large cardboard boxes. - -For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions. - - -Description of Components -------------------------- - -.. _user-guide-devkitm-1-v1-board-front: - -.. figure:: ../../../_static/esp32-s2-devkitm-1-v1-annotated-photo.png - :align: center - :alt: ESP32-S2-DevKitM-1 - front - :figclass: align-center - - ESP32-S2-DevKitM-1 - front - -.. figure:: ../../../_static/esp32-s2-devkitm-1u-v1-annotated-photo.png - :align: center - :alt: ESP32-S2-DevKitM-1U - front - :figclass: align-center - - ESP32-S2-DevKitM-1U - front - -The key components of the board are described in a clockwise direction. - -.. list-table:: - :widths: 30 70 - :header-rows: 1 - - * - Key Component - - Description - * - On-board module (ESP32-S2-MINI-1 or ESP32-S2-MINI-1U in figures above) - - ESP32-S2-MINI series modules with an on-board PCB antenna or a connector for an external antenna. This series of modules, known for its small size, have a flash and/or a PSRAM integrated in the chip package. For more information, please refer to :ref:`user-guide-s2-devkitm-1-v1-ordering-info`. - * - Pin Headers - - All available GPIO pins (except for the SPI bus for flash) are broken out to the pin headers on the board. Users can program ESP32-S2FH4 chip to enable multiple functions such as SPI, I2S, UART, I2C, touch sensors, PWM etc. For details, please see :ref:`user-guide-devkitm-1-v1-header-blocks`. - * - 3.3 V Power On LED - - Turns on when the USB power is connected to the board. - * - USB to UART Bridge - - Single USB-UART bridge chip provides transfer rates up to 3 Mbps. - * - Reset Button - - Reset button. - * - Micro-USB Port - - USB interface. Power supply for the board as well as the communication interface between a computer and the ESP32-S2FH4 chip. - * - Boot Button - - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port. - * - RGB LED - - Addressable RGB LED, driven by GPIO18. - * - 5 V to 3.3 V LDO - - Power regulator that converts a 5 V supply into a 3.3 V output. - * - External Antenna Connector - - On **ESP32-S2-MINI-2U** and **ESP32-S2-MINI-1U** module only. For connector dimensions, please refer to Section External Antenna Connector Dimensions in module datasheet. - - -Start Application Development ------------------------------ - -Before powering up your ESP32-S2-DevKitM-1, please make sure that it is in good condition with no obvious signs of damage. - - -Required Hardware -^^^^^^^^^^^^^^^^^ - -- ESP32-S2-DevKitM-1 -- USB 2.0 cable (Standard-A to Micro-B) -- Computer running Windows, Linux, or macOS - -.. note:: - - Be sure to use an appropriate USB cable. Some cables are for charging only and do not provide the needed data lines nor work for programming the boards. - - -Software Setup -^^^^^^^^^^^^^^ - -Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example into your ESP32-S2-DevKitM-1. - -.. note:: - - ESP32-S2 series of chips only is only supported in ESP-IDF master or version v4.2 and higher. - - -Hardware Reference -================== - -Block Diagram -------------- - -A block diagram below shows the components of ESP32-S2-DevKitM-1 and their interconnections. - -.. figure:: ../../../_static/esp32-s2-devkitm-1-v1-block-diagram.png - :align: center - :scale: 70% - :alt: ESP32-S2-DevKitM-1 (click to enlarge) - :figclass: align-center - - ESP32-S2-DevKitM-1 (click to enlarge) - - -Power Supply Options -^^^^^^^^^^^^^^^^^^^^ - -There are three mutually exclusive ways to provide power to the board: - -- Micro-USB Port, default power supply -- 5V and GND pin headers -- 3V3 and GND pin headers - -It is recommended to use the first option: micro USB Port. - - -.. _user-guide-devkitm-1-v1-header-blocks: - -Header Block ------------- - -The two tables below provide the **Name** and **Function** of the pin headers on both sides of the board (J1 and J3). The pin header names are shown in :ref:`user-guide-devkitm-1-v1-board-front`. The numbering is the same as in the `ESP32-S2-DevKitM-1 Schematics `_ (PDF). - - -J1 -^^^ - -=== ==== ========== ============================================================= -No. Name Type [#]_ Function -=== ==== ========== ============================================================= -1 3V3 P 3.3 V power supply -2 0 I/O/T RTC_GPIO0, GPIO0 -3 1 I/O/T RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0 -4 2 I/O/T RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1 -5 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 -6 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 -7 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 -8 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 -9 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 -10 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 -11 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD -12 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 -13 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 -14 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 -15 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 -16 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS -17 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P -18 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N -19 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 -20 5V P 5 V power supply -21 G G Ground -=== ==== ========== ============================================================= - - -J3 -^^^ - -=== ==== ===== ======================================================== -No. Name Type Function -=== ==== ===== ======================================================== -1 G G Ground -2 RST I CHIP_PU -3 46 I GPIO46 -4 45 I/O/T GPIO45 -5 RX I/O/T U0RXD, GPIO44, CLK_OUT2 -6 TX I/O/T U0TXD, GPIO43, CLK_OUT1 -7 42 I/O/T MTMS, GPIO42 -8 41 I/O/T MTDI, GPIO41, CLK_OUT1 -9 40 I/O/T MTDO, GPIO40, CLK_OUT2 -10 39 I/O/T MTCK, GPIO39, CLK_OUT3 -11 38 I/O/T GPIO38, FSPIWP -12 37 I/O/T SPIDQS, GPIO37, FSPIQ -13 36 I/O/T SPIIO7, GPIO36, FSPICLK -14 35 I/O/T SPIIO6, GPIO35, FSPID -15 34 I/O/T SPIIO5, GPIO34, FSPICS0 -16 33 I/O/T SPIIO4, GPIO33, FSPIHD -17 26 I/O/T SPICS1, GPIO26 -18 21 I/O/T RTC_GPIO21, GPIO21 -19 20 I/O/T RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+ -20 19 I/O/T RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D- -21 18 I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED -=== ==== ===== ======================================================== - -.. [#] P: Power supply; I: Input; O: Output; T: High impedance. - - -Pin Layout -^^^^^^^^^^^ - -.. figure:: ../../../_static/esp32-s2-devkitm-1-v1-pin-layout.png - :align: center - :scale: 15% - :alt: ESP32-S2-DevKitM-1 (click to enlarge) - :figclass: align-center - - ESP32-S2-DevKitM-1 Pin Layout (click to enlarge) - - -Hardware Revision Details -========================= - -This is the first revision of this board released. - - -Related Documents -================= - -* `ESP32-S2 Series Chip Revision v1.0 Datasheet`_ (PDF) -* `ESP32-S2 Series Chip Revision v0.0 Datasheet `_ (PDF) -* `ESP32-S2 Series SoC Errata`_ (PDF) -* `ESP32-S2-MINI-2 & ESP32-S2-MINI-2U Module Datasheet `_ (PDF) -* `ESP32-S2-MINI-1 & ESP32-S2-MINI-1U Module Datasheet `_ (PDF) -* `ESP32-S2-DevKitM-1 Schematics `_ (PDF) -* `ESP32-S2-DevKitM-1 PCB Layout `_ (PDF) -* `ESP32-S2-DevKitM-1 Dimensions `_ (PDF) -* `ESP Product Selector `_ - -For other design documentation for the board, please contact us at `sales@espressif.com `_. - -.. _NRND: https://www.espressif.com/en/products/longevity-commitment?id=nrnd -.. _ESP32-S2 Series Chip Revision v1.0 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_en.pdf -.. _ESP32-S2 Series SoC Errata: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_en.pdf diff --git a/docs/en/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst b/docs/en/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst deleted file mode 100644 index d14331f64b97..000000000000 --- a/docs/en/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst +++ /dev/null @@ -1,313 +0,0 @@ -================== -ESP32-S2-DevKitC-1 -================== - -:link_to_translation:`zh_CN:[中文]` - -This user guide will help you get started with ESP32-S2-DevKitC-1 and will also provide more in-depth information. - -ESP32-S2-DevKitC-1 is an entry-level development board. This board integrates complete Wi-Fi functions. Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S2-DevKitC-1 on a breadboard. - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-isometric.png - :align: center - :alt: ESP32-S2-DevKitC-1 with the ESP32-S2-SOLO Module - :figclass: align-center - - ESP32-S2-DevKitC-1 with the ESP32-S2-SOLO Module - -The document consists of the following major sections: - -- `Getting Started`_: Overview of ESP32-S2-DevKitC-1 and hardware/software setup instructions to get started. -- `Hardware Reference`_: More detailed information about the ESP32-S2-DevKitC-1's hardware. -- `Hardware Revision Details`_: Revision history, known issues, and links to user guides for previous versions (if any) of ESP32-S2-DevKitC-1. -- `Related Documents`_: Links to related documentation. - - -Getting Started -=============== - -This section provides a brief introduction of ESP32-S2-DevKitC-1, instructions on how to do the initial hardware setup and how to flash firmware onto it. - - -Description of Components -------------------------- - -.. _user-guide-s2-devkitc-1-v1-board-front: - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-annotated-photo.png - :align: center - :alt: ESP32-S2-DevKitC-1 - front - :figclass: align-center - - ESP32-S2-DevKitC-1 - front - -The key components of the board are described in a clockwise direction. - -.. list-table:: - :widths: 30 70 - :header-rows: 1 - - * - Key Component - - Description - * - On-board module (ESP32-S2-SOLO or ESP32-S2-SOLO-U in the above figure) - - ESP32-S2-SOLO series modules with an on-board PCB antenna or a connector for an external antenna. This series of modules have multiple options for flash and PSRAM size. For more information, please refer to :ref:`user-guide-s2-devkitc-1-v1-ordering-info`. - * - 3.3 V Power On LED - - Turns on when the USB power is connected to the board. - * - USB-to-UART Bridge - - Single USB-to-UART bridge chip provides transfer rates up to 3 Mbps. - * - Pin Headers - - All available GPIO pins (except for the SPI bus for flash) are broken out to the pin headers on the board. For details, please see :ref:`user-guide-s2-devkitc-1-v1-header-blocks`. - * - ESP32-S2 USB Port - - ESP32-S2 full-speed USB OTG interface, compliant with the USB 1.1 specifications. The interface is used for power supply to the board, for flashing applications to the chip, and for communication with the chip using USB 1.1 protocols. - * - Reset Button - - Press this button to restart the system. - * - Boot Button - - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port. - * - USB-to-UART Port - - A Micro-USB port used for power supply to the board, for flashing applications to the chip, as well as the communication with the chip via the on-board USB-to-UART bridge. - * - RGB LED - - Addressable RGB LED, driven by GPIO18. - * - 5 V to 3.3 V LDO - - Power regulator that converts a 5 V supply into a 3.3 V output. - - -Start Application Development ------------------------------ - -Before powering up your ESP32-S2-DevKitC-1, please make sure that it is in good condition with no obvious signs of damage. - - -Required Hardware -^^^^^^^^^^^^^^^^^ - -- ESP32-S2-DevKitC-1 -- USB 2.0 cable (Standard-A to Micro-B) -- Computer running Windows, Linux, or macOS - -.. note:: - - Be sure to use an appropriate USB cable. Some cables are for charging only and do not provide the needed data lines nor work for programming the boards. - - -Hardware Setup -^^^^^^^^^^^^^^ - -Connect the board with the computer using **USB-to-UART Port** or **ESP32-S2 USB Port**. In subsequent steps, **USB-to-UART Port** will be used by default. - - -Software Setup -^^^^^^^^^^^^^^ - -Please proceed to `ESP-IDF Get Started `_, where Section `Installation Step by Step `_ will quickly help you set up the development environment and then flash an application example into your ESP32-S2-DevKitC-1. - - -Contents and Packaging ----------------------- - -.. _user-guide-s2-devkitc-1-v1-ordering-info: - -Ordering Information -^^^^^^^^^^^^^^^^^^^^ - -The development board has a variety of variants to choose from, as shown in the table below. - -.. list-table:: - :header-rows: 1 - :widths: 41 24 9 8 18 - - * - Ordering Code - - On-board Module [#]_ - - Flash - - PSRAM - - Antenna - * - ESP32-S2-DevKitC-1-N8R2 - - ESP32-S2-SOLO-2 - - (Recommended) - - 8 MB - - 2 MB - - PCB on-board antenna - * - ESP32-S2-DevKitC-1U-N8R2 - - ESP32-S2-SOLO-2U - - (Recommended) - - 8 MB - - 2 MB - - External antenna connector - * - ESP32-S2-DevKitC-1 - - ESP32-S2-SOLO - - 4 MB - - --- - - PCB on-board antenna - * - ESP32-S2-DevKitC-1U - - ESP32-S2-SOLO-U - - 4 MB - - --- - - External antenna connector - * - ESP32-S2-DevKitC-1R - - ESP32-S2-SOLO - - 4 MB - - 2 MB - - PCB on-board antenna - * - ESP32-S2-DevKitC-1RU - - ESP32-S2-SOLO-U - - 4 MB - - 2 MB - - External antenna connector - -.. [#] The ESP32-S2-SOLO-2 and ESP32-S2-SOLO-2U modules use chip revision v1.0, and the rest use chip revision v0.0. For more information about chip revisions, please refer to `ESP32-S2 Series SoC Errata`_. - - -Retail Orders -^^^^^^^^^^^^^ - -If you order a few samples, each ESP32-S2-DevKitC-1 comes in an individual package in either antistatic bag or any packaging depending on your retailer. - -For retail orders, please go to https://www.espressif.com/en/contact-us/get-samples. - - -Wholesale Orders -^^^^^^^^^^^^^^^^ - -If you order in bulk, the boards come in large cardboard boxes. - -For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions. - - -Hardware Reference -================== - -Block Diagram -------------- - -The block diagram below shows the components of ESP32-S2-DevKitC-1 and their interconnections. - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-block-diags.png - :align: center - :scale: 70% - :alt: ESP32-S2-DevKitC-1 (click to enlarge) - :figclass: align-center - - ESP32-S2-DevKitC-1 (click to enlarge) - - -Power Supply Options -^^^^^^^^^^^^^^^^^^^^ - -There are three mutually exclusive ways to provide power to the board: - -- USB-to-UART Port and ESP32-S2 USB Port (either one or both), default power supply (recommended) -- 5V and G (GND) pins -- 3V3 and G (GND) pins - - -.. _user-guide-s2-devkitc-1-v1-header-blocks: - -Header Block ------------- - -The two tables below provide the **Name** and **Function** of the pin headers on both sides of the board (J1 and J3). The pin header names are shown in :ref:`user-guide-s2-devkitc-1-v1-board-front`. The numbering is the same as in the `ESP32-S2-DevKitC-1 Schematic`_ (PDF). - - -J1 -^^^ - -=== ========= ========== ========================================================================== -No. Name Type [#]_ Function -=== ========= ========== ========================================================================== -1 3V3 P 3.3 V power supply -2 3V3 P 3.3 V power supply -3 RST I CHIP_PU -4 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 -5 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 -6 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 -7 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 -8 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P -9 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N -10 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 -11 18 [#]_ I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED -12 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 -13 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 -14 46 I GPIO46 -15 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD -16 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 -17 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 -18 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 -19 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 -20 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS -21 5V P 5 V power supply -22 G G Ground -=== ========= ========== ========================================================================== - - -J3 -^^^ - -=== ==== ===== ============================================================ -No. Name Type Function -=== ==== ===== ============================================================ -1 G G Ground -2 TX I/O/T U0TXD, GPIO43, CLK_OUT1 -3 RX I/O/T U0RXD, GPIO44, CLK_OUT2 -4 1 I/O/T RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0 -5 2 I/O/T RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1 -6 42 I/O/T MTMS, GPIO42 -7 41 I/O/T MTDI, GPIO41, CLK_OUT1 -8 40 I/O/T MTDO, GPIO40, CLK_OUT2 -9 39 I/O/T MTCK, GPIO39, CLK_OUT3 -10 38 I/O/T GPIO38, FSPIWP -11 37 I/O/T SPIDQS, GPIO37, FSPIQ -12 36 I/O/T SPIIO7, GPIO36, FSPICLK -13 35 I/O/T SPIIO6, GPIO35, FSPID -14 0 I/O/T RTC_GPIO0, GPIO0 -15 45 I/O/T GPIO45 -16 34 I/O/T SPIIO5, GPIO34, FSPICS0 -17 33 I/O/T SPIIO4, GPIO33, FSPIHD -18 21 I/O/T RTC_GPIO21, GPIO21 -19 20 I/O/T RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+ -20 19 I/O/T RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D- -21 G G Ground -22 G G Ground -=== ==== ===== ============================================================ - -.. [#] P: Power supply; I: Input; O: Output; T: High impedance. -.. [#] GPIO18 is not pulled up on boards with an ESP32-S2-SOLO-2 or ESP32-S2-SOLO-2U module. - - -Pin Layout -^^^^^^^^^^ - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-pinout.png - :align: center - :scale: 45% - :alt: ESP32-S2-DevKitC-1 (click to enlarge) - :figclass: align-center - - ESP32-S2-DevKitC-1 Pin Layout (click to enlarge) - - -Hardware Revision Details -========================= - -This is the first revision of this board released. - - -Related Documents -================= - -* `ESP32-S2 Series Chip Revision v1.0 Datasheet`_ (PDF) -* `ESP32-S2 Series Chip Revision v0.0 Datasheet `_ (PDF) -* `ESP32-S2 Series SoC Errata`_ (PDF) -* `ESP32-S2-SOLO-2 & ESP32-S2-SOLO-2U Module Datasheet `_ (PDF) -* `ESP32-S2-SOLO & ESP32-S2-SOLO-U Module Datasheet `_ (PDF) -* `ESP32-S2-DevKitC-1 Schematic`_ (PDF) -* `ESP32-S2-DevKitC-1 PCB Layout `_ (PDF) -* `ESP32-S2-DevKitC-1 Dimensions `_ (PDF) -* `ESP32-S2-DevKitC-1 Dimensions source file `_ (DXF) - You can view it with `Autodesk Viewer `_ online - -For further design documentation for the board, please contact us at `sales@espressif.com `_. - -.. _NRND: https://www.espressif.com/en/products/longevity-commitment?id=nrnd -.. _ESP32-S2 Series Chip Revision v1.0 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_en.pdf -.. _ESP32-S2 Series SoC Errata: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_en.pdf -.. _ESP32-S2-DevKitC-1 Schematic: https://dl.espressif.com/dl/schematics/esp-idf/SCH_ESP32-S2-DEVKITC-1_V1_20220817.pdf diff --git a/docs/en/security/index.rst b/docs/en/security/index.rst index 8e15f6a8ce0d..7f5c1c9dcc9b 100644 --- a/docs/en/security/index.rst +++ b/docs/en/security/index.rst @@ -26,3 +26,9 @@ Workflows host-based-security-workflows +Vulnerabilities +--------------- +.. toctree:: + :maxdepth: 1 + + vulnerabilities diff --git a/docs/en/security/secure-boot-v2.rst b/docs/en/security/secure-boot-v2.rst index cec77d9253ef..4b84a2780faa 100644 --- a/docs/en/security/secure-boot-v2.rst +++ b/docs/en/security/secure-boot-v2.rst @@ -13,11 +13,11 @@ Secure Boot v2 {IDF_TARGET_ECO_VERSION:default="", esp32="(v3.0 onwards)", esp32c3="(v3.0 onwards)"} -{IDF_TARGET_RSA_TIME:default="", esp32c6="about 2.7 ms", esp32h2="about 4.5 ms"} +{IDF_TARGET_RSA_TIME:default="", esp32c6="about 2.7 ms", esp32h2="about 4.5 ms", esp32p4="about 2.4 ms"} -{IDF_TARGET_ECDSA_TIME:default="", esp32c6="about 21.5 ms", esp32h2="about 36 ms"} +{IDF_TARGET_ECDSA_TIME:default="", esp32c6="about 21.5 ms", esp32h2="about 36 ms", esp32p4="about 10.3 ms"} -{IDF_TARGET_CPU_FREQ:default="", esp32c6="160 MHz", esp32h2="96 MHz"} +{IDF_TARGET_CPU_FREQ:default="", esp32c6="160 MHz", esp32h2="96 MHz", esp32p4="360 MHz"} {IDF_TARGET_SBV2_DEFAULT_SCHEME:default="RSA", esp32c2="ECDSA (v2)"} diff --git a/docs/en/security/vulnerabilities.rst b/docs/en/security/vulnerabilities.rst new file mode 100644 index 000000000000..32a188891c24 --- /dev/null +++ b/docs/en/security/vulnerabilities.rst @@ -0,0 +1,164 @@ +Vulnerabilities +=============== + +This page briefly lists all of the vulnerabilities that are discovered and fixed in each release. Please note that for the on-going issues or the issues under embargo period, the information on this page may reflect once the desired resolution has been achieved. + + +.. note:: + Please refer to ``latest`` version of this documentation guide for up-to-date information. + +CVE-2024 +-------- + +CVE-2024-28183 +~~~~~~~~~~~~~~ + +Bootloader TOCTOU Vulnerability in Anti-rollback Scheme + +* Espressif Advisory: NA (Published on GitHub) +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details +* Advisory pointer: `GHSA-22x6-3756-pfp8`_ + + +CVE-2023 +-------- + +CVE-2023-35818 +~~~~~~~~~~~~~~ + +Security Advisory Concerning Bypassing Secure Boot and Flash Encryption Using EMFI + +* Espressif Advisory: `AR2023-005`_ +* Impact: Applicable for ESP32 Chip Revision v3.0/v3.1 +* Resolution: Please see advisory for details + + +CVE-2023-24023 +~~~~~~~~~~~~~~ + +Security Advisory Concerning the Bluetooth BLUFFS Vulnerability + +* Espressif Advisory: `AR2023-010`_ +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details + +CVE-2022 +-------- + +CVE-2022-24893 +~~~~~~~~~~~~~~ + +Espressif Bluetooth Mesh Stack Vulnerability + +* Espressif Advisory: NA (Published on GitHub) +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details +* Advisory pointer: `GHSA-7f7f-jj2q-28wm`_ + + +CVE-2021 +-------- + +CVE-2021-32020 +~~~~~~~~~~~~~~ + +Insufficient bounds checking during management of heap memory in FreeRTOS + +* Impact: ESP-IDF uses its own heap allocator and hence not applicable +* Resolution: NA + +CVE-2021-43997 +~~~~~~~~~~~~~~ + +Privilege escalation issue in FreeRTOS ARMv7-M and ARMv8-M MPU ports + +* Impact: Not applicable for Espressif chips +* Resolution: NA + +CVE-2021-3420 +~~~~~~~~~~~~~ + +Security Advisory on "BadAlloc" Vulnerabilities + +* Espressif Advisory: `AR2021-005`_ +* Impact: Not applicable for ESP-IDF +* Resolution: NA + +CVE-2021-31571 +~~~~~~~~~~~~~~ + +Security Advisory on "BadAlloc" Vulnerabilities + +* Espressif Advisory: `AR2021-005`_ +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details + +CVE-2021-31572 +~~~~~~~~~~~~~~ + +Security Advisory on "BadAlloc" Vulnerabilities + +* Espressif Advisory: `AR2021-005`_ +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details + +CVE-2021-28139 +~~~~~~~~~~~~~~ + +Security Advisory for Bluetooth Vulnerability + +* Covers additional CVEs: CVE-2020-10135, CVE-2020-13595, CVE-2020-26555, CVE-2020-26556, CVE-2020-26557, CVE-2020-26558, CVE-2020-26559, CVE-2020-26560, CVE-2021-28135, CVE-2021-28136 +* Espressif Advisory: `AR2021-004`_ +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details + + +CVE-2020 +-------- + +CVE-2020-22283 +~~~~~~~~~~~~~~ + +Buffer overflow vulnerability in lwIP stack + +* Espressif Advisory: NA +* Impact: Applicable for ESP-IDF +* Resolution: Fix cherry-picked and available in ESP-IDF >= v4.4.1 + +CVE-2020-22284 +~~~~~~~~~~~~~~ + +Buffer overflow vulnerability in lwIP stack + +* Espressif Advisory: NA +* Impact: Applicable for ESP-IDF +* Resolution: Fix cherry-picked and available in ESP-IDF >= v4.4.1 + +CVE-2020-26142 +~~~~~~~~~~~~~~ + +Security Advisory for WLAN FragAttacks + +* Espressif Advisory: `AR2023-008`_ +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details + +CVE-2020-12638 +~~~~~~~~~~~~~~ + +Security Advisory Concerning Wi-Fi Authentication Bypass + +* Espressif Advisory: `AR2020-002`_ +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details + + +.. _`AR2020-002`: https://www.espressif.com/sites/default/files/advisory_downloads/AR2020-002%20Security%20Advisory%20Concerning%20Wi-Fi%20Authentication%20Bypass%20V1.1%20EN.pdf +.. _`AR2021-004`: https://www.espressif.com/sites/default/files/advisory_downloads/AR2021-004%20Bluetooth%20Security%20Advisory.pdf +.. _`AR2021-005`: https://www.espressif.com/sites/default/files/advisory_downloads/AR2021-005%20Security%20Advisory%20on%20BadAlloc%20Vulnerabilities.pdf +.. _`AR2023-005`: https://www.espressif.com/sites/default/files/advisory_downloads/AR2023-005%20Security%20Advisory%20Concerning%20Bypassing%20Secure%20Boot%20and%20Flash%20Encryption%20Using%20EMFI%20EN.pdf +.. _`AR2023-008`: https://www.espressif.com/sites/default/files/advisory_downloads/AR2023-008%20Security%20Advisory%20for%20WLAN%20FragAttacks%20v1.1%20EN_0.pdf +.. _`AR2023-010`: https://www.espressif.com/sites/default/files/advisory_downloads/AR2023-010%20Security%20Advisory%20Concerning%20the%20Bluetooth%20BLUFFS%20Vulnerability%20EN.pdf +.. _`GHSA-22x6-3756-pfp8` : https://github.com/espressif/esp-idf/security/advisories/GHSA-22x6-3756-pfp8 +.. _`GHSA-7f7f-jj2q-28wm` : https://github.com/espressif/esp-idf/security/advisories/GHSA-7f7f-jj2q-28wm diff --git a/docs/zh_CN/_templates/layout.html b/docs/zh_CN/_templates/layout.html index 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+ {% endblock %} diff --git a/docs/zh_CN/api-guides/code-quality/index.rst b/docs/zh_CN/api-guides/code-quality/index.rst new file mode 100644 index 000000000000..ca7ea3741c31 --- /dev/null +++ b/docs/zh_CN/api-guides/code-quality/index.rst @@ -0,0 +1 @@ +.. include:: ../../../en/api-guides/code-quality/index.rst diff --git a/docs/zh_CN/api-guides/code-quality/static-analyzer.rst b/docs/zh_CN/api-guides/code-quality/static-analyzer.rst new file mode 100644 index 000000000000..74131eedf611 --- /dev/null +++ b/docs/zh_CN/api-guides/code-quality/static-analyzer.rst @@ -0,0 +1 @@ +.. include:: ../../../en/api-guides/code-quality/static-analyzer.rst diff --git a/docs/zh_CN/api-guides/error-handling.rst b/docs/zh_CN/api-guides/error-handling.rst index 859de9a26d20..f6bf76f9fd5a 100644 --- a/docs/zh_CN/api-guides/error-handling.rst +++ b/docs/zh_CN/api-guides/error-handling.rst @@ -12,34 +12,34 @@ - 可恢复的错误： - - 通过函数的返回值（错误码）表示的错误 - - 使用 ``throw`` 关键字抛出的 C++ 异常 + - 通过函数的返回值（错误码）表示的错误 + - 使用 ``throw`` 关键字抛出的 C++ 异常 - 不可恢复（严重）的错误： - - 断言失败（使用 ``assert`` 宏或者其它类似方法，可参考 :ref:`assertions`）或者直接调用 ``abort()`` 函数造成的错误 - - CPU 异常：访问受保护的内存区域、非法指令等 - - 系统级检查：看门狗超时、缓存访问错误、堆栈溢出、堆栈粉碎、堆栈损坏等 + - 断言失败（使用 ``assert`` 宏或者其它类似方法，可参考 :ref:`assertions`）或者直接调用 ``abort()`` 函数造成的错误 + - CPU 异常：访问受保护的内存区域、非法指令等 + - 系统级检查：看门狗超时、缓存访问错误、堆栈溢出、堆栈粉碎、堆栈损坏等 本文将介绍 ESP-IDF 中针对可恢复错误的错误处理机制，并提供一些常见错误的处理模式。 -关于如何处理不可恢复的错误，请查阅 :doc:`不可恢复错误 `。 +关于如何处理不可恢复的错误，请参阅 :doc:`/api-guides/fatal-errors`。 错误码 ------ -ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， :cpp:type:`esp_err_t` 实质上是带符号的整型，``ESP_OK`` 代表成功（没有错误），具体值定义为 0。 +ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码，:cpp:type:`esp_err_t` 实质上是带符号的整型，``ESP_OK`` 代表成功（没有错误），具体值定义为 0。 在 ESP-IDF 中，许多头文件都会使用预处理器，定义可能出现的错误代码。这些错误代码通常均以 ``ESP_ERR_`` 前缀开头，一些常见错误（比如内存不足、超时、无效参数等）的错误代码则已经在 ``esp_err.h`` 文件中定义好了。此外，ESP-IDF 中的各种组件 (component) 也都可以针对具体情况，自行定义更多错误代码。 -完整错误代码列表，请见 :doc:`错误代码参考 <../api-reference/error-codes>` 中查看完整的错误列表。 +请参考 :doc:`错误代码参考 <../api-reference/error-codes>` 查看完整的错误列表。 -错误码到错误消息 ----------------- +错误码转换为错误消息 +------------------------------ -错误代码并不直观，因此 ESP-IDF 还可以使用 :cpp:func:`esp_err_to_name` 或者 :cpp:func:`esp_err_to_name_r` 函数，将错误代码转换为具体的错误消息。例如，我们可以向 :cpp:func:`esp_err_to_name` 函数传递错误代码 ``0x101``，可以得到返回字符串 “ESP_ERR_NO_MEM”。这样一来，我们可以在日志中输出更加直观的错误消息，而不是简单的错误码，从而帮助研发人员更快理解发生了何种错误。 +错误代码并不直观，因此 ESP-IDF 还可以使用 :cpp:func:`esp_err_to_name` 或者 :cpp:func:`esp_err_to_name_r` 函数，将错误代码转换为具体的错误消息。例如，我们可以向 :cpp:func:`esp_err_to_name` 函数传递错误代码 ``0x101``，可以得到返回字符串 ``ESP_ERR_NO_MEM``。这样一来，我们可以在日志中输出更加直观的错误消息，而不是简单的错误码，从而帮助研发人员更快理解发生了何种错误。 此外，如果出现找不到匹配的 ``ESP_ERR_`` 值的情况，函数 :cpp:func:`esp_err_to_name_r` 则会尝试将错误码作为一种 `标准 POSIX 错误代码 `_ 进行解释。具体过程为：POSIX 错误代码（例如 ``ENOENT``， ``ENOMEM``）定义在 ``errno.h`` 文件中，可以通过 ``errno`` 变量获得，进而调用 ``strerror_r`` 函数实现。在 ESP-IDF 中，``errno`` 是一个基于线程的局部变量，即每个 FreeRTOS 任务都有自己的 ``errno`` 副本，通过函数修改 ``errno`` 也只会作用于当前任务中的 ``errno`` 变量值。 @@ -53,23 +53,27 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， 宏 :c:macro:`ESP_ERROR_CHECK` 的功能和 ``assert`` 类似，不同之处在于：这个宏会检查 :cpp:type:`esp_err_t` 的值，而非判断 ``bool`` 条件。如果传给 :c:macro:`ESP_ERROR_CHECK` 的参数不等于 :c:macro:`ESP_OK` ，则会在控制台上打印错误消息，然后调用 ``abort()`` 函数。 -错误消息通常如下所示:: +错误消息通常如下所示： - ESP_ERROR_CHECK failed: esp_err_t 0x107 (ESP_ERR_TIMEOUT) at 0x400d1fdf +.. code-block:: none - file: "/Users/user/esp/example/main/main.c" line 20 - func: app_main - expression: sdmmc_card_init(host, &card) + ESP_ERROR_CHECK failed: esp_err_t 0x107 (ESP_ERR_TIMEOUT) at 0x400d1fdf - Backtrace: 0x40086e7c:0x3ffb4ff0 0x40087328:0x3ffb5010 0x400d1fdf:0x3ffb5030 0x400d0816:0x3ffb5050 + file: "/Users/user/esp/example/main/main.c" line 20 + func: app_main + expression: sdmmc_card_init(host, &card) -.. note:: 如果使用 :doc:`IDF 监视器 `，则最后一行回溯结果中的地址将会被自动解析为相应的文件名和行号。 + Backtrace: 0x40086e7c:0x3ffb4ff0 0x40087328:0x3ffb5010 0x400d1fdf:0x3ffb5030 0x400d0816:0x3ffb5050 -- 第一行打印错误代码的十六进制表示，及该错误在源代码中的标识符。这个标识符取决于 :ref:`CONFIG_ESP_ERR_TO_NAME_LOOKUP` 选项的设定。最后，第一行还会打印程序中该错误发生的具体位置。 +.. note:: + + 如果使用 :doc:`tools/idf-monitor`，则最后一行回溯结果中的地址将会被自动解析为相应的文件名和行号。 -- 下面几行显示了程序中调用 :c:macro:`ESP_ERROR_CHECK` 宏的具体位置，以及传递给该宏的参数。 +- 第一行打印错误代码的十六进制表示，及该错误在源代码中的标识符。这个标识符取决于 :ref:`CONFIG_ESP_ERR_TO_NAME_LOOKUP` 选项的设定。最后，第一行还会打印程序中该错误发生的具体位置。 -- 最后一行打印回溯结果。对于所有不可恢复错误，这里在应急处理程序中打印的内容都是一样的。更多有关回溯结果的详细信息，请参阅 :doc:`不可恢复错误 ` 。 +- 下面几行显示了程序中调用 :c:macro:`ESP_ERROR_CHECK` 宏的具体位置，以及传递给该宏的参数。 + +- 最后一行打印回溯结果。对于所有不可恢复错误，这里在应急处理程序中打印的内容都是一样的。更多有关回溯结果的详细信息，请参阅 :doc:`/api-guides/fatal-errors`。 .. _esp-error-check-without-abort-macro: @@ -77,7 +81,7 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， ``ESP_ERROR_CHECK_WITHOUT_ABORT`` 宏 ------------------------------------ -宏 :c:macro:`ESP_ERROR_CHECK_WITHOUT_ABORT` 的功能和 ``ESP_ERROR_CHECK`` 类似, 不同之处在于它不会调用 ``abort()``. +宏 :c:macro:`ESP_ERROR_CHECK_WITHOUT_ABORT` 的功能和 ``ESP_ERROR_CHECK`` 类似，不同之处在于它不会调用 ``abort()``。 .. _esp-return-on-error-macro: @@ -85,7 +89,7 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， ``ESP_RETURN_ON_ERROR`` 宏 -------------------------- -宏 :c:macro:`ESP_RETURN_ON_ERROR` 用于错误码检查, 如果错误码不等于 :c:macro:`ESP_OK`, 该宏会打印错误信息，并使原函数立刻返回。 +宏 :c:macro:`ESP_RETURN_ON_ERROR` 用于错误码检查，如果错误码不等于 :c:macro:`ESP_OK`， 该宏会打印错误信息，并使原函数立刻返回。 .. _esp-goto-on-error-macro: @@ -93,7 +97,7 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， ``ESP_GOTO_ON_ERROR`` 宏 ------------------------ -宏 :c:macro:`ESP_GOTO_ON_ERROR` 用于错误码检查, 如果错误码不等于 :c:macro:`ESP_OK`, 该宏会打印错误信息，将局部变量 `ret` 赋值为该错误码, 并使原函数跳转至给定的 `goto_tag`. +宏 :c:macro:`ESP_GOTO_ON_ERROR` 用于错误码检查，如果错误码不等于 :c:macro:`ESP_OK`，该宏会打印错误信息，将局部变量 ``ret`` 赋值为该错误码，并使原函数跳转至给定的 ``goto_tag``。 .. _esp-return-on-false-macro: @@ -101,7 +105,7 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， ``ESP_RETURN_ON_FALSE`` 宏 -------------------------- -宏 :c:macro:`ESP_RETURN_ON_FALSE` 用于条件检查, 如果给定条件不等于 `true`, 该宏会打印错误信息，并使原函数立刻返回，返回值为给定的 `err_code`. +宏 :c:macro:`ESP_RETURN_ON_FALSE` 用于条件检查，如果给定条件不等于 ``true``，该宏会打印错误信息，并使原函数立刻返回，返回值为给定的 ``err_code``。 .. _esp-goto-on-false-macro: @@ -109,7 +113,7 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， ``ESP_GOTO_ON_FALSE`` 宏 ------------------------ -宏 :c:macro:`ESP_GOTO_ON_FALSE` 用于条件检查, 如果给定条件不等于 `true`, 该宏会打印错误信息，将局部变量 `ret` 赋值为给定的 `err_code`, 并使原函数跳转至给定的 `goto_tag`. +宏 :c:macro:`ESP_GOTO_ON_FALSE` 用于条件检查，如果给定条件不等于 ``true``，该宏会打印错误信息，将局部变量 ``ret`` 赋值为给定的 ``err_code``，并使原函数跳转至给定的 ``goto_tag``。 .. _check_macros_examples: @@ -117,7 +121,9 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， ``CHECK 宏使用示例`` ------------------------- -示例:: +示例： + +.. code-block:: c static const char* TAG = "Test"; @@ -125,12 +131,12 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， { esp_err_t ret = ESP_OK; - ESP_ERROR_CHECK(x); // err message printed if `x` is not `ESP_OK`, and then `abort()`. - ESP_ERROR_CHECK_WITHOUT_ABORT(x); // err message printed if `x` is not `ESP_OK`, without `abort()`. - ESP_RETURN_ON_ERROR(x, TAG, "fail reason 1"); // err message printed if `x` is not `ESP_OK`, and then function returns with code `x`. - ESP_GOTO_ON_ERROR(x, err, TAG, "fail reason 2"); // err message printed if `x` is not `ESP_OK`, `ret` is set to `x`, and then jumps to `err`. - ESP_RETURN_ON_FALSE(a, err_code, TAG, "fail reason 3"); // err message printed if `a` is not `true`, and then function returns with code `err_code`. - ESP_GOTO_ON_FALSE(a, err_code, err, TAG, "fail reason 4"); // err message printed if `a` is not `true`, `ret` is set to `err_code`, and then jumps to `err`. + ESP_ERROR_CHECK(x); // 如果错误码不等于 `ESP_OK`，则打印错误信息，然后调用 `abort()`。 + ESP_ERROR_CHECK_WITHOUT_ABORT(x); // 如果错误码不等于 `ESP_OK`，则打印错误信息，不调用 `abort()`。 + ESP_RETURN_ON_ERROR(x, TAG, "fail reason 1"); // 如果错误码不等于 `ESP_OK`，则打印错误信息，并使原函数立刻返回，返回值为给定的错误码. + ESP_GOTO_ON_ERROR(x, err, TAG, "fail reason 2"); // 如果错误码不等于 `ESP_OK`，则打印错误信息，将局部变量 `ret` 赋值为该错误码，并使原函数跳转至 `err`。 + ESP_RETURN_ON_FALSE(a, err_code, TAG, "fail reason 3"); // 如果给定条件不等于 `true`，则打印错误信息，并使原函数立刻返回，返回值为给定的错误码。 + ESP_GOTO_ON_FALSE(a, err_code, err, TAG, "fail reason 4"); // 如果给定条件不等于 `true`，该宏会打印错误信息，将局部变量 `ret` 赋值为给定的 `err_code`，并使原函数跳转至 `err`。 err: // clean up @@ -139,7 +145,7 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， .. note:: - 如果 Kconfig 中的 :ref:`CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT` 选项被打开, CHECK 宏将不会打印错误信息，其他功能不变。 + 如果 Kconfig 中的 :ref:`CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT` 选项被打开，CHECK 宏将不会打印错误信息，其他功能不变。 ``ESP_RETURN_xx`` 和 ``ESP_GOTO_xx`` 宏不可以在中断服务程序里被调用。如需要在中断中使用类似功能，请使用 ``xx_ISR`` 宏，如 ``ESP_RETURN_ON_ERROR_ISR`` 等。 @@ -153,43 +159,49 @@ ESP-IDF 中大多数函数会返回 :cpp:type:`esp_err_t` 类型的错误码， - 尝试删除该驱动，然后重新进行“初始化”； - 采用其他带外机制，修改导致错误发生的条件（例如，对一直没有响应的外设进行复位等）。 - 示例:: + 示例： - esp_err_t err; - do { - err = sdio_slave_send_queue(addr, len, arg, timeout); - // 如果发送队列已满就不断重试 - } while (err == ESP_ERR_TIMEOUT); - if (err != ESP_OK) { - // 处理其他错误 - } + .. code-block:: c + + esp_err_t err; + do { + err = sdio_slave_send_queue(addr, len, arg, timeout); + // 如果发送队列已满就不断重试 + } while (err == ESP_ERR_TIMEOUT); + if (err != ESP_OK) { + // 处理其他错误 + } 2. 将错误传递回调用程序。在某些中间件组件中，采用此类处理模式代表函数必须以相同的错误码退出，这样才能确保所有分配的资源都能得到释放。 - 示例:: - - sdmmc_card_t* card = calloc(1, sizeof(sdmmc_card_t)); - if (card == NULL) { - return ESP_ERR_NO_MEM; - } - esp_err_t err = sdmmc_card_init(host, &card); - if (err != ESP_OK) { - // 释放内存 - free(card); - // 将错误码传递给上层（例如通知用户） - // 或者，应用程序可以自定义错误代码并返回 - return err; - } + 示例： + + .. code-block:: c + + sdmmc_card_t* card = calloc(1, sizeof(sdmmc_card_t)); + if (card == NULL) { + return ESP_ERR_NO_MEM; + } + esp_err_t err = sdmmc_card_init(host, &card); + if (err != ESP_OK) { + // 释放内存 + free(card); + // 将错误码传递给上层（例如通知用户） + // 或者，应用程序可以自定义错误代码并返回 + return err; + } 3. 转为不可恢复错误，比如使用 ``ESP_ERROR_CHECK``。详情请见 `ESP_ERROR_CHECK 宏 <#esp-error-check-macro>`_ 章节。 - 对于中间件组件而言，通常并不希望在发生错误时中止应用程序。不过，有时在应用程序级别，这种做法是可以接受的。 + 对于中间件组件而言，通常并不希望在发生错误时中止应用程序。不过，有时在应用程序级别，这种做法是可以接受的。 + + 在 ESP-IDF 的示例代码中，很多都会使用 ``ESP_ERROR_CHECK`` 来处理各种 API 引发的错误，虽然这不是应用程序的最佳做法，但可以让示例代码看起来更加简洁。 - 在 ESP-IDF 的示例代码中，很多都会使用 ``ESP_ERROR_CHECK`` 来处理各种 API 引发的错误，虽然这不是应用程序的最佳做法，但可以让示例代码看起来更加简洁。 + 示例： - 示例:: + .. code-block:: c - ESP_ERROR_CHECK(spi_bus_initialize(host, bus_config, dma_chan)); + ESP_ERROR_CHECK(spi_bus_initialize(host, bus_config, dma_chan)); C++ 异常 diff --git a/docs/zh_CN/api-guides/index.rst b/docs/zh_CN/api-guides/index.rst index 4286f988235b..74f41e5ae666 100644 --- a/docs/zh_CN/api-guides/index.rst +++ b/docs/zh_CN/api-guides/index.rst @@ -14,6 +14,7 @@ API 指南 :SOC_SUPPORT_COEXISTENCE: coexist c cplusplus + code-quality/index core_dump current-consumption-measurement-modules :SOC_RTC_MEM_SUPPORTED: deep-sleep-stub diff --git a/docs/zh_CN/api-guides/performance/size.rst b/docs/zh_CN/api-guides/performance/size.rst index c1832b41110b..a8731a84556b 100644 --- a/docs/zh_CN/api-guides/performance/size.rst +++ b/docs/zh_CN/api-guides/performance/size.rst @@ -382,6 +382,7 @@ ESP-IDF 构建系统会编译项目和 ESP-IDF 中所有源文件，但只有程 - 将 :ref:`CONFIG_COMPILER_OPTIMIZATION` 设置为 ``Optimize for size (-Os)``。在某些情况下，相较于默认设置， ``Optimize for size (-Os)`` 也可以减小二进制文件的大小。请注意，若代码包含 C 或 C++ 的未定义行为，提高编译器优化级别可能会暴露出原本不存在的错误。 - 通过降低应用程序的 :ref:`CONFIG_LOG_DEFAULT_LEVEL` ，可以减少编译时的日志输出。如果改变 :ref:`CONFIG_LOG_MAXIMUM_LEVEL` 的默认选项，则可以控制二进制文件的大小。减少编译时的日志输出可以减少二进制文件中的字符串数量，并减小调用日志函数的代码大小。 + - 如果应用程序不需要动态更改日志级别，并且不需要使用标签来控制每个模块的日志，建议禁用 :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` 并更改 :ref:`CONFIG_LOG_TAG_LEVEL_IMPL`。与默认选项相比，这可以节约大概 260 字节的 IRAM、264 字节的 DRAM、以及 1 KB 的 flash，同时还可以加快日志记录的速度。 - 将 :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL` 设置为 ``Silent``，可以避免为所有可能失败的断言编译专门的断言字符串和源文件名。尽管如此，仍可以通过查看断言失败时的内存地址以在代码中找到失败断言。 - 除 :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL` 外，还可以通过设置 :ref:`CONFIG_HAL_DEFAULT_ASSERTION_LEVEL` 单独禁用或静默 HAL 组件的断言。请注意，即使将 :ref:`CONFIG_HAL_DEFAULT_ASSERTION_LEVEL` 设置为 full-assertion 级别，ESP-IDF 在引导加载程序中也会把 HAL 断言级别降为 silent，以减小引导加载程序的大小。 - 设置 :ref:`CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT` 会移除针对 ESP-IDF 内部错误检查宏的特定错误消息。错误消息移除后，通过阅读日志输出来调试某些错误条件可能变得更加困难。 diff --git a/docs/zh_CN/api-guides/performance/speed.rst b/docs/zh_CN/api-guides/performance/speed.rst index 81c53f0ff56c..71ad09557560 100644 --- a/docs/zh_CN/api-guides/performance/speed.rst +++ b/docs/zh_CN/api-guides/performance/speed.rst @@ -128,6 +128,7 @@ - 通过调低应用日志默认等级 :ref:`CONFIG_LOG_DEFAULT_LEVEL` （引导加载程序日志等级的相应配置为 :ref:`CONFIG_BOOTLOADER_LOG_LEVEL`）来减少日志输出量。这样做不仅可以减小二进制文件大小，还可以节省一些 CPU 用于格式化字符串的时间。 :not SOC_USB_OTG_SUPPORTED: - 增加 :ref:`CONFIG_ESP_CONSOLE_UART_BAUDRATE` ，可以提高日志输出速度。 :SOC_USB_OTG_SUPPORTED: - 增加 :ref:`CONFIG_ESP_CONSOLE_UART_BAUDRATE` ，可以提高日志输出速度。如果使用内置 USB-CDC 作为串口控制台，那么串口传输速率不会受配置的波特率影响。 + - 如果应用程序不需要动态更改日志级别，并且不需要使用标签来控制每个模块的日志，建议禁用 :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` 并更改 :ref:`CONFIG_LOG_TAG_LEVEL_IMPL`。与默认选项相比，这可以减少内存使用，并且将应用程序中的日志操作速度提高约 10 倍。 不建议的选项 ^^^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-reference/peripherals/gptimer.rst b/docs/zh_CN/api-reference/peripherals/gptimer.rst index ecf9cf4cb49f..6e23d755dd42 100644 --- a/docs/zh_CN/api-reference/peripherals/gptimer.rst +++ b/docs/zh_CN/api-reference/peripherals/gptimer.rst @@ -42,15 +42,12 @@ 要安装一个定时器实例，需要提前提供配置结构体 :cpp:type:`gptimer_config_t`： -- :cpp:member:`gptimer_config_t::clk_src` 选择定时器的时钟源。:cpp:type:`gptimer_clock_source_t` 中列出多个可用时钟，仅可选择其中一个时钟。了解不同时钟源对功耗的影响，请查看章节 :ref:`gptimer-power-management`。 - -- :cpp:member:`gptimer_config_t::direction` 设置定时器的计数方向，:cpp:type:`gptimer_count_direction_t` 中列出多个支持的方向，仅可选择其中一个方向。 - -- :cpp:member:`gptimer_config_t::resolution_hz` 设置内部计数器的分辨率。计数器每滴答一次相当于 **1 / resolution_hz** 秒。 - -- :cpp:member:`gptimer_config::intr_priority` 设置中断的优先级。如果设置为 ``0``，则会分配一个默认优先级的中断，否则会使用指定的优先级。 - -- 选用 :cpp:member:`gptimer_config_t::intr_shared` 设置是否将定时器中断源标记为共享源。了解共享中断的优缺点，请参考 :doc:`Interrupt Handling <../../api-reference/system/intr_alloc>`。 +- :cpp:member:`gptimer_config_t::clk_src` 选择定时器的时钟源。:cpp:type:`gptimer_clock_source_t` 中列出多个可用时钟，仅可选择其中一个时钟。了解不同时钟源对功耗的影响，请查看章节 :ref:`gptimer-power-management`。 +- :cpp:member:`gptimer_config_t::direction` 设置定时器的计数方向，:cpp:type:`gptimer_count_direction_t` 中列出多个支持的方向，仅可选择其中一个方向。 +- :cpp:member:`gptimer_config_t::resolution_hz` 设置内部计数器的分辨率。计数器每滴答一次相当于 **1 / resolution_hz** 秒。 +- :cpp:member:`gptimer_config::intr_priority` 设置中断的优先级。如果设置为 ``0``，则会分配一个默认优先级的中断，否则会使用指定的优先级。 +- :cpp:member:`gptimer_config::backup_before_sleep` 用于使能在进入睡眠模式前备份 GPTimer 寄存器。这个选项需要用户在功耗和内存使用之间取得平衡。如果功耗不是一个问题，可以禁用这个选项来节省内存。但如果想要节省功耗，应该使能这个选项，在进入睡眠模式前备份 GPTimer 寄存器，并在唤醒后恢复它们。这个功能依赖于特定的硬件模块，如果你在不支持的芯片上启用它，你会得到一个错误信息，如 ``register back up is not supported``。 +- 可选地， :cpp:member:`gptimer_config_t::intr_shared` 设置是否将定时器中断源标记为共享源。了解共享中断的优缺点，请参考 :doc:`Interrupt Handling <../../api-reference/system/intr_alloc>`。 完成上述结构配置之后，可以将结构传递给 :cpp:func:`gptimer_new_timer`，用以实例化定时器实例并返回定时器句柄。 @@ -284,9 +281,13 @@ 电源管理 ^^^^^^^^ -有些电源管理的策略会在某些时刻关闭时钟源，或者改变时钟源的频率，以求降低功耗。比如在启用 DFS 后，APB 时钟源会降低频率。如果浅睡眠 (Light-sleep) 模式也被开启，PLL 和 XTAL 时钟都会被默认关闭，从而导致 GPTimer 的计时不准确。 +当电源管理 :ref:`CONFIG_PM_ENABLE` 被启用的时候，系统在进入睡眠前可能会调整或禁用时钟源。结果导致 GPTimer 的计时不准确。 + +驱动程序可以通过创建一个电源管理锁来防止上述问题。锁的类型会根据不同的时钟源来设置。驱动程序将在 :cpp:func:`gptimer_enable` 中拿锁，并在 :cpp:func:`gptimer_disable` 中释放锁。这意味着，在这两个函数之间，定时器可以正确工作，因为此时时钟源不会被禁用或改变频率。 + +.. only:: SOC_TIMER_SUPPORT_SLEEP_RETENTION -驱动程序会根据具体的时钟源选择，通过创建不同的电源锁来避免上述情况的发生。驱动会在 :cpp:func:`gptimer_enable` 函数中增加电源锁的引用计数，并在 :cpp:func:`gptimer_disable` 函数中减少电源锁的引用计数，从而保证了在 :cpp:func:`gptimer_enable` 和 :cpp:func:`gptimer_disable` 之间，GPTimer 的时钟源始处于稳定工作的状态。 + 除了时钟源的潜在变化外，当启用电源管理时，系统还可以关闭 GPTimer 寄存器所在的电源域。为确保 GPTimer 驱动程序在睡眠后继续工作，用户要么选择将 GPTimer 相关的寄存器备份到 RAM 中，要么拒绝关闭电源域。你可以根据应用需求在 :cpp:member:`gptimer_config_t::backup_before_sleep` 中设置是否需要启用寄存器备份，在功耗和内存使用之间做权衡。 .. _gptimer-iram-safe: diff --git a/docs/zh_CN/api-reference/peripherals/i2c.rst b/docs/zh_CN/api-reference/peripherals/i2c.rst index e06e1c8f439b..363bbca349e4 100644 --- a/docs/zh_CN/api-reference/peripherals/i2c.rst +++ b/docs/zh_CN/api-reference/peripherals/i2c.rst @@ -351,7 +351,7 @@ I2C 主机读取 i2c_master_receive(dev_handle, data_rd, DATA_LENGTH, -1); -I2C 主机写入和读取 +I2C 主机写入后读取 ~~~~~~~~~~~~~~~~~~~ 从一些 I2C 设备中读取数据之前需要进行写入配置，可通过 :cpp:func:`i2c_master_transmit_receive` 接口进行配置。下图解释了该函数的原理。 @@ -362,7 +362,7 @@ I2C 主机写入和读取 I2C 主机向从机设备写入并从从机设备读取数据 -向从机设备写入并从从机设备读取数据的简单示例： +请注意，在写入操作和读取操作之间没有插入 STOP 条件位，因此该功能适用于从 I2C 设备读取寄存器。以下是向从机设备写入数据并从从机设备读取数据的简单示例： .. code:: c @@ -625,6 +625,14 @@ Kconfig 选项 - :ref:`CONFIG_I2C_ISR_IRAM_SAFE` 将在 cache 被禁用时控制默认的 ISR 处理程序正常工作，详情请参阅 `IRAM 安全 <#iram-safe>`__。 - :ref:`CONFIG_I2C_ENABLE_DEBUG_LOG` 可启用调试日志，但会增加固件二进制文件大小。 +应用示例 +-------- + +.. list:: + + - :example:`peripherals/i2c/i2c_eeprom` 通过读取和写入 I2C 连接的 EEPROM 展示了 I2C 驱动程序的使用方法。 + - :example:`peripherals/i2c/i2c_tools` 基于 ESP32 控制台组件实现了一些 I2C 工具的基本功能。 + API 参考 -------- diff --git a/docs/zh_CN/api-reference/system/efuse.rst b/docs/zh_CN/api-reference/system/efuse.rst index eacf03699527..7beb1e600f8e 100644 --- a/docs/zh_CN/api-reference/system/efuse.rst +++ b/docs/zh_CN/api-reference/system/efuse.rst @@ -1 +1,570 @@ -.. include:: ../../../en/api-reference/system/efuse.rst +eFuse 管理器 +============= + +:link_to_translation:`en:[English]` + +{IDF_TARGET_CODING_SCHEMES:default="Reed-Solomon", esp32="3/4 或 Repeat"} + + +简介 +------------ + +eFuse 是一种微型的一次性可编程保险丝，可以通过“烧录”（即编程）将数据存储到 {IDF_TARGET_NAME} 中。eFuse 位组成不同的数据字段，用于系统参数（即 {IDF_TARGET_NAME} 的 ESP-IDF 使用的数据参数）或用户自定义参数。 + +eFuse 管理器组件中集合了多种工具和 API，可帮助定义、烧录和访问 eFuse 参数。常用的工具和 API 包括： + +* 表格格式，用于在 CSV 文件中定义 eFuse 数据字段 +* ``efuse_table_gen.py`` 工具，用于生成 CSV 文件指定的 eFuse 数据字段对应的 C 结构体 +* 用于读/写 eFuse 数据字段的 C API 集合 + +eFuse Manager 与 ``idf.py`` +--------------------------- + +``idf.py`` 通过 ``idf.py efuse-`` 命令为 eFuse 管理器提供了部分功能。本文档主要使用基于 ``idf.py`` 的命令，只有在涉及高级功能或罕见情况时，会使用基于 ``espefuse.py`` 的命令。要查看所有可用的命令，请运行 ``idf.py --help`` 并搜索以 ``efuse-`` 为前缀的命令。 + +硬件描述 +-------------------- + +{IDF_TARGET_NAME} 有多个 eFuse，可用于存储系统参数和用户参数。每个 eFuse 都是一个一位字段，可以烧写为 1，之后就不能再恢复为 0。eFuse 位被分成了多个 256 位的块，每个块又被分成 8 个 32 位寄存器。部分块保留用于系统参数，其它块可用于用户参数。 + +如需了解更多内容，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *eFuse 控制器 (eFuse)* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。 + +.. only:: esp32 + + {IDF_TARGET_NAME} 有 4 个 eFuse 块，每个块的大小为 256 位（并非所有位都可用于用户参数）： + + * EFUSE_BLK0 完全用于系统用途； + * EFUSE_BLK1 用于 flash 加密密钥。如果不使用 flash 加密功能，此块也可以用于用户参数； + * EFUSE_BLK2 用于安全启动密钥。如果不使用安全启动功能，此块也可以用于用户参数； + * EFUSE_BLK3 可以部分保留，以存储自定义 MAC 地址，或者完全用于用户参数。请注意，一些位已经用于 ESP-IDF。 + +.. only:: not esp32 and not esp32c2 + + {IDF_TARGET_NAME} 有 11 个 eFuse 块，每个块的大小为 256 位（并非所有位都可用于用户参数）： + + .. list:: + + * EFUSE_BLK0 完全用于系统参数； + * EFUSE_BLK1 完全用于系统参数； + * EFUSE_BLK2 完全用于系统参数； + * EFUSE_BLK3（也称为 EFUSE_BLK_USER_DATA）可用于用户参数； + * EFUSE_BLK4 至 EFUSE_BLK8（即 EFUSE_BLK_KEY0 至 EFUSE_BLK_KEY4）可以存储安全启动或 flash 加密的密钥。不使用这两个功能时，可以用于用户参数。 + :SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and SOC_ECDSA_SUPPORTED: * EFUSE_BLK9（即 EFUSE_BLK_KEY5）可用于任何用途，但由于硬件问题，不能用于 flash 加密或 ECDSA； + :SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and not SOC_ECDSA_SUPPORTED: * EFUSE_BLK9（即 EFUSE_BLK_KEY5）可用于任何用途，但由于硬件问题，不能用于 flash 加密； + :not SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK: * EFUSE_BLK9（即 EFUSE_BLK_KEY5）可用于存储安全启动或 flash 加密的密钥。不使用这两个功能时，可用于用户参数。 + * EFUSE_BLK10（即 EFUSE_BLK_SYS_DATA_PART2）保留用于系统参数。 + +.. only:: esp32c2 + + {IDF_TARGET_NAME} 有 4 个 eFuse 块，每个块的大小为 256 位（并非所有位都可用于用户参数）： + + * EFUSE_BLK0 完全用于系统参数 + * EFUSE_BLK1 完全用于系统参数 + * EFUSE_BLK2 完全用于系统参数 + * EFUSE_BLK3（即 EFUSE_BLK_KEY0）可用于存储安全启动或 flash 加密的密钥。不使用这两个功能时，可用于用户参数。 + +定义 eFuse 字段 +----------------------- + +eFuse 字段通过 CSV 文件中特定格式的表格进行定义。通过这种格式，可定义任意长度和任意位数的 eFuse 字段。 + +另外，通过这种格式，可以结构化地定义由子字段组成的 eFuse 字段，这意味着一个父 eFuse 字段可能由占用相同 eFuse 位的多个子 eFuse 字段组成。 + +定义格式 +^^^^^^^^^^^^^^^^^^ + +一般情况下，每个记录在定义表格中占据一行，每行包含以下值（也就是列）： + +{IDF_TARGET_MAX_EFUSE_BLK:default = "EFUSE_BLK10", esp32 = "EFUSE_BLK3", esp32c2 = "EFUSE_BLK3"} + +.. code-block:: none + + # field_name, efuse_block(EFUSE_BLK0..{IDF_TARGET_MAX_EFUSE_BLK}), bit_start(0..255), bit_count(1..256), comment + +- ``field_name`` + + - eFuse 字段的名称。 + - 字段名称前会自动添加 ``ESP_EFUSE_`` 前缀，在 C 代码中，可通过此名称来访问 eFuse 字段。 + - 对于每个 eFuse 字段，``field_name`` 必须唯一。 + - 如果此值为空，说明该行与前一行合并。这样就可以定义任意位排序的 eFuse 字段（例如通用表中的 ``MAC_FACTORY`` 字段）。 + - 使用 ``.`` 来定义一个子 eFuse 字段。详情请参考 :ref:`structured-efuse-fields`。 + +- ``efuse_block`` + + - eFuse 字段的块号。例如 EFUSE_BLK0 到 {IDF_TARGET_MAX_EFUSE_BLK}。 + - 这一字段决定了 eFuse 字段在哪个块中。 + +- ``bit_start`` + + - eFuse 字段在块内的位置偏移（0 至 255 位）。 + - ``bit_start`` 是可选项，可省略。 + + - 当省略时，如果上一条记录位于同一个 eFuse 块中，``bit_start`` 会被设置为上一条记录的 ``bit_start + bit_count``。 + - 如果上一条记录位于不同的 eFuse 块中，则会报错。 + +- ``bit_count`` + + - eFuse 字段的大小，以位为单位（1 至 N）。 + - ``bit_count`` 不能省略 + - 如将其设置为 ``MAX_BLK_LEN``，则此 eFuse 字段为块中允许的最大 eFuse 字段大小。 + + .. only:: esp32 + + - ``MAX_BLK_LEN`` 考虑了 eFuse 的编码方案。 + - 根据 :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR` 选择的编码方案，``MAX_BLK_LEN`` 可能是 256("None")、192 ("3/4") 或 128 ("REPEAT") 位。 + +- ``comment`` + + - 描述 eFuse 字段的注释。 + - 此注释会逐字复制到 C 头文件中。 + +如果一个 eFuse 字段需要非顺序位序，那么该 eFuse 字段将占用多行。应在第一行的 ``field_name`` 处定该 eFuse 字段的名称，并且将其他行的 ``field_name`` 留空。这样就表明这些行属于同一个 eFuse 字段。 + +以下示例中定义了两个 eFuse 字段。首先定义非连续的 eFuse 字段 ``MAC_FACTORY``，然后定义了常规 eFuse 字段 ``MAC_FACTORY_CRC``： + +.. code-block:: none + + # Factory MAC address # + ####################### + MAC_FACTORY, EFUSE_BLK0, 72, 8, Factory MAC addr [0] + , EFUSE_BLK0, 64, 8, Factory MAC addr [1] + , EFUSE_BLK0, 56, 8, Factory MAC addr [2] + , EFUSE_BLK0, 48, 8, Factory MAC addr [3] + , EFUSE_BLK0, 40, 8, Factory MAC addr [4] + , EFUSE_BLK0, 32, 8, Factory MAC addr [5] + MAC_FACTORY_CRC, EFUSE_BLK0, 80, 8, CRC8 for factory MAC address + +在 C 代码中，可以通过 ``ESP_EFUSE_MAC_FACTORY`` 和 ``ESP_EFUSE_MAC_FACTORY_CRC`` 使用这两个字段。 + +.. _structured-efuse-fields: + +结构化 eFuse 字段 +----------------------- + +通常情况下，一个 eFuse 字段代表一个特定的参数。不过，在某些情况下，一个 eFuse 字段可能由多个子字段组成，因此有必要隔离访问这些子字段。例如，如果一个 eFuse 字段包含一个浮点参数，则可以将浮点的符号、指数和尾数字段作为单独的 eFuse 字段进行访问。 + +因此，可以在 ``field_name`` 中使用 ``.`` 操作符，以结构化的方式定义 eFuse 字段。例如，``XX.YY.ZZ`` 定义了一个 eFuse 字段 ``ZZ``，它是 eFuse 字段 ``YY`` 的子字段，而 ``YY`` 又是 eFuse 字段 ``XX`` 的子字段。 + +以下示例展示了如何以定义结构化 eFuse 字段： + +.. code-block:: none + + WR_DIS, EFUSE_BLK0, 0, 32, Write protection + WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS + WR_DIS.FIELD_1, EFUSE_BLK0, 1, 1, Write protection for FIELD_1 + WR_DIS.FIELD_2, EFUSE_BLK0, 2, 4, Write protection for FIELD_2 (includes B1 and B2) + WR_DIS.FIELD_2.B1, EFUSE_BLK0, 2, 2, Write protection for FIELD_2.B1 + WR_DIS.FIELD_2.B2, EFUSE_BLK0, 4, 2, Write protection for FIELD_2.B2 + WR_DIS.FIELD_3, EFUSE_BLK0, 5, 1, Write protection for FIELD_3 + WR_DIS.FIELD_3.ALIAS, EFUSE_BLK0, 5, 1, Write protection for FIELD_3 (just a alias for WR_DIS.FIELD_3) + WR_DIS.FIELD_4, EFUSE_BLK0, 7, 1, Write protection for FIELD_4 + +在上例中可以看出： + +* ``WR_DIS`` 为父 eFuse 字段。其他所有行的 ``field_name`` 都具有 ``WR_DIS.`` 前缀，因此都是 ``WR_DIS`` 的子字段。 +* 子字段必须与父字段使用相同的位。注意子字段和父字段的 ``bit_start`` 和 ``bit_count``： + + * 子字段的位总是在其父字段范围内。例如，``WR_DIS.RD_DIS`` 和 ``WR_DIS.RD_DIS`` 占用了 ``WR_DIS`` 的第一位和第二位。 + * 子字段使用的位不能重叠（子字段有别名时除外）。 + +* 可以将别名创建为子字段。例如，``WR_DIS.FIELD_3.ALIAS`` 既是 ``WR_DIS.FIELD_3`` 的子字段，又是别名，因为它们占用的位相同。 + +所有 eFuse 字段最终都会通过 ``efuse_table_gen.py`` 工具转换为 C 结构体。每个 C 结构体从 eFuse 字段的 ``field_name`` 中衍生出标识符，并用 ``_`` 替换所有的 ``.`` 符号。以 ``WR_DIS.RD_DIS`` 和 ``WR_DIS.FIELD_2.B1`` 为例，这两个 eFuse 字段用 C 语言分别表示为 ``ESP_EFUSE_WR_DIS_RD_DIS`` 和 ``ESP_EFUSE_WR_DIS_FIELD_2_B1``。 + +``efuse_table_gen.py`` 工具还会检查字段是否相互重叠并在字段范围内。如有违反，会生成以下错误： + +.. code-block:: none + + Field at USER_DATA, EFUSE_BLK3, 0, 256 intersected with SERIAL_NUMBER, EFUSE_BLK3, 0, 32 + +要解决此问题，可使用 ``USER_DATA.SERIAL_NUMBER``，让 ``SERIAL_NUMBER`` 成为 ``USER_DATA`` 的子字段。 + +.. code-block:: none + + Field at FIELD, EFUSE_BLK3, 0, 50 out of range FIELD.MAJOR_NUMBER, EFUSE_BLK3, 60, 32 + +要解决此问题，可将 ``FIELD.MAJOR_NUMBER`` 的 ``bit_start`` 从 ``60`` 改为 ``0``，使 ``MAJOR_NUMBER`` 与 ``FIELD`` 重叠。 + +``efuse_table_gen.py`` 工具 +--------------------------- + +``efuse_table_gen.py`` 工具能够从 CSV 文件生成 C 源文件，其中包含 CSV 文件中定义的 eFuse 字段的对应 C 结构体（类型为 :cpp:type:`esp_efuse_desc_t`）。此外，该工具还会在生成 C 源文件前对 CSV 文件进行检查，以确保： + +- eFuse 字段的名称唯一 +- eFuse 字段使用的位不重叠 + +如前所述，eFuse 字段可用于存储系统参数或用户参数。由于系统参数 eFuse 字段是 ESP-IDF 和 {IDF_TARGET_NAME} 的内在要求，这些 eFuse 字段被定义在 **通用** CSV 文件中，即 ``esp_efuse_table.csv`` 中，是 ESP-IDF 的一部分。对于用户参数 eFuse 字段，用户应在 **自定义** CSV 文件（如 ``esp_efuse_custom_table.csv``）中进行定义。 + +要从 **通用** CSV 文件生成 C 源文件，运行 ``idf.py efuse-common-table`` 或以下命令： + +.. code-block:: bash + + cd $IDF_PATH/components/efuse/ + ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv + +然后，就会在路径 ``$IDF_PATH/components/efuse/{IDF_TARGET_PATH_NAME}`` 中生成以下 C 源文件/头文件： + +* ``esp_efuse_table.c`` 文件，包含系统参数 eFuse 字段的 C 结构体。 +* ``esp_efuse_table.h`` 文件，位于 ``include`` 文件夹。应用程序可包含该头文件，以使用上述 C 结构体。 + +要使用 **自定义** CSV 文件生成 C 源文件，请运行 ``idf.py efuse-custom-table`` 或以下命令： + +.. code-block:: bash + + cd $IDF_PATH/components/efuse/ + ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv PROJECT_PATH/main/esp_efuse_custom_table.csv + +然后在 ``PROJECT_PATH/main`` 路径下生成 C 源/头文件： + +* ``esp_efuse_custom_table.c`` 文件，包含用户参数 eFuse 字段的 C 结构体。 +* ``esp_efuse_custom_table.h`` 文件，位于 ``include`` 文件夹。应用程序可包含该头文件，以使用上述 C 结构体。 + +要使用生成的字段，需添加以下头文件： + +.. code-block:: c + + #include "esp_efuse.h" + #include "esp_efuse_table.h" // 或 "esp_efuse_custom_table.h" + + +支持的编码方式 +----------------------- + +eFuse 支持各种编码方式，能够检测或纠正错误，保护 eFuse 数据不受损坏。 + +.. only:: esp32 + + {IDF_TARGET_NAME} 支持以下 eFuse 编码方式： + + * ``非编码`` 方式（值为 0），即不采用编码方式。 + * ``3/4 编码`` 方式（值为 1）。 + * ``重复编码`` 方式（值为 2）。不完全受到 IDF 支持，不推荐使用。 + + 以上编码方案对每个 eFuse 块进行单独编码。此外，只有 EFUSE_BLK1、EFUSE_BLK2 和 EFUSE_BLK3 将被编码，这意味着 EUSE_BLK0 始终采用 ``非编码`` 方式。 + + 编码方案要求将 eFuse 块中的某些位用作开销。因此，采用编码方案后，每个 eFuse 块的 256 位中只有一部分可用于 eFuse 字段。 + + * ``非编码``：256 位 + * ``3/4 编码``：192 位 + * ``重复编码``：128 位 + + 当使用一种编码方式时，可以写入的有效载荷长度是有限的。如需了解更多内容，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *章节 20 eFuse 控制器 (eFuse)* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__] > *章节 20.3.1.3 系统参数 coding_scheme*。 + + 通过以下步骤查看芯片的编码方式： + + * 运行 ``idf.py efuse-summary`` 命令。 + * 在烧录期间从 ``esptool`` 应用程序日志中查看。 + * 在应用程序中调用 :cpp:func:`esp_efuse_get_coding_scheme` 函数查看 EFUSE_BLK3 块的编码方式。 + + CSV 文件中指定的 eFuse 字段必须始终符合芯片使用的 eFuse 编码方案。可以通过 :ref:`CONFIG_EFUSE_CODE_SCHEME_SELECTOR` 选择 CSV 文件使用的编码方案。生成源文件时，如果 CSV 文件中的内容不符合编码方案，则会显示错误信息。在这种情况下，必须调整错误行的 ``bit_start`` 和 ``bit_count``，以满足所选编码方案的限制。 + + .. note:: + + 更改编码方式后，运行 ``efuse_common_table`` 和 ``efuse_custom_table`` 命令以查看采用新编码方式的 CSV 表格。 + + 如果程序是用 ``非编码`` 方式编译的，而芯片中使用的是 ``3/4 编码`` 方式，那么调用 eFuse API 时可能会出现 ``ESP_ERR_CODING`` 错误（字段超出块边界）。如果字段符合新的块边界，则 API 会正常运行。 + + ``非编码`` 方式 + ^^^^^^^^^^^^^^^^^ + + ``非编码`` 方式表示不使用编码方案，因此 eFuse 数据块的 256 位都可以使用。不过，这中方式无法防止 eFuse 位的数据损坏。 + + ``3/4 编码`` 方式 + ^^^^^^^^^^^^^^^^^^^^^ + + ``3/4 编码`` 方式会限制写入一个编码单元的位数。长度为 256 位的块被划分为 4 个编码单元，每个编码单元包含 6 字节的有用数据和 2 字节的服务数据。这 2 字节的服务数据中存储了前 6 个数据字节的校验和。 + + 由于要计算每个编码单元的校验和，写入过程必须根据不同的编码单元进行划分。在这种情况下，通过多个写入操作分别烧录各 eFuse 位（ ``非编码`` 方式的烧录方法）的常规做法将不再适用，必须一次性同时烧写该编码单元的 eFuse 字段数据和校验和。这就是所谓的批量写入模式。 + + 由于采用批量写入模式，一个编码单元只能写入一次，禁止在同一编码单元重复写入。这意味着，在运行时写入的编码单元中只能包含一个 eFuse 字段。但是，如果事先通过 CSV 文件指定了编码单元的 eFuse 字段，或通过 :cpp:func:`esp_efuse_write_block` 写入编码单元的 eFuse 字段，那么一个编码单元中仍可包含多个 eFuse 字段。 + + + ``重复编码`` 方式 + ^^^^^^^^^^^^^^^^^^^^^^^^ + ``重复编码`` 方式只是简单重复每个 eFuse 位，不会像 ``3/4 编码`` 方式那样受到批量写入模式的限制。不过，这样做会产生很大的开销，每个 eFuse 块中只有 128 个位可用。 + +.. only:: not esp32 + + {IDF_TARGET_NAME} 不支持选择编码方式，会自动将以下编码方案应用于各 eFuse 块： + + * ``非编码`` 方式，应用于 EFUSE_BLK0。 + * ``RS 编码`` 方式。应用于 EFUSE_BLK1 - {IDF_TARGET_MAX_EFUSE_BLK}。 + + ``非编码`` 方式 + ^^^^^^^^^^^^^^^^^^^^^^ + + ``非编码`` 方式会自动应用于 EFUSE_BLK0。此方式不涉及任何编码，只是在硬件中维护 EFUSE_BLK0 的四个备份，因此，每个位实际存储四次，EFUSE_BLK0 也可以多次写入。 + + 该方案由硬件自动应用，软件中不可见。 + + ``RS 编码`` 方式 + ^^^^^^^^^^^^^^^^^^^^^^ + + * ``RS 编码`` 方式，即 Reed-Solomon 编码方式，会自动应用于 EFUSE_BLK1 至 {IDF_TARGET_MAX_EFUSE_BLK}。该编码方式支持至多 6 个字节的自动纠错。 + + 软件使用 ``RS(44, 32)`` 对 32 字节的 EFUSE_BLKx 进行编码，生成一个 12 字节的校验码，然后将 EFUSE_BLKx 和校验码同时烧录到 eFuse 中。 + + 在回读 eFuse 块时，eFuse 控制器会对 ``RS 编码`` 进行自动解码和纠错。因为 ``RS`` 校验码是根据整个 256 位 eFuse 块生成的，所以每个块只能写入一次，且必须采用批量写入模式。 + +批量写入模式 +^^^^^^^^^^^^ + +如需在运行时写入 eFuse 字段，可能要采用批量写入模式，具体取决于 eFuse 块使用的编码方案。批量写入模式的使用步骤如下： + +#. 调用 :cpp:func:`esp_efuse_batch_write_begin` 启用批量写入模式。 +#. 使用各 ``esp_efuse_write_...`` 函数，按照常规方法写入 eFuse 字段。 +#. 完成所有写入后，调用 :cpp:func:`esp_efuse_batch_write_commit` 将准备好的数据烧录到 eFuse 块中。 + +.. warning:: + + 如果 eFuse 块中已经存在通过 ``{IDF_TARGET_CODING_SCHEMES}`` 编码方案预先写入的数据，则无法在不破坏先前数据校验和/校验符号的情况下，写入额外的内容（即使需要写入的位为空）。 + + 先前的校验和/校验符号会被新的校验和/校验符号覆盖，并完全销毁。（但不会损坏有效负载 eFuse）。 + + 如发现在 CUSTOM_MAC、SPI_PAD_CONFIG_HD、SPI_PAD_CONFIG_CS 等块中存在预写入数据，请联系乐鑫获取所需的预烧录 eFuse。 + + 仅供测试（不推荐）：可以忽略或抑制违反编码方式数据的错误，从而在 eFuse 块中烧录必要的位。 + +.. _efuse_API: + +eFuse API +--------- + +可以通过指向描述结构的指针来访问 eFuse 字段。API 函数可以实现一些基本操作： + +* :cpp:func:`esp_efuse_read_field_blob` - 返回读取的 eFuse 位的数组。 +* :cpp:func:`esp_efuse_read_field_cnt` - 返回烧写为 “1” 的位的数量。 +* :cpp:func:`esp_efuse_write_field_blob` - 写入一个数组。 +* :cpp:func:`esp_efuse_write_field_cnt` - 将所需数量的位写为 “1”。 +* :cpp:func:`esp_efuse_get_field_size` - 返回字段的位数。 +* :cpp:func:`esp_efuse_read_reg` - 返回 eFuse 寄存器的值。 +* :cpp:func:`esp_efuse_write_reg` - 将值写入 eFuse 寄存器。 +* :cpp:func:`esp_efuse_get_coding_scheme` - 返回块的 eFuse 编码方式。 +* :cpp:func:`esp_efuse_read_block` - 从指定偏移位置开始读取指定大小的 eFuse 块中的密钥。 +* :cpp:func:`esp_efuse_write_block` - 从指定偏移位置开始将密钥写入指定大小的 eFuse 块中。 +* :cpp:func:`esp_efuse_batch_write_begin` - 设置字段写入的批处理模式。 +* :cpp:func:`esp_efuse_batch_write_commit` - 写入所有为批处理写入模式准备的数据，并重置批处理写入模式。 +* :cpp:func:`esp_efuse_batch_write_cancel` - 重置批处理写入模式和准备的数据。 +* :cpp:func:`esp_efuse_get_key_dis_read` - 返回密钥块的读保护状态。 +* :cpp:func:`esp_efuse_set_key_dis_read` - 设置密钥块的读保护状态。 +* :cpp:func:`esp_efuse_get_key_dis_write` - 返回密钥块的写保护状态。 +* :cpp:func:`esp_efuse_set_key_dis_write` - 设置密钥块的写保护状态。 +* :cpp:func:`esp_efuse_get_key_purpose` - 返回 eFuse 密钥块当前设置的用途。 +* :cpp:func:`esp_efuse_write_key` - 将一块密钥数据烧写到一个 eFuse 块。 +* :cpp:func:`esp_efuse_write_keys` - 将密钥烧写到未使用的 eFuse 块。 +* :cpp:func:`esp_efuse_find_purpose` - 查找设置为特定用途的密钥块。 +* :cpp:func:`esp_efuse_get_keypurpose_dis_write` - 返回 eFuse 密钥块的密钥用途字段的写保护状态（对于 esp32 始终为 true）。 +* :cpp:func:`esp_efuse_key_block_unused` - 如果密钥块未使用，则返回 true，否则返回 false。 +* :cpp:func:`esp_efuse_destroy_block` - 销毁此 eFuse 块中的数据。该函数有两个作用：(1) 如果未开启写保护，则将不为 1 的位都烧写为 1；(2) 如果未开启读保护，则开启读保护。 + +经常使用的字段有专门的函数可供使用，例如 :cpp:func:`esp_efuse_get_pkg_ver`。 + +.. only:: SOC_EFUSE_KEY_PURPOSE_FIELD or SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + + eFuse 密钥 API + ------------------ + + .. only:: SOC_EFUSE_KEY_PURPOSE_FIELD + + EFUSE_BLK_KEY0 - EFUSE_BLK_KEY5 可以保存 6 个长度为 256 位的密钥。每个密钥都有一个 ``ESP_EFUSE_KEY_PURPOSE_x`` 字段说明密钥用途。用途字段描述见 :cpp:type:`esp_efuse_purpose_t`。 + + 类似 ``ESP_EFUSE_KEY_PURPOSE_XTS_AES_...`` 的用途用于 flash 加密。 + + 类似 ``ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST...`` 的用途用于安全启动。 + + 一些 eFuse API 可用于处理密钥状态： + + * :cpp:func:`esp_efuse_get_purpose_field` - 返回一个指向 eFuse 密钥块的密钥用途的指针。 + * :cpp:func:`esp_efuse_get_key` - 返回一个指向密钥块的指针。 + * :cpp:func:`esp_efuse_set_key_purpose` - 为一个 eFuse 密钥块设置密钥用途。 + * :cpp:func:`esp_efuse_set_keypurpose_dis_write` - 为 eFuse 密钥块的密钥用途字段设置写保护。 + * :cpp:func:`esp_efuse_find_unused_key_block` - 搜索未使用的密钥块并返回找到的第一个结果。 + * :cpp:func:`esp_efuse_count_unused_key_blocks` - 返回 EFUSE_BLK_KEY0..EFUSE_BLK_KEY_MAX 范围中未使用的 eFuse 密钥块数量。 + + .. only:: SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + + * :cpp:func:`esp_efuse_get_digest_revoke` - 返回安全启动公钥摘要撤销位的状态。 + * :cpp:func:`esp_efuse_set_digest_revoke` - 设置安全启动公钥摘要撤销位。 + * :cpp:func:`esp_efuse_get_write_protect_of_digest_revoke` - 返回安全启动公钥摘要撤销位的写保护。 + * :cpp:func:`esp_efuse_set_write_protect_of_digest_revoke` - 设置安全启动公钥摘要撤销位的写保护。 + + +如何添加新字段 +---------------------- + +1. 为新字段查找空闲位。运行 ``idf.py show-efuse-table`` 查看 ``esp_efuse_table.csv`` 文件，或运行以下命令： + +.. include:: inc/show-efuse-table_{IDF_TARGET_NAME}.rst + +不包含在方括号中的位是空闲的（一些位是乐鑫的保留位）。已检查所有字段的位重叠情况。 + +要在现有字段中添加子字段，请参考 :ref:`structured-efuse-fields`。例如，可使用 ``.`` 操作符将字段 ``SERIAL_NUMBER``、``MODEL_NUMBER`` 和 ``HARDWARE_REV`` 添加到现有的 ``USER_DATA`` 字段中，如下所示： + +.. code-block:: none + + USER_DATA.SERIAL_NUMBER, EFUSE_BLK3, 0, 32, + USER_DATA.MODEL_NUMBER, EFUSE_BLK3, 32, 10, + USER_DATA.HARDWARE_REV, EFUSE_BLK3, 42, 10, + +通常按照如下步骤添加新的 eFuse 字段： + +#. 在 CSV 文件中为每个 eFuse 字段添加一行记录。 +#. 运行 ``show_efuse_table`` 命令检查 eFuse 表。 +#. 如要生成源文件，运行 ``efuse_common_table`` 或 ``efuse_custom_table`` 命令。 + +如果遇到 ``intersects with`` 或 ``out of range`` 等错误，请参阅 :ref:`structured-efuse-fields` 中的解决办法。 + +位序 +---- + +eFuse 位序采取小字节序（参见下方示例），这说明 eFuse 位按照从 LSB 到 MSB 的顺序进行读写： + +.. code-block:: none + + $ espefuse.py dump + + USER_DATA (BLOCK3 ) [3 ] read_regs: 03020100 07060504 0B0A0908 0F0E0D0C 13121111 17161514 1B1A1918 1F1E1D1C + BLOCK4 (BLOCK4 ) [4 ] read_regs: 03020100 07060504 0B0A0908 0F0E0D0C 13121111 17161514 1B1A1918 1F1E1D1C + + where is the register representation: + + EFUSE_RD_USR_DATA0_REG = 0x03020100 + EFUSE_RD_USR_DATA1_REG = 0x07060504 + EFUSE_RD_USR_DATA2_REG = 0x0B0A0908 + EFUSE_RD_USR_DATA3_REG = 0x0F0E0D0C + EFUSE_RD_USR_DATA4_REG = 0x13121111 + EFUSE_RD_USR_DATA5_REG = 0x17161514 + EFUSE_RD_USR_DATA6_REG = 0x1B1A1918 + EFUSE_RD_USR_DATA7_REG = 0x1F1E1D1C + + where is the byte representation: + + byte[0] = 0x00, byte[1] = 0x01, ... byte[3] = 0x03, byte[4] = 0x04, ..., byte[31] = 0x1F + +例如，CSV 文件描述了 ``USER_DATA`` 字段，该字段占用 256 位，即一个完整的块。 + +.. code-block:: none + + USER_DATA, EFUSE_BLK3, 0, 256, User data + USER_DATA.FIELD1, EFUSE_BLK3, 16, 16, Field1 + + ID, EFUSE_BLK4, 8, 3, ID bit[0..2] + , EFUSE_BLK4, 16, 2, ID bit[3..4] + , EFUSE_BLK4, 32, 3, ID bit[5..7] + +因此，读取如上 eFuse ``USER_DATA`` 块会得到以下结果： + +.. code-block:: c + + uint8_t buf[32] = { 0 }; + esp_efuse_read_field_blob(ESP_EFUSE_USER_DATA, &buf, sizeof(buf) * 8); + // buf[0] = 0x00, buf[1] = 0x01, ... buf[31] = 0x1F + + uint32_t field1 = 0; + size_t field1_size = ESP_EFUSE_USER_DATA[0]->bit_count; // 可以用于这种情况，因为它只包含一个条目 + esp_efuse_read_field_blob(ESP_EFUSE_USER_DATA, &field1, field1_size); + // field1 = 0x0302 + + uint32_t field1_1 = 0; + esp_efuse_read_field_blob(ESP_EFUSE_USER_DATA, &field1_1, 2); // 只读取前两位 + // field1 = 0x0002 + + uint8_t id = 0; + size_t id_size = esp_efuse_get_field_size(ESP_EFUSE_ID); // 返回 6 + // size_t id_size = ESP_EFUSE_USER_DATA[0]->bit_count; // 不能用于这种情况，因为其中包含 3 个条目，会返回 3 而不是 6 + esp_efuse_read_field_blob(ESP_EFUSE_ID, &id, id_size); + // id = 0x91 + // b'100 10 001 + // [3] [2] [3] + + uint8_t id_1 = 0; + esp_efuse_read_field_blob(ESP_EFUSE_ID, &id_1, 3); + // id = 0x01 + // b'001 + + +在构建阶段获取 eFuse 状态 +------------------------- + +要在项目的构建阶段获取 eFuse 状态，可以使用以下两个 CMake 函数： + +* ``espefuse_get_json_summary()`` - 调用 ``espefuse.py summary --format json`` 命令并返回一个 JSON 字符串（该字符串不存储在文件中）。 +* ``espefuse_get_efuse()`` - 在此 JSON 字符串中找到给定的 eFuse 名称并返回其属性。 + +该 JSON 字符串具有以下属性： + +.. code-block:: json + + { + "MAC": { + "bit_len": 48, + "block": 0, + "category": "identity", + "description": "Factory MAC Address", + "efuse_type": "bytes:6", + "name": "MAC", + "pos": 0, + "readable": true, + "value": "94:b9:7e:5a:6e:58 (CRC 0xe2 OK)", + "word": 1, + "writeable": true + }, + } + +可以通过项目顶层目录下的 ``CMakeLists.txt`` (:example_file:`get-started/hello_world/CMakeLists.txt`) 来使用这些函数： + +.. code-block:: cmake + + # ... + project(hello_world) + + espefuse_get_json_summary(efuse_json) + espefuse_get_efuse(ret_data ${efuse_json} "MAC" "value") + message("MAC:" ${ret_data}) + +``value`` 属性的格式与 ``espefuse.py summary`` 中显示的格式相同。 + +.. code-block:: none + + MAC:94:b9:7e:5a:6e:58 (CRC 0xe2 OK) + +在示例测试 :example_file:`system/efuse/CMakeLists.txt` 中，添加了一个自定义目标 ``efuse-summary``。这样，不仅在项目构建阶段，而在任何时候都可以运行 ``idf.py efuse-summary`` 命令读取所需的 eFuse（在 ``efuse_names`` 列表中指定）。 + +调试 eFuse & 单元测试 +------------------------ + +.. _virtual-efuses: + +虚拟 eFuse +^^^^^^^^^^^^^^ + +Kconfig 选项 :ref:`CONFIG_EFUSE_VIRTUAL` 在 eFuse 管理器中虚拟了 eFuse 值，因此写入操作是仿真操作，不会永久更改 eFuse 值。这对于应用程序调试和单元测试很有用处。 + +在启动时，eFuses 被复制到 RAM 中。此时，所有的 eFuse 操作（读和写）都是通过 RAM 执行，而不是通过实际的 eFuse 寄存器执行的。 + +除了 :ref:`CONFIG_EFUSE_VIRTUAL` 选项外，还有 :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` 选项，该选项可将 eFuse 保留在 flash 内存中。要使用此模式，partition_table 在 ``partition.csv`` 中包含名为 ``efuse`` 的分区： + +.. code-block:: none + + efuse_em, data, efuse, , 0x2000, + +在启动阶段，eFuse 会从 flash 中复制到 RAM 中，在 flash 为空的情况下，则从实际的 eFuse 复制到 RAM 中，然后更新 flash。此选项能够在重启后仍然保留 eFuse，用于测试安全启动和 flash 加密功能。 + +flash 加密测试 +"""""""""""""" + +flash 加密是一项硬件功能，需要物理烧录 eFuse ``key`` 和 ``FLASH_CRYPT_CNT``。如果 flash 加密实际未启用，那么启用 :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` 选项只是提供了测试的可能性，而不会加密 flash 中的任何内容，即使日志中显示了加密操作。 + +为此，可使用 :cpp:func:`bootloader_flash_write` 函数。但是，如果运行应用程序时芯片已启用 flash 加密，或者以 :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` 选项创建了启动加载程序，则 flash 加密/解密操作会正常进行。这意味着数据写入加密 flash 分区时被加密，从加密分区读取时被解密。 + +``espefuse.py`` +^^^^^^^^^^^^^^^ + +esptool 中包含一个用于读取/写入 {IDF_TARGET_NAME} eFuse 位的有用工具： `espefuse.py `_。 + +``idf.py`` 命令也可以直接提供上述工具的部分功能。例如，运行 ``idf.py efuse-summary`` 命令，效果等同于 ``espefuse.py summary``。 + +.. include:: inc/espefuse_summary_{IDF_TARGET_NAME}.rst + +.. include-build-file:: inc/esp_efuse_chip.inc +.. include-build-file:: inc/esp_efuse.inc diff --git a/docs/zh_CN/api-reference/system/log.rst b/docs/zh_CN/api-reference/system/log.rst index ccfa490c3958..991c2fad13d7 100644 --- a/docs/zh_CN/api-reference/system/log.rst +++ b/docs/zh_CN/api-reference/system/log.rst @@ -10,7 +10,7 @@ - **编译时**：在 menuconfig 中，使用选项 :ref:`CONFIG_LOG_DEFAULT_LEVEL` 来设置日志级别。 - 另外，还可以选择在 menuconfig 中使用选项 :ref:`CONFIG_LOG_MAXIMUM_LEVEL` 设置最高日志级别。这个选项默认被配置为默认级别，但这个选项也可以被配置为更高级别，将更多的可选日志编译到固件中。 -- **运行时**：默认启用所有级别低于 :ref:`CONFIG_LOG_DEFAULT_LEVEL` 的日志。:cpp:func:`esp_log_level_set` 函数可以为各个模块分别设置不同的日志级别，可通过人类可读的 ASCII 零终止字符串标签来识别不同的模块。 +- **运行时**：默认启用所有级别低于 :ref:`CONFIG_LOG_DEFAULT_LEVEL` 的日志。:cpp:func:`esp_log_level_set` 函数可以为各个模块分别设置不同的日志级别，可通过人类可读的 ASCII 零终止字符串标签来识别不同的模块。注意，在运行时是否可以更改日志级别由 :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` 决定。 - **运行时**：启用 :ref:`CONFIG_LOG_MASTER_LEVEL` 时，可以使用 :cpp:func:`esp_log_set_level_master` 函数设置 ``主日志级别`` (Master logging level)。该选项会为所有已编译的日志添加额外的日志级别检查。注意，使用此选项会增加应用程序大小。如果希望在运行时编译大量可选日志，同时避免在不需要日志输出时查找标签及其级别带来的性能损耗，此功能会非常有用。 以下是不同的日志级别： @@ -72,6 +72,9 @@ target_compile_definitions(${COMPONENT_LIB} PUBLIC "-DLOG_LOCAL_LEVEL=ESP_LOG_VERBOSE") +动态控制日志级别 +---------------- + 如需在运行时按模块配置日志输出，请按如下方式调用 :cpp:func:`esp_log_level_set` 函数： .. code-block:: c @@ -86,6 +89,19 @@ 即使已通过标签名称禁用日志输出，每个条目仍需约 10.9 微秒的处理时间。 +日志组件提供多种选项，可以更好地调整系统以满足需求，从而减少内存使用并提高操作速度。:ref:`CONFIG_LOG_TAG_LEVEL_IMPL` 可配置检查标签级别： + +- ``None``：选择此选项，则会禁用为每个标签设置日志级别的功能。在运行时是否可以更改日志级别取决于 :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL`。如果禁用，则无法在运行时使用 :cpp:func:`esp_log_level_set` 更改日志级别。该选项适用于高度受限的环境。 +- ``Linked list (no cache)``：选择此选项，则会启用为每个标签设置日志级别的功能。此方法在链表中搜索所有标签的日志级别。如果标签数量比较多，这种方法可能会比较慢，但内存要求可能低于下面的 cache 方式。 +- ``Cache + Linked List`` （默认选项）：选择此选项，则会启用为每个标签设置日志级别的功能。这种混合方法在速度和内存使用之间实现了平衡。cache 中存储最近访问的日志标签及其相应的日志级别，从而更快地查找常用标签。 + +启用 :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL` 选项后，则可在运行时通过 :cpp:func:`esp_log_level_set` 更改日志级别。动态更改日志级别提高了灵活性，但也会产生额外的代码开销。 +如果应用程序不需要动态更改日志级别，并且不需要使用标签来控制每个模块的日志，建议禁用 :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL`。与默认选项相比，这可以节约大概 260 字节的 IRAM、264 字节的 DRAM、以及 1 KB 的 flash。这不仅可以简化日志，提高内存效率，还可以将应用程序中的日志操作速度提高约 10 倍。 + +.. note:: + + ``Linked list`` 和 ``Cache + Linked List`` 选项将自动启用 :ref:`CONFIG_LOG_DYNAMIC_LEVEL_CONTROL`。 + 主日志级别 ^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-reference/system/power_management.rst b/docs/zh_CN/api-reference/system/power_management.rst index bcbf880543a5..a9221f19128e 100644 --- a/docs/zh_CN/api-reference/system/power_management.rst +++ b/docs/zh_CN/api-reference/system/power_management.rst @@ -142,15 +142,14 @@ Light-sleep 外设下电 - INT_MTX - TEE/APM - IO_MUX / GPIO - - UART0 - - TIMG0 + - UART0/1 + - GPTimer - SPI0/1 - SYSTIMER - RMT 以下外设尚未支持： - ETM - - TIMG1 - ASSIST_DEBUG - Trace - Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA @@ -164,7 +163,6 @@ Light-sleep 外设下电 - SARADC - SDIO - PARL_IO - - UART1 对于未支持 Light-sleep 上下文备份的外设，若启用了电源管理功能，应在外设工作时持有 ``ESP_PM_NO_LIGHT_SLEEP`` 锁以避免进入休眠导致外设工作上下文丢失。 diff --git a/docs/zh_CN/api-reference/system/ulp-lp-core.rst b/docs/zh_CN/api-reference/system/ulp-lp-core.rst index f44bd3efa600..b98d804857c5 100644 --- a/docs/zh_CN/api-reference/system/ulp-lp-core.rst +++ b/docs/zh_CN/api-reference/system/ulp-lp-core.rst @@ -7,7 +7,7 @@ ULP LP-Core（低功耗内核）协处理器是 {IDF_TARGET_NAME} 中 ULP 的一 ULP LP-Core 协处理器具有以下功能： -* 利用基于 RISC-V ISA 的 32 位处理器，包括标准扩展整数 (I)、乘法/除法 (M)、原子 (A) 和压缩 (C)。 +* RV32I 处理器（32 位 RISC-V ISA），支持乘法/除法 (M)、原子 (A) 和压缩 (C) 扩展。 * 中断控制器。 * 包含一个调试模块，支持通过 JTAG 进行外部调试。 * 当整个系统处于 active 模式时，可以访问所有的高功耗 (HP) SRAM 和外设。 @@ -22,6 +22,8 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 2. 在 CMakeLists.txt 文件中注册组件后，调用 ``ulp_embed_binary`` 函数。例如： +.. code-block:: cmake + idf_component_register() set(ulp_app_name ulp_${COMPONENT_NAME}) @@ -83,7 +85,9 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二 注意，所有的符号（变量、数组、函数）都被声明为 ``uint32_t`` 类型。对于函数和数组，获取符号的地址并将其转换为合适的类型。 -生成的链接器脚本文件定义了 LP_MEM 中符号的位置:: +生成的链接器脚本文件定义了 LP_MEM 中符号的位置： + +.. code-block:: none PROVIDE ( ulp_measurement_count = 0x50000060 ); @@ -178,13 +182,49 @@ ULP LP-Core 支持的外设 在任何情况下，这些函数都存在于 LP-ROM 中，因此在程序中使用这些函数可以减少 ULP 应用程序的 RAM 占用。 +ULP LP-Core 中断 +---------------- + +配置 LP-Core 协处理器，可以处理各种类型的中断，例如 LP IO 低/高电平中断或是 LP 定时器中断。只需重写 IDF 提供的任何一个弱处理函数，就可以注册一个中断处理程序。所有处理程序可见 :component_file:`ulp_lp_core_interrupts.h `。有关特定目标可使用的中断的详细信息，请参阅 **{IDF_TARGET_NAME} 技术参考手册** [`PDF <{IDF_TARGET_TRM_CN_URL}#ulp>`__]。 + +例如，要重写 LP IO 中断的处理程序，可以在 ULP LP-Core 代码中定义以下函数： + +.. code-block:: c + + void LP_CORE_ISR_ATTR ulp_lp_core_lp_io_intr_handler(void) + { + // 处理中断，清除中断源 + } + +:c:macro:`LP_CORE_ISR_ATTR` 宏用于定义中断处理函数，可确保调用中断处理程序时妥善保存并恢复寄存器。 + +除了为需要处理的中断源配置相关的中断寄存器外，还要调用 :cpp:func:`ulp_lp_core_intr_enable` 函数，在 LP-Core 中断控制器中使能全局中断。 + +调试 ULP LP-Core 应用程序 +------------------------- + +在编程 LP-Core 时，有时很难弄清楚程序未按预期运行的原因。请参考以下策略，调试 LP-Core 程序： + +* 使用 LP-UART 打印：LP-Core 可以访问 LP-UART 外设，在主 CPU 处于睡眠状态时独立打印信息。有关使用此驱动程序的示例，请参阅 :example:`system/ulp/lp_core/lp_uart/lp_uart_print`。 + +* 通过共享变量共享程序状态：如 :ref:`ulp-lp-core-access-variables` 所述，主 CPU 和 ULP 内核都可以轻松访问 RTC 内存中的全局变量。若想了解 ULP 内核的运行状态，可以将状态信息从 ULP 写入变量中，并通过主 CPU 读取信息。这种方法的缺点在于它需要主 CPU 一直处于唤醒状态，而这通常很难实现。另外，若主 CPU 一直处于唤醒状态，可能会掩盖某些问题，因为部分问题只会在特定电源域断电时发生。 + +* 紧急处理程序：当检测到异常时，LP-Core 的紧急处理程序会把 LP-Core 寄存器的状态通过 LP-UART 发送出去。将 :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` 选项设置为 ``y``，可以启用紧急处理程序。禁用此选项将减少 LP-Core 应用程序的 LP-RAM 使用量。若想从紧急转储中解析栈回溯，可以使用 esp-idf-monitor_，例如： + + .. code-block:: bash + + python -m esp_idf_monitor --toolchain-prefix riscv32-esp-elf- --target {IDF_TARGET_NAME} --decode-panic backtrace PATH_TO_ULP_ELF_FILE + + 应用示例 --------------------- +-------- * 在示例 :example:`system/ulp/lp_core/gpio` 中，ULP LP-Core 协处理器在主 CPU 深度睡眠时轮询 GPIO。 * 在示例 :example:`system/ulp/lp_core/lp_i2c` 中，ULP LP-Core 协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。 * 在示例 :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 中，低功耗内核上运行的 LP UART 驱动程序读取并回显写入串行控制台的数据。 * :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。 +* :example:`system/ulp/lp_core/interrupt` 展示了如何在 LP 内核上注册中断处理程序，接收由主 CPU 触发的中断。 +* :example:`system/ulp/lp_core/gpio_intr_pulse_counter` 展示了如何在主 CPU 处于 Deep-sleep 模式时，使用 GPIO 中断为脉冲计数。 API 参考 ------------- @@ -204,3 +244,6 @@ LP 内核 API 参考 .. include-build-file:: inc/ulp_lp_core_i2c.inc .. include-build-file:: inc/ulp_lp_core_uart.inc .. include-build-file:: inc/ulp_lp_core_print.inc +.. include-build-file:: inc/ulp_lp_core_interrupts.inc + +.. _esp-idf-monitor: https://github.com/espressif/esp-idf-monitor diff --git a/docs/zh_CN/contribute/install-pre-commit-hook.rst b/docs/zh_CN/contribute/install-pre-commit-hook.rst index d098d1d30e00..bf4fec4bb273 100644 --- a/docs/zh_CN/contribute/install-pre-commit-hook.rst +++ b/docs/zh_CN/contribute/install-pre-commit-hook.rst @@ -3,12 +3,6 @@ :link_to_translation:`en:[English]` -环境依赖 ---------------- - -我们向 IDF 开发人员推荐 Python 3.8.* 及以上版本。 - -如果你已安装了不兼容的 Python 版本，应在安装 pre-commit 工具前进行更新。 安装 ``pre-commit`` 工具 --------------------------- diff --git a/docs/zh_CN/get-started/index.rst b/docs/zh_CN/get-started/index.rst index 4cdf2bd8ede6..4a6889e3ff40 100644 --- a/docs/zh_CN/get-started/index.rst +++ b/docs/zh_CN/get-started/index.rst @@ -121,8 +121,8 @@ :maxdepth: 1 ESP32-S2-Saola-1 <../hw-reference/esp32s2/user-guide-saola-1-v1.2> - ESP32-S2-DevKitM-1 <../hw-reference/esp32s2/user-guide-devkitm-1-v1> - ESP32-S2-DevKitC-1 <../hw-reference/esp32s2/user-guide-s2-devkitc-1> + ESP32-S2-DevKitM-1 + ESP32-S2-DevKitC-1 ESP32-S2-Kaluga-Kit <../hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit> .. only:: esp32c3 diff --git a/docs/zh_CN/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst b/docs/zh_CN/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst deleted file mode 100644 index 03e03e38de76..000000000000 --- a/docs/zh_CN/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst +++ /dev/null @@ -1,321 +0,0 @@ -================== -ESP32-S2-DevKitM-1 -================== - -:link_to_translation:`en: [English]` - -本指南介绍了乐鑫的小型开发板 ESP32-S2-DevKitM-1。 - -ESP32-S2-DevKitM-1 是乐鑫一款入门级开发板。板上模组大部分管脚均已引出至两侧排针，开发人员可根据实际需求，轻松通过跳线连接多种外围设备，同时也可将开发板插在面包板上使用。 - -+----------------------+-----------------------+ -| |ESP32-S2-DevKitM-1| | |ESP32-S2-DevKitM-1U| | -+----------------------+-----------------------+ -| ESP32-S2-DevKitM-1 | ESP32-S2-DevKitM-1U | -+----------------------+-----------------------+ - -.. |ESP32-S2-DevKitM-1| image:: ../../../_static/esp32-s2-devkitm-1-v1-isometric.png - -.. |ESP32-S2-DevKitM-1U| image:: ../../../_static/esp32-s2-devkitm-1u-v1-isometric.png - -本指南包括如下内容： - -- `入门指南`_: 简要介绍了 ESP32-S2-DevKitM-1 和硬件、软件设置指南。 -- `硬件参考`_: 详细介绍了 ESP32-S2-DevKitM-1 的硬件。 -- `硬件版本`_：介绍硬件历史版本和已知问题，并提供链接至历史版本开发板的入门指南（如有）。 -- `相关文档`_: 列出了相关文档的链接。 - - -入门指南 -======== - -本节介绍了如何快速上手 ESP32-S2-DevKitM-1。开头部分介绍了 ESP32-S2-DevKitM-1，`开始开发应用`_ 小节介绍了怎样在 ESP32-S2-DevKitM-1 上烧录固件及相关准备工作。 - - -内含组件和包装 --------------- - - -.. _user-guide-devkitm-1-v1-ordering-info: - -订购信息 -^^^^^^^^ - -该开发板有多种型号可供选择，详见下表。 - -.. list-table:: - :header-rows: 1 - :widths: 30 30 10 10 20 - - * - 订购代码 - - 搭载模组 [#]_ - - Flash - - PSRAM - - 天线 - * - ESP32-S2-DevKitM-1-N4R2 - - ESP32-S2-MINI-1-2 - - （推荐） - - 4 MB - - 2 MB - - PCB 板载天线 - * - ESP32-S2-DevKitM-1U-N4R2 - - ESP32-S2-MINI-1-2U - - （推荐） - - 4 MB - - 2 MB - - 外部天线连接器 - * - ESP32-S2-DevKitM-1 - - ESP32-S2-MINI-1 - - 4 MB - - --- - - PCB 板载天线 - * - ESP32-S2-DevKitM-1U - - ESP32-S2-MINI-1U - - 4 MB - - --- - - 外部天线连接器 - * - ESP32-S2-DevKitM-1R - - ESP32-S2-MINI-1 - - 4 MB - - 2 MB - - PCB 板载天线 - * - ESP32-S2-DevKitM-1RU - - ESP32-S2-MINI-1U - - 4 MB - - 2 MB - - 外部天线连接器 - - -.. [#] ESP32-S2-MINI-2 和 ESP32-S2-MINI-2U 模组使用 v1.0 版本芯片，其余模组使用 v0.0 版本芯片。更多关于芯片版本的信息，请参考 `《ESP32-S2 系列芯片勘误表》`_。 - - -零售订单 -^^^^^^^^ - -如购买样品，每个 ESP32-S2-DevKitM-1 开发板将以防静电袋或零售商选择的其他方式包装。 - -零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。 - - -批量订单 -^^^^^^^^ - -如批量购买，ESP32-S2-DevKitM-1 开发板将以大纸板箱包装。 - -批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。 - - -组件介绍 --------- - -.. _user-guide-devkitm-1-v1-board-front: - -.. figure:: ../../../_static/esp32-s2-devkitm-1-v1-annotated-photo.png - :align: center - :alt: ESP32-S2-DevKitM-1 - 正面 - :figclass: align-center - - ESP32-S2-DevKitM-1 - 正面 - -.. figure:: ../../../_static/esp32-s2-devkitm-1u-v1-annotated-photo.png - :align: center - :alt: ESP32-S2-DevKitM-1U - 正面 - :figclass: align-center - - ESP32-S2-DevKitM-1U - 正面 - -以下按照顺时针的顺序依次介绍开发板上的主要组件。 - -.. list-table:: - :widths: 30 70 - :header-rows: 1 - - * - 主要组件 - - 介绍 - * - 板载模组（上图中为 ESP32-S2-MINI-1 或 ESP32-S2-MINI-1U） - - ESP32-S2-MINI 系列模组，可搭载 PCB 板载天线或外部天线连接器。该系列模组尺寸小，flash 和/或 PSRAM 集成在芯片封装内。更多信息，详见 :ref:`user-guide-devkitm-1-v1-ordering-info`。 - * - Pin Headers（排针） - - 所有可用 GPIO 管脚（除 flash 的 SPI 总线）均已引出至开发板的排针。用户可对 ESP32-S2FH4 芯片编程，使能 SPI、I2S、UART、I2C、触摸传感器、PWM 等多种功能。请查看 :ref:`user-guide-devkitm-1-v1-header-blocks` 获取更多信息。 - * - 3.3 V Power On LED（3.3 V 电源指示灯） - - 开发板连接 USB 电源后，该指示灯亮起。 - * - USB-to-UART Bridge（USB 转 UART 桥接器） - - 单芯片 USB 至 UART 桥接器，可提供高达 3 Mbps 的传输速率。 - * - Reset Button（Reset 键） - - 复位按键。 - * - Micro-USB（Micro-USB 接口） - - USB 接口。可用作开发板的供电电源或 PC 和 ESP32-S2FH4 芯片的通信接口。 - * - Boot Button（Boot 键） - - 下载按键。按住 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件。 - * - RGB LED - - 可寻址 RGB 发光二极管，由 GPIO18 驱动。 - * - 5 V to 3.3 V LDO（5 V 转 3.3 V LDO） - - 电源转换器，输入 5 V，输出 3.3 V。 - * - External Antenna Connector（外部天线连接器） - - 仅 **ESP32-S2-MINI-2U** 和 **ESP32-S2-MINI-1U** 模组带有外部天线连接器。连接器尺寸，请参考模组规格书的 外部天线连接器尺寸章节。 - - -开始开发应用 ------------- - -通电前，请确保 ESP32-S2-DevKitM-1 完好无损。 - - -必备硬件 -^^^^^^^^ - -- ESP32-S2-DevKitM-1 -- USB 2.0 数据线（标准 A 型转 Micro-B 型） -- 电脑（Windows、Linux 或 macOS） - -.. 注解:: - - 请确保使用适当的 USB 数据线。部分数据线仅可用于充电，无法用于数据传输和编程。 - - -软件设置 -^^^^^^^^ - -请前往 :doc:`../../get-started/index`，在 :ref:`get-started-step-by-step` 一节查看如何快速设置开发环境，将应用程序烧录至 ESP32-S2-DevKitM-1。 - -.. 注解:: - - ESP32-S2 系列芯片仅支持 ESP-IDF master 分支或 v4.2 以上版本。 - - -硬件参考 -======== - -功能框图 --------- - -ESP32-S2-DevKitM-1 的主要组件和连接方式如下图所示。 - -.. figure:: ../../../_static/esp32-s2-devkitm-1-v1-block-diagram.png - :align: center - :scale: 70% - :alt: ESP32-S2-DevKitM-1 （点击放大） - :figclass: align-center - - ESP32-S2-DevKitM-1 （点击放大） - - -电源选项 -^^^^^^^^ - -以下任一供电方式均可给 ESP32-S2-DevKitM-1 供电： - -- Micro-USB 接口供电（默认） -- 5V 和 GND 排针供电 -- 3V3 和 GND 排针供电 - -建议选择第一种供电方式：micro USB 接口供电。 - - -.. _user-guide-devkitm-1-v1-header-blocks: - -排针 ----- - -下表列出了开发板两侧排针（J1 和 J3）的 **名称** 和 **功能**，排针的名称如图 :ref:`user-guide-devkitm-1-v1-board-front` 所示，排针的序号与 `ESP32-S2-DevKitM-1 原理图 `_ (PDF) 一致。 - - -J1 -^^^ - -==== ==== ========= ========================================================================= -序号 名称 类型 [#]_ 功能 -==== ==== ========= ========================================================================= -1 3V3 P 3.3 V 电源 -2 0 I/O/T RTC_GPIO0, GPIO0 -3 1 I/O/T RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0 -4 2 I/O/T RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1 -5 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 -6 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 -7 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 -8 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 -9 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 -10 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 -11 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD -12 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 -13 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 -14 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 -15 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 -16 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS -17 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P -18 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N -19 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 -20 5V P 5 V 电源 -21 G G 接地 -==== ==== ========= ========================================================================= - - -J3 -^^^ - -==== ==== ===== ======================================================== -序号 名称 类型 功能 -==== ==== ===== ======================================================== -1 G G 接地 -2 RST I CHIP_PU -3 46 I GPIO46 -4 45 I/O/T GPIO45 -5 RX I/O/T U0RXD, GPIO44, CLK_OUT2 -6 TX I/O/T U0TXD, GPIO43, CLK_OUT1 -7 42 I/O/T MTMS, GPIO42 -8 41 I/O/T MTDI, GPIO41, CLK_OUT1 -9 40 I/O/T MTDO, GPIO40, CLK_OUT2 -10 39 I/O/T MTCK, GPIO39, CLK_OUT3 -11 38 I/O/T GPIO38, FSPIWP -12 37 I/O/T SPIDQS, GPIO37, FSPIQ -13 36 I/O/T SPIIO7, GPIO36, FSPICLK -14 35 I/O/T SPIIO6, GPIO35, FSPID -15 34 I/O/T SPIIO5, GPIO34, FSPICS0 -16 33 I/O/T SPIIO4, GPIO33, FSPIHD -17 26 I/O/T SPICS1, GPIO26 -18 21 I/O/T RTC_GPIO21, GPIO21 -19 20 I/O/T RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+ -20 19 I/O/T RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D- -21 18 I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED -==== ==== ===== ======================================================== - -.. [#] P：电源；I：输入；O：输出；T：可设置为高阻。 - - -管脚布局 -^^^^^^^^ - -.. figure:: ../../../_static/esp32-s2-devkitm-1-v1-pin-layout.png - :align: center - :scale: 15% - :alt: ESP32-S2-DevKitM-1 管脚布局（点击放大） - :figclass: align-center - - ESP32-S2-DevKitM-1 管脚布局（点击放大） - - -硬件版本 -========== - -无历史版本。 - - -相关文档 -======== - -* `ESP32-S2 系列芯片 v1.0 版本技术规格书`_ (PDF) -* `ESP32-S2 系列芯片 v0.0 版本技术规格书 `_ (PDF) -* `《ESP32-S2 系列芯片勘误表》`_ (PDF) -* `《ESP32-S2-MINI-2 & ESP32-S2-MINI-2U 技术规格书》 `_ (PDF) -* `《ESP32-S2-MINI-1 & ESP32-S2-MINI-1U 技术规格书》 `_ (PDF) -* `ESP32-S2-DevKitM-1 原理图 `_ (PDF) -* `ESP32-S2-DevKitM-1 PCB 布局 `_ (PDF) -* `ESP32-S2-DevKitM-1 尺寸图 `_ (PDF) -* `乐鑫产品选型工具 `__ - -有关本开发板的更多设计文档，请联系我们的商务部门 `sales@espressif.com `_。 - -.. _不推荐用于新设计: https://www.espressif.com/zh-hans/products/longevity-commitment -.. _ESP32-S2 系列芯片 v1.0 版本技术规格书: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_cn.pdf -.. _《ESP32-S2 系列芯片勘误表》: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_cn.pdf diff --git a/docs/zh_CN/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst b/docs/zh_CN/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst deleted file mode 100644 index 117a7a742525..000000000000 --- a/docs/zh_CN/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst +++ /dev/null @@ -1,313 +0,0 @@ -================== -ESP32-S2-DevKitC-1 -================== - -:link_to_translation:`en: [English]` - -本指南将帮助你快速上手 ESP32-S2-DevKitC-1，并提供该款开发板的详细信息。 - -ESP32-S2-DevKitC-1 是一款入门级开发板，具备完整的 Wi-Fi 功能。板上模组大部分管脚均已引出至两侧排针，开发人员可根据实际需求，轻松通过跳线连接多种外围设备，同时也可将开发板插在面包板上使用。 - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-isometric.png - :align: center - :alt: ESP32-S2-DevKitC-1（板载 ESP32-S2-SOLO 模组） - :figclass: align-center - - ESP32-S2-DevKitC-1（板载 ESP32-S2-SOLO 模组） - -本指南包括如下内容： - -- `入门指南`_：简要介绍了 ESP32-S2-DevKitC-1 和硬件、软件设置指南。 -- `硬件参考`_：详细介绍了 ESP32-S2-DevKitC-1 的硬件。 -- `硬件版本`_：介绍硬件历史版本和已知问题，并提供链接至历史版本开发板的入门指南（如有）。 -- `相关文档`_：列出了相关文档的链接。 - - -入门指南 -======== - -本小节将简要介绍 ESP32-S2-DevKitC-1，说明如何在 ESP32-S2-DevKitC-1 上烧录固件及相关准备工作。 - - -组件介绍 --------- - -.. _user-guide-s2-devkitc-1-v1-board-front: - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-annotated-photo.png - :align: center - :alt: ESP32-S2-DevKitC-1 - 正面 - :figclass: align-center - - ESP32-S2-DevKitC-1 - 正面 - -以下按照顺时针的顺序依次介绍开发板上的主要组件。 - -.. list-table:: - :widths: 30 70 - :header-rows: 1 - - * - 主要组件 - - 介绍 - * - 板载模组（上图中为 ESP32-S2-SOLO 或 ESP32-S2-SOLO-U） - - ESP32-S2-SOLO 系列模组，可搭载 PCB 板载天线或外部天线连接器，支持多种 flash 和 PSRAM 大小。更多信息，详见 :ref:`user-guide-s2-devkitc-1-v1-ordering-info`。 - * - 3.3 V Power On LED（3.3 V 电源指示灯） - - 开发板连接 USB 电源后，该指示灯亮起。 - * - USB-to-UART Bridge（USB 转 UART 桥接器） - - 单芯片 USB 转 UART 桥接器，可提供高达 3 Mbps 的传输速率。 - * - Pin Headers（排针） - - 所有可用 GPIO 管脚（除 flash 的 SPI 总线）均已引出至开发板的排针。请查看 :ref:`user-guide-s2-devkitc-1-v1-header-blocks` 获取更多信息。 - * - ESP32-S2 USB Port（ESP32-S2 USB 接口） - - ESP32-S2 USB OTG 接口，支持全速 USB 1.1 标准。该接口可用作开发板的供电接口，可烧录固件至芯片，也可通过 USB 协议与芯片通信。 - * - Reset Button（Reset 键） - - 复位按键。 - * - Boot Button（Boot 键） - - 下载按键。按住 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件。 - * - USB-to-UART Port（USB 转 UART 接口） - - Micro-USB 接口，可用作开发板的供电接口，可烧录固件至芯片，也可作为通信接口，通过板载 USB 转 UART 桥接器与 ESP32-S2 芯片通信。 - * - RGB LED - - 可寻址 RGB 发光二极管，由 GPIO18 驱动。 - * - 5 V to 3.3 V LDO（5 V 转 3.3 V LDO） - - 电源转换器，输入 5 V，输出 3.3 V。 - - -开始开发应用 ------------- - -通电前，请确保 ESP32-S2-DevKitC-1 完好无损。 - - -必备硬件 -^^^^^^^^ - -- ESP32-S2-DevKitC-1 -- USB 2.0 数据线（标准 A 型转 Micro-B 型） -- 电脑（Windows、Linux 或 macOS） - -.. 注解:: - - 请确保使用适当的 USB 数据线。部分数据线仅可用于充电，无法用于数据传输和编程。 - - -硬件设置 -^^^^^^^^ - -通过 **USB 转 UART 接口** 或 **ESP32-S2 USB 接口** 连接开发板与电脑。在后续步骤中，默认使用 **USB 转 UART 接口**。 - - -软件设置 -^^^^^^^^ - -请前往 `ESP-IDF 快速入门 `_，在 `详细安装步骤 `_ 小节查看如何快速设置开发环境，将应用程序烧录至 ESP32-S2-DevKitC-1。 - - -内含组件和包装 --------------- - -.. _user-guide-s2-devkitc-1-v1-ordering-info: - -订购信息 -^^^^^^^^ - -该开发板有多种型号可供选择，详见下表。 - -.. list-table:: - :header-rows: 1 - :widths: 35 25 10 10 20 - - * - 订购代码 - - 搭载模组 [#]_ - - Flash - - PSRAM - - 天线 - * - ESP32-S2-DevKitC-1-N8R2 - - ESP32-S2-SOLO-2 - - （推荐） - - 8 MB - - 2 MB - - PCB 板载天线 - * - ESP32-S2-DevKitC-1U-N8R2 - - ESP32-S2-SOLO-2U - - （推荐） - - 8 MB - - 2 MB - - 外部天线连接器 - * - ESP32-S2-DevKitC-1 - - ESP32-S2-SOLO - - 4 MB - - --- - - PCB 板载天线 - * - ESP32-S2-DevKitC-1U - - ESP32-S2-SOLO-U - - 4 MB - - --- - - 外部天线连接器 - * - ESP32-S2-DevKitC-1R - - ESP32-S2-SOLO - - 4 MB - - 2 MB - - PCB 板载天线 - * - ESP32-S2-DevKitC-1RU - - ESP32-S2-SOLO-U - - 4 MB - - 2 MB - - 外部天线连接器 - -.. [#] ESP32-S2-SOLO-2 和 ESP32-S2-SOLO-2U 模组使用 v1.0 版本芯片，其余模组使用 v0.0 版本芯片。更多关于芯片版本的信息，请参考 `《ESP32-S2 系列芯片勘误表》`_。 - - -零售订单 -^^^^^^^^ - -如购买样品，每个 ESP32-S2-DevKitC-1 将以防静电袋或零售商选择的其他方式包装。 - -零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。 - - -批量订单 -^^^^^^^^ - -如批量购买，ESP32-S2-DevKitC-1 将以大纸板箱包装。 - -批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。 - - -硬件参考 -======== - -功能框图 --------- - -ESP32-S2-DevKitC-1 的主要组件和连接方式如下图所示。 - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-block-diags.png - :align: center - :scale: 70% - :alt: ESP32-S2-DevKitC-1（点击放大） - :figclass: align-center - - ESP32-S2-DevKitC-1（点击放大） - - -电源选项 -^^^^^^^^ - -以下任一供电方式均可给 ESP32-S2-DevKitC-1 供电： - -- USB 转 UART 接口供电或 ESP32-S2 USB 接口供电（选择其一或同时供电），默认供电方式（推荐） -- 5V 和 G (GND) 排针供电 -- 3V3 和 G (GND) 排针供电 - - -.. _user-guide-s2-devkitc-1-v1-header-blocks: - -排针 ----- - -下表列出了开发板两侧排针（J1 和 J3）的 **名称** 和 **功能**，排针的名称如图 :ref:`user-guide-s2-devkitc-1-v1-board-front` 所示，排针的序号与 `ESP32-S2-DevKitC-1 原理图`_ (PDF) 一致。 - - -J1 -^^^ - -==== ========= ========= ========================================================================= -序号 名称 类型 [#]_ 功能 -==== ========= ========= ========================================================================= -1 3V3 P 3.3 V 电源 -2 3V3 P 3.3 V 电源 -3 RST I CHIP_PU -4 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 -5 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 -6 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 -7 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 -8 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P -9 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N -10 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 -11 18 [#]_ I/O/T RTC_GPIO18, GPIO18[#]_, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED -12 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 -13 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 -14 46 I GPIO46 -15 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD -16 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 -17 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 -18 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 -19 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 -20 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS -21 5V P 5 V 电源 -22 G G 接地 -==== ========= ========= ========================================================================= - - -J3 -^^^ - -==== ==== ===== ================================================================ -序号 名称 类型 功能 -==== ==== ===== ================================================================ -1 G G 接地 -2 TX I/O/T U0TXD, GPIO43, CLK_OUT1 -3 RX I/O/T U0RXD, GPIO44, CLK_OUT2 -4 1 I/O/T RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0 -5 2 I/O/T RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1 -6 42 I/O/T MTMS, GPIO42 -7 41 I/O/T MTDI, GPIO41, CLK_OUT1 -8 40 I/O/T MTDO, GPIO40, CLK_OUT2 -9 39 I/O/T MTCK, GPIO39, CLK_OUT3 -10 38 I/O/T GPIO38, FSPIWP -11 37 I/O/T SPIDQS, GPIO37, FSPIQ -12 36 I/O/T SPIIO7, GPIO36, FSPICLK -13 35 I/O/T SPIIO6, GPIO35, FSPID -14 0 I/O/T RTC_GPIO0, GPIO0 -15 45 I/O/T GPIO45 -16 34 I/O/T SPIIO5, GPIO34, FSPICS0 -17 33 I/O/T SPIIO4, GPIO33, FSPIHD -18 21 I/O/T RTC_GPIO21, GPIO21 -19 20 I/O/T RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+ -20 19 I/O/T RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D- -21 G G 接地 -22 G G 接地 -==== ==== ===== ================================================================ - -.. [#] P：电源；I：输入；O：输出；T：可设置为高阻。 -.. [#] 搭载 ESP32-S2-SOLO-2 或 ESP32-S2-SOLO-2U 的开发板未上拉 GPIO18。 - - -管脚布局 -^^^^^^^^ - -.. figure:: ../../../_static/esp32-s2-devkitc-1-v1-pinout.png - :align: center - :scale: 45% - :alt: ESP32-S2-DevKitC-1 管脚布局（点击放大） - :figclass: align-center - - ESP32-S2-DevKitC-1 管脚布局（点击放大） - - -硬件版本 -========== - -无历史版本。 - - -相关文档 -======== - -* `ESP32-S2 系列芯片 v1.0 版本技术规格书`_ (PDF) -* `ESP32-S2 系列芯片 v0.0 版本技术规格书 `_ (PDF) -* `《ESP32-S2 系列芯片勘误表》`_ (PDF) -* `《ESP32-S2-SOLO-2 & ESP32-S2-SOLO-2U 模组技术规格书》 `_ (PDF) -* `《ESP32-S2-SOLO & ESP32-S2-SOLO-U 模组技术规格书》 `_ (PDF) -* `ESP32-S2-DevKitC-1 原理图`_ (PDF) -* `ESP32-S2-DevKitC-1 PCB 布局图 `_ (PDF) -* `ESP32-S2-DevKitC-1 尺寸图 `_ (PDF) -* `ESP32-S2-DevKitC-1 尺寸图源文件 `_ (DXF) - 可使用 `Autodesk Viewer `_ 查看 - -有关本开发板的更多设计文档，请联系我们的商务部门 `sales@espressif.com `_。 - -.. _不推荐用于新设计: https://www.espressif.com/zh-hans/products/longevity-commitment -.. _ESP32-S2 系列芯片 v1.0 版本技术规格书: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_cn.pdf -.. _《ESP32-S2 系列芯片勘误表》: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_cn.pdf -.. _ESP32-S2-DevKitC-1 原理图: https://dl.espressif.com/dl/schematics/esp-idf/SCH_ESP32-S2-DEVKITC-1_V1_20220817.pdf diff --git a/docs/zh_CN/security/index.rst b/docs/zh_CN/security/index.rst index 846dace5d517..8a179acefca4 100644 --- a/docs/zh_CN/security/index.rst +++ b/docs/zh_CN/security/index.rst @@ -26,3 +26,9 @@ host-based-security-workflows +漏洞 +--------- +.. toctree:: + :maxdepth: 1 + + vulnerabilities diff --git a/docs/zh_CN/security/secure-boot-v2.rst b/docs/zh_CN/security/secure-boot-v2.rst index adeb24204a12..83e53013d7f3 100644 --- a/docs/zh_CN/security/secure-boot-v2.rst +++ b/docs/zh_CN/security/secure-boot-v2.rst @@ -13,11 +13,11 @@ {IDF_TARGET_ECO_VERSION:default="", esp32="（v3.0 及以上版本）", esp32c3="（v3.0 及以上版本）"} -{IDF_TARGET_RSA_TIME:default="", esp32c6="约 2.7 ms", esp32h2="约 4.5 ms"} +{IDF_TARGET_RSA_TIME:default="", esp32c6="约 2.7 ms", esp32h2="约 4.5 ms", esp32p4="约 2.4 ms"} -{IDF_TARGET_ECDSA_TIME:default="", esp32c6="约 21.5 ms", esp32h2="约 36 ms"} +{IDF_TARGET_ECDSA_TIME:default="", esp32c6="约 21.5 ms", esp32h2="约 36 ms", esp32p4="约 10.3 ms"} -{IDF_TARGET_CPU_FREQ:default="", esp32c6="160 MHz", esp32h2="96 MHz"} +{IDF_TARGET_CPU_FREQ:default="", esp32c6="160 MHz", esp32h2="96 MHz", esp32p4="360 MHz"} {IDF_TARGET_SBV2_DEFAULT_SCHEME:default="RSA", esp32c2="ECDSA (v2)"} diff --git a/docs/zh_CN/security/vulnerabilities.rst b/docs/zh_CN/security/vulnerabilities.rst new file mode 100644 index 000000000000..a63494ff42cd --- /dev/null +++ b/docs/zh_CN/security/vulnerabilities.rst @@ -0,0 +1 @@ +.. include:: ../../en/security/vulnerabilities.rst diff --git a/examples/bluetooth/nimble/power_save/README.md b/examples/bluetooth/nimble/power_save/README.md index bfad7b536ddf..048de15e2576 100644 --- a/examples/bluetooth/nimble/power_save/README.md +++ b/examples/bluetooth/nimble/power_save/README.md @@ -140,4 +140,5 @@ X: This feature is currently not supported. - ESP32 does not support the use of main XTAL in light sleep mode, so an external 32kHz crystal is required. - ESP32C2 support XTAL frequency of 26MHz and 40MHz, the XTAL frequency is set to 26MHz in default. -- ESP32C2 support external 32kHz crystal by connecting the crystal to the chip through pin0 \ No newline at end of file +- ESP32C2 support external 32kHz crystal by connecting the crystal to the chip through pin0 +- ESP32C6 REQUIRES CONFIG_ESP_PHY_MAC_BB_PD to be set for light sleep to run properly \ No newline at end of file diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 16a6e4fc8295..6949eafd2062 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -256,20 +256,12 @@ examples/peripherals/mcpwm/mcpwm_sync: examples/peripherals/parlio: disable: - if: SOC_PARLIO_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: lack of runner depends_components: - esp_driver_parlio examples/peripherals/parlio/parlio_rx: disable: - if: SOC_PARLIO_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: lack of runner depends_components: - esp_driver_parlio diff --git a/examples/peripherals/i2c/i2c_eeprom/README.md b/examples/peripherals/i2c/i2c_eeprom/README.md index ee701ba71433..6132f3446cc6 100644 --- a/examples/peripherals/i2c/i2c_eeprom/README.md +++ b/examples/peripherals/i2c/i2c_eeprom/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # I2C EEPROM example diff --git a/examples/peripherals/i2c/i2c_tools/README.md b/examples/peripherals/i2c/i2c_tools/README.md index 84d1595edb27..d72d84901fb3 100644 --- a/examples/peripherals/i2c/i2c_tools/README.md +++ b/examples/peripherals/i2c/i2c_tools/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # I2C Tools Example diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md index 00f001896c27..b3b26f69ebde 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # I2S TDM Example -- ES7210 4-Ch ADC Codec diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md index 7bd46beba262..0ab480ffb284 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # I2S ES8311 Example diff --git a/examples/peripherals/lcd/i2c_oled/README.md b/examples/peripherals/lcd/i2c_oled/README.md index 9269489ef534..90503cf7c647 100644 --- a/examples/peripherals/lcd/i2c_oled/README.md +++ b/examples/peripherals/lcd/i2c_oled/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # I2C OLED example diff --git a/examples/peripherals/parlio/parlio_rx/logic_analyzer/README.md b/examples/peripherals/parlio/parlio_rx/logic_analyzer/README.md index 1881bdf2238c..2f7fed8c938c 100644 --- a/examples/peripherals/parlio/parlio_rx/logic_analyzer/README.md +++ b/examples/peripherals/parlio/parlio_rx/logic_analyzer/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | -------- | # Logic Analyzer Example diff --git a/examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py b/examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py new file mode 100644 index 000000000000..270d0dc4d4b6 --- /dev/null +++ b/examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py @@ -0,0 +1,22 @@ +# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32c6 +@pytest.mark.esp32h2 +@pytest.mark.esp32p4 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'flash_stream', + ], + indirect=True, +) +def test_logic_analyzer_flash_stream(dut: Dut) -> None: + dut.expect(r'flash_fat: Probe data partition base addr: \w+ size: \w+') + dut.expect(r'flash_fat: flash FATFS mounted') + dut.expect(r'esp_probe: Dump data size reached the max dump size') + dut.expect(r'example: Probe finished! [0-9]+ \(\w+\) bytes dumped') diff --git a/examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream b/examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream new file mode 100644 index 000000000000..4149416a65fd --- /dev/null +++ b/examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream @@ -0,0 +1 @@ +CONFIG_EXAMPLE_FLASH_STREAM=y diff --git a/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/README.md b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/README.md index ce33f425ea6d..a17b3b57abe1 100644 --- a/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/README.md +++ b/examples/peripherals/usb_serial_jtag/usb_serial_jtag_echo/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # USB SERIAL JTAG Echo Example diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index b8668629a8ac..2e9ebc5bbd4e 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -77,7 +77,16 @@ examples/system/flash_suspend: temporary: true reason: the other targets are not tested yet -examples/system/freertos: +examples/system/freertos/basic_freertos_smp_usage: + enable: + - if: IDF_TARGET == "esp32c3" or IDF_TARGET == "esp32s3" + reason: no target specific functionality, testing on a single core target and a multiple core target is sufficient + depends_components: + - freertos + - console + - esp_timer + +examples/system/freertos/real_time_stats: disable: - if: IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux") reason: no target specific functionality, testing on a single target is sufficient @@ -259,13 +268,14 @@ examples/system/task_watchdog: examples/system/ulp/lp_core/gpio: enable: - - if: SOC_LP_CORE_SUPPORTED == 1 + - if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_RTCIO_PIN_COUNT > 0) + depends_components: - ulp examples/system/ulp/lp_core/gpio_intr_pulse_counter: enable: - - if: SOC_LP_CORE_SUPPORTED == 1 + - if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_ULP_LP_UART_SUPPORTED == 1) depends_components: - ulp diff --git a/examples/system/deep_sleep/README.md b/examples/system/deep_sleep/README.md index 1d6129b5bed9..681fc586540d 100644 --- a/examples/system/deep_sleep/README.md +++ b/examples/system/deep_sleep/README.md @@ -19,7 +19,7 @@ Note: Some wake up sources can be disabled via configuration (see section on [pr Warning: On ESP32, touch wake up source cannot be used together with EXT0 wake up source. If they co-exist, IDF will give a runtime error and the program will crash. By default in this example, touch wake up is enabled, and the other two are disabled. You can switch to enable the other wake up sources via menuconfig. -In this example, the `CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` Kconfig option is used, which allows you to reduce the boot time of the bootloader during waking up from deep sleep. The bootloader stores in rtc memory the address of a running partition and uses it when it wakes up. This example allows you to skip all image checks and speed up the boot. +In this example, the `CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` Kconfig option is used, which allows you to reduce the boot time of the bootloader during waking up from deep sleep. The bootloader stores in RTC memory the address of a running partition and uses it when it wakes up (ESP32-C2 does not have RTC memory, so a running partition cannot be saved there, instead the partition table is read to select an application). This example allows you to skip all image checks and speed up the boot. ## How to use example diff --git a/examples/system/deep_sleep/partitions.csv b/examples/system/deep_sleep/partitions.csv new file mode 100644 index 000000000000..a48d23ea2e7d --- /dev/null +++ b/examples/system/deep_sleep/partitions.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, , 0x4000, +otadata, data, ota, , 0x2000, +factory, app, factory, , 600K, +ota_0, app, ota_0, , 600K, +ota_1, app, ota_1, , 600K, diff --git a/examples/system/deep_sleep/pytest_deep_sleep.py b/examples/system/deep_sleep/pytest_deep_sleep.py index 883dd2f89bb4..a026e16def3a 100644 --- a/examples/system/deep_sleep/pytest_deep_sleep.py +++ b/examples/system/deep_sleep/pytest_deep_sleep.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import logging import time @@ -67,11 +67,7 @@ def expect_enable_deep_sleep_no_touch() -> None: logging.info('Host measured sleep time at {:.2f}s'.format(sleep_time)) assert 18 < sleep_time < 22 # note: high tolerance as measuring time on the host may have some timing skew - # This line indicates that the CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP option set in sdkconfig.defaults - # has correctly allowed skipping verification on wakeup - # Note: this feature depends on rtc mem - if dut.app.sdkconfig.get('SOC_RTC_MEM_SUPPORTED') is True: - dut.expect_exact('boot: Fast booting app from partition', timeout=2) + dut.expect_exact('boot: Fast booting app from partition', timeout=2) # Check that it measured 2xxxxms in deep sleep, i.e at least 20 seconds: expect_enable_deep_sleep() diff --git a/examples/system/deep_sleep/sdkconfig.ci.basic b/examples/system/deep_sleep/sdkconfig.ci.basic index 6aa89f368a23..87020672f4c0 100644 --- a/examples/system/deep_sleep/sdkconfig.ci.basic +++ b/examples/system/deep_sleep/sdkconfig.ci.basic @@ -8,3 +8,4 @@ CONFIG_ULP_COPROC_ENABLED=y CONFIG_ULP_COPROC_RESERVE_MEM=512 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y CONFIG_RTC_CLK_SRC_INT_RC=y +CONFIG_PARTITION_TABLE_CUSTOM=y diff --git a/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore b/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore index d4587def0fd2..0cabcb5f0277 100644 --- a/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore +++ b/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore @@ -13,3 +13,4 @@ CONFIG_ULP_COPROC_ENABLED=y CONFIG_ULP_COPROC_RESERVE_MEM=512 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y CONFIG_RTC_CLK_SRC_INT_RC=y +CONFIG_PARTITION_TABLE_CUSTOM=y diff --git a/examples/system/deep_sleep/sdkconfig.defaults b/examples/system/deep_sleep/sdkconfig.defaults index 9f61a9a651e9..b508ab21b76f 100644 --- a/examples/system/deep_sleep/sdkconfig.defaults +++ b/examples/system/deep_sleep/sdkconfig.defaults @@ -5,3 +5,4 @@ CONFIG_ULP_COPROC_RESERVE_MEM=512 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y CONFIG_RTC_CLK_SRC_INT_RC=y CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y +CONFIG_PARTITION_TABLE_CUSTOM=y diff --git a/examples/system/freertos/basic_freertos_smp_usage/CMakeLists.txt b/examples/system/freertos/basic_freertos_smp_usage/CMakeLists.txt new file mode 100644 index 000000000000..6d220730a254 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/CMakeLists.txt @@ -0,0 +1,8 @@ +# For more information about build system see +# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(basic_freertos_smp_usage) diff --git a/examples/system/freertos/basic_freertos_smp_usage/README.md b/examples/system/freertos/basic_freertos_smp_usage/README.md new file mode 100644 index 000000000000..43c593aa431d --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/README.md @@ -0,0 +1,204 @@ +| Supported Targets | ESP32-C3 | ESP32-S3 | +| ----------------- | -------- | -------- | + +# FreeRTOS basic API SMP usages Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +FreeRTOS offers a rich array of communication objects and task notification mechanisms that facilitate interaction and synchronization between concurrent tasks. This example demonstrates the applications of some useful APIs, including task creation, queue, mutex / spinlock, and task notification, within the context of a Symmetric Multiprocessor (SMP) architecture. + +## Contents of this example +Below is short explanation of remaining files in the project folder. + +``` +├── CMakeLists.txt +├── main +│   ├── CMakeLists.txt +│   ├── basic_freertos_smp_usage.h +│   ├── basic_freertos_smp_usage.c +│   ├── create_task_example.c +│   ├── queue_example.c +│   ├── lock_example.c +│   ├── task_notify_example.c +│   └── batch_processing_example.c +├── pytest_smp_examples.py +└── README.md This is the file you are currently reading +``` + +This example includes 5 parts: + +### Creating task example + +The first part is shows how to create tasks that can be pinned (affinity with a specific core) or unpinned (no particular affinity with any core) on ESP32 series CPU cores thanks to the API function `xTaskCreatePinnedToCore()`. + +In this case, there are 4 tasks created in total: +* `pinned_task0_core0` task is created and pinned on core 0 +* `pinned_task1_core0` task is also created and pinned on core 0 +* `pinned_task2_core1` task is created and pinned on core 1 +* `unpinned_task` task is the last one, it is unpinned, which means it can be scheduled to run on any core. + +A task can be unpinned by setting the `xCoreID` field to `tskNO_AFFINITY` when calling `xTaskCreatePinnedToCore()`. + + +#### Example Output +In the task function, the API `esp_cpu_get_core_id()` is called to query on which core this task is currently running. The example should have the following console output that, "pinned_task0_core0" and "pinned_task1_core0" are running on core#0, while "pinned_task2_core1" is running on core#1, and "unpinned_task" can be running on both core#0 and core#1: + +``` +... +I (2123) create task example: task#0 is running on core#0 +I (2133) create task example: task#1 is running on core#0 +I (2133) create task example: task#2 is running on core#1 +I (2153) create task example: task#3 is running on core#0 +I (2283) create task example: task#0 is running on core#0 +I (2293) create task example: task#1 is running on core#0 +I (2313) create task example: task#2 is running on core#1 +I (2323) create task example: task#3 is running on core#0 +I (2453) create task example: task#0 is running on core#0 +I (2463) create task example: task#1 is running on core#0 +I (2483) create task example: task#3 is running on core#0 +I (2483) create task example: task#2 is running on core#1 +I (2623) create task example: task#0 is running on core#0 +I (2633) create task example: task#1 is running on core#0 +I (2643) create task example: task#3 is running on core#0 +I (2653) create task example: task#2 is running on core#1 +I (2793) create task example: task#0 is running on core#0 +I (2803) create task example: task#1 is running on core#0 +I (2803) create task example: task#3 is running on core#1 +... + +``` + +### Queue communication example +The second part is about how to use FreeRTOS built-in queue to transmit data between tasks. In this example, one task is sending a number every 250 millisecond to a msg queue by calling API `xQueueGenericSend()`, and another task receives data from this queue by calling API `xQueueReceive()` + +#### Example Output +The example should have the following console output: + +``` +I (1737813) queue example: sent data = 0 +I (1737813) queue example: received data = 0 +I (1738063) queue example: sent data = 1 +I (1738063) queue example: received data = 1 +I (1738313) queue example: sent data = 2 +I (1738313) queue example: received data = 2 +I (1738563) queue example: sent data = 3 +I (1738563) queue example: received data = 3 +I (1738813) queue example: sent data = 4 +I (1738813) queue example: received data = 4 +I (1739063) queue example: sent data = 5 +I (1739063) queue example: received data = 5 +I (1739313) queue example: sent data = 6 +I (1739313) queue example: received data = 6 +I (1739563) queue example: sent data = 7 +I (1739563) queue example: received data = 7 +I (1739813) queue example: sent data = 8 +I (1739813) queue example: received data = 8 +I (1740063) queue example: sent data = 9 +I (1740063) queue example: received data = 9 +I (1740313) queue example: sent data = 10 +I (1740313) queue example: received data = 10 +... +``` + +### Locks example +In the third part, a simple comparison of performance between mutexes, spinlocks and atomic operations is presented, along with an instance of how to use mutexes as a mechanism for protecting shared resources. + +To highlight the differences in performance between mutexes, spinlocks and atomic operations, this example implements two tasks that share a resource, which will be protected by mutex and spinlock and declared as an atomic type variable, respectively. Note: if this example runs on single core, only 1 task of each type will be created. + +The result illustrates that the spinlocks are faster because they don't trigger any context switch, but they are CPU-intensive. Using atomic operation is faster than using spinlock, because it doesn't involve entering and exiting critical sections. + +#### Example Output +The example should have the following console output: +``` +I (5025) lock example: mutex task took 1562156 us on core1 +I (5025) lock example: mutex task took 1567546 us on core0 +I (7095) lock example: spinlock task took 73325 us on core0 +I (7095) lock example: spinlock task took 68326 us on core1 +I (9105) lock example: atomic task took 11806 us on core0 +I (9105) lock example: atomic task took 6810 us on core1 +I (10105) lock example: mutex task 0 created +I (10105) lock example: task0 read value = 0 on core #0 +I (10105) lock example: mutex task 1 created +I (10605) lock example: task0 set value = 1 +I (10605) lock example: task1 read value = 1 on core #1 +I (11105) lock example: task1 set value = 2 +I (11105) lock example: task0 read value = 2 on core #1 +I (11605) lock example: task0 set value = 3 +I (11605) lock example: task1 read value = 3 on core #1 +I (12105) lock example: task1 set value = 4 +I (12105) lock example: task0 read value = 4 on core #1 +I (12605) lock example: task0 set value = 5 +I (12605) lock example: task1 read value = 5 on core #1 +I (13105) lock example: task1 set value = 6 +... +``` + +### Task notification example +Two tasks communicate via FreeRTOS task notification systems: one is sending notifications while the other receives them. + +#### Example Output +The example should have the following console output: +``` +I (392163) task notify example: send_task sends a notification +I (392163) task notify example: 1 tasks pending +I (392163) task notify example: rcv_task is processing this task notification +I (393163) task notify example: send_task sends a notification +I (393163) task notify example: 1 tasks pending +I (393163) task notify example: rcv_task is processing this task notification +I (394163) task notify example: send_task sends a notification +I (394163) task notify example: 1 tasks pending +I (394163) task notify example: rcv_task is processing this task notification +I (395163) task notify example: send_task sends a notification +I (395163) task notify example: 1 tasks pending +I (395163) task notify example: rcv_task is processing this task notification +I (396163) task notify example: send_task sends a notification +I (396163) task notify example: 1 tasks pending +I (396163) task notify example: rcv_task is processing this task notification +... +``` + +### Batch processing example +In the last part, a practical demonstration is provided wherein queues, mutexes, and task notifications are integrated to implement a realistic workflow, thereby exemplifying their practical utility in real-world scenarios. + +A task named **rcv_data_task** mimics receiving the irregularly arrived data. Every time a data item is received, it is pushed into a queue, and the received item number is increased by 1; once the task collects 5 data items, it sends a task notification to the **proc_data_task** to process this batch of data from the queue. When the latter task finishes processing, it will decrease the received item number by 5. Because both these 2 tasks can modify this global number, the modification action is protected by a mutex. + +#### Example Output +The example should have the following console output: +``` +I (2675163) batch processing example: enqueue data = 43 +I (2675563) batch processing example: enqueue data = 29 +I (2676013) batch processing example: enqueue data = 8 +I (2676463) batch processing example: enqueue data = 56 +I (2676873) batch processing example: enqueue data = 19 +I (2676873) batch processing example: dequeue data = 43 +I (2676873) batch processing example: dequeue data = 29 +I (2676883) batch processing example: dequeue data = 8 +I (2676883) batch processing example: dequeue data = 56 +I (2676883) batch processing example: dequeue data = 19 +I (2676893) batch processing example: decrease s_rcv_item_num to 0 +I (2677413) batch processing example: enqueue data = 51 +I (2677713) batch processing example: enqueue data = 5 +I (2678243) batch processing example: enqueue data = 93 +I (2678603) batch processing example: enqueue data = 66 +I (2679213) batch processing example: enqueue data = 32 +I (2679213) batch processing example: dequeue data = 51 +I (2679213) batch processing example: dequeue data = 5 +I (2679223) batch processing example: dequeue data = 93 +I (2679223) batch processing example: dequeue data = 66 +I (2679233) batch processing example: dequeue data = 32 +I (2679233) batch processing example: decrease s_rcv_item_num to 0 +... +``` + +## How to use this example + +This example utilizes an interactive console component so that you can select the part you would like to run through the terminal. You can type 'help' to get the list of commands; use UP/DOWN arrows to navigate through command history; press TAB when typing command name to auto-complete. For more information on the interactive terminal console component, please refer to [console](../../console/README.md). The supported commands include: + +* **help**: get the list of commands +* **create_task**: run the creating task example +* **queue**: run the queue example +* **lock**: run the locks example +* **task_notification**: run the task notification example +* **batch_processing**: run the batch processing example + +Once a component starts running, it will be stopped in about 5 seconds. If you would like to extend the running time, please modify the value of macro **COMP_LOOP_PERIOD** in the header file inc.h. \ No newline at end of file diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/CMakeLists.txt b/examples/system/freertos/basic_freertos_smp_usage/main/CMakeLists.txt new file mode 100644 index 000000000000..eafe3a558220 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/CMakeLists.txt @@ -0,0 +1,9 @@ +set(srcs "basic_freertos_smp_usage.c" + "create_task_example.c" + "queue_example.c" + "lock_example.c" + "task_notify_example.c" + "batch_processing_example.c") +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS "." + PRIV_REQUIRES console esp_timer) diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/basic_freertos_smp_usage.c b/examples/system/freertos/basic_freertos_smp_usage/main/basic_freertos_smp_usage.c new file mode 100644 index 000000000000..d20016e1cd16 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/basic_freertos_smp_usage.c @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "esp_console.h" +#include "basic_freertos_smp_usage.h" +#include "sdkconfig.h" + + +static void register_creating_task(void) +{ + const esp_console_cmd_t creating_task_cmd = { + .command = "create_task", + .help = "Run the example that demonstrates how to create and run pinned and unpinned tasks", + .hint = NULL, + .func = &comp_creating_task_entry_func, + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&creating_task_cmd)); +} + +static void register_queue(void) +{ + const esp_console_cmd_t queue_cmd = { + .command = "queue", + .help = "Run the example that demonstrates how to use queue to communicate between tasks", + .hint = NULL, + .func = &comp_queue_entry_func, + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&queue_cmd)); +} + +static void register_lock(void) +{ + const esp_console_cmd_t lock_cmd = { + .command = "lock", + .help = "Run the example that demonstrates how to use mutex and spinlock to protect a shared resource", + .hint = NULL, + .func = &comp_lock_entry_func, + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&lock_cmd)); +} + +static void register_task_notification(void) +{ + const esp_console_cmd_t task_notification_cmd = { + .command = "task_notification", + .help = "Run the example that demonstrates how to use task notifications to synchronize tasks", + .hint = NULL, + .func = &comp_task_notification_entry_func, + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&task_notification_cmd)); +} + +static void register_batch_proc_example(void) +{ + const esp_console_cmd_t batch_proc_example_cmd = { + .command = "batch_processing", + .help = "Run the example that combines queue, mutex, task notification together", + .hint = NULL, + .func = &comp_batch_proc_example_entry_func, + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&batch_proc_example_cmd)); +} + +static void config_console(void) +{ + esp_console_repl_t *repl = NULL; + esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); + /* Prompt to be printed before each line. + * This can be customized, made dynamic, etc. + */ + repl_config.prompt = PROMPT_STR ">"; + repl_config.max_cmdline_length = 1024; + esp_console_dev_uart_config_t uart_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_console_new_repl_uart(&uart_config, &repl_config, &repl)); + + esp_console_register_help_command(); + + // register entry functions for each component + register_creating_task(); + register_queue(); + register_lock(); + register_task_notification(); + register_batch_proc_example(); + + ESP_ERROR_CHECK(esp_console_start_repl(repl)); + printf("\n" + "Please type the component you would like to run.\n"); +} + +void app_main(void) +{ + config_console(); +} diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/basic_freertos_smp_usage.h b/examples/system/freertos/basic_freertos_smp_usage/main/basic_freertos_smp_usage.h new file mode 100644 index 000000000000..4148de0ea161 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/basic_freertos_smp_usage.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +/*------------------------------------------------------------*/ +/* Macros */ +#define PROMPT_STR CONFIG_IDF_TARGET +#define TASK_PRIO_3 3 +#define TASK_PRIO_2 2 +#define COMP_LOOP_PERIOD 5000 +#define SEM_CREATE_ERR_STR "semaphore creation failed" +#define QUEUE_CREATE_ERR_STR "queue creation failed" + +int comp_creating_task_entry_func(int argc, char **argv); +int comp_queue_entry_func(int argc, char **argv); +int comp_lock_entry_func(int argc, char **argv); +int comp_task_notification_entry_func(int argc, char **argv); +int comp_batch_proc_example_entry_func(int argc, char **argv); diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/batch_processing_example.c b/examples/system/freertos/basic_freertos_smp_usage/main/batch_processing_example.c new file mode 100644 index 000000000000..1f3dfa80b3a8 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/batch_processing_example.c @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "freertos/FreeRTOS.h" +#include "esp_log.h" +#include "basic_freertos_smp_usage.h" + +#define DATA_BATCH_SIZE 5 + +// static TaskHandle_t proc_data_task_hdl; +static QueueHandle_t msg_queue; +static const uint8_t msg_queue_len = 10; +static SemaphoreHandle_t s_mutex; // mutex to protect shared resource "s_rcv_item_num" +static volatile int s_rcv_item_num; // received data item number +static volatile bool timed_out; +const static char *TAG = "batch processing example"; + + +/* This example describes a realistic scenario where there are 2 tasks, one of them receives irregularly arrived external data, +and the other task is responsible for processing the received data items. For some reason, every 5 data items form a batch +and they are meant to be processed together. Once the receiving data obtains a data item, it will increment a global variable +named s_rcv_item_num by 1, then push the data into a queue, of which the maximal size is 10; when s_rcv_item_num is not less +than 5, the receiving thread sends a task notification to the processing thread, which is blocked waiting for this signal to +proceed. Processing thread dequeues the first 5 data items from the queue and process them, and finally decrease the s_rcv_item_num by 5. +Please refer to README.md for more details. +*/ + +static void rcv_data_task(void *arg) +{ + int random_delay_ms; + int data; + TaskHandle_t proc_data_task_hdl = (TaskHandle_t)arg; + + while (!timed_out) { + // random delay to mimic this thread receives data irregularly + data = rand() % 100; + random_delay_ms = (rand() % 500 + 200); + vTaskDelay(random_delay_ms / portTICK_PERIOD_MS); + // increase receive item num by 1 + if (xSemaphoreTake(s_mutex, portMAX_DELAY) == pdTRUE) { + s_rcv_item_num += 1; + xSemaphoreGive(s_mutex); + } + // enqueue the received data + (void)xQueueGenericSend(msg_queue, (void *)&data, portMAX_DELAY, queueSEND_TO_BACK); + ESP_LOGI(TAG, "enqueue data = %d", data); + + // if s_rcv_item_num >= batch size, send task notification to proc thread to process them together + if (s_rcv_item_num >= DATA_BATCH_SIZE) { + xTaskNotifyGive(proc_data_task_hdl); + } + } + + vTaskDelete(NULL); +} + +static void proc_data_task(void *arg) +{ + int rcv_data_buffer[DATA_BATCH_SIZE] ; + int rcv_item_num; + int data_idx; + while (!timed_out) { + // blocking wait for task notification + while (ulTaskNotifyTake(pdFALSE, portMAX_DELAY)) { + // every time this task receives notification, reset received data item number + rcv_item_num = 0; + for (data_idx = 0; data_idx < DATA_BATCH_SIZE; data_idx++) { + // keep reading message queue until it's empty + if (xQueueReceive(msg_queue, (void *)&rcv_data_buffer[data_idx], 0) == pdTRUE) { + ESP_LOGI(TAG, "dequeue data = %d", rcv_data_buffer[data_idx]); + rcv_item_num += 1; + } else { + break; + } + } + + // mimic to process the data in buffer and then clean it + for (data_idx = 0; data_idx < rcv_item_num; data_idx++) { + rcv_data_buffer[data_idx] = 0; + } + + // decrease the s_rcv_item_num by batch size if it's not less the batch size, else set it as 0 + if (xSemaphoreTake(s_mutex, portMAX_DELAY) == pdTRUE) { + s_rcv_item_num -= rcv_item_num; + xSemaphoreGive(s_mutex); + ESP_LOGI(TAG, "decrease s_rcv_item_num to %d", s_rcv_item_num); + } + } + } + + vTaskDelete(NULL); +} + +// batch processing example: demonstrate how to use task notification to implement batch processing +// use queue to transmit data between tasks, and use mutex to protect a shared global number +int comp_batch_proc_example_entry_func(int argc, char **argv) +{ + timed_out = false; + + s_mutex = xSemaphoreCreateMutex(); + if (s_mutex == NULL) { + ESP_LOGE(TAG, SEM_CREATE_ERR_STR); + return 1; + } + msg_queue = xQueueGenericCreate(msg_queue_len, sizeof(int), queueQUEUE_TYPE_SET); + if (msg_queue == NULL) { + ESP_LOGE(TAG, QUEUE_CREATE_ERR_STR); + return 1; + } + TaskHandle_t proc_data_task_hdl; + xTaskCreatePinnedToCore(proc_data_task, "proc_data_task", 4096, NULL, TASK_PRIO_3, &proc_data_task_hdl, tskNO_AFFINITY); + xTaskCreatePinnedToCore(rcv_data_task, "rcv_data_task", 4096, proc_data_task_hdl, TASK_PRIO_3, NULL, tskNO_AFFINITY); + + // time out and stop running after COMP_LOOP_PERIOD milliseconds + vTaskDelay(pdMS_TO_TICKS(COMP_LOOP_PERIOD)); + timed_out = true; + // delay to let tasks finish the last loop + vTaskDelay(1500 / portTICK_PERIOD_MS); + return 0; +} diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/create_task_example.c b/examples/system/freertos/basic_freertos_smp_usage/main/create_task_example.c new file mode 100644 index 000000000000..5f49566f5709 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/create_task_example.c @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "freertos/FreeRTOS.h" +#include "esp_log.h" +#include "basic_freertos_smp_usage.h" + + +#define SPIN_ITER 350000 //actual CPU cycles consumed will depend on compiler optimization +#define CORE0 0 +// only define xCoreID CORE1 as 1 if this is a multiple core processor target, else define it as tskNO_AFFINITY +#define CORE1 ((CONFIG_FREERTOS_NUMBER_OF_CORES > 1) ? 1 : tskNO_AFFINITY) + + +static volatile bool timed_out; +const static char *TAG = "create task example"; + +static void spin_iteration(int spin_iter_num) +{ + for (int i = 0; i < spin_iter_num; i++) { + __asm__ __volatile__("NOP"); + } +} + +static void spin_task(void *arg) +{ + // convert arg pointer from void type to int type then dereference it + int task_id = (int)arg; + ESP_LOGI(TAG, "created task#%d", task_id); + while (!timed_out) { + int core_id = esp_cpu_get_core_id(); + ESP_LOGI(TAG, "task#%d is running on core#%d", task_id, core_id); + // consume some CPU cycles to keep Core#0 a little busy, so task3 has opportunity to be scheduled on Core#1 + spin_iteration(SPIN_ITER); + vTaskDelay(pdMS_TO_TICKS(150)); + } + + vTaskDelete(NULL); +} + +// Creating task example: show how to create pinned and unpinned tasks on CPU cores +int comp_creating_task_entry_func(int argc, char **argv) +{ + timed_out = false; + // pin 2 tasks on same core and observe in-turn execution, + // and pin another task on the other core to observe "simultaneous" execution + int task_id0 = 0, task_id1 = 1, task_id2 = 2, task_id3 = 3; + xTaskCreatePinnedToCore(spin_task, "pinned_task0_core0", 4096, (void*)task_id0, TASK_PRIO_3, NULL, CORE0); + xTaskCreatePinnedToCore(spin_task, "pinned_task1_core0", 4096, (void*)task_id1, TASK_PRIO_3, NULL, CORE0); + xTaskCreatePinnedToCore(spin_task, "pinned_task2_core1", 4096, (void*)task_id2, TASK_PRIO_3, NULL, CORE1); + // Create a unpinned task with xCoreID = tskNO_AFFINITY, which can be scheduled on any core, hopefully it can be observed that the scheduler moves the task between the different cores according to the workload + xTaskCreatePinnedToCore(spin_task, "unpinned_task", 4096, (void*)task_id3, TASK_PRIO_2, NULL, tskNO_AFFINITY); + + // time out and stop running after 5 seconds + vTaskDelay(pdMS_TO_TICKS(COMP_LOOP_PERIOD)); + timed_out = true; + // delay to let tasks finish the last loop + vTaskDelay(500 / portTICK_PERIOD_MS); + return 0; +} diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c b/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c new file mode 100644 index 000000000000..670b13edc120 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c @@ -0,0 +1,171 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include "freertos/FreeRTOS.h" +#include "esp_log.h" +#include "esp_timer.h" +#include "basic_freertos_smp_usage.h" + +#define SHARE_RES_THREAD_NUM 2 +#define ITERATION_NUMBER 100000 + + +// declare a static global integer as a protected shared resource that is accessible to multiple tasks +static volatile int s_global_num = 0; +static atomic_int s_atomic_global_num; +static SemaphoreHandle_t s_mutex; +static portMUX_TYPE s_spinlock = portMUX_INITIALIZER_UNLOCKED; +static volatile bool timed_out; +const static char *TAG = "lock example"; + +// Take a mutex to protect the shared resource. If mutex is already taken, this task will be blocked until it is available; +// when the mutex is available, FreeRTOS will reschedule this task and this task can further access the shared resource +static void inc_num_mutex_iter(void *arg) +{ + int core_id = esp_cpu_get_core_id(); + int64_t start_time, end_time, duration = 0; + start_time = esp_timer_get_time(); + while (s_global_num < ITERATION_NUMBER) { + if (xSemaphoreTake(s_mutex, portMAX_DELAY) == pdTRUE) { + s_global_num++; + xSemaphoreGive(s_mutex); + } + } + end_time = esp_timer_get_time(); + duration = end_time - start_time; + ESP_LOGI(TAG, "mutex task took %lld us on core%d", duration, core_id); + + vTaskDelete(NULL); +} + +// Enter a critical section and take a spinlock to protect the shared resource. If the spinlock is already taken, this task busy-wait here until it is available. +// In contrast to the mutex, when in a critical section interrupts are disabled, which means nothing will interrupt the task and the freertos scheduler will never run +// and reschedule the task. +static void inc_num_spinlock_iter(void *arg) +{ + int core_id = esp_cpu_get_core_id(); + int64_t start_time, end_time, duration = 0; + start_time = esp_timer_get_time(); + while (s_global_num < ITERATION_NUMBER) { + portENTER_CRITICAL(&s_spinlock); + s_global_num++; + portEXIT_CRITICAL(&s_spinlock); + } + end_time = esp_timer_get_time(); + duration = end_time - start_time; + ESP_LOGI(TAG, "spinlock task took %lld us on core%d", duration, core_id); + + vTaskDelete(NULL); +} + +static void inc_num_atomic_iter(void *arg) +{ + int core_id = esp_cpu_get_core_id(); + int64_t start_time, end_time, duration = 0; + start_time = esp_timer_get_time(); + while (atomic_load(&s_atomic_global_num) < ITERATION_NUMBER) { + atomic_fetch_add(&s_atomic_global_num, 1); + } + end_time = esp_timer_get_time(); + duration = end_time - start_time; + ESP_LOGI(TAG, "atomic task took %lld us on core%d", duration, core_id); + + vTaskDelete(NULL); +} + +static void inc_num_mutex(void *arg) +{ + int task_index = *(int*)arg; + ESP_LOGI(TAG, "mutex task %d created", task_index); + + while (!timed_out) { + xSemaphoreTake(s_mutex, portMAX_DELAY); // == pdTRUE + + int core_id = esp_cpu_get_core_id(); + ESP_LOGI(TAG, "task%d read value = %d on core #%d", task_index, s_global_num, core_id); + s_global_num++; + // delay for 500 ms + vTaskDelay(pdMS_TO_TICKS(500)); + xSemaphoreGive(s_mutex); + ESP_LOGI(TAG, "task%d set value = %d", task_index, s_global_num); + } + + vTaskDelete(NULL); +} + + +/* Lock example: show how to use mutex and spinlock to protect shared resources + +Firstly, a shared resource `s_global_num` is protected by a mutex and there are 2 tasks, +whose task function is `inc_num_mutex_iter`, take turns to access and increase this number. +Once the number value reaches 100000, the time duration from starting running till the +current time is measured and recorded, then both these 2 tasks will be deleted. + +Next, `s_global_num` is reset and there are another 2 tasks, calling task function +`inc_num_spinlock_iter`, that access and increase this shared resource until it reaches +100000, under the protection of a spinlock. The expected result is these 2 tasks will have +less time overhead in comparison with the previous 2 tasks because they involve less context +switching for task execution. + +After that, another 2 tasks are create to complete the same +addition job, but the shared resource is an atomic type integer. It should have a shorter +running time than the spinlock tasks, because atomic operation is a kind of look-free implementation +and it saves the time of entering and exiting the critical section. + +Note: if this example runs on single core, only 1 task of each type will be created. + +Finally, it illustrates show the shared resource `s_global_num` is protected by a mutex +and in turn accessed by multiple tasks. */ +int comp_lock_entry_func(int argc, char **argv) +{ + s_global_num = 0; + int thread_id; + int core_id; + + timed_out = false; + + // create mutex + s_mutex = xSemaphoreCreateMutex(); + if (s_mutex == NULL) { + ESP_LOGE(TAG, SEM_CREATE_ERR_STR); + return 1; + } + + // create 2 tasks accessing a shared resource protected by mutex + for (core_id = 0; core_id < CONFIG_FREERTOS_NUMBER_OF_CORES; core_id++) { + xTaskCreatePinnedToCore(inc_num_mutex_iter, NULL, 4096, NULL, TASK_PRIO_3, NULL, core_id); + } + + // reset s_global_num + vTaskDelay(2000 / portTICK_PERIOD_MS); + s_global_num = 0; + // create 2 tasks accessing a shared resource protected by spinlock + for (core_id = 0; core_id < CONFIG_FREERTOS_NUMBER_OF_CORES; core_id++) { + xTaskCreatePinnedToCore(inc_num_spinlock_iter, NULL, 4096, NULL, TASK_PRIO_3, NULL, core_id); + } + + vTaskDelay(2000 / portTICK_PERIOD_MS); + // create 2 tasks accessing an atomic shared resource + atomic_init(&s_atomic_global_num, 0); + for (core_id = 0; core_id < CONFIG_FREERTOS_NUMBER_OF_CORES; core_id++) { + xTaskCreatePinnedToCore(inc_num_atomic_iter, NULL, 4096, NULL, TASK_PRIO_3, NULL, core_id); + } + + // reset s_global_num + vTaskDelay(1000 / portTICK_PERIOD_MS); + s_global_num = 0; + // create 2 tasks to increase a shared number in turn + for (thread_id = 0; thread_id < SHARE_RES_THREAD_NUM; thread_id++) { + xTaskCreatePinnedToCore(inc_num_mutex, NULL, 4096, &thread_id, TASK_PRIO_3, NULL, tskNO_AFFINITY); + } + + // time out and stop running after 5 seconds + vTaskDelay(pdMS_TO_TICKS(COMP_LOOP_PERIOD)); + timed_out = true; + // delay to let tasks finish the last loop + vTaskDelay(1500 / portTICK_PERIOD_MS); + return 0; +} diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/queue_example.c b/examples/system/freertos/basic_freertos_smp_usage/main/queue_example.c new file mode 100644 index 000000000000..0024aded7bfd --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/queue_example.c @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "freertos/FreeRTOS.h" +#include "esp_log.h" +#include "basic_freertos_smp_usage.h" + + +static QueueHandle_t msg_queue; +static const uint8_t msg_queue_len = 40; +static volatile bool timed_out; +const static char *TAG = "queue example"; + +static void print_q_msg(void *arg) +{ + int data; // data type should be same as queue item type + int to_wait_ms = 1000; // the maximal blocking waiting time of millisecond + const TickType_t xTicksToWait = pdMS_TO_TICKS(to_wait_ms); + + while (!timed_out) { + if (xQueueReceive(msg_queue, (void *)&data, xTicksToWait) == pdTRUE) { + ESP_LOGI(TAG, "received data = %d", data); + } else { + ESP_LOGI(TAG, "Did not received data in the past %d ms", to_wait_ms); + } + } + + vTaskDelete(NULL); +} + +static void send_q_msg(void *arg) +{ + int sent_num = 0; + + while (!timed_out) { + // Try to add item to queue, fail immediately if queue is full + if (xQueueGenericSend(msg_queue, (void *)&sent_num, portMAX_DELAY, queueSEND_TO_BACK) != pdTRUE) { + ESP_LOGI(TAG, "Queue full\n"); + } + ESP_LOGI(TAG, "sent data = %d", sent_num); + sent_num++; + + // send an item for every 250ms + vTaskDelay(250 / portTICK_PERIOD_MS); + } + + vTaskDelete(NULL); +} + +// Queue example: illustrate how queues can be used to synchronize between tasks +int comp_queue_entry_func(int argc, char **argv) +{ + timed_out = false; + + msg_queue = xQueueGenericCreate(msg_queue_len, sizeof(int), queueQUEUE_TYPE_SET); + if (msg_queue == NULL) { + ESP_LOGE(TAG, QUEUE_CREATE_ERR_STR); + return 1; + } + xTaskCreatePinnedToCore(print_q_msg, "print_q_msg", 4096, NULL, TASK_PRIO_3, NULL, tskNO_AFFINITY); + xTaskCreatePinnedToCore(send_q_msg, "send_q_msg", 4096, NULL, TASK_PRIO_3, NULL, tskNO_AFFINITY); + + // time out and stop running after 5 seconds + vTaskDelay(pdMS_TO_TICKS(COMP_LOOP_PERIOD)); + timed_out = true; + // delay to let tasks finish the last loop + vTaskDelay(500 / portTICK_PERIOD_MS); + return 0; +} diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/task_notify_example.c b/examples/system/freertos/basic_freertos_smp_usage/main/task_notify_example.c new file mode 100644 index 000000000000..046320d2f592 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/main/task_notify_example.c @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "freertos/FreeRTOS.h" +#include "esp_log.h" +#include "basic_freertos_smp_usage.h" + +static volatile bool timed_out; +const static char *TAG = "task notify example"; + +/* In this example, there is a thread waiting for a synchronization signal from another thread before it start processing +Task synchronization could also be achieved with `xSemaphoreTake`, but FreeRTOS suggest using task notifications +as a faster and more lightweight alternative. +*/ + +static void notification_rcv_func(void *arg) +{ + int pending_notification_task_num; + while (!timed_out) { + pending_notification_task_num = ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + { + ESP_LOGI(TAG, "%d tasks pending", pending_notification_task_num); + while (pending_notification_task_num > 0) { + // do something to process the received notification + ESP_LOGI(TAG, "rcv_task is processing this task notification"); + pending_notification_task_num--; + } + } + } + + vTaskDelete(NULL); +} + +static void notification_send_func(void *arg) +{ + TaskHandle_t rcv_task_hdl = (TaskHandle_t)arg; + // send a task notification every 1000 ms + while (!timed_out) { + xTaskNotifyGive(rcv_task_hdl); + ESP_LOGI(TAG, "send_task sends a notification"); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + + vTaskDelete(NULL); +} + +int comp_task_notification_entry_func(int argc, char **argv) +{ + timed_out = false; + TaskHandle_t rcv_task_hdl; + xTaskCreatePinnedToCore(notification_rcv_func, NULL, 8192, NULL, TASK_PRIO_3, &rcv_task_hdl, tskNO_AFFINITY); + xTaskCreatePinnedToCore(notification_send_func, NULL, 8192, rcv_task_hdl, TASK_PRIO_3, NULL, tskNO_AFFINITY); + + // time out and stop running after 5 seconds + vTaskDelay(pdMS_TO_TICKS(COMP_LOOP_PERIOD)); + timed_out = true; + // delay to let tasks finish the last loop + vTaskDelay(500 / portTICK_PERIOD_MS); + return 0; +} diff --git a/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py b/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py new file mode 100644 index 000000000000..5019db6a4b40 --- /dev/null +++ b/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py @@ -0,0 +1,92 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import pytest +from pytest_embedded_idf.dut import IdfDut + + +@pytest.mark.esp32c3 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_creating_task( + dut: IdfDut +) -> None: + dut.expect(r'esp32(?:[a-zA-Z]\d)?>') + # test creating_task + dut.write('create_task') + dut.expect('create task example: task#0 is running on core#0') + dut.expect('create task example: task#1 is running on core#0') + dut.expect(r'create task example: task#2 is running on core#\d') + dut.expect(r'create task example: task#3 is running on core#\d') + + +@pytest.mark.esp32c3 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_queue( + dut: IdfDut +) -> None: + dut.expect(r'esp32(?:[a-zA-Z]\d)?>') + # test queue tasks + verify_amount = 5 + dut.write('queue') + dut.expect('queue example: sent data') + dut.expect('queue example: received data') + + for _ in range(verify_amount): + data = eval(dut.expect(r'queue example: sent data = (\d+)').group(1)) + dut.expect('queue example: received data = ' + str(data)) + + +@pytest.mark.esp32c3 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_locks( + dut: IdfDut +) -> None: + dut.expect(r'esp32(?:[a-zA-Z]\d)?>') + # test locks + dut.write('lock') + dut.expect(r'lock example: mutex task took \d+ us on core\d') + dut.expect(r'lock example: spinlock task took \d+ us on core\d') + dut.expect(r'lock example: atomic task took \d+ us on core\d') + dut.expect(r'task0 read value = 0 on core #\d') + dut.expect('task0 set value = 1') + dut.expect(r'task\d read value = 1 on core #\d') + dut.expect(r'task\d set value = 2') + dut.expect(r'task0 read value = 2 on core #\d') + + +@pytest.mark.esp32c3 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_task_notification( + dut: IdfDut +) -> None: + dut.expect(r'esp32(?:[a-zA-Z]\d)?>') + # test task notification + dut.write('task_notification') + dut.expect('task notify example: send_task sends a notification') + dut.expect('task notify example: 1 tasks pending') + dut.expect('task notify example: rcv_task is processing this task notification') + + +@pytest.mark.esp32c3 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_batch_proc_example( + dut: IdfDut +) -> None: + dut.expect(r'esp32(?:[a-zA-Z]\d)?>') + # test batch processing example + dut.write('batch_processing') + + batch_size = 5 + data_buf = [None] * batch_size + + for i in range(batch_size): + res = dut.expect(r'batch processing example: enqueue data = (\d+)') + data_buf[i] = eval(res.group(1)) if res else None + for i in range(batch_size): + expected_string = 'batch processing example: dequeue data = ' + str(data_buf[i]) + dut.expect(expected_string) + dut.expect(r'batch processing example: decrease s_rcv_item_num to \d') diff --git a/examples/system/freertos/basic_freertos_smp_usage/sdkconfig.ci b/examples/system/freertos/basic_freertos_smp_usage/sdkconfig.ci new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/examples/system/ulp/lp_core/interrupt/README.md b/examples/system/ulp/lp_core/interrupt/README.md index b508bd913da0..082a827ba49a 100644 --- a/examples/system/ulp/lp_core/interrupt/README.md +++ b/examples/system/ulp/lp_core/interrupt/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | # LP-Core example with interrupt triggered from HP-Core: diff --git a/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md b/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md index 8c5072dbac79..909255ff5236 100644 --- a/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md +++ b/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md @@ -19,10 +19,11 @@ To run this example, you should have an ESP32-C6 based development board and a h **Note:** The following pin assignments are used by default. -| | Rx | Tx | -| ----------------------- | ------| ------| -| ESP32-C6 | GPIO4 | GPIO5 | -| Host machine | Tx | Rx | +| | Rx | Tx | +| ----------------------- | -------| -------| +| ESP32-C6 | GPIO4 | GPIO5 | +| ESP32-P4 | GPIO15 | GPIO14 | +| Host machine | Tx | Rx | ### Build and Flash diff --git a/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md b/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md index 411d1c1645f6..cbe260c640b3 100644 --- a/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md +++ b/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md @@ -20,10 +20,11 @@ To run this example, you should have an ESP32-C6 based development board and a h **Note:** The following pin assignments are used by default. -| | Tx | -| ----------------------- | ------| -| ESP32-C6 | GPIO5 | -| Host machine | Rx | +| | Tx | +| ----------------------- | -------| +| ESP32-C6 | GPIO5 | +| ESP32-P4 | GPIO14 | +| Host machine | Rx | ### Build and Flash diff --git a/export.ps1 b/export.ps1 index af35dceb65f3..fec71aeca722 100644 --- a/export.ps1 +++ b/export.ps1 @@ -26,10 +26,10 @@ foreach ($line in $envars_raw) { $envars_array += (, ($var_name, $var_val)) } -if ($IsWindows -eq $null) { +if ($null -eq $IsWindows) { # $IsWindows was added in PowerShell Core 6 and PowerShell 7 together with multi-platform support. # I.E. if this # internal variable is not set then PowerShell 5 is used and # the platform cannot be # anything else than Windows. - $IsWindows = $true + $Windows = $true } foreach ($pair in $envars_array) { @@ -38,7 +38,7 @@ foreach ($pair in $envars_array) { $var_val = $pair[1].Trim() # trim spaces on the ends of the val if ($var_name -eq "PATH") { # trim "%PATH%" or "`$PATH" - if ($IsWindows) { + if ($IsWindows || $Windows) { $var_val = $var_val.Trim($S + "%PATH%") } else { $var_val = $var_val.Trim($S + "`$PATH") @@ -60,7 +60,7 @@ function parttool.py { &python "$IDF_PATH\components\partition_table\parttool.py #Compare Path's OLD vs. NEW $NEW_PATH = $env:PATH.split($S) | Select-Object -Unique # array without duplicates $dif_Path = Compare-Object -ReferenceObject $OLD_PATH -DifferenceObject $NEW_PATH -PassThru -if ($dif_Path -ne $null) { +if ($null -ne $dif_Path) { Write-Output "`nAdded to PATH`n-------------" Write-Output $dif_Path } else { diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 9016a55af8d1..287137abcb9e 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -407,7 +407,6 @@ components/esp_hid/include/esp_hidh_bluedroid.h components/esp_hid/include/esp_hidh_gattc.h components/esp_hid/private/bt_hidd.h components/esp_hid/private/bt_hidh.h -components/esp_local_ctrl/src/esp_local_ctrl_handler.c components/esp_local_ctrl/src/esp_local_ctrl_priv.h components/esp_local_ctrl/src/esp_local_ctrl_transport_ble.c components/esp_phy/test/test_phy_rtc.c diff --git a/tools/ci/check_register_rw_half_word.cmake b/tools/ci/check_register_rw_half_word.cmake new file mode 100644 index 000000000000..3a7cc2890e8b --- /dev/null +++ b/tools/ci/check_register_rw_half_word.cmake @@ -0,0 +1,33 @@ +function(check_register_rw_half_word) + set(options) + set(oneValueArgs) + set(multiValueArgs SOC_MODULES HAL_MODULES) + cmake_parse_arguments(ARG "${options}" "${oneValueArgs}" "${multiValueArgs}" ${ARGN}) + + if(NOT ARG_SOC_MODULES) + message(FATAL_ERROR "SOC_MODULES are required") + endif() + + if(NOT ARG_HAL_MODULES) + message(FATAL_ERROR "HAL_MODULES are required") + endif() + + idf_build_get_property(python PYTHON) + idf_build_get_property(idf_target IDF_TARGET) + + execute_process( + COMMAND ${python} $ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.py + --target-chip ${idf_target} + --soc-modules ${ARG_SOC_MODULES} + --hal-modules ${ARG_HAL_MODULES} + RESULT_VARIABLE result + OUTPUT_VARIABLE output + ERROR_VARIABLE error + OUTPUT_STRIP_TRAILING_WHITESPACE + ERROR_STRIP_TRAILING_WHITESPACE + ) + + if(result) + message(FATAL_ERROR "${output}") + endif() +endfunction() diff --git a/tools/ci/check_register_rw_half_word.py b/tools/ci/check_register_rw_half_word.py new file mode 100644 index 000000000000..3a5aa569dd52 --- /dev/null +++ b/tools/ci/check_register_rw_half_word.py @@ -0,0 +1,99 @@ +# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import argparse +import os +import re +import sys +from pathlib import Path +from typing import Iterator +from typing import List + +idf_path = os.environ.get('IDF_PATH', None) + + +def find_files(base_path: str, patterns: List[str]) -> Iterator[Path]: + for pattern in patterns: + yield from Path(base_path).rglob(f'**/{pattern}') + + +def read_and_capture_suspicious_fields(file_path: Path) -> List[str]: + with open(file_path, 'r') as file: + content = file.read() + captures = re.findall(r'uint32_t\s+(\w+)\s*:\s*(16|8)\s*;', content) + return [capture[0] for capture in captures if not capture[0].startswith('reserve')] + + +def main( + target_chip: str, soc_module_patterns: List[str], hal_module_patterns: List[str] +) -> None: + soc_path = f'{idf_path}/components/soc/{target_chip}/' + hal_path = f'{idf_path}/components/hal/{target_chip}/' + struct_file_patterns = [f'{pattern}_struct.h' for pattern in soc_module_patterns] + ll_file_patterns = [f'{pattern}_ll.h' for pattern in hal_module_patterns] + + # Find `xxx_struct.h` files and `hal/yyy_ll.h` files + struct_files = find_files(soc_path, struct_file_patterns) + + no_violation_found = True + for struct_file in struct_files: + # Capture suspicious fields from `xxx_struct.h` + captures = read_and_capture_suspicious_fields(struct_file) + # if no suspicious fields found, continue to next struct file + if not captures: + continue + + # check if any of the captured fields are being read/written as half-words + ll_files = find_files(hal_path, ll_file_patterns) + for ll_file in ll_files: + with open(ll_file, 'r') as f: + content = f.read() + for capture in captures: + error_usages = [f'.{capture}', f'->{capture}'] + for error_usage in error_usages: + word_bound_pattern = rf'{re.escape(error_usage)}\b' + # print the line number where the error_usage is found + for match in re.finditer(word_bound_pattern, content, re.MULTILINE): + no_violation_found = False + start_line = content.count('\n', 0, match.start()) + 1 + print( + f'Found pattern {error_usage} at line {start_line} in file {ll_file}' + ) + + if no_violation_found: + print('No violations found') + else: + sys.exit(1) + + +if __name__ == '__main__': + if idf_path is None: + print('IDF_PATH must be set before running this script', file=sys.stderr) + sys.exit(1) + + parser = argparse.ArgumentParser( + description='Check if any register fields are being read/written as half-words.' + ) + parser.add_argument( + '--target-chip', + type=str, + required=True, + help='The name of the chip. e.g. esp32s3', + ) + parser.add_argument( + '--soc-modules', + required=True, + type=str, + nargs='+', # allow multiple soc modules + help='Name pattern for the SOC module. e.g. spi means spi_struct.h', + ) + parser.add_argument( + '--hal-modules', + required=True, + type=str, + nargs='+', # allow multiple hal modules + help='Name pattern for the HAL module. e.g. spi means spi_ll.h', + ) + + args = parser.parse_args() + + main(args.target_chip, args.soc_modules, args.hal_modules) diff --git a/tools/ci/dynamic_pipelines/models.py b/tools/ci/dynamic_pipelines/models.py index 5fff31c3f5b4..e661e3ded31d 100644 --- a/tools/ci/dynamic_pipelines/models.py +++ b/tools/ci/dynamic_pipelines/models.py @@ -135,6 +135,8 @@ class TestCase: ci_job_url: t.Optional[str] = None ci_dashboard_url: t.Optional[str] = None dut_log_url: t.Optional[str] = None + latest_total_count: int = 0 + latest_failed_count: int = 0 @property def is_failure(self) -> bool: @@ -179,3 +181,45 @@ def from_test_case_node(cls, node: Element) -> t.Optional['TestCase']: kwargs['skipped'] = skipped_node.attrib['message'] return cls(**kwargs) # type: ignore + + +@dataclass +class GitlabJob: + id: int + name: str + stage: str + status: str + url: str + ci_dashboard_url: str + failure_reason: t.Optional[str] = None + failure_log: t.Optional[str] = None + latest_total_count: int = 0 + latest_failed_count: int = 0 + + @property + def is_failed(self) -> bool: + return self.status == 'failed' + + @property + def is_success(self) -> bool: + return self.status == 'success' + + @classmethod + def from_json_data(cls, job_data: dict, failure_data: dict) -> t.Optional['GitlabJob']: + grafana_base_url = urllib.parse.urljoin(os.getenv('CI_DASHBOARD_HOST', ''), '/d/LoUa-qLWz/job-list') + encoded_params = urllib.parse.urlencode({'var-job_name': job_data['name']}, quote_via=urllib.parse.quote) + + kwargs = { + 'id': job_data['id'], + 'name': job_data['name'], + 'stage': job_data['stage'], + 'status': job_data['status'], + 'url': job_data['url'], + 'ci_dashboard_url': f'{grafana_base_url}?{encoded_params}', + 'failure_reason': job_data['failure_reason'], + 'failure_log': job_data['failure_log'], + 'latest_total_count': failure_data.get('total_count', 0), + 'latest_failed_count': failure_data.get('failed_count', 0), + } + + return cls(**kwargs) # type: ignore diff --git a/tools/ci/dynamic_pipelines/report.py b/tools/ci/dynamic_pipelines/report.py index 1f0de199aaa2..dd3951c107d0 100644 --- a/tools/ci/dynamic_pipelines/report.py +++ b/tools/ci/dynamic_pipelines/report.py @@ -18,7 +18,9 @@ from .constants import COMMENT_START_MARKER from .constants import REPORT_TEMPLATE_FILEPATH from .constants import TEST_RELATED_APPS_DOWNLOAD_URLS_FILENAME +from .models import GitlabJob from .models import TestCase +from .utils import fetch_failed_testcases_failure_ratio from .utils import is_url from .utils import load_known_failure_cases @@ -58,25 +60,150 @@ def generate_html_report(self, table_str: str) -> str: def table_to_html_str(table: PrettyTable) -> str: return html.unescape(table.get_html_string()) # type: ignore + def create_table_section( + self, + report_sections: list, + title: str, + items: list, + headers: list, + row_attrs: list, + value_functions: t.Optional[list] = None, + ) -> None: + """ + Appends a formatted section to a report based on the provided items. This section includes + a header and a table constructed from the items list with specified headers and attributes. + + :param report_sections: List where the HTML report sections are collected. This list is + modified in-place by appending new sections. + :param title: Title for the report section. This title is used as a header above the table. + :param items: List of item objects to include in the table. Each item should have attributes + that correspond to the row_attrs and value_functions specified. + :param headers: List of strings that will serve as the column headers in the generated table. + :param row_attrs: List of attributes to include from each item for the table rows. These + should be attributes or keys that exist on the items in the 'items' list. + :param value_functions: Optional list of tuples containing additional header and corresponding + value function. Each tuple should specify a header (as a string) and + a function that takes an item and returns a string. This is used for + generating dynamic columns based on item data. + + :return: None. The function modifies the 'report_sections' list by appending new HTML sections. + """ + if not items: + return + + report_sections.append(f'

{title}

') + report_sections.append( + self._create_table_for_items( + items=items, headers=headers, row_attrs=row_attrs, value_functions=value_functions or [] + ) + ) + + def _create_table_for_items( + self, + items: t.Union[t.List[TestCase], t.List[GitlabJob]], + headers: t.List[str], + row_attrs: t.List[str], + value_functions: t.Optional[t.List[t.Tuple[str, t.Callable[[t.Union[TestCase, GitlabJob]], str]]]] = None, + ) -> str: + """ + Create a PrettyTable and convert it to an HTML string for the provided test cases. + :param items: List of item objects to include in the table. + :param headers: List of strings for the table headers. + :param row_attrs: List of attributes to include in each row. + :param value_functions: List of tuples containing additional header and corresponding value function. + :return: HTML table string. + """ + table = PrettyTable() + table.field_names = headers + + # Create a mapping of header names to their corresponding index in the headers list + header_index_map = {header: i for i, header in enumerate(headers)} + + for item in items: + row = [] + for attr in row_attrs: + value = str(getattr(item, attr, '')) + if is_url(value): + link = f'link' + row.append(link) + else: + row.append(value) + + # Insert values computed by value functions at the correct column position based on their headers + if value_functions: + for header, func in value_functions: + index = header_index_map.get(header) + if index is not None: + computed_value = func(item) + row.insert(index, computed_value) + + table.add_row(row) + + return self.table_to_html_str(table) + + @staticmethod + def _filter_items( + items: t.Union[t.List[TestCase], t.List[GitlabJob]], condition: t.Callable[[t.Union[TestCase, GitlabJob]], bool] + ) -> t.List[TestCase]: + """ + Filter items s based on a given condition. + + :param items: List of items to filter by given condition. + :param condition: A function that evaluates to True or False for each items. + :return: List of filtered instances. + """ + return [item for item in items if condition(item)] + + @staticmethod + def _sort_items( + items: t.List[t.Union[TestCase, GitlabJob]], + key: t.Union[str, t.Callable[[t.Union[TestCase, GitlabJob]], t.Any]], + order: str = 'asc', + ) -> t.List[t.Union[TestCase, GitlabJob]]: + """ + Sort items based on a given key and order. + + :param items: List of items to sort. + :param key: A string representing the attribute name or a function to extract the sorting key. + :param order: Order of sorting ('asc' for ascending, 'desc' for descending). + :return: List of sorted instances. + """ + key_func = None + if isinstance(key, str): + + def key_func(item: t.Any) -> t.Any: + return getattr(item, key) + + if key_func is not None: + try: + items = sorted(items, key=key_func, reverse=(order == 'desc')) + except TypeError: + print(f'Comparison for the key {key} is not supported') + return items + @abc.abstractmethod def _get_report_str(self) -> str: raise NotImplementedError def post_report(self, job_id: int, commit_id: str) -> None: # report in html format, otherwise will exceed the limit - with open(self.output_filepath, 'w') as fw: - fw.write(self._get_report_str()) + comment = f'#### {self.title}\n' - # for example, {URL}/-/esp-idf/-/jobs/{id}/artifacts/list_job_84.txt - # CI_PAGES_URL is {URL}/esp-idf, which missed one `-` - url = os.getenv('CI_PAGES_URL', '').replace('esp-idf', '-/esp-idf') + report_str = self._get_report_str() - comment = f'#### {self.title}\n' if self.additional_info: comment += f'{self.additional_info}\n' - comment += f""" -Full {self.title} here: {url}/-/jobs/{job_id}/artifacts/{self.output_filepath} (with commit {commit_id}) + if report_str: + with open(self.output_filepath, 'w') as fw: + fw.write(report_str) + + # for example, {URL}/-/esp-idf/-/jobs/{id}/artifacts/list_job_84.txt + # CI_PAGES_URL is {URL}/esp-idf, which missed one `-` + url = os.getenv('CI_PAGES_URL', '').replace('esp-idf', '-/esp-idf') + + comment += f""" +Full {self.title} here: {url}/-/jobs/{job_id}/artifacts/{self.output_filepath} (with commit {commit_id[:8]}) """ print(comment) @@ -265,94 +392,172 @@ def get_known_failure_cases(self) -> t.List[TestCase]: ] return matched_cases - def _filter_test_cases(self, condition: t.Callable[[TestCase], bool]) -> t.List[TestCase]: - """ - Filter test cases based on a given condition. In this scenario, we filter by status, - however it is possible to filter by other criteria. - - :param condition: A function that evaluates to True or False for each test case. - :return: List of filtered TestCase instances. - """ - return [tc for tc in self.test_cases if condition(tc)] - - def _create_table_for_test_cases( - self, test_cases: t.List[TestCase], headers: t.List[str], row_attrs: t.List[str] - ) -> str: - """ - Create a PrettyTable and convert it to an HTML string for the provided test cases. - :param test_cases: List of TestCase objects to include in the table. - :param headers: List of strings for the table headers. - :param row_attrs: List of attributes to include in each row. - :return: HTML table string. - """ - table = PrettyTable() - table.field_names = headers - for tc in test_cases: - row = [] - for attr in row_attrs: - value = getattr(tc, attr, '') - if is_url(value): - link = f'link' - row.append(link) - else: - row.append(value) - table.add_row(row) - - return self.table_to_html_str(table) - def _get_report_str(self) -> str: """ Generate a complete HTML report string by processing test cases. :return: Complete HTML report string. """ - table_str = '' + report_parts: list = [] known_failures = self.get_known_failure_cases() known_failure_case_names = {case.name for case in known_failures} - failed_test_cases = self._filter_test_cases( - lambda tc: tc.is_failure and tc.name not in known_failure_case_names + failed_test_cases = self._filter_items( + self.test_cases, lambda tc: tc.is_failure and tc.name not in known_failure_case_names ) - skipped_test_cases = self._filter_test_cases(lambda tc: tc.is_skipped) - successful_test_cases = self._filter_test_cases(lambda tc: tc.is_success) - - if failed_test_cases: - table_str += '

Failed Test Cases (Excludes Known Failure Cases)

' - table_str += self._create_table_for_test_cases( - test_cases=failed_test_cases, - headers=['Test Case', 'Test Script File Path', 'Failure Reason', 'Job URL', 'Grafana URL'], - row_attrs=['name', 'file', 'failure', 'ci_job_url', 'ci_dashboard_url'], - ) + failed_test_cases_with_ratio = self._sort_items( + fetch_failed_testcases_failure_ratio(failed_test_cases), key='latest_failed_count' + ) + skipped_test_cases = self._filter_items(self.test_cases, lambda tc: tc.is_skipped) + successful_test_cases = self._filter_items(self.test_cases, lambda tc: tc.is_success) - if known_failures: - table_str += '

Known Failure Cases

' - table_str += self._create_table_for_test_cases( - test_cases=known_failures, - headers=['Test Case', 'Test Script File Path', 'Failure Reason', 'Job URL', 'Grafana URL'], - row_attrs=['name', 'file', 'failure', 'ci_job_url', 'ci_dashboard_url'], - ) + current_branch_failures = self._sort_items( + self._filter_items(failed_test_cases_with_ratio, lambda tc: tc.latest_failed_count == 0), + key='latest_failed_count', + ) + other_branch_failures = self._sort_items( + self._filter_items( + failed_test_cases_with_ratio, lambda tc: tc.name not in [t.name for t in current_branch_failures] + ), + key='latest_failed_count', + ) - if skipped_test_cases: - table_str += '

Skipped Test Cases

' - table_str += self._create_table_for_test_cases( - test_cases=skipped_test_cases, - headers=['Test Case', 'Test Script File Path', 'Skipped Reason', 'Grafana URL'], - row_attrs=['name', 'file', 'skipped', 'ci_dashboard_url'], - ) + self.create_table_section( + report_sections=report_parts, + title='Failed Test Cases on Your branch (Excludes Known Failure Cases)', + items=current_branch_failures, + headers=[ + 'Test Case', + 'Test Script File Path', + 'Failure Reason', + 'Failures across all other branches (20 latest testcases)', + 'Job URL', + 'Grafana URL', + ], + row_attrs=['name', 'file', 'failure', 'ci_job_url', 'ci_dashboard_url'], + value_functions=[ + ( + 'Failures across all other branches (20 latest testcases)', + lambda item: f"{getattr(item, 'latest_failed_count', '')} / {getattr(item, 'latest_total_count', '')}", + ) + ], + ) + self.create_table_section( + report_sections=report_parts, + title='Failed Test Cases on Other branches (Excludes Known Failure Cases)', + items=other_branch_failures, + headers=[ + 'Test Case', + 'Test Script File Path', + 'Failure Reason', + 'Failures across all other branches (20 latest testcases)', + 'Job URL', + 'Grafana URL', + ], + row_attrs=['name', 'file', 'failure', 'ci_job_url', 'ci_dashboard_url'], + value_functions=[ + ( + 'Failures across all other branches (20 latest testcases)', + lambda item: f"{getattr(item, 'latest_failed_count', '')} / {getattr(item, 'latest_total_count', '')}", + ) + ], + ) + + self.create_table_section( + report_sections=report_parts, + title='Known Failure Cases', + items=known_failures, + headers=['Test Case', 'Test Script File Path', 'Failure Reason', 'Job URL', 'Grafana URL'], + row_attrs=['name', 'file', 'failure', 'ci_job_url', 'ci_dashboard_url'], + ) + self.create_table_section( + report_sections=report_parts, + title='Skipped Test Cases', + items=skipped_test_cases, + headers=['Test Case', 'Test Script File Path', 'Skipped Reason', 'Grafana URL'], + row_attrs=['name', 'file', 'skipped', 'ci_dashboard_url'], + ) + self.create_table_section( + report_sections=report_parts, + title='Succeeded Test Cases', + items=successful_test_cases, + headers=['Test Case', 'Test Script File Path', 'Job URL', 'Grafana URL'], + row_attrs=['name', 'file', 'ci_job_url', 'ci_dashboard_url'], + ) - if successful_test_cases: - table_str += '

Succeeded Test Cases

' - table_str += self._create_table_for_test_cases( - test_cases=successful_test_cases, - headers=['Test Case', 'Test Script File Path', 'Job URL', 'Grafana URL'], - row_attrs=['name', 'file', 'ci_job_url', 'ci_dashboard_url'], - ) self.additional_info = ( '**Test Case Summary:**\n' - f'- **Failed Test Cases (Excludes Known Failure Cases):** {len(failed_test_cases)}\n' + f'- **Failed Test Cases on Your Branch (Excludes Known Failure Cases):** {len(current_branch_failures)}.\n' + f'- **Failed Test Cases on Other Branches (Excludes Known Failure Cases):** {len(other_branch_failures)}.\n' f'- **Known Failures:** {len(known_failures)}\n' f'- **Skipped Test Cases:** {len(skipped_test_cases)}\n' f'- **Succeeded Test Cases:** {len(successful_test_cases)}\n\n' - f'Please check report below for more information.\n\n' + 'Please check report below for more information.\n\n' ) - return self.generate_html_report(table_str) + return self.generate_html_report(''.join(report_parts)) + + +class JobReportGenerator(ReportGenerator): + def __init__( + self, + project_id: int, + mr_iid: int, + pipeline_id: int, + *, + title: str = 'Job Report', + jobs: t.List[GitlabJob], + ): + super().__init__(project_id, mr_iid, pipeline_id, title=title) + self.jobs = jobs + + def _get_report_str(self) -> str: + """ + Generate a complete HTML report string by processing jobs. + :return: Complete HTML report string. + """ + report_str: str = '' + report_parts: list = [] + + if not self.jobs: + print('No jobs found, skip generating job report') + return 'No Job Found' + + relevant_failed_jobs = self._sort_items( + self._filter_items( + self.jobs, lambda job: job.is_failed and job.stage not in ['integration_test', 'target_test'] + ), + key='latest_failed_count', + ) + succeeded_jobs = self._filter_items(self.jobs, lambda job: job.is_success) + + self.additional_info = ( + '**Job Summary:**\n' + f'- **Failed Jobs (Excludes "integration_test" and "target_test" jobs):** {len(relevant_failed_jobs)}\n' + f'- **Succeeded Jobs:** {len(succeeded_jobs)}\n\n' + ) + + if relevant_failed_jobs: + self.create_table_section( + report_sections=report_parts, + title='Failed Jobs (Excludes "integration_test" and "target_test" jobs)', + items=relevant_failed_jobs, + headers=[ + 'Job Name', + 'Failure Reason', + 'Failure Log', + 'Failures across all other branches (10 latest jobs)', + 'URL', + 'CI Dashboard URL', + ], + row_attrs=['name', 'failure_reason', 'failure_log', 'url', 'ci_dashboard_url'], + value_functions=[ + ( + 'Failures across all other branches (10 latest jobs)', + lambda item: f"{getattr(item, 'latest_failed_count', '')} / {getattr(item, 'latest_total_count', '')}", + ) + ], + ) + self.additional_info += f'Please check report below for more information.\n\n' + report_str = self.generate_html_report(''.join(report_parts)) + + return report_str diff --git a/tools/ci/dynamic_pipelines/scripts/generate_build_report.py b/tools/ci/dynamic_pipelines/scripts/generate_build_report.py deleted file mode 100644 index cef16271fedb..000000000000 --- a/tools/ci/dynamic_pipelines/scripts/generate_build_report.py +++ /dev/null @@ -1,59 +0,0 @@ -# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 - -import argparse -import glob -import os - -import __init__ # noqa: F401 # inject the system path -from dynamic_pipelines.report import BuildReportGenerator -from idf_ci.app import import_apps_from_txt - -if __name__ == '__main__': - parser = argparse.ArgumentParser( - description='Update Build Report in MR pipelines', - formatter_class=argparse.ArgumentDefaultsHelpFormatter, - ) - parser.add_argument( - '--project-id', - type=int, - default=os.getenv('CI_PROJECT_ID'), - help='Project ID', - ) - parser.add_argument( - '--mr-iid', - type=int, - default=os.getenv('CI_MERGE_REQUEST_IID'), - help='Merge Request IID', - ) - parser.add_argument( - '--pipeline-id', - type=int, - default=os.getenv('PARENT_PIPELINE_ID'), - help='Pipeline ID', - ) - parser.add_argument( - '--job-id', - type=int, - default=os.getenv('CI_JOB_ID'), - help='Job ID', - ) - parser.add_argument( - '--commit-id', - default=os.getenv('CI_COMMIT_SHORT_SHA'), - help='MR commit ID', - ) - parser.add_argument( - '--app-list-filepattern', - default='list_job_*.txt', - help='App list file pattern', - ) - - args = parser.parse_args() - - apps = [] - for f in glob.glob(args.app_list_filepattern): - apps.extend(import_apps_from_txt(f)) - - report_generator = BuildReportGenerator(args.project_id, args.mr_iid, args.pipeline_id, apps=apps) - report_generator.post_report(args.job_id, args.commit_id) diff --git a/tools/ci/dynamic_pipelines/scripts/generate_report.py b/tools/ci/dynamic_pipelines/scripts/generate_report.py new file mode 100644 index 000000000000..bb2996d19107 --- /dev/null +++ b/tools/ci/dynamic_pipelines/scripts/generate_report.py @@ -0,0 +1,101 @@ +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import argparse +import glob +import os +import typing as t + +import __init__ # noqa: F401 # inject the system path +from dynamic_pipelines.report import BuildReportGenerator +from dynamic_pipelines.report import JobReportGenerator +from dynamic_pipelines.report import TargetTestReportGenerator +from dynamic_pipelines.utils import fetch_failed_jobs +from dynamic_pipelines.utils import parse_testcases_from_filepattern +from idf_ci.app import import_apps_from_txt + + +def main() -> None: + parser: argparse.ArgumentParser = setup_argument_parser() + args: argparse.Namespace = parser.parse_args() + + report_actions: t.Dict[str, t.Callable[[argparse.Namespace], None]] = { + 'build': generate_build_report, + 'target_test': generate_target_test_report, + 'job': generate_jobs_report, + } + + report_action = report_actions.get(args.report_type) + if report_action is None: + raise ValueError('Unknown report type is requested to be generated.') + + report_action(args) + + +def setup_argument_parser() -> argparse.ArgumentParser: + report_type_parser: argparse.ArgumentParser = argparse.ArgumentParser(add_help=False) + report_type_parser.add_argument( + '--report-type', choices=['build', 'target_test', 'job'], required=True, help='Type of report to generate' + ) + report_type_args: argparse.Namespace + remaining_args: t.List[str] + report_type_args, remaining_args = report_type_parser.parse_known_args() + + parser: argparse.ArgumentParser = argparse.ArgumentParser( + description='Update reports in MR pipelines based on the selected report type', + formatter_class=argparse.ArgumentDefaultsHelpFormatter, + parents=[report_type_parser], + ) + + common_arguments(parser) + conditional_arguments(report_type_args, parser) + + return parser + + +def common_arguments(parser: argparse.ArgumentParser) -> None: + parser.add_argument('--project-id', type=int, default=os.getenv('CI_PROJECT_ID'), help='Project ID') + parser.add_argument('--mr-iid', type=int, default=os.getenv('CI_MERGE_REQUEST_IID'), help='Merge Request IID') + parser.add_argument('--pipeline-id', type=int, default=os.getenv('PARENT_PIPELINE_ID'), help='Pipeline ID') + parser.add_argument('--job-id', type=int, default=os.getenv('CI_JOB_ID'), help='Job ID') + parser.add_argument('--commit-id', default=os.getenv('CI_COMMIT_SHA'), help='MR commit ID') + + +def conditional_arguments(report_type_args: argparse.Namespace, parser: argparse.ArgumentParser) -> None: + if report_type_args.report_type == 'build': + parser.add_argument('--app-list-filepattern', default='list_job_*.txt', help='Pattern to match app list files') + elif report_type_args.report_type == 'target_test': + parser.add_argument( + '--junit-report-filepattern', default='XUNIT_RESULT*.xml', help='Pattern to match JUnit report files' + ) + + +def generate_build_report(args: argparse.Namespace) -> None: + apps: t.List[t.Any] = [ + app for file_name in glob.glob(args.app_list_filepattern) for app in import_apps_from_txt(file_name) + ] + report_generator = BuildReportGenerator( + args.project_id, args.mr_iid, args.pipeline_id, apps=apps + ) + report_generator.post_report(args.job_id, args.commit_id) + + +def generate_target_test_report(args: argparse.Namespace) -> None: + test_cases: t.List[t.Any] = parse_testcases_from_filepattern(args.junit_report_filepattern) + report_generator = TargetTestReportGenerator( + args.project_id, args.mr_iid, args.pipeline_id, test_cases=test_cases + ) + report_generator.post_report(args.job_id, args.commit_id) + + +def generate_jobs_report(args: argparse.Namespace) -> None: + jobs: t.List[t.Any] = fetch_failed_jobs(args.commit_id) + + if not jobs: + return + + report_generator = JobReportGenerator(args.project_id, args.mr_iid, args.pipeline_id, jobs=jobs) + report_generator.post_report(args.job_id, args.commit_id) + + +if __name__ == '__main__': + main() diff --git a/tools/ci/dynamic_pipelines/scripts/generate_target_test_report.py b/tools/ci/dynamic_pipelines/scripts/generate_target_test_report.py deleted file mode 100644 index 07a8952bcf54..000000000000 --- a/tools/ci/dynamic_pipelines/scripts/generate_target_test_report.py +++ /dev/null @@ -1,55 +0,0 @@ -# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 -import argparse -import os - -import __init__ # noqa: F401 # inject the system path -from dynamic_pipelines.report import TargetTestReportGenerator -from dynamic_pipelines.utils import parse_testcases_from_filepattern - - -if __name__ == '__main__': - parser = argparse.ArgumentParser( - description='Update Build Report in MR pipelines', - formatter_class=argparse.ArgumentDefaultsHelpFormatter, - ) - parser.add_argument( - '--project-id', - type=int, - default=os.getenv('CI_PROJECT_ID'), - help='Project ID', - ) - parser.add_argument( - '--mr-iid', - type=int, - default=os.getenv('CI_MERGE_REQUEST_IID'), - help='Merge Request IID', - ) - parser.add_argument( - '--pipeline-id', - type=int, - default=os.getenv('PARENT_PIPELINE_ID'), - help='Pipeline ID', - ) - parser.add_argument( - '--job-id', - type=int, - default=os.getenv('CI_JOB_ID'), - help='Job ID', - ) - parser.add_argument( - '--commit-id', - default=os.getenv('CI_COMMIT_SHORT_SHA'), - help='MR commit ID', - ) - parser.add_argument( - '--junit-report-filepattern', - default='XUNIT_RESULT*.xml', - help='Junit Report file pattern', - ) - - args = parser.parse_args() - - test_cases = parse_testcases_from_filepattern(args.junit_report_filepattern) - report_generator = TargetTestReportGenerator(args.project_id, args.mr_iid, args.pipeline_id, test_cases=test_cases) - report_generator.post_report(args.job_id, args.commit_id) diff --git a/tools/ci/dynamic_pipelines/templates/generate_target_test_report.yml b/tools/ci/dynamic_pipelines/templates/generate_target_test_report.yml index 6559bc350239..8fe17af72e74 100644 --- a/tools/ci/dynamic_pipelines/templates/generate_target_test_report.yml +++ b/tools/ci/dynamic_pipelines/templates/generate_target_test_report.yml @@ -8,4 +8,4 @@ generate_pytest_report: - target_test_report.html script: - python tools/ci/get_known_failure_cases_file.py - - python tools/ci/dynamic_pipelines/scripts/generate_target_test_report.py + - python tools/ci/dynamic_pipelines/scripts/generate_report.py --report-type target_test diff --git a/tools/ci/dynamic_pipelines/templates/report.template.html b/tools/ci/dynamic_pipelines/templates/report.template.html index f8da79ff7ed3..6997fa45c1c5 100644 --- a/tools/ci/dynamic_pipelines/templates/report.template.html +++ b/tools/ci/dynamic_pipelines/templates/report.template.html @@ -1,23 +1,57 @@ - + {{title}} - - - - - - + + + + +
{{table}}
- + + diff --git a/tools/ci/dynamic_pipelines/templates/test_child_pipeline.yml b/tools/ci/dynamic_pipelines/templates/test_child_pipeline.yml index 1b531790ebc3..336b74f0a656 100644 --- a/tools/ci/dynamic_pipelines/templates/test_child_pipeline.yml +++ b/tools/ci/dynamic_pipelines/templates/test_child_pipeline.yml @@ -10,7 +10,7 @@ generate_pytest_build_report: - build_report.html - test_related_apps_download_urls.yml script: - - python tools/ci/dynamic_pipelines/scripts/generate_build_report.py + - python tools/ci/dynamic_pipelines/scripts/generate_report.py --report-type build generate_pytest_child_pipeline: # finally, we can get some use out of the default behavior that downloads all artifacts from the previous stage diff --git a/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/expected_job_report.html b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/expected_job_report.html new file mode 100644 index 000000000000..cb76abeacf5c --- /dev/null +++ b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/expected_job_report.html @@ -0,0 +1,94 @@ + + + + + Job Report + + + + + +

Failed Jobs (Excludes "integration_test" and "target_test" jobs)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Job NameFailure ReasonFailure LogFailures across all other branches (10 latest jobs)URLCI Dashboard URL
build_clang_test_apps_esp32h2Some Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure LogSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Reason2 / 10linklink
build_template_appSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure LogSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Reason3 / 10linklink
check_public_headersSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Log4 / 10linklink
+ + + + + + diff --git a/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/expected_target_test_report.html b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/expected_target_test_report.html index b4c143879b32..4353e38771ab 100644 --- a/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/expected_target_test_report.html +++ b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/expected_target_test_report.html @@ -1,26 +1,32 @@ - + Test Report - - - - - - -

Failed Test Cases (Excludes Known Failure Cases)

+ + + + + +

Failed Test Cases on Your branch (Excludes Known Failure Cases)

+ @@ -30,20 +36,68 @@ + + + + + + + + + + + + + + + + + + +
Test Case Test Script File Path Failure ReasonFailures across all other branches (20 latest testcases) Job URL Grafana URL
('esp32h2', 'esp32h2').('defaults', 'defaults').test_i2c_multi_device components/driver/test_apps/i2c_test_apps/pytest_i2c.py failed on setup with "EOFError"0 / 20 link
esp32c3.release.test_esp_timercomponents/esp_timer/test_apps/pytest_esp_timer_ut.pypexpect.exceptions.TIMEOUT: Not found "Press ENTER to see the list of tests" Bytes in current buffer (color code eliminated): ce710,len:0x2afc entry 0x403cc710 Please check the full log here: /builds/espressif/esp-idf/pytest_embedded/2024-05-17_17-50-04/esp32c3.release.test_esp_timer/dut.txt0 / 20link
esp32c3.default.test_wpa_supplicant_utcomponents/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.pypexpect.exceptions.TIMEOUT: Not found "Press ENTER to see the list of tests" Bytes in current buffer (color code eliminated): 0 d4 000 00x0000 x0000x00 000000 0 Please check the full log here: /builds/espressif/esp-idf/pytest_embedded/2024-05-17_17-50-04/esp32c3.default.test_wpa_supplicant_ut/dut.txt0 / 20link

Failed Test Cases on Other branches (Excludes Known Failure Cases)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -174,5 +228,34 @@ - + + diff --git a/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/failure_rate_jobs_response.json b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/failure_rate_jobs_response.json new file mode 100644 index 000000000000..18e4bea1e215 --- /dev/null +++ b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/failure_rate_jobs_response.json @@ -0,0 +1,7 @@ +{ + "jobs": [ + {"failed_count": 2, "failure_ratio": 0.2, "total_count": 10, "name": "build_clang_test_apps_esp32h2"}, + {"failed_count": 3, "failure_ratio": 0.3, "total_count": 10, "name": "build_template_app"}, + {"failed_count": 4, "failure_ratio": 0.4, "total_count": 10, "name": "check_public_headers"} + ] +} diff --git a/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/jobs_api_response.json b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/jobs_api_response.json new file mode 100644 index 000000000000..844e2545b59f --- /dev/null +++ b/tools/ci/dynamic_pipelines/tests/test_report_generator/reports_sample_data/jobs_api_response.json @@ -0,0 +1,212 @@ +{ + "jobs": [ + { + "duration_sec": 42.158688, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:38:16, 24 May 2024", + "id": 48838677, + "name": "check_pre_commit", + "pending_sec": 1.15148, + "runner_name": "FA002598-build", + "stage": "pre_check", + "status": "success", + "url": "https://test.com/-/jobs/48838677" + }, + { + "duration_sec": 35.438477, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:37:32, 24 May 2024", + "id": 48838675, + "name": "run-danger-mr-linter", + "pending_sec": 0.371668, + "runner_name": "BrnoVM0211", + "stage": "pre_check", + "status": "success", + "url": "https://test.com/-/jobs/48838675" + }, + { + "duration_sec": 30.202475, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:37:28, 24 May 2024", + "id": 48838682, + "name": "check_esp_system", + "pending_sec": 1.148756, + "runner_name": "ruby6-cent9 [32]", + "stage": "pre_check", + "status": "success", + "url": "https://test.com/-/jobs/48838682" + }, + { + "duration_sec": 33.75121, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:37:31, 24 May 2024", + "id": 48838679, + "name": "check_blobs", + "pending_sec": 0.725292, + "runner_name": "gem3-cent9 [32]", + "stage": "pre_check", + "status": "success", + "url": "https://test.com/-/jobs/48838679" + }, + { + "duration_sec": 121.84324, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:41:35, 24 May 2024", + "id": 48838687, + "name": "code_quality_check", + "pending_sec": 0.271973, + "runner_name": "ruby15-cent9 [32]", + "stage": "build", + "status": "success", + "url": "https://test.com/-/jobs/48838687" + }, + { + "duration_sec": 153.68849, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:39:32, 24 May 2024", + "id": 48838686, + "name": "fast_template_app", + "pending_sec": 2.319577, + "runner_name": "FA002598-build", + "stage": "pre_check", + "status": "success", + "url": "https://test.com/-/jobs/48838686" + }, + { + "duration_sec": 25.572954, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:37:23, 24 May 2024", + "id": 48838684, + "name": "check_configure_ci_environment_parsing", + "pending_sec": 1.184287, + "runner_name": "gem3-cent9 [32]", + "stage": "pre_check", + "status": "success", + "url": "https://test.com/-/jobs/48838684" + }, + { + "duration_sec": 120.95287, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:41:34, 24 May 2024", + "id": 48838690, + "name": "build_clang_test_apps_esp32s3", + "pending_sec": 0.671956, + "runner_name": "ruby7-cent9 [32]", + "stage": "build", + "status": "success", + "url": "https://test.com/-/jobs/48838690" + }, + { + "duration_sec": 165.74513, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:42:19, 24 May 2024", + "id": 48838692, + "name": "build_clang_test_apps_esp32c2", + "pending_sec": 0.82007, + "runner_name": "PowerfulBuildRunner03 [16]", + "stage": "build", + "status": "success", + "url": "https://test.com/-/jobs/48838692" + }, + { + "duration_sec": 95.72326, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:41:09, 24 May 2024", + "id": 48838696, + "name": "build_clang_test_apps_esp32p4", + "pending_sec": 0.567116, + "runner_name": "gem3-cent9 [32]", + "stage": "build", + "status": "success", + "url": "https://test.com/-/jobs/48838696" + }, + { + "duration_sec": 122.19848, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:41:36, 24 May 2024", + "id": 48838691, + "name": "build_clang_test_apps_esp32c3", + "pending_sec": 0.709112, + "runner_name": "ruby6-cent9 [32]", + "stage": "build", + "status": "success", + "url": "https://test.com/-/jobs/48838691" + }, + { + "duration_sec": 148.09895, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:42:02, 24 May 2024", + "id": 48838694, + "name": "build_clang_test_apps_esp32c5", + "pending_sec": 0.779584, + "runner_name": "PowerfulBuildRunner04 [15]", + "stage": "build", + "status": "success", + "url": "https://test.com/-/jobs/48838694" + }, + { + "duration_sec": 20.275927, + "failure_log": null, + "failure_reason": null, + "finished_at": "03:39:54, 24 May 2024", + "id": 48838699, + "name": "gen_integration_pipeline", + "pending_sec": 0.868898, + "runner_name": "FA002598-build", + "stage": "assign_test", + "status": "success", + "url": "https://test.com/-/jobs/48838699" + }, + { + "duration_sec": 103.08849, + "failure_log": "Some Failure LogSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Reason", + "failure_reason": "Some Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Reason", + "finished_at": "03:41:17, 24 May 2024", + "id": 48838695, + "name": "build_clang_test_apps_esp32h2", + "pending_sec": 0.765111, + "runner_name": "gem2-cent9 [32]", + "stage": "build", + "status": "failed", + "url": "https://test.com/-/jobs/48838695" + }, + { + "duration_sec": 634.59467, + "failure_log": "Some Failure LogSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Reason", + "failure_reason": "Some Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Reason", + "finished_at": "03:50:09, 24 May 2024", + "id": 48838704, + "name": "build_template_app", + "pending_sec": 0.161796, + "runner_name": "ruby6-cent9 [32]", + "stage": "host_test", + "status": "failed", + "url": "https://test.com/-/jobs/48838704" + }, + { + "duration_sec": 1060.0835, + "failure_log": "Some Failure Log", + "failure_reason": "Some Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure ReasonSome Failure Reason", + "finished_at": "03:55:14, 24 May 2024", + "id": 48838705, + "name": "check_public_headers", + "pending_sec": 0.449408, + "runner_name": "ruby6-cent9 [32]", + "stage": "host_test", + "status": "failed", + "url": "https://test.com/-/jobs/48838705" + } + ] +} diff --git a/tools/ci/dynamic_pipelines/tests/test_report_generator/test_report_generator.py b/tools/ci/dynamic_pipelines/tests/test_report_generator/test_report_generator.py new file mode 100644 index 000000000000..551eaece9f5d --- /dev/null +++ b/tools/ci/dynamic_pipelines/tests/test_report_generator/test_report_generator.py @@ -0,0 +1,127 @@ +#!/usr/bin/env python +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import json +import os.path +import sys +import unittest +from unittest.mock import MagicMock +from unittest.mock import patch + +sys.path.insert(0, os.path.join(f'{os.environ.get("IDF_PATH")}', 'tools', 'ci', 'python_packages')) +sys.path.insert(0, os.path.join(f'{os.environ.get("IDF_PATH")}', 'tools', 'ci')) + +from dynamic_pipelines.models import GitlabJob # noqa: E402 +from dynamic_pipelines.report import JobReportGenerator, TargetTestReportGenerator # noqa: E402 +from dynamic_pipelines.utils import load_file, parse_testcases_from_filepattern # noqa: E402 + + +class TestReportGeneration(unittest.TestCase): + def setUp(self) -> None: + self.reports_sample_data_path = os.path.join( + os.environ.get('IDF_PATH', ''), 'tools', 'ci', 'dynamic_pipelines', 'tests', 'test_report_generator', 'reports_sample_data' + ) + self.setup_patches() + self.load_test_and_job_reports() + self.create_report_generators() + + def setup_patches(self) -> None: + self.gitlab_patcher = patch('dynamic_pipelines.report.Gitlab') + self.failure_rate_patcher = patch('dynamic_pipelines.report.fetch_failed_testcases_failure_ratio') + self.env_patcher = patch.dict('os.environ', { + 'CI_DASHBOARD_HOST': 'https://test_dashboard_host', + 'CI_PAGES_URL': 'https://artifacts_path', + 'CI_JOB_ID': '1', + }) + + self.MockGitlab = self.gitlab_patcher.start() + self.test_cases_failure_rate = self.failure_rate_patcher.start() + self.env_patcher.start() + + self.mock_project = MagicMock() + self.mock_mr = MagicMock() + self.MockGitlab.return_value.project = self.mock_project + self.mock_project.mergerequests.get.return_value = self.mock_mr + + self.addCleanup(self.gitlab_patcher.stop) + self.addCleanup(self.env_patcher.stop) + self.addCleanup(self.failure_rate_patcher.stop) + + def load_test_and_job_reports(self) -> None: + self.expected_target_test_report_html = load_file( + os.path.join(self.reports_sample_data_path, 'expected_target_test_report.html') + ) + self.expected_job_report_html = load_file( + os.path.join(self.reports_sample_data_path, 'expected_job_report.html') + ) + + def create_report_generators(self) -> None: + jobs_response_raw = load_file(os.path.join(self.reports_sample_data_path, 'jobs_api_response.json')) + failure_rate_jobs_response = load_file(os.path.join(self.reports_sample_data_path, 'failure_rate_jobs_response.json')) + failure_rates = {item['name']: item for item in json.loads(failure_rate_jobs_response).get('jobs', [])} + jobs = [GitlabJob.from_json_data(job_json, failure_rates.get(job_json['name'], {})) for job_json in json.loads(jobs_response_raw)['jobs']] + test_cases = parse_testcases_from_filepattern(os.path.join(self.reports_sample_data_path, 'XUNIT_*.xml')) + self.target_test_report_generator = TargetTestReportGenerator( + project_id=123, mr_iid=1, pipeline_id=456, title='Test Report', test_cases=test_cases) + self.job_report_generator = JobReportGenerator( + project_id=123, mr_iid=1, pipeline_id=456, title='Job Report', jobs=jobs) + self.target_test_report_generator._known_failure_cases_set = { + '*.test_wpa_supplicant_ut', + 'esp32c3.release.test_esp_timer', + '*.512safe.test_wear_levelling', + } + test_cases_failed = [tc for tc in test_cases if tc.is_failure] + for index, tc in enumerate(test_cases_failed): + tc.latest_total_count = 20 + if index % 3 == 0: + tc.latest_failed_count = 0 + else: + tc.latest_failed_count = 3 + self.test_cases_failure_rate.return_value = test_cases_failed + + def test_known_failure_cases(self) -> None: + known_failure_cases = self.target_test_report_generator.get_known_failure_cases() + self.assertEqual(len(known_failure_cases), 4) + + def test_failed_cases_in_target_test_report(self) -> None: + known_failures = self.target_test_report_generator.get_known_failure_cases() + known_failure_case_names = {case.name for case in known_failures} + failed_testcases = self.target_test_report_generator._filter_items( + self.target_test_report_generator.test_cases, + lambda tc: tc.is_failure and tc.name not in known_failure_case_names, + ) + self.assertEqual(len(failed_testcases), 3) + + def test_skipped_cases_in_target_test_report(self) -> None: + skipped_testcases = self.target_test_report_generator._filter_items( + self.target_test_report_generator.test_cases, lambda tc: tc.is_skipped + ) + self.assertEqual(len(skipped_testcases), 1) + + def test_successful_cases_in_target_test_report(self) -> None: + succeeded_testcases = self.target_test_report_generator._filter_items( + self.target_test_report_generator.test_cases, lambda tc: tc.is_success + ) + self.assertEqual(len(succeeded_testcases), 9) + + def test_target_test_report_html_structure(self) -> None: + report = self.target_test_report_generator._get_report_str() + self.assertEqual(report, self.expected_target_test_report_html) + + def test_failed_jobs_in_job_report(self) -> None: + failed_jobs = self.job_report_generator._filter_items(self.job_report_generator.jobs, lambda job: job.is_failed) + self.assertEqual(len(failed_jobs), 3) + + def test_successful_jobs_in_job_report(self) -> None: + succeeded_jobs = self.job_report_generator._filter_items( + self.job_report_generator.jobs, lambda job: job.is_success + ) + self.assertEqual(len(succeeded_jobs), 13) + + def test_job_report_html_structure(self) -> None: + report = self.job_report_generator._get_report_str() + self.assertEqual(report, self.expected_job_report_html) + + +if __name__ == '__main__': + unittest.main() diff --git a/tools/ci/dynamic_pipelines/tests/test_report_generator/test_target_test_report_generator.py b/tools/ci/dynamic_pipelines/tests/test_report_generator/test_target_test_report_generator.py deleted file mode 100644 index a3d517e3dc5b..000000000000 --- a/tools/ci/dynamic_pipelines/tests/test_report_generator/test_target_test_report_generator.py +++ /dev/null @@ -1,96 +0,0 @@ -#!/usr/bin/env python -# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 -import os.path -import sys -import unittest -from unittest.mock import MagicMock -from unittest.mock import patch - -sys.path.insert(0, os.path.join(f'{os.environ.get("IDF_PATH")}', 'tools', 'ci', 'python_packages')) -sys.path.insert(0, os.path.join(f'{os.environ.get("IDF_PATH")}', 'tools', 'ci')) - - -from dynamic_pipelines.report import TargetTestReportGenerator # noqa: E402 -from dynamic_pipelines.utils import parse_testcases_from_filepattern # noqa: E402 - - -class TestReportGeneration(unittest.TestCase): - @classmethod - def load_expected_report(cls, file_path: str) -> str: - """ - Loads the content of an expected report HTML file. - - :param file_path: The path to the file containing the expected HTML report. - :return: The content of the file as a string. - """ - with open(file_path, 'r') as file: - return file.read() - - def setUp(self) -> None: - patcher = patch('dynamic_pipelines.report.Gitlab') - env_patcher = patch.dict('os.environ', { - 'CI_DASHBOARD_HOST': 'https://test_dashboard_host', - 'CI_PAGES_URL': 'https://artifacts_path', - 'CI_JOB_ID': '1', - }) - env_patcher.start() - self.MockGitlab = patcher.start() - self.addCleanup(patcher.stop) - self.addCleanup(env_patcher.stop) - self.reports_sample_data_path = os.path.join( - os.environ.get('IDF_PATH', ''), # type: ignore - 'tools', - 'ci', - 'dynamic_pipelines', - 'tests', - 'test_report_generator', - 'reports_sample_data' - ) - self.mock_project = MagicMock() - self.mock_mr = MagicMock() - - self.MockGitlab.return_value.project = self.mock_project - self.mock_project.mergerequests.get.return_value = self.mock_mr - - self.expected_report_html = self.load_expected_report( - os.path.join(self.reports_sample_data_path, 'expected_target_test_report.html') - ) - - test_cases = parse_testcases_from_filepattern(os.path.join(self.reports_sample_data_path, 'XUNIT_*.xml')) - self.report_generator = TargetTestReportGenerator( - project_id=123, mr_iid=1, pipeline_id=456, title='Test Report', test_cases=test_cases - ) - self.report_generator._known_failure_cases_set = { - '*.test_wpa_supplicant_ut', - 'esp32c3.release.test_esp_timer', - '*.512safe.test_wear_levelling', - } - - def test_known_failure_cases(self) -> None: - known_failure_cases = self.report_generator.get_known_failure_cases() - self.assertEqual(len(known_failure_cases), 4) - - def test_failed_cases_in_report(self) -> None: - known_failures = self.report_generator.get_known_failure_cases() - known_failure_case_names = {case.name for case in known_failures} - failed_testcases = self.report_generator._filter_test_cases( - lambda tc: tc.is_failure and tc.name not in known_failure_case_names - ) - self.assertEqual(len(failed_testcases), 3) - - def test_skipped_cases_in_report(self) -> None: - skipped_testcases = self.report_generator._filter_test_cases(lambda tc: tc.is_skipped) - self.assertEqual(len(skipped_testcases), 1) - - def test_successful_cases_in_report(self) -> None: - succeeded_testcases = self.report_generator._filter_test_cases(lambda tc: tc.is_success) - self.assertEqual(len(succeeded_testcases), 9) - - def test_complete_html_structure(self) -> None: - report = self.report_generator._get_report_str() - self.assertEqual(report, self.expected_report_html) - - -if __name__ == '__main__': - unittest.main() diff --git a/tools/ci/dynamic_pipelines/utils.py b/tools/ci/dynamic_pipelines/utils.py index d10bfce50a96..c8252f58ad04 100644 --- a/tools/ci/dynamic_pipelines/utils.py +++ b/tools/ci/dynamic_pipelines/utils.py @@ -7,8 +7,10 @@ import xml.etree.ElementTree as ET from urllib.parse import urlparse +import requests import yaml +from .models import GitlabJob from .models import Job from .models import TestCase @@ -81,3 +83,86 @@ def is_url(string: str) -> bool: """ parsed = urlparse(string) return bool(parsed.scheme) and bool(parsed.netloc) + + +def fetch_failed_jobs(commit_id: str) -> t.List[GitlabJob]: + """ + Fetches a list of jobs from the specified commit_id using an API request to ci-dashboard-api. + :param commit_id: The commit ID for which to fetch jobs. + :return: A list of jobs if the request is successful, otherwise an empty list. + """ + token = os.getenv('ESPCI_TOKEN', '') + ci_dash_api_backend_host = os.getenv('CI_DASHBOARD_API', '') + response = requests.get( + f'{ci_dash_api_backend_host}/commits/{commit_id}/jobs', + headers={'Authorization': f'Bearer {token}'} + ) + if response.status_code != 200: + print(f'Failed to fetch jobs data: {response.status_code} with error: {response.text}') + return [] + + data = response.json() + jobs = data.get('jobs', []) + + if not jobs: + return [] + + failed_job_names = [job['name'] for job in jobs if job['status'] == 'failed'] + response = requests.post( + f'{ci_dash_api_backend_host}/jobs/failure_ratio', + headers={'Authorization': f'Bearer {token}'}, + json={'job_names': failed_job_names, 'exclude_branches': [os.getenv('CI_COMMIT_BRANCH', '')]}, + ) + if response.status_code != 200: + print(f'Failed to fetch jobs failure rate data: {response.status_code} with error: {response.text}') + return [] + + failure_rate_data = response.json() + failure_rates = {item['name']: item for item in failure_rate_data.get('jobs', [])} + + combined_jobs = [] + for job in jobs: + failure_data = failure_rates.get(job['name'], {}) + combined_jobs.append(GitlabJob.from_json_data(job, failure_data)) + + return combined_jobs + + +def fetch_failed_testcases_failure_ratio(failed_testcases: t.List[TestCase]) -> t.List[TestCase]: + """ + Fetches info about failure rates of testcases using an API request to ci-dashboard-api. + :param failed_testcases: The list of failed testcases models. + :return: A list of testcases with enriched with failure rates data. + """ + token = os.getenv('ESPCI_TOKEN', '') + ci_dash_api_backend_host = os.getenv('CI_DASHBOARD_API', '') + response = requests.post( + f'{ci_dash_api_backend_host}/testcases/failure_ratio', + headers={'Authorization': f'Bearer {token}'}, + json={'testcase_names': [testcase.name for testcase in failed_testcases], + 'exclude_branches': [os.getenv('CI_COMMIT_BRANCH', '')], + }, + ) + if response.status_code != 200: + print(f'Failed to fetch testcases failure rate data: {response.status_code} with error: {response.text}') + return [] + + failure_rate_data = response.json() + failure_rates = {item['name']: item for item in failure_rate_data.get('testcases', [])} + + for testcase in failed_testcases: + testcase.latest_total_count = failure_rates.get(testcase.name, {}).get('total_count', 0) + testcase.latest_failed_count = failure_rates.get(testcase.name, {}).get('failed_count', 0) + + return failed_testcases + + +def load_file(file_path: str) -> str: + """ + Loads the content of a file. + + :param file_path: The path to the file needs to be loaded. + :return: The content of the file as a string. + """ + with open(file_path, 'r') as file: + return file.read() diff --git a/tools/cmake/build.cmake b/tools/cmake/build.cmake index 85b11d00391e..a86340a75208 100644 --- a/tools/cmake/build.cmake +++ b/tools/cmake/build.cmake @@ -61,6 +61,35 @@ function(idf_build_unset_property property) idf_build_set_property(__BUILD_PROPERTIES "${build_properties}") endfunction() +# idf_build_replace_option_from_property +# +# @brief Replace specified option with new one in a given property. +# +# @param[in] property_name the property in which to replace the options (ex.: COMPILE_OPTIONS, C_COMPILE_OPTIONS,..) +# +# @param[in] option_to_remove the option to be replaced +# @param[in] new_option the option to replace with (if empty, the old option will be removed) +# +# Example usage: +# idf_build_replace_options_from_property(COMPILE_OPTIONS "-Werror" "-Werror=all") +# idf_build_replace_options_from_property(COMPILE_OPTIONS "-Wno-error=extra" "") +# +function(idf_build_replace_option_from_property property_name option_to_remove new_option) + idf_build_get_property(current_list_of_options ${property_name}) + + set(new_list_of_options) + foreach(option ${current_list_of_options}) + if(option STREQUAL option_to_remove) + list(APPEND new_list_of_options "${new_option}") + else() + list(APPEND new_list_of_options "${option}") + endif() + endforeach() + + # Set the updated list back + idf_build_set_property(${property_name} "${new_list_of_options}") +endfunction() + # # Retrieve the IDF_PATH repository's version, either using a version # file or Git revision. Sets the IDF_VER build property. @@ -101,12 +130,13 @@ function(__build_set_default_build_specifications) "-fdata-sections" # warning-related flags "-Wall" - "-Werror=all" + "-Werror" "-Wno-error=unused-function" "-Wno-error=unused-variable" "-Wno-error=unused-but-set-variable" "-Wno-error=deprecated-declarations" "-Wextra" + "-Wno-error=extra" "-Wno-unused-parameter" "-Wno-sign-compare" # ignore multiple enum conversion warnings since gcc 11 diff --git a/tools/esp_prov/transport/transport_console.py b/tools/esp_prov/transport/transport_console.py index 8fbcc2fe9c1d..246a15e7aaa9 100644 --- a/tools/esp_prov/transport/transport_console.py +++ b/tools/esp_prov/transport/transport_console.py @@ -1,8 +1,7 @@ -# SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # - -from utils import hex_str_to_bytes, str_to_bytes +from utils import str_to_bytes from .transport import Transport @@ -16,4 +15,4 @@ async def send_data(self, path, data, session_id=0): except Exception as err: print('error:', err) return None - return hex_str_to_bytes(resp) + return bytearray.fromhex(resp).decode('latin-1') diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index baff996045dd..78a16b9be423 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -320,6 +320,11 @@ re: "Error: libusb_open\\(\\) failed with LIBUSB_ERROR_NOT_FOUND" hint: "Device drivers are not correct.\nPlease check configuration of USB drivers: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/configure-ft2232h-jtag.html?highlight=zadig#configure-usb-drivers" +- + re: "-Werror=(address-of-packed-member|aggressive-loop-optimizations|attribute-warning|builtin-macro-redefined|cpp|designated-init|deprecated-declarations|discarded-array-qualifiers|discarded-qualifiers|div-by-zero|endif-labels|free-nonheap-object|if-not-aligned|ignored-attributes|incompatible-pointer-types|int-conversion|int-to-pointer-cast|lto-type-mismatch|multichar|overflow|override-init-side-effects|packed-bitfield-compat|pointer-compare|pointer-to-int-cast|return-local-addr|scalar-storage-order|shift-count-negative|shift-count-overflow|sizeof-array-argument|stringop-truncation| switch-bool|switch-outside-range|varargs)" + hint: "The error(s) '{}' may appear after IDF upgrade since previous versions were not considering those warnings as errors.\nTo suppress these warnings use 'idf.py menuconfig' to enable configure option 'Compiler options' -> 'Disabe errors for default warnings'\nPlease note that this is not a permanent solution, and this option will be removed in a future update of the ESP-IDF.\nIt is strongly recommended to fix all warnings, as they may indicate potential issues!" + match_to_output: True + - re: "(-Werror=address|-Werror=use-after-free)" hint: "The warning(s) '{}' may appear after compiler update above GCC-12\nTo suppress these warnings use 'idf.py menuconfig' to enable configure option 'Compiler options' -> 'Disable new warnings introduced in GCC 12'\nPlease note that this is not a permanent solution, and this option will be removed in a future update of the ESP-IDF.\nIt is strongly recommended to fix all warnings, as they may indicate potential issues!" diff --git a/tools/idf_py_actions/serial_ext.py b/tools/idf_py_actions/serial_ext.py index 71b649b7c9f4..bc7218abda2f 100644 --- a/tools/idf_py_actions/serial_ext.py +++ b/tools/idf_py_actions/serial_ext.py @@ -12,6 +12,7 @@ from typing import Tuple import click +from idf_py_actions.errors import FatalError from idf_py_actions.global_options import global_options from idf_py_actions.tools import ensure_build_directory from idf_py_actions.tools import get_default_serial_port @@ -117,12 +118,10 @@ def monitor( if project_desc['target'] != 'linux': if no_reset and args.port is None: - msg = ( - 'WARNING: --no-reset is ignored. ' + raise FatalError( + 'Error: --no-reset is only supported when used with a port.' 'Please specify the port with the --port argument in order to use this option.' ) - yellow_print(msg) - no_reset = False args.port = args.port or get_default_serial_port() monitor_args += ['-p', args.port] @@ -927,7 +926,8 @@ def efuse_write_protect(action: str, ctx: click.core.Context, args: PropertyDict 'help': ( 'Disable reset on monitor startup. ' 'IDF Monitor will not reset the MCU target by toggling DTR/RTS lines on startup ' - 'if this option is set.' + 'if this option is set. ' + 'This option only works if --port argument is specified.' ), }, { diff --git a/tools/test_apps/configs/sdkconfig.debug_helpers b/tools/test_apps/configs/sdkconfig.debug_helpers index 9bb49614b9ae..2193c60124ae 100644 --- a/tools/test_apps/configs/sdkconfig.debug_helpers +++ b/tools/test_apps/configs/sdkconfig.debug_helpers @@ -5,3 +5,4 @@ CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y CONFIG_COMPILER_STACK_CHECK=y CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES=y +CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS=n diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml index 64f3807f118b..8d2ca6ffd4dc 100644 --- a/tools/test_apps/system/.build-test-rules.yml +++ b/tools/test_apps/system/.build-test-rules.yml @@ -45,12 +45,6 @@ tools/test_apps/system/gdb_loadable_elf: temporary: true reason: target esp32c6, esp32h2 is not supported yet -tools/test_apps/system/gdbstub_runtime: - disable: - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: not supported yet #TODO: IDF-7510 - tools/test_apps/system/longjmp_test: enable: - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3"] diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.werror b/tools/test_apps/system/build_test/sdkconfig.ci.werror new file mode 100644 index 000000000000..613937594cdd --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.werror @@ -0,0 +1 @@ +CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS=n diff --git a/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt b/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt index 695b17a1b3ee..59cbf3f832ab 100644 --- a/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt +++ b/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt @@ -1,6 +1,12 @@ -idf_component_register(SRCS cxx_build_test_main.cpp - test_soc_reg_macros.cpp - test_cxx_standard.cpp +set(srcs cxx_build_test_main.cpp + test_soc_reg_macros.cpp + test_cxx_standard.cpp) + +if(CONFIG_SOC_I2C_SUPPORTED) + list(APPEND srcs test_i2c_lcd.cpp) +endif() + +idf_component_register(SRCS "${srcs}" INCLUDE_DIRS "." - PRIV_REQUIRES driver + PRIV_REQUIRES driver esp_lcd REQUIRES soc) diff --git a/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp b/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp new file mode 100644 index 000000000000..cb058d62c06c --- /dev/null +++ b/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "esp_lcd_panel_vendor.h" +#include "esp_lcd_panel_io.h" +#include "driver/i2c_master.h" + +const esp_lcd_panel_dev_config_t panel_config0 = { + .reset_gpio_num = 0, + .color_space = ESP_LCD_COLOR_SPACE_MONOCHROME, + .data_endian = LCD_RGB_DATA_ENDIAN_LITTLE, + .bits_per_pixel = 16, + .flags = { + .reset_active_high = false, + }, + .vendor_config = NULL, +}; + +const esp_lcd_panel_dev_config_t panel_config1 = { + .reset_gpio_num = 0, + .color_space = ESP_LCD_COLOR_SPACE_BGR, + .data_endian = LCD_RGB_DATA_ENDIAN_LITTLE, + .bits_per_pixel = 16, + .flags = { + .reset_active_high = false, + }, + .vendor_config = NULL, +}; + +const esp_lcd_panel_dev_config_t panel_config2 = { + .reset_gpio_num = 0, + .rgb_endian = LCD_RGB_ENDIAN_BGR, + .data_endian = LCD_RGB_DATA_ENDIAN_LITTLE, + .bits_per_pixel = 16, + .flags = { + .reset_active_high = false, + }, + .vendor_config = NULL, +}; + +void test_i2c_lcd_apis(void) +{ + i2c_master_bus_config_t i2c_bus_conf = { + .i2c_port = -1, + .sda_io_num = GPIO_NUM_0, + .scl_io_num = GPIO_NUM_2, + .clk_source = I2C_CLK_SRC_DEFAULT, + .glitch_ignore_cnt = 0, + .intr_priority = 1, + .trans_queue_depth = 4, + .flags = { + .enable_internal_pullup = true, + } + }; + + i2c_master_bus_handle_t bus_handle; + i2c_new_master_bus(&i2c_bus_conf, &bus_handle); + + esp_lcd_panel_io_handle_t io_handle = NULL; + esp_lcd_panel_io_i2c_config_t io_config = { + .dev_addr = 0x3c, + .on_color_trans_done = NULL, + .user_ctx = NULL, + .control_phase_bytes = 1, + .dc_bit_offset = 6, + .lcd_cmd_bits = 8, + .lcd_param_bits = 8, + .flags = { + .dc_low_on_data = false, + .disable_control_phase = false, + }, + .scl_speed_hz = 10 * 1000, + }; + + esp_lcd_new_panel_io_i2c(bus_handle, &io_config, &io_handle); +} diff --git a/tools/test_apps/system/gdbstub_runtime/README.md b/tools/test_apps/system/gdbstub_runtime/README.md index 56b3c23513fb..3a502b1f86f4 100644 --- a/tools/test_apps/system/gdbstub_runtime/README.md +++ b/tools/test_apps/system/gdbstub_runtime/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/tools/test_apps/system/gdbstub_runtime/pytest_runtime.py b/tools/test_apps/system/gdbstub_runtime/pytest_runtime.py index 040e7f2c8352..f2c3fa2c08a3 100644 --- a/tools/test_apps/system/gdbstub_runtime/pytest_runtime.py +++ b/tools/test_apps/system/gdbstub_runtime/pytest_runtime.py @@ -1,5 +1,6 @@ # SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 +import os import os.path as path import sys @@ -18,7 +19,6 @@ def get_line_number(lookup: str, offset: int = 0) -> int: return -1 -@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD') # TODO: IDF-8992 @pytest.mark.supported_targets @pytest.mark.generic def test_gdbstub_runtime(dut: PanicTestDut) -> None: @@ -106,7 +106,8 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: assert dut.find_gdb_response('running', 'notify', responses) is not None # test ctrl-c - responses = dut.gdbmi.send_signal_to_gdb(2) + os.kill(dut.gdbmi.gdb_process.pid, 2) + # responses = dut.gdbmi.send_signal_to_gdb(2) # https://github.com/cs01/pygdbmi/issues/97 # assert dut.find_gdb_response('stopped', 'notify', responses) is not None # ?? No response? check we stopped dut.gdb_backtrace() diff --git a/tools/tools_schema.json b/tools/tools_schema.json index e4c756f711c2..5c3efad01297 100644 --- a/tools/tools_schema.json +++ b/tools/tools_schema.json @@ -218,7 +218,7 @@ "type": "array", "items": { "type": "string", - "enum": ["linux-i686", "linux-amd64", "linux-armel", "linux-arm64", "macos", "macos-arm64", "win32", "win64"] + "enum": ["linux-i686", "linux-amd64", "linux-armel", "linux-armhf", "linux-arm64", "macos", "macos-arm64", "win32", "win64"] } }, "export_paths": {
Test CaseTest Script File PathFailure ReasonFailures across all other branches (20 latest testcases)Job URLGrafana URL
('esp32h2', 'esp32h2').('default', 'default').test_i2s_multi_dev components/driver/test_apps/i2s_test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py failed on setup with "EOFError"3 / 20 link
esp32c2.default.test_wpa_supplicant_utcomponents/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.pyAssertionError: Unity test failed3 / 20link
esp32c3.512safe.test_wear_levellingcomponents/wear_levelling/test_apps/pytest_wear_levelling.pypexpect.exceptions.TIMEOUT: Not found "re.compile(b'^[-]+\\s*(\\d+) Tests (\\d+) Failures (\\d+) Ignored\\s*(?POK|FAIL)', re.MULTILINE)" Bytes in current buffer (color code eliminated): Serial port /dev/ttyUSB16 Connecting.... Connecting.... esptool.py v4.7.0 Found 1 serial ports Chip is ESP32-C3 (QFN32) (revision v0.3) Features: WiFi, BLE, Embedded Flash 4MB... (total 6673 bytes) Please check the full log here: /builds/espressif/esp-idf/pytest_embedded/2024-05-17_17-50-04/esp32c3.512safe.test_wear_levelling/dut.txt3 / 20link
esp32c3.release.test_wear_levelling components/wear_levelling/test_apps/pytest_wear_levelling.py pexpect.exceptions.TIMEOUT: Not found "re.compile(b'^[-]+\\s*(\\d+) Tests (\\d+) Failures (\\d+) Ignored\\s*(?POK|FAIL)', re.MULTILINE)" Bytes in current buffer (color code eliminated): Serial port /dev/ttyUSB16 Connecting.... Connecting.... esptool.py v4.7.0 Found 1 serial ports Chip is ESP32-C3 (QFN32) (revision v0.3) Features: WiFi, BLE, Embedded Flash 4MB... (total 24528 bytes) Please check the full log here: /builds/espressif/esp-idf/pytest_embedded/2024-05-17_17-50-04/esp32c3.release.test_wear_levelling/dut.txt3 / 20 link