From a80fb72f7756baf1f81469f5cacf46a885018376 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Fri, 27 Oct 2023 10:55:01 +0800 Subject: [PATCH 01/15] fix(adc): fix adc oneshot mod do not split clk --- components/hal/adc_hal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index 614a3117a72..625fbc36deb 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -491,6 +491,8 @@ static bool adc_hal_intr_get_raw(adc_hal_event_t event) //--------------------Single Read-------------------------------// static void adc_hal_onetime_start(void) { + adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT); + adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT); /** * There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the * ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller From 61ac7f8a91e1f28567cd52d9408915e6f50e5cdb Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 4 Jan 2024 12:03:53 +0800 Subject: [PATCH 02/15] fix(cache): fix wrong dcache size 0 configuration issue on s2 Closes https://github.com/espressif/esp-idf/issues/12711 --- components/spi_flash/cache_utils.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index 3e0f0ba2d05..d415d26b5ec 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -401,12 +401,17 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void) IRAM_ATTR void esp_config_data_cache_mode(void) { +#define CACHE_SIZE_0KB 99 //If Cache set to 0 KB, cache is bypassed, the cache size doesn't take into effect. Set this macro to a unique value for log + cache_size_t cache_size; cache_ways_t cache_ways; cache_line_size_t cache_line_size; #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB -#if CONFIG_ESP32S2_DATA_CACHE_8KB +#if CONFIG_ESP32S2_DATA_CACHE_0KB + Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID); + cache_size = CACHE_SIZE_0KB; +#elif CONFIG_ESP32S2_DATA_CACHE_8KB Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID); cache_size = CACHE_SIZE_8KB; #else @@ -414,7 +419,10 @@ IRAM_ATTR void esp_config_data_cache_mode(void) cache_size = CACHE_SIZE_16KB; #endif #else -#if CONFIG_ESP32S2_DATA_CACHE_8KB +#if CONFIG_ESP32S2_DATA_CACHE_0KB + Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID); + cache_size = CACHE_SIZE_0KB; +#elif CONFIG_ESP32S2_DATA_CACHE_8KB Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID); cache_size = CACHE_SIZE_8KB; #else @@ -429,7 +437,7 @@ IRAM_ATTR void esp_config_data_cache_mode(void) #else cache_line_size = CACHE_LINE_SIZE_32B; #endif - ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32); + ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", (cache_size == CACHE_SIZE_0KB) ? 0 : ((cache_size == CACHE_SIZE_8KB) ? 8 : 16), 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32); Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size); Cache_Invalidate_DCache_All(); } From 2746916f21c01a5729f528c1c51d2202bc4e829e Mon Sep 17 00:00:00 2001 From: Rahul Tank Date: Wed, 17 Jan 2024 14:41:27 +0530 Subject: [PATCH 03/15] fix(nimble): Add minor debug fixes --- components/bt/host/nimble/nimble | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index c50690e1b77..13edbb9a047 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit c50690e1b7794b9485921b1991b86387141832c0 +Subproject commit 13edbb9a04772d8629e575f60fcbb1db3fef8fce From 75b4fb5a663b92a29cf7bf19bd5884a7731db22c Mon Sep 17 00:00:00 2001 From: zhangyanjiao Date: Thu, 25 Jan 2024 11:05:53 +0800 Subject: [PATCH 04/15] feat(lwip): add fall back dns config in menuconfig Closes https://github.com/espressif/esp-idf/issues/12530 --- components/lwip/Kconfig | 31 +++++++++++++++++-- components/lwip/lwip | 2 +- components/lwip/port/esp32/include/lwipopts.h | 15 +++++++-- 3 files changed, 42 insertions(+), 6 deletions(-) diff --git a/components/lwip/Kconfig b/components/lwip/Kconfig index 779b3c8ffc3..13a78a2f431 100644 --- a/components/lwip/Kconfig +++ b/components/lwip/Kconfig @@ -656,8 +656,8 @@ menu "LWIP" cause Wi-Fi/Ethernet fail to release RX buffer in time. It is possible that all RX buffers for MAC layer are used by OOSEQ. - Control the number of out-of-order pbufs to ensure that the MAC layer has enough RX buffer - to receive packets. + Control the number of out-of-order pbufs to ensure that the MAC layer has + enough RX buffer to receive packets. In the Wi-Fi scenario, recommended OOSEQ PBUFS Range: 0 <= TCP_OOSEQ_MAX_PBUFS <= CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM/(MAX_TCP_NUMBER + 1) @@ -1010,6 +1010,33 @@ menu "LWIP" endmenu # SNTP + menu "DNS" + + config LWIP_DNS_MAX_SERVERS + int "Maximum number of DNS servers" + default 3 + range 1 4 + help + Set maximum number of DNS servers. + If fallback DNS servers are supported, + the number of DNS servers needs to be greater than or equal to 3. + + config LWIP_FALLBACK_DNS_SERVER_SUPPORT + bool "Enable DNS fallback server support" + default n + depends on LWIP_DNS_MAX_SERVERS >= 3 + help + Enable this feature to support DNS fallback server. + + config LWIP_FALLBACK_DNS_SERVER_ADDRESS + string "DNS fallback server address" + default "114.114.114.114" + depends on LWIP_FALLBACK_DNS_SERVER_SUPPORT + help + This option allows you to config dns fallback server address. + + endmenu # DNS + config LWIP_ESP_LWIP_ASSERT bool "Enable LWIP ASSERT checks" default y diff --git a/components/lwip/lwip b/components/lwip/lwip index 1de11efadd0..a45be9e438f 160000 --- a/components/lwip/lwip +++ b/components/lwip/lwip @@ -1 +1 @@ -Subproject commit 1de11efadd0083469f26c8782be3d55073829767 +Subproject commit a45be9e438f6cf9c54ec150581819c3b95d5af6b diff --git a/components/lwip/port/esp32/include/lwipopts.h b/components/lwip/port/esp32/include/lwipopts.h index ece4fe337d9..ef838b65a7b 100644 --- a/components/lwip/port/esp32/include/lwipopts.h +++ b/components/lwip/port/esp32/include/lwipopts.h @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * SPDX-FileContributor: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2015-2024 Espressif Systems (Shanghai) CO LTD */ #ifndef __LWIPOPTS_H__ @@ -375,8 +375,16 @@ static inline uint32_t timeout_from_offered(uint32_t lease, uint32_t min) */ #define LWIP_DNS 1 -#define DNS_MAX_SERVERS 3 -#define DNS_FALLBACK_SERVER_INDEX (DNS_MAX_SERVERS - 1) +#define DNS_MAX_SERVERS CONFIG_LWIP_DNS_MAX_SERVERS +#define DNS_FALLBACK_SERVER_INDEX (DNS_MAX_SERVERS - 1) + +#ifdef CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT +#define FALLBACK_DNS_SERVER_ADDRESS(address) \ + do { ip_addr_t *server_dns = address; \ + char server_ip[] = CONFIG_LWIP_FALLBACK_DNS_SERVER_ADDRESS; \ + ipaddr_aton(server_ip, server_dns); \ + } while (0) +#endif /* CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT */ /* --------------------------------- @@ -1123,6 +1131,7 @@ static inline uint32_t timeout_from_offered(uint32_t lease, uint32_t min) #define ESP_LWIP_LOCK 1 #define ESP_THREAD_PROTECTION 1 #define ESP_IP_FORWARD 1 +#define ESP_LWIP_FALLBACK_DNS_PREFER_IPV4 0 #ifdef CONFIG_LWIP_IPV6_AUTOCONFIG #define ESP_IPV6_AUTOCONFIG CONFIG_LWIP_IPV6_AUTOCONFIG From 6340b958fe00162ea1c562448ff639db084b96b0 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Thu, 11 Jan 2024 20:12:44 +0800 Subject: [PATCH 05/15] fix(i2s): fixed incorrect reg base name on C3 Closes https://github.com/espressif/esp-idf/issues/12643 --- components/soc/esp32c3/include/soc/soc.h | 2 +- components/soc/esp32h2/include/soc/soc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index dca148feca9..72b5a5f7d6d 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -72,7 +72,7 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index db5c19720e3..ace5d258f7e 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -100,7 +100,7 @@ #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) // only one I2S on H2 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) From b244b6e86b9292d03d7ba3da5331d2caf13215ee Mon Sep 17 00:00:00 2001 From: Ondrej Kosta Date: Mon, 22 Jan 2024 10:45:59 +0100 Subject: [PATCH 06/15] ci(esp_eth): enabled Ethernet IP101 runner back Moved LAN8720 test to different runner --- .gitlab/ci/target-test.yml | 10 +++- .../esp_eth/test_apps/component_ut_test.py | 34 +++++++------ .../esp_eth/test_apps/main/esp_eth_test.c | 51 +++++++++++++++---- 3 files changed, 68 insertions(+), 27 deletions(-) diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index 02c13671caa..be84866f303 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -782,8 +782,16 @@ UT_S3_FLASH: - ESP32S3_IDF - UT_T1_ESP_FLASH +component_ut_test_ip101: + extends: .component_ut_esp32_template + image: $CI_DOCKER_REGISTRY/ubuntu-test-env + tags: + - ESP32 + - eth_ip101 + component_ut_test_lan8720: extends: .component_ut_esp32_template + image: $CI_DOCKER_REGISTRY/ubuntu-test-env tags: - ESP32 - - COMPONENT_UT_LAN8720 + - eth_lan8720 diff --git a/components/esp_eth/test_apps/component_ut_test.py b/components/esp_eth/test_apps/component_ut_test.py index ce5c94bb5bf..e0c54d1e420 100644 --- a/components/esp_eth/test_apps/component_ut_test.py +++ b/components/esp_eth/test_apps/component_ut_test.py @@ -19,6 +19,8 @@ def configure_eth_if(func): # type: (typing.Any) -> typing.Any def inner(*args, **kwargs): # type: (typing.Any, typing.Any) -> typing.Any # try to determine which interface to use netifs = os.listdir('/sys/class/net/') + # order matters - ETH NIC with the highest number is connected to DUT on CI runner + netifs.sort(reverse=True) target_if = '' print('detected interfaces: ' + str(netifs)) for netif in netifs: @@ -65,17 +67,19 @@ def send_eth_packet(so, mac): # type: (socket.socket, str) -> None @configure_eth_if def recv_resp_poke(so, i): # type: (socket.socket, int) -> None - so.settimeout(10) + so.settimeout(30) try: - eth_frame = Ether(so.recv(60)) - - if eth_frame.type == 0x2222 and eth_frame.load[0] == 0xfa: - if eth_frame.load[1] != i: - raise Exception('Missed Poke Packet') - eth_frame.dst = eth_frame.src - eth_frame.src = so.getsockname()[4] - eth_frame.load = bytes.fromhex('fb') # POKE_RESP code - so.send(raw(eth_frame)) + for _ in range(10): + eth_frame = Ether(so.recv(60)) + + if eth_frame.type == 0x2222 and eth_frame.load[0] == 0xfa: + if eth_frame.load[1] != i: + raise Exception('Missed Poke Packet') + eth_frame.dst = eth_frame.src + eth_frame.src = so.getsockname()[4] + eth_frame.load = bytes.fromhex('fb') # POKE_RESP code + so.send(raw(eth_frame)) + break except Exception as e: raise e @@ -145,16 +149,16 @@ def test_component_ut_esp_eth(env, appname): # type: (tiny_test_fw.Env, str) -> ttfw_idf.ComponentUTResult.parse_result(stdout, test_format=TestFormat.UNITY_BASIC) -# @ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_IP101', target=['esp32']) -# def test_component_ut_esp_eth_ip101(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None -# test_component_ut_esp_eth(env, 'ip101') +@ttfw_idf.idf_component_unit_test(env_tag='eth_ip101', target=['esp32']) +def test_component_ut_esp_eth_ip101(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None + test_component_ut_esp_eth(env, 'ip101') -@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_LAN8720', target=['esp32']) +@ttfw_idf.idf_component_unit_test(env_tag='eth_lan8720', target=['esp32']) def test_component_ut_esp_eth_lan8720(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None test_component_ut_esp_eth(env, 'lan8720') if __name__ == '__main__': - # test_component_ut_esp_eth_ip101() + test_component_ut_esp_eth_ip101() test_component_ut_esp_eth_lan8720() diff --git a/components/esp_eth/test_apps/main/esp_eth_test.c b/components/esp_eth/test_apps/main/esp_eth_test.c index eb6f77cf363..c7eee060d46 100644 --- a/components/esp_eth/test_apps/main/esp_eth_test.c +++ b/components/esp_eth/test_apps/main/esp_eth_test.c @@ -58,6 +58,7 @@ TEST_CASE("start_and_stop", "[esp_eth]") #if defined(CONFIG_TARGET_ETH_PHY_DEVICE_IP101) esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // create PHY instance #elif defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) + phy_config.phy_addr = 0; esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config); #endif TEST_ASSERT_NOT_NULL(phy); @@ -109,6 +110,7 @@ TEST_CASE("get_set_mac", "[esp_eth]") #if defined(CONFIG_TARGET_ETH_PHY_DEVICE_IP101) esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // create PHY instance #elif defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) + phy_config.phy_addr = 0; esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config); #endif TEST_ASSERT_NOT_NULL(phy); @@ -139,6 +141,8 @@ TEST_CASE("get_set_mac", "[esp_eth]") vSemaphoreDelete(mutex); } +static uint8_t local_mac_addr[6] = {}; + TEST_CASE("ethernet_broadcast_transmit", "[esp_eth]") { void eth_event_handler(void *arg, esp_event_base_t event_base, @@ -162,6 +166,7 @@ TEST_CASE("ethernet_broadcast_transmit", "[esp_eth]") #if defined(CONFIG_TARGET_ETH_PHY_DEVICE_IP101) esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // create PHY instance #elif defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) + phy_config.phy_addr = 0; esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config); #endif TEST_ASSERT_NOT_NULL(phy); @@ -173,19 +178,22 @@ TEST_CASE("ethernet_broadcast_transmit", "[esp_eth]") TEST_ESP_OK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, ð_event_handler, mutex)); TEST_ASSERT_EQUAL(ESP_OK, esp_eth_start(eth_handle)); // start Ethernet driver state machine + TEST_ASSERT_EQUAL(ESP_OK, mac->get_addr(mac, local_mac_addr)); + TEST_ASSERT(xSemaphoreTake(mutex, pdMS_TO_TICKS(3000))); - // even if PHY (IP101) indicates autonegotiation done and link up, it sometimes may miss few packets after atonego reset, hence wait a bit - vTaskDelay(pdMS_TO_TICKS(100)); + // even if PHY indicates link up, it sometimes may miss few packets since switch port may not be forwarding yet (executing RSTP) + vTaskDelay(pdMS_TO_TICKS(500)); emac_frame_t *pkt = malloc(1024); pkt->proto = 0x2222; + memcpy(pkt->src, local_mac_addr, 6); memset(pkt->dest, 0xff, 6); // broadcast addr for (int i = 0; i < (1024 - ETH_HEADER_LEN); ++i){ pkt->data[i] = i & 0xff; } TEST_ASSERT_EQUAL(ESP_OK, esp_eth_transmit(eth_handle, pkt, 1024)); - vTaskDelay(pdMS_TO_TICKS(100)); + vTaskDelay(pdMS_TO_TICKS(500)); free(pkt); TEST_ASSERT_EQUAL(ESP_OK, esp_eth_stop(eth_handle)); @@ -196,8 +204,6 @@ TEST_CASE("ethernet_broadcast_transmit", "[esp_eth]") vSemaphoreDelete(mutex); } -static uint8_t local_mac_addr[6] = {}; - esp_err_t l2_packet_txrx_test_cb(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv) { EventGroupHandle_t eth_event_group = (EventGroupHandle_t)priv; emac_frame_t *pkt = (emac_frame_t *) buffer; @@ -224,6 +230,20 @@ esp_err_t l2_packet_txrx_test_cb(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t TEST_CASE("recv_pkt", "[esp_eth]") { + void eth_event_handler(void *arg, esp_event_base_t event_base, + int32_t event_id, void *event_data){ + SemaphoreHandle_t mutex = (SemaphoreHandle_t)arg; + switch (event_id) { + case ETHERNET_EVENT_CONNECTED: + xSemaphoreGive(mutex); + break; + default: + break; + } + } + SemaphoreHandle_t mutex = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_NULL(mutex); + EventGroupHandle_t eth_event_group = xEventGroupCreate(); TEST_ASSERT(eth_event_group != NULL); @@ -234,6 +254,7 @@ TEST_CASE("recv_pkt", "[esp_eth]") #if defined(CONFIG_TARGET_ETH_PHY_DEVICE_IP101) esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // create PHY instance #elif defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) + phy_config.phy_addr = 0; esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config); #endif TEST_ASSERT_NOT_NULL(phy); @@ -242,8 +263,13 @@ TEST_CASE("recv_pkt", "[esp_eth]") TEST_ASSERT_EQUAL(ESP_OK, esp_eth_driver_install(&config, ð_handle)); // install driver TEST_ASSERT_NOT_NULL(eth_handle); TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_create_default()); + TEST_ESP_OK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, ð_event_handler, mutex)); TEST_ASSERT_EQUAL(ESP_OK, esp_eth_start(eth_handle)); // start Ethernet driver state machine + TEST_ASSERT(xSemaphoreTake(mutex, pdMS_TO_TICKS(3000))); + // even if PHY indicates link up, it sometimes may miss few packets since switch port may not be forwarding yet (executing RSTP) + vTaskDelay(pdMS_TO_TICKS(500)); + TEST_ASSERT_EQUAL(ESP_OK, mac->get_addr(mac, local_mac_addr)); // test app will parse the DUT MAC from this line of log output printf("DUT MAC: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", local_mac_addr[0], local_mac_addr[1], local_mac_addr[2], @@ -254,6 +280,7 @@ TEST_CASE("recv_pkt", "[esp_eth]") EventBits_t bits = 0; bits = xEventGroupWaitBits(eth_event_group, ETH_BROADCAST_RECV_BIT | ETH_MULTICAST_RECV_BIT | ETH_UNICAST_RECV_BIT, true, true, pdMS_TO_TICKS(3000)); + printf("recv bits 0x%x\n", bits); TEST_ASSERT((bits & (ETH_BROADCAST_RECV_BIT | ETH_MULTICAST_RECV_BIT | ETH_UNICAST_RECV_BIT)) == (ETH_BROADCAST_RECV_BIT | ETH_MULTICAST_RECV_BIT | ETH_UNICAST_RECV_BIT)); @@ -263,6 +290,7 @@ TEST_CASE("recv_pkt", "[esp_eth]") phy->del(phy); mac->del(mac); vEventGroupDelete(eth_event_group); + vSemaphoreDelete(mutex); } typedef struct @@ -328,6 +356,7 @@ TEST_CASE("start_stop_stress_test", "[esp_eth]") #if defined(CONFIG_TARGET_ETH_PHY_DEVICE_IP101) esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); // create PHY instance #elif defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) + phy_config.phy_addr = 0; esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config); #endif TEST_ASSERT_NOT_NULL(phy); @@ -357,7 +386,7 @@ TEST_CASE("start_stop_stress_test", "[esp_eth]") // create dummy data packet used for traffic generation emac_frame_t *pkt = calloc(1, 1500); - pkt->proto = 0x2222; + pkt->proto = 0x2223; // we don't care about dest MAC address much, however it is better to not be broadcast or multifcast to not flood // other network nodes memset(pkt->dest, 0xBA, 6); @@ -368,8 +397,8 @@ TEST_CASE("start_stop_stress_test", "[esp_eth]") TEST_ASSERT_EQUAL(ESP_OK, esp_eth_start(eth_handle)); // start Ethernet driver state machine bits = xEventGroupWaitBits(eth_event_group, ETH_CONNECT_BIT, true, true, pdMS_TO_TICKS(3000)); TEST_ASSERT((bits & ETH_CONNECT_BIT) == ETH_CONNECT_BIT); - // even if PHY (IP101) indicates autonegotiation done and link up, it sometimes may miss few packets after atonego reset, hence wait a bit - vTaskDelay(pdMS_TO_TICKS(100)); + // even if PHY indicates link up, it sometimes may miss few packets since switch port may not be forwarding yet (executing RSTP) + vTaskDelay(pdMS_TO_TICKS(500)); // at first, check that Tx/Rx path works as expected by poking the test script // this also serves as main PASS/FAIL criteria @@ -384,7 +413,7 @@ TEST_CASE("start_stop_stress_test", "[esp_eth]") for (int j = 0; j < 150; j++) { // return value is not checked on purpose since it is expected that it may fail time to time because // we may try to queue more packets than hardware is able to handle - pkt->data[0] = j & 0xFF; + pkt->data[0] = j & 0xFF; // just for debug purposes esp_eth_transmit(eth_handle, pkt, 1500); } TEST_ASSERT_EQUAL(ESP_OK, esp_eth_stop(eth_handle)); @@ -399,8 +428,8 @@ TEST_CASE("start_stop_stress_test", "[esp_eth]") TEST_ASSERT_EQUAL(ESP_OK, esp_eth_start(eth_handle)); // start Ethernet driver state machine bits = xEventGroupWaitBits(eth_event_group, ETH_CONNECT_BIT, true, true, pdMS_TO_TICKS(3000)); TEST_ASSERT((bits & ETH_CONNECT_BIT) == ETH_CONNECT_BIT); - // even if PHY (IP101) indicates autonegotiation done and link up, it sometimes may miss few packets after atonego reset, hence wait a bit - vTaskDelay(pdMS_TO_TICKS(100)); + // even if PHY indicates link up, it sometimes may miss few packets since switch port may not be forwarding yet (executing RSTP) + vTaskDelay(pdMS_TO_TICKS(500)); ctrl_pkt->data[0] = POKE_REQ; ctrl_pkt->data[1] = rx_i; From 28ac68224d67cc5deea399a1822f902ca4a7e392 Mon Sep 17 00:00:00 2001 From: zhiweijian Date: Tue, 19 Dec 2023 14:26:00 +0800 Subject: [PATCH 07/15] fix(esp_phy): Fixed BLE TX 2M problem causing by phy_wifi_enable_set() 1. Fixed BLE 2M phy TX problem causing by phy_wifi_enable_set() on ESP32-C3 and ESP32-S3 2. Fixed BLE and WIFI could not receive packets after entering light sleep for a long time on ESP32-C3 and ESP32-S3 --- components/esp_phy/lib | 2 +- components/esp_phy/src/phy_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/esp_phy/lib b/components/esp_phy/lib index 47707e6af46..dcfdccf6cc2 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit 47707e6af4684107bdf7c5a34b67fd18362d3fd3 +Subproject commit dcfdccf6cc2fc02d0886624b7998c890d1a19b28 diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 5b86bff2581..88fd1fd0eb6 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -685,7 +685,7 @@ void esp_phy_load_cal_and_init(void) // Set PHY whether in combo module // For comode mode, phy enable will be not in WiFi RX state #if SOC_PHY_COMBO_MODULE - phy_init_param_set(0); + phy_init_param_set(1); #endif esp_phy_calibration_data_t* cal_data = From 2a7e9fc4852a2cf1c174a173bc3443c7379cf2d3 Mon Sep 17 00:00:00 2001 From: xiongweichao Date: Thu, 11 Jan 2024 14:39:25 +0800 Subject: [PATCH 08/15] fix(ble): Fixed Bluetooth not waking up due to clock drift --- components/bt/controller/esp32c3/bt.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index a53df45e6d8..43f2270864c 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -763,19 +763,26 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) return; } - // start a timer to wake up and acquire the pm_lock before modem_sleep awakes uint32_t us_to_sleep = btdm_lpcycles_2_hus(lpcycles, NULL) >> 1; #define BTDM_MIN_TIMER_UNCERTAINTY_US (1800) +#define BTDM_RTC_SLOW_CLK_RC_DRIFT (7 / 100) assert(us_to_sleep > BTDM_MIN_TIMER_UNCERTAINTY_US); // allow a maximum time uncertainty to be about 488ppm(1/2048) at least as clock drift // and set the timer in advance uint32_t uncertainty = (us_to_sleep >> 11); +#if CONFIG_FREERTOS_USE_TICKLESS_IDLE + if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) { + uncertainty = us_to_sleep * BTDM_RTC_SLOW_CLK_RC_DRIFT; + } +#endif + if (uncertainty < BTDM_MIN_TIMER_UNCERTAINTY_US) { uncertainty = BTDM_MIN_TIMER_UNCERTAINTY_US; } assert (s_lp_stat.wakeup_timer_started == 0); + // start a timer to wake up and acquire the pm_lock before modem_sleep awakes if (esp_timer_start_once(s_btdm_slp_tmr, us_to_sleep - uncertainty) == ESP_OK) { s_lp_stat.wakeup_timer_started = 1; } else { @@ -794,12 +801,12 @@ static void btdm_sleep_enter_phase2_wrapper(void) assert(0); } - if (s_lp_stat.pm_lock_released == 0) { #ifdef CONFIG_PM_ENABLE + if (s_lp_stat.pm_lock_released == 0) { esp_pm_lock_release(s_pm_lock); -#endif s_lp_stat.pm_lock_released = 1; } +#endif } } From 8e41d56dbed76f2606e0e8be3b11849c35f44b1f Mon Sep 17 00:00:00 2001 From: xiongweichao Date: Mon, 29 Jan 2024 11:29:01 +0800 Subject: [PATCH 09/15] fix(ble): Fixed macro definition error for 136K clock drift --- components/bt/controller/esp32c3/bt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 43f2270864c..7ac77f3ea10 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -766,14 +766,14 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) uint32_t us_to_sleep = btdm_lpcycles_2_hus(lpcycles, NULL) >> 1; #define BTDM_MIN_TIMER_UNCERTAINTY_US (1800) -#define BTDM_RTC_SLOW_CLK_RC_DRIFT (7 / 100) +#define BTDM_RTC_SLOW_CLK_RC_DRIFT_PERCENT 7 assert(us_to_sleep > BTDM_MIN_TIMER_UNCERTAINTY_US); // allow a maximum time uncertainty to be about 488ppm(1/2048) at least as clock drift // and set the timer in advance uint32_t uncertainty = (us_to_sleep >> 11); #if CONFIG_FREERTOS_USE_TICKLESS_IDLE if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) { - uncertainty = us_to_sleep * BTDM_RTC_SLOW_CLK_RC_DRIFT; + uncertainty = us_to_sleep * BTDM_RTC_SLOW_CLK_RC_DRIFT_PERCENT / 100; } #endif From 577a076bff865a72ee9d5fc78f254b521c4a2794 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Tue, 9 Jan 2024 19:52:15 +0100 Subject: [PATCH 10/15] feat: Use python-reorder-imports instead of isort --- .pre-commit-config.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 30933a024d8..e803541eb07 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -36,11 +36,12 @@ repos: hooks: - id: flake8 args: ['--config=.flake8', '--tee', '--benchmark'] - - repo: https://github.com/pycqa/isort - rev: 5.11.5 # python 3.7 compatible + - repo: https://github.com/asottile/reorder-python-imports + rev: v3.12.0 hooks: - - id: isort - name: isort (python) + - id: reorder-python-imports + name: Reorder Python imports + args: [--py36-plus] exclude: > (?x)^( .*_pb2.py From 93ae438d598b4fd05c3993c4536114fe77a17585 Mon Sep 17 00:00:00 2001 From: Darshan Dobariya Date: Thu, 11 Jan 2024 12:43:54 +0530 Subject: [PATCH 11/15] fix(nimble): Added change to ensure that API execution returns success (v4.4) --- components/bt/host/nimble/nimble | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 13edbb9a047..2e8d2add8da 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 13edbb9a04772d8629e575f60fcbb1db3fef8fce +Subproject commit 2e8d2add8dae7acbbf38b5925e5774fae9fb6af0 From 7bfc2b0418144f5843e1cee8a6934b788b48a16b Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Sat, 24 Jun 2023 20:38:53 +0800 Subject: [PATCH 12/15] spi_flash: fixed issue that enabling HPM-DC by default may cause app unable to restart --- components/bootloader/Kconfig.projbuild | 89 ++++++++---- components/bootloader/sdkconfig.rename | 4 + .../src/esp32s3/bootloader_esp32s3.c | 2 +- components/esp32s3/Kconfig | 2 +- components/esptool_py/Kconfig.projbuild | 12 +- components/esptool_py/project_include.cmake | 2 +- components/spi_flash/CMakeLists.txt | 5 + components/spi_flash/Kconfig | 137 ++++++++++++++---- .../spi_flash/esp32s3/spi_timing_config.c | 6 +- components/spi_flash/esp_flash_spi_init.c | 2 +- components/spi_flash/flash_ops.c | 6 +- components/spi_flash/include/esp_flash.h | 2 + .../include/esp_private/spi_flash_os.h | 6 + components/spi_flash/linker.lf | 2 + components/spi_flash/spi_flash_hpm_enable.c | 132 +++++++++++++---- .../storage/spi_flash_optional_feature.rst | 58 +++++++- .../flash_psram/sdkconfig.ci.f4r4_120sdr | 2 + .../sdkconfig.ci.f4r4_120sdr_120sdr | 2 + .../sdkconfig.ci.f4r4_120sdr_40sdr | 2 + .../sdkconfig.ci.f4r4_120sdr_os_silent | 2 + .../flash_psram/sdkconfig.ci.f4r8_120sdr | 2 + 21 files changed, 361 insertions(+), 116 deletions(-) diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 895085d383b..f428bec2e6f 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -62,34 +62,67 @@ menu "Bootloader config" default 4 if BOOTLOADER_LOG_LEVEL_DEBUG default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE - config BOOTLOADER_SPI_CUSTOM_WP_PIN - bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)" - depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT) - default y if BOOTLOADER_SPI_WP_PIN != 7 # backwards compatibility, can remove in IDF 5 - default n - help - This setting is only used if the SPI flash pins have been overridden by setting the eFuses - SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT. + menu "Serial Flash Configurations" + config BOOTLOADER_SPI_CUSTOM_WP_PIN + bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)" + depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT) + default y if BOOTLOADER_SPI_WP_PIN != 7 # backwards compatibility, can remove in IDF 5 + default n + help + This setting is only used if the SPI flash pins have been overridden by setting the eFuses + SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT. + + When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka + ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used + for external SPIRAM if it is enabled. + + If this config item is set to N (default), the correct WP pin will be automatically used for any + Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to + Y and specify the GPIO number connected to the WP. + + config BOOTLOADER_SPI_WP_PIN + int "Custom SPI Flash WP Pin" + range 0 33 + default 7 + depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT) + #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN # backwards compatibility, can uncomment in IDF 5 + help + The option "Use custom SPI Flash WP Pin" must be set or this value is ignored - When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka - ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used - for external SPIRAM if it is enabled. + If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this + value to the GPIO number of the SPI flash WP pin. - If this config item is set to N (default), the correct WP pin will be automatically used for any - Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to - Y and specify the GPIO number connected to the WP. + config BOOTLOADER_FLASH_DC_AWARE + bool "Allow app adjust Dummy Cycle bits in SPI Flash for higher frequency (READ HELP FIRST)" + help + This will force 2nd bootloader to be loaded by DOUT mode, and will restore Dummy Cycle setting by + resetting the Flash - config BOOTLOADER_SPI_WP_PIN - int "Custom SPI Flash WP Pin" - range 0 33 - default 7 - depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT) - #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN # backwards compatibility, can uncomment in IDF 5 - help - The option "Use custom SPI Flash WP Pin" must be set or this value is ignored + config BOOTLOADER_FLASH_XMC_SUPPORT + bool "Enable the support for flash chips of XMC (READ DOCS FIRST)" + default y + depends on !IDF_ENV_BRINGUP + help + Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow. + XMC chips will be forbidden to be used, when this option is disabled. + + DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING. - If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this - value to the GPIO number of the SPI flash WP pin. + comment "Features below require specific hardware (READ DOCS FIRST!)" + + config BOOTLOADER_FLASH_32BIT_ADDR + bool + default y if ESPTOOLPY_FLASHSIZE_32MB || ESPTOOLPY_FLASHSIZE_64MB || ESPTOOLPY_FLASHSIZE_128MB + default n + help + This is a helper config for 32bits address flash. Invisible for users. + + config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH + bool + default y if ESPTOOLPY_OCT_FLASH && SPI_FLASH_32BIT_ADDRESS + default n + + endmenu choice BOOTLOADER_VDDSDIO_BOOST bool "VDDSDIO LDO voltage" @@ -393,14 +426,6 @@ menu "Bootloader config" in this area of memory, you can increase it. It must be a multiple of 4 bytes. This area (rtc_retain_mem_t) is reserved and has access from the bootloader and an application. - config BOOTLOADER_FLASH_XMC_SUPPORT - bool "Enable the support for flash chips of XMC (READ HELP FIRST)" - default y - help - Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow. - XMC chips will be forbidden to be used, when this option is disabled. - - DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING. endmenu # Bootloader diff --git a/components/bootloader/sdkconfig.rename b/components/bootloader/sdkconfig.rename index bdcfe364878..bbc1846e7a8 100644 --- a/components/bootloader/sdkconfig.rename +++ b/components/bootloader/sdkconfig.rename @@ -23,3 +23,7 @@ CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE CONFIG_SECURE_FLASH_ # Secure Boot Scheme CONFIG_SECURE_BOOT_ENABLED CONFIG_SECURE_BOOT_V1_ENABLED + +CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH +CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH +CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index f61080f508d..a9ff89ffa7e 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -218,7 +218,7 @@ static esp_err_t bootloader_init_spi_flash(void) } #endif -#if CONFIG_SPI_FLASH_HPM_ENABLE +#if CONFIG_BOOTLOADER_FLASH_DC_AWARE // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot. bootloader_spi_flash_reset(); #endif diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig index 53f2e498c95..e6a1654252b 100644 --- a/components/esp32s3/Kconfig +++ b/components/esp32s3/Kconfig @@ -307,7 +307,7 @@ menu "ESP32S3-Specific" config SPIRAM_SPEED_120M depends on SPIRAM_MODE_QUAD - bool "120MHz clock speed" + bool "120MHz clock speed (READ DOCS FIRST)" config SPIRAM_SPEED_80M bool "80MHz clock speed" config SPIRAM_SPEED_40M diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index dad043f7fd0..19fe84b2044 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -118,6 +118,10 @@ menu "Serial flasher config" # information get from efuse, so don't care this dout choice. default "dout" if ESPTOOLPY_FLASHMODE_OPI + config ESPTOOLPY_S3_STR + bool + default y if IDF_TARGET_ESP32S3 && ESPTOOLPY_FLASH_SAMPLE_MODE_STR + choice ESPTOOLPY_FLASHFREQ prompt "Flash SPI speed" default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32H2 @@ -126,9 +130,11 @@ menu "Serial flasher config" The SPI flash frequency to be used. config ESPTOOLPY_FLASHFREQ_120M - depends on IDF_TARGET_ESP32S3 && ESPTOOLPY_FLASH_SAMPLE_MODE_STR - bool "120 MHz" - select SPI_FLASH_HPM_ENABLE + bool "120 MHz (READ DOCS FIRST)" + depends on ESPTOOLPY_S3_STR && (SPI_FLASH_HPM_ON || ESPTOOLPY_OCT_FLASH) + help + - Optional feature for QSPI Flash. Read docs and enable `CONFIG_SPI_FLASH_HPM_ENA` first! + config ESPTOOLPY_FLASHFREQ_80M bool "80 MHz" config ESPTOOLPY_FLASHFREQ_40M diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index c9a7fd27d8e..93135e01eda 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -15,7 +15,7 @@ set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py") set(ESPEFUSEPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espefuse.py") set(ESPMONITOR ${python} "${idf_path}/tools/idf_monitor.py") -if(CONFIG_SPI_FLASH_HPM_ENABLE) +if(CONFIG_BOOTLOADER_FLASH_DC_AWARE) # When set flash frequency to 120M, must keep 1st bootloader work under ``DOUT`` mode # because on some flash chips, 120M will modify the status register, # which will make ROM won't work. diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index 6d4099fb7f6..60a950c6858 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -23,6 +23,11 @@ else() list(APPEND srcs "esp32s3/spi_timing_config.c" "spi_flash_timing_tuning.c" + ) + endif() + + if(CONFIG_SPI_FLASH_HPM_ON) + list(APPEND srcs "spi_flash_hpm_enable.c") endif() diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index 68096cbfb5b..91dec00950c 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -1,3 +1,108 @@ +menu "Main Flash configuration" + depends on !APP_BUILD_TYPE_PURE_RAM_APP + + menu "SPI Flash behavior when brownout" + + config SPI_FLASH_BROWNOUT_RESET_XMC + bool "Enable sending reset when brownout for XMC flash chips" + default y + select SPI_FLASH_BROWNOUT_RESET + help + When this option is selected, the patch will be enabled for XMC. + Follow the recommended flow by XMC for better stability. + + DO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING. + + config SPI_FLASH_BROWNOUT_RESET + bool + default y + select ESP_SYSTEM_BROWNOUT_INTR + help + When brownout happens during flash erase/write operations, + send reset command to stop the flash operations to improve stability. + + endmenu + + menu "Optional and Experimental Features (READ DOCS FIRST)" + + comment "Features here require specific hardware (READ DOCS FIRST!)" + + config SPI_FLASH_UNDER_HIGH_FREQ + bool + default y if ESPTOOLPY_FLASHFREQ_120M + help + This is a helper config for HPM. Invisible for users. + + choice SPI_FLASH_HPM + prompt "High Performance Mode (READ DOCS FIRST, > 80MHz)" + # Currently, only esp32s3 allows high performance mode. + depends on IDF_TARGET_ESP32S3 && !ESPTOOLPY_OCT_FLASH + default SPI_FLASH_HPM_AUTO + help + Whether the High Performance Mode of Flash is enabled. As an optional feature, user needs to manually + enable this option as a confirmation. To be back-compatible with earlier IDF versionn, this option is + automatically enabled with warning when Flash running > 80Mhz. + + config SPI_FLASH_HPM_ENA + # Not using name of SPI_FLASH_HPM_ENABLE because it was used as an invisible option and we don't want + # to inherit the value of that one + bool "Enable" + config SPI_FLASH_HPM_AUTO + bool "Auto (Not recommended)" + config SPI_FLASH_HPM_DIS + bool "Disabled" + endchoice + + config SPI_FLASH_HPM_ON + bool + # For ESP32-S3, it's enabled by default. For later chips it should be disabled by default + default y if SPI_FLASH_HPM_ENA || (IDF_TARGET_ESP32S3 && SPI_FLASH_HPM_AUTO) + help + This option is invisible, and will be selected automatically + when ``ESPTOOLPY_FLASHFREQ_120M`` is selected. + + choice SPI_FLASH_HPM_DC + prompt "Support HPM using DC (READ DOCS FIRST)" + depends on SPI_FLASH_HPM_ON + default SPI_FLASH_HPM_DC_AUTO + help + This feature needs your bootloader to be compiled DC-aware (BOOTLOADER_FLASH_DC_AWARE=y). Otherwise the + chip will not be able to boot after a reset. + + config SPI_FLASH_HPM_DC_AUTO + bool "Auto (Enable when bootloader support enabled (BOOTLOADER_FLASH_DC_AWARE))" + config SPI_FLASH_HPM_DC_DISABLE + bool "Disable (READ DOCS FIRST)" + endchoice + + config SPI_FLASH_HPM_DC_ON + bool + default y if SPI_FLASH_HPM_DC_AUTO && BOOTLOADER_FLASH_DC_AWARE + help + This is a helper config for HPM. Whether HPM-DC is enabled is also determined by bootloader. + Invisible for users. + + config SPI_FLASH_AUTO_SUSPEND + bool "Auto suspend long erase/write operations (READ DOCS FIRST)" + default n + depends on IDF_TARGET_ESP32C3 && !SPI_FLASH_USE_LEGACY_IMPL && !SPI_FLASH_ROM_IMPL + help + This option is disabled by default because it is supported only + for specific flash chips and for specific Espressif chips. + To evaluate if you can use this feature refer to + `Optional Features for Flash` > `Auto Suspend & Resume` of the `ESP-IDF Programming Guide`. + + CAUTION: If you want to OTA to an app with this feature turned on, please make + sure the bootloader has the support for it. (later than IDF v4.3) + + If you are using an official Espressif module, please contact Espressif Business support + to check if the module has the flash that support this feature installed. + Also refer to `Concurrency Constraints for Flash on SPI1` > `Flash Auto Suspend Feature` + before enabling this option. + + endmenu +endmenu + menu "SPI Flash driver" config SPI_FLASH_VERIFY_WRITE @@ -147,20 +252,6 @@ menu "SPI Flash driver" help Defines how many ticks will be before returning to continue a erasing. - config SPI_FLASH_AUTO_SUSPEND - bool "Auto suspend long erase/write operations (READ DOCS FIRST)" - default n - depends on IDF_TARGET_ESP32C3 && !SPI_FLASH_USE_LEGACY_IMPL && !SPI_FLASH_ROM_IMPL - help - This option is default n before ESP32-C3, because it needs bootloader support. - - CAUTION: If you want to OTA to an app with this feature turned on, please make - sure the bootloader has the support for it. (later than IDF v4.3) - - Auto-suspend feature only supported by XMC chip. - If you are using an official module, please contact Espressif Business support. - Also reading auto suspend part in `SPI Flash API` document before you enable this function. - config SPI_FLASH_WRITE_CHUNK_SIZE int "Flash write chunk size" default 8192 @@ -279,22 +370,4 @@ menu "SPI Flash driver" application is not using flash encryption feature and is in need of some additional memory from IRAM region (~1KB) then this config can be disabled. - config SPI_FLASH_HPM_ENABLE - bool - default n - help - This option is invisible, and will be selected automatically - when ``ESPTOOLPY_FLASHFREQ_120M`` is selected. - - config SPI_FLASH_32BIT_ADDRESS - bool - default y if ESPTOOLPY_FLASHSIZE_32MB || ESPTOOLPY_FLASHSIZE_64MB || ESPTOOLPY_FLASHSIZE_128MB - default n - help - This is a helper config for 32bits address flash. Invisible for users. - - config SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE - bool - default y if ESPTOOLPY_OCT_FLASH && SPI_FLASH_32BIT_ADDRESS - default n endmenu diff --git a/components/spi_flash/esp32s3/spi_timing_config.c b/components/spi_flash/esp32s3/spi_timing_config.c index 978f4ebcb31..b96918a9ca1 100644 --- a/components/spi_flash/esp32s3/spi_timing_config.c +++ b/components/spi_flash/esp32s3/spi_timing_config.c @@ -146,8 +146,8 @@ static uint32_t spi_timing_config_get_dummy(void) abort(); } -#if CONFIG_SPI_FLASH_HPM_ENABLE - if (spi_flash_hpm_dummy_adjust()) { // HPM is enabled +#if CONFIG_SPI_FLASH_HPM_DC_ON + if (spi_flash_hpm_dummy_adjust()) { // HPM-DC is enabled const spi_flash_hpm_dummy_conf_t *hpm_dummy = spi_flash_hpm_get_dummy(); switch (ctrl_reg & MULTI_LINE_MASK_QUAD_FLASH) { case SPI_FLASH_QIO_MODE: @@ -167,7 +167,7 @@ static uint32_t spi_timing_config_get_dummy(void) } } else #endif - { // HPM is not enabled + { // HPM-DC is not enabled switch (ctrl_reg & MULTI_LINE_MASK_QUAD_FLASH) { case SPI_FLASH_QIO_MODE: return SPI1_R_QIO_DUMMY_CYCLELEN; diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 6b69a0352df..516d6736ba0 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -333,7 +333,7 @@ esp_err_t esp_flash_init_default_chip(void) } #endif -#if CONFIG_SPI_FLASH_HPM_ENABLE +#if CONFIG_SPI_FLASH_HPM_DC_ON if (spi_flash_hpm_dummy_adjust()) { default_chip.hpm_dummy_ena = 1; } diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index 637fec94cc3..67e3c4d1723 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -187,12 +187,10 @@ esp_err_t IRAM_ATTR spi_flash_init_chip_state(void) #if CONFIG_ESPTOOLPY_OCT_FLASH return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id); #else -#if CONFIG_IDF_TARGET_ESP32S3 - // Currently, only esp32s3 allows high performance mode. +#if CONFIG_SPI_FLASH_HPM_ON return spi_flash_enable_high_performance_mode(); -#else +#endif // CONFIG_SPI_FLASH_HPM_ON return ESP_OK; -#endif // CONFIG_IDF_TARGET_ESP32S3 #endif // CONFIG_ESPTOOLPY_OCT_FLASH } diff --git a/components/spi_flash/include/esp_flash.h b/components/spi_flash/include/esp_flash.h index bfb7e88c1e5..bd34a97d4b4 100644 --- a/components/spi_flash/include/esp_flash.h +++ b/components/spi_flash/include/esp_flash.h @@ -172,6 +172,8 @@ esp_err_t esp_flash_get_size(esp_flash_t *chip, uint32_t *out_size); esp_err_t esp_flash_get_physical_size(esp_flash_t *chip, uint32_t *flash_size); /** @brief Read flash unique ID via the common "RDUID" SPI flash command. + * + * @note This is an optional feature, which is not supported on all flash chips. READ PROGRAMMING GUIDE FIRST! * * @param chip Pointer to identify flash chip. Must have been successfully initialised via esp_flash_init(). * @param[out] out_id Pointer to receive unique ID value. diff --git a/components/spi_flash/include/esp_private/spi_flash_os.h b/components/spi_flash/include/esp_private/spi_flash_os.h index f2a89112eb6..9fac59a21b8 100644 --- a/components/spi_flash/include/esp_private/spi_flash_os.h +++ b/components/spi_flash/include/esp_private/spi_flash_os.h @@ -139,9 +139,14 @@ bool spi_timing_is_tuned(void); */ void spi_flash_set_vendor_required_regs(void); +#if CONFIG_SPI_FLASH_HPM_ON /** * @brief Enable SPI flash high performance mode. * + * @note 1. When `CONFIG_SPI_FLASH_HPM_ON` is True, caller can always call this function without taking whether the used + * frequency falls into the HPM range into consideration. + * 2. However, caller shouldn't attempt to call this function on Octal flash. + * * @return ESP_OK if success. */ esp_err_t spi_flash_enable_high_performance_mode(void); @@ -161,6 +166,7 @@ const spi_flash_hpm_dummy_conf_t *spi_flash_hpm_get_dummy(void); * @return true Yes, and work under HPM with adjusting dummy. Otherwise, false. */ bool spi_flash_hpm_dummy_adjust(void); +#endif //CONFIG_SPI_FLASH_HPM_ON #ifdef __cplusplus } diff --git a/components/spi_flash/linker.lf b/components/spi_flash/linker.lf index 501e1fd415c..10098ec1041 100644 --- a/components/spi_flash/linker.lf +++ b/components/spi_flash/linker.lf @@ -15,6 +15,8 @@ entries: spi_flash_timing_tuning (noflash) spi_timing_config (noflash) spi_flash_chip_mxic_opi (noflash) + + if SPI_FLASH_HPM_ON = y: spi_flash_hpm_enable (noflash) if IDF_TARGET_ESP32S3 = y && ESPTOOLPY_OCT_FLASH = y: diff --git a/components/spi_flash/spi_flash_hpm_enable.c b/components/spi_flash/spi_flash_hpm_enable.c index d8f81a2e056..3d58b5dd6ad 100644 --- a/components/spi_flash/spi_flash_hpm_enable.c +++ b/components/spi_flash/spi_flash_hpm_enable.c @@ -29,14 +29,22 @@ * 3. Some flash chips adjust dummy cycles. ******************************************************************************/ -#if CONFIG_ESPTOOLPY_FLASHFREQ_120M -#define FLASH_FREQUENCY 120 -#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define FLASH_FREQUENCY 80 -#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M -#define FLASH_FREQUENCY 40 -#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M -#define FLASH_FREQUENCY 20 +/* + * Note: This file should only be compiled when HPM_ON, which is only available when !CONFIG_ESPTOOLPY_OCT_FLASH. + * However when HPM_ON, there are still some cases this file is not actually used: + * + * - !CONFIG_SPI_FLASH_UNDER_HIGH_FREQ: + * It mean that the flash not running under frequency requires HPM. spi_flash_enable_high_performance_mode() still + * called because caller shouldn't take care of the frequency. + */ + +void spi_flash_hpm_get_dummy_generic(spi_flash_hpm_dummy_conf_t *dummy_conf); + +#if CONFIG_SPI_FLASH_UNDER_HIGH_FREQ + +#if CONFIG_SPI_FLASH_HPM_AUTO +// This only happens on S3, where HPM_AUTO leads to HPM_ON +#warning High Performance Mode (QSPI Flash > 80MHz) is optional feature that depends on flash model. Read Docs First! #endif const static char *HPM_TAG = "flash HPM"; @@ -121,6 +129,7 @@ static esp_err_t spi_flash_high_performance_check_hpf_bit_5(void) //-----------------For flash chips which enter HPM via adjust dummy-----------------------// +#if CONFIG_SPI_FLASH_HPM_DC_ON /** * @brief Probe the chip whether adjust dummy to enable HPM mode. Take XMC as an example: * Adjust dummy bits to enable HPM mode of the flash. If XMC works under 80MHz, the dummy bits @@ -199,6 +208,14 @@ static void spi_flash_hpm_get_dummy_xmc(spi_flash_hpm_dummy_conf_t *dummy_conf) dummy_conf->qout_dummy = 8; dummy_conf->fastrd_dummy = 8; } +#elif !CONFIG_SPI_FLASH_HPM_DC_DISABLE + +//This is because bootloader doesn't support this +#warning HPM-DC, which helps to run some flash > 80MHz by adjusting dummy cycles, is no longer enabled by default. +#warning To enable this feature, your bootloader needs to have the support for it (by explicitly selecting BOOTLOADER_FLASH_DC_AWARE). +#warning If your bootloader does not support it, select SPI_FLASH_HPM_DC_DISABLE to suppress the warning. READ DOCS FIRST! + +#endif //CONFIG_SPI_FLASH_HPM_DC_ON //-----------------For flash chips which enter HPM via write status register-----------------------// @@ -248,33 +265,38 @@ static void spi_flash_turn_high_performance_write_hpf_bit_5(void) esp_rom_spiflash_wait_idle(&g_rom_flashchip); } -//-----------------------generic functions-------------------------------------// - -/** - * @brief Default dummy for almost all flash chips. If your flash does't need to reconfigure dummy, - * just call this function. - */ -void __attribute__((weak)) spi_flash_hpm_get_dummy_generic(spi_flash_hpm_dummy_conf_t *dummy_conf) -{ - dummy_conf->dio_dummy = 4; - dummy_conf->dout_dummy = 8; - dummy_conf->qio_dummy = 6; - dummy_conf->qout_dummy = 8; - dummy_conf->fastrd_dummy = 8; -} - const spi_flash_hpm_info_t __attribute__((weak)) spi_flash_hpm_enable_list[] = { /* vendor, chip_id, freq_threshold, temperature threshold, operation for setting high performance, reading HPF status, get dummy */ { "command", spi_flash_hpm_probe_chip_with_cmd, spi_flash_hpm_chip_hpm_requirement_check_with_cmd, spi_flash_enable_high_performance_send_cmd, spi_flash_high_performance_check_hpf_bit_5, spi_flash_hpm_get_dummy_generic }, +#if CONFIG_SPI_FLASH_HPM_DC_ON { "dummy", spi_flash_hpm_probe_chip_with_dummy, spi_flash_hpm_chip_hpm_requirement_check_with_dummy, spi_flash_turn_high_performance_reconfig_dummy, spi_flash_high_performance_check_dummy_sr, spi_flash_hpm_get_dummy_xmc}, +#endif //CONFIG_SPI_FLASH_HPM_DC_ON { "write sr3-bit5", spi_flash_hpm_probe_chip_with_write_hpf_bit_5, spi_flash_hpm_chip_hpm_requirement_check_with_write_hpf_bit_5, spi_flash_turn_high_performance_write_hpf_bit_5, spi_flash_high_performance_check_hpf_bit_5, spi_flash_hpm_get_dummy_generic}, // default: do nothing, but keep the dummy get function. The first item with NULL as its probe will be the fallback. { "NULL", NULL, NULL, NULL, NULL, spi_flash_hpm_get_dummy_generic}, }; static const spi_flash_hpm_info_t *chip_hpm = NULL; -static spi_flash_hpm_dummy_conf_t dummy_conf; -static bool hpm_dummy_changed = false; + +#if CONFIG_SPI_FLASH_HPM_DC_ON +static bool s_hpm_dummy_changed = false; +static spi_flash_hpm_dummy_conf_t s_dummy_conf; + +const spi_flash_hpm_dummy_conf_t *spi_flash_hpm_get_dummy(void) +{ + chip_hpm->flash_get_dummy(&s_dummy_conf); + return &s_dummy_conf; +} + +bool spi_flash_hpm_dummy_adjust(void) +{ + return s_hpm_dummy_changed; +} +#endif //CONFIG_SPI_FLASH_HPM_DC_ON + +#if CONFIG_ESPTOOLPY_FLASHFREQ_120M +#define FLASH_FREQUENCY 120 +#endif esp_err_t spi_flash_enable_high_performance_mode(void) { @@ -285,6 +307,21 @@ esp_err_t spi_flash_enable_high_performance_mode(void) int voltage = 0; int temperature = 0; +#if CONFIG_SPI_FLASH_HPM_AUTO + ESP_EARLY_LOGW(HPM_TAG, "HPM mode is optional feature that depends on flash model. Read Docs First!"); +#endif + +#if CONFIG_SPI_FLASH_HPM_DC_DISABLE + // case 1: force disabled + ESP_EARLY_LOGI(HPM_TAG, "w/o HPM-DC support"); +#elif CONFIG_SPI_FLASH_HPM_DC_ON + // case 2: auto, and actually enabled + ESP_EARLY_LOGI(HPM_TAG, "with HPM-DC support"); +#else + // case 3: auto, but disabled (not supported by bootloader) + ESP_EARLY_LOGW(HPM_TAG, "HPM mode with DC adjustment is disabled. Some flash models may not be supported. Read Docs First!"); +#endif + const spi_flash_hpm_info_t *chip = spi_flash_hpm_enable_list; esp_err_t ret = ESP_OK; while (chip->probe) { @@ -296,10 +333,12 @@ esp_err_t spi_flash_enable_high_performance_mode(void) } chip_hpm = chip; + /* When > 80 MHz, flash chips usually need special HPM support to run normally. The support is chip-specific. When + * the chip is not in the known flash list, nothing will be done and there will be an warning. + * When <= 80 MHz, it's assumed that all flash chips can run without chip-specific HPM support. This function will not be called and there will be no warning. + */ if (ret != ESP_OK) { -#if (FLASH_FREQUENCY == 120) - ESP_EARLY_LOGW(HPM_TAG, "Flash high performance mode hasn't been supported"); -#endif + ESP_EARLY_LOGW(HPM_TAG, "High performance mode of this flash model hasn't been supported."); return ret; } @@ -313,21 +352,50 @@ esp_err_t spi_flash_enable_high_performance_mode(void) ESP_EARLY_LOGE(HPM_TAG, "Flash high performance mode hasn't been executed successfully"); return ESP_FAIL; } - hpm_dummy_changed = (hpm_requirement_check == SPI_FLASH_HPM_DUMMY_NEEDED) ? true : false; +#if CONFIG_SPI_FLASH_HPM_DC_ON + s_hpm_dummy_changed = (hpm_requirement_check == SPI_FLASH_HPM_DUMMY_NEEDED) ? true : false; +#else + assert(hpm_requirement_check != SPI_FLASH_HPM_DUMMY_NEEDED); +#endif } else if (hpm_requirement_check == SPI_FLASH_HPM_BEYOND_LIMIT) { ESP_EARLY_LOGE(HPM_TAG, "Flash does not have the ability to raise to that frequency"); return ESP_FAIL; } return ESP_OK; } +#else +//!CONFIG_SPI_FLASH_UNDER_HIGH_FREQ + +static spi_flash_hpm_dummy_conf_t s_dummy_conf; + +esp_err_t spi_flash_enable_high_performance_mode(void) +{ + return ESP_OK; +} const spi_flash_hpm_dummy_conf_t *spi_flash_hpm_get_dummy(void) { - chip_hpm->flash_get_dummy(&dummy_conf); - return &dummy_conf; + spi_flash_hpm_get_dummy_generic(&s_dummy_conf); + return &s_dummy_conf; } bool spi_flash_hpm_dummy_adjust(void) { - return hpm_dummy_changed; + return false; +} +#endif //CONFIG_SPI_FLASH_UNDER_HIGH_FREQ + +//-----------------------generic functions-------------------------------------// + +/** + * @brief Default dummy for almost all flash chips. If your flash does't need to reconfigure dummy, + * just call this function. + */ +void __attribute__((weak)) spi_flash_hpm_get_dummy_generic(spi_flash_hpm_dummy_conf_t *dummy_conf) +{ + dummy_conf->dio_dummy = SPI_FLASH_DIO_DUMMY_BITLEN; + dummy_conf->dout_dummy = SPI_FLASH_DOUT_DUMMY_BITLEN; + dummy_conf->qio_dummy = SPI_FLASH_QIO_DUMMY_BITLEN; + dummy_conf->qout_dummy = SPI_FLASH_QOUT_DUMMY_BITLEN; + dummy_conf->fastrd_dummy = SPI_FLASH_FASTRD_DUMMY_BITLEN; } diff --git a/docs/en/api-reference/storage/spi_flash_optional_feature.rst b/docs/en/api-reference/storage/spi_flash_optional_feature.rst index 93e52a829eb..b6a7523891f 100644 --- a/docs/en/api-reference/storage/spi_flash_optional_feature.rst +++ b/docs/en/api-reference/storage/spi_flash_optional_feature.rst @@ -15,7 +15,7 @@ Some features are not supported on all ESP chips and Flash chips. You can check .. note:: - - The features listed above needs to be supported by both esp chips and flash chips. + When Flash optional features listed in this page are used, aside from the capability of ESP chips, and ESP-IDF verison you are using, you will also need to make sure these features are supported by flash chips used. - If you are using an official Espressif modules/SiP. Some of the modules/SiPs always support the feature, in this case you can see these features listed in the datasheet. Otherwise please contact `Espressif's business team `_ to know if we can supply such products for you. @@ -66,22 +66,64 @@ High performance mode This section is provided for Dual mode (DOUT/DIO) and Quad mode (QIO/QOUT) flash chips. Octal flash used on ESP-chips support High performance mode by default so far, you can refer to the octal flash support list below. -High performance mode (HPM) means that the SPI1 and flash chip works under high frequency. Usually, when the operating frequency of the flash is greater than 80MHz, it is considered that the flash works under HPM. As far as we acknowledged, flash chips have more than two different coping strategies when flash work under HPM. For some flash chips, HPM is controlled by high performance flag (HPF) in status register and for some flash chips, HPM is controlled by dummy cycle bit. +High performance mode (HPM) means that the SPI1 and flash chip works under high frequency. Usually, when the operating frequency of the flash is greater than 80 MHz, it is considered that the flash works under HPM. -For following conditions， IDF start code deals with HPM internally. +As far as we acknowledged, there are more than three strategies for High Performance Mode (HPM) in typical SPI flash parts. For some flash chips, HPM is controlled by dummy cycle bit in the registers, while for other chips, it can be controlled by other bits (like HPM bit) in the register, or some special command. The difference in strategies requires the driver to explicitly add support for each chip. + +.. attention:: + + It is hard to create several strategies to cover all situations, so all flash chips using HPM need to be supported explicitly. Therefore, if you try to use a flash not listed in :ref:`hpm_dc_support_list`, it might cause some error. So, when you try to use the flash chip beyond supported list, please test properly. + +Moreover, when the `Dummy Cycle adjustment` strategy is adopted by the flash chip, the flash remains in a state in which DC is different from the default value after a software reset. The sub mode of HPM that adjusts the dummy cycle to run at higher frequency in the application is called `HPM-DC`. `HPM-DC` feature needs a feature `DC Aware` to be enabled in the bootloader. Otherwise different DC value will forbid the 2nd bootloader from being boot up after reset. + +To enable High Performance Mode: + +1. De-select :ref:`CONFIG_ESPTOOLPY_OCT_FLASH`. HPM is not used for Octal flash, enabling related options may bypass HPM functions. + +2. Enable ``CONFIG_SPI_FLASH_HPM_ENA`` option. + +3. Switch Flash frequency to HPM ones. For example, ``CONFIG_ESPTOOLPY_FLASHFREQ_120M``. + +4. Make sure the config option for `HPM-DC` feature (under ``CONFIG_SPI_FLASH_HPM_DC`` choices) is selected correctly according to whether the bootloader supports `DC Aware`. + + - If bootloader supports `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_AUTO``. This allows the usage of flash chips that adopted `Dummy Cycle adjustment` strategy. + + - If bootloader doesn't support `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_DISABLE``. It avoid consequences caused by running HPM-DC with non-DC-aware bootloaders. But please avoid using flash chips that adopts `Dummy Cycle adjustment` strategy if ``CONFIG_SPI_FLASH_HPM_DC_DISABLE`` is selected. See list of flash models that adpot DC strategy below. + +Check whether the bootloader supports `DC Aware` in the following way: + +- If you are starting a new project, it's suggested to enable `DC Aware` by selecting :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` option in the bootloader menu. Please note that, you won't be able to modify this option via OTA, because the support is in the bootloader. + +- If you are working on an existing project and want to update `HPM-DC` config option in the app via OTA, check the sdkconfig file used to build your bootloader: (Upgrading ESP-IDF version may make this file different from the one used by bootloader to build.) + + - For latest version (ESP-IDF v4.4.7+, v5.2 and above), if :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` is selected, the bootloader supports `DC Aware`. + + - For versions in this range: (v4.4.4-v4.4.6, v5.0+, and v5.1+), if ``CONFIG_ESPTOOLPY_FLASHFREQ_120M`` is selected, the bootloader supports `DC Aware`. In this case, enable :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` to confirm this (though it will not affect bootloader in devices in the field). + + - For versions below v4.4.4, the bootloader doesn't support `DC Aware`. ESP Chips List: 1. ESP32S3 -Flash Chips (name & ID) List: +(The SW support for other chips haven't been done yet) + +.. _hpm_dc_support_list: + +Quad Flash HPM support list +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Flash chips that don't need HPM-DC: 1. GD25Q64C (ID: 0xC84017) 2. GD25Q32C (ID: 0xC84016) +3. ZB25VQ32B (ID: 0x5E4016) +4. GD25LQ255E (ID: 0xC86019) -.. attention:: +Following flash chips also have HPM feature, but requires the bootloader to support `DC Aware`: - It is hard to create several strategies to cover all situations, so all flash chips using HPM need to be supported explicitly. Therefore, if you try to use a flash not listed as supported under high performance mode, it might cause some error. So, when you try to use the flash chip beyond supported list, please test properly. +1. GD25Q64E (ID: 0xC84017) +2. GD25Q128E (ID: 0xC84018) OPI flash support ----------------- @@ -115,3 +157,7 @@ Flash Chips List: 1. W25Q256 2. GD25Q256 + +.. important:: + + Over 16 MBytes space on flash mentioned above can be only used for ``data saving``, like file system. If your data/instructions over 16 MBytes spaces need to be mapped to MMU (so as to be accessed by the CPU), please upgrade to ESP-IDF v5.2 and read the latest docs. \ No newline at end of file diff --git a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr index 537b02e9fde..b2625493196 100644 --- a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr +++ b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr @@ -1,5 +1,7 @@ # Legacy, F4R4, Flash 120M SDR, PSRAM disable CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y +CONFIG_SPI_FLASH_HPM_ENA=y CONFIG_ESPTOOLPY_FLASHFREQ_120M=y +CONFIG_BOOTLOADER_FLASH_DC_AWARE=y CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y diff --git a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_120sdr b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_120sdr index 9e2cf2e9f7c..eda1fed0772 100644 --- a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_120sdr +++ b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_120sdr @@ -1,7 +1,9 @@ # Legacy, F4R4, Flash 120M SDR, PSRAM 120M SDR CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y +CONFIG_SPI_FLASH_HPM_ENA=y CONFIG_ESPTOOLPY_FLASHFREQ_120M=y +CONFIG_BOOTLOADER_FLASH_DC_AWARE=y CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y CONFIG_ESP32S3_SPIRAM_SUPPORT=y CONFIG_SPIRAM_SPEED_120M=y diff --git a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_40sdr b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_40sdr index 05d6318a64e..d8284127cdb 100644 --- a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_40sdr +++ b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_40sdr @@ -1,7 +1,9 @@ # Legacy, F4R4, Flash 120M SDR, PSRAM 40M SDR CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y +CONFIG_SPI_FLASH_HPM_ENA=y CONFIG_ESPTOOLPY_FLASHFREQ_120M=y +CONFIG_BOOTLOADER_FLASH_DC_AWARE=y CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y CONFIG_ESP32S3_SPIRAM_SUPPORT=y CONFIG_SPIRAM_SPEED_40M=y diff --git a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_os_silent b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_os_silent index 41cbec6a1ef..a6bb08b12c3 100644 --- a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_os_silent +++ b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_os_silent @@ -5,5 +5,7 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y +CONFIG_SPI_FLASH_HPM_ENA=y CONFIG_ESPTOOLPY_FLASHFREQ_120M=y +CONFIG_BOOTLOADER_FLASH_DC_AWARE=y CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y diff --git a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r8_120sdr b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r8_120sdr index 2caeb8de79a..03b00c420c9 100644 --- a/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r8_120sdr +++ b/tools/test_apps/system/flash_psram/sdkconfig.ci.f4r8_120sdr @@ -1,5 +1,7 @@ # Legacy, F4R8, Flash 120M SDR, PSRAM disable CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y +CONFIG_SPI_FLASH_HPM_ENA=y CONFIG_ESPTOOLPY_FLASHFREQ_120M=y +CONFIG_BOOTLOADER_FLASH_DC_AWARE=y CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y From 87182c9c763b0907e92c5ee3a4aa84fd14fba19d Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Tue, 17 Oct 2023 15:16:35 +0800 Subject: [PATCH 13/15] doc(spi_flash): hide unsupported optional features --- components/bootloader/Kconfig.projbuild | 3 +- components/bootloader/sdkconfig.rename | 2 - .../include/bootloader_flash_override.h | 2 +- .../bootloader_support/src/bootloader_flash.c | 2 +- .../src/esp32s3/bootloader_esp32s3.c | 2 +- components/spi_flash/Kconfig | 22 ---- .../storage/spi_flash_optional_feature.rst | 109 +++++++++--------- 7 files changed, 57 insertions(+), 85 deletions(-) diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index f428bec2e6f..f62af13ef83 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -101,7 +101,6 @@ menu "Bootloader config" config BOOTLOADER_FLASH_XMC_SUPPORT bool "Enable the support for flash chips of XMC (READ DOCS FIRST)" default y - depends on !IDF_ENV_BRINGUP help Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow. XMC chips will be forbidden to be used, when this option is disabled. @@ -119,7 +118,7 @@ menu "Bootloader config" config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH bool - default y if ESPTOOLPY_OCT_FLASH && SPI_FLASH_32BIT_ADDRESS + default y if ESPTOOLPY_OCT_FLASH && BOOTLOADER_FLASH_32BIT_ADDR default n endmenu diff --git a/components/bootloader/sdkconfig.rename b/components/bootloader/sdkconfig.rename index bbc1846e7a8..6aecd1523a1 100644 --- a/components/bootloader/sdkconfig.rename +++ b/components/bootloader/sdkconfig.rename @@ -24,6 +24,4 @@ CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE CONFIG_SECURE_FLASH_ # Secure Boot Scheme CONFIG_SECURE_BOOT_ENABLED CONFIG_SECURE_BOOT_V1_ENABLED -CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH -CONFIG_SPI_FLASH_QUAD_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH diff --git a/components/bootloader_support/include/bootloader_flash_override.h b/components/bootloader_support/include/bootloader_flash_override.h index 3650e28e0ae..6055e1781c7 100644 --- a/components/bootloader_support/include/bootloader_flash_override.h +++ b/components/bootloader_support/include/bootloader_flash_override.h @@ -96,7 +96,7 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup */ esp_err_t IRAM_ATTR __attribute__((weak)) bootloader_flash_unlock(void); -#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE +#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH /** * @brief Enable 32bits address flash(larger than 16MB) can map to cache. * diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index e73d77eb6ce..60620bdd826 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -487,7 +487,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size) return spi_to_esp_err(rc); } -#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE +#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode) { esp_rom_opiflash_spi0rd_t cache_rd = {}; diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index a9ff89ffa7e..f044e808a79 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -228,7 +228,7 @@ static esp_err_t bootloader_init_spi_flash(void) #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT bootloader_enable_qio_mode(); #endif -#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE +#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode()); #endif print_flash_info(&bootloader_image_hdr); diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index 91dec00950c..c9b51749b37 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -1,28 +1,6 @@ menu "Main Flash configuration" depends on !APP_BUILD_TYPE_PURE_RAM_APP - menu "SPI Flash behavior when brownout" - - config SPI_FLASH_BROWNOUT_RESET_XMC - bool "Enable sending reset when brownout for XMC flash chips" - default y - select SPI_FLASH_BROWNOUT_RESET - help - When this option is selected, the patch will be enabled for XMC. - Follow the recommended flow by XMC for better stability. - - DO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING. - - config SPI_FLASH_BROWNOUT_RESET - bool - default y - select ESP_SYSTEM_BROWNOUT_INTR - help - When brownout happens during flash erase/write operations, - send reset command to stop the flash operations to improve stability. - - endmenu - menu "Optional and Experimental Features (READ DOCS FIRST)" comment "Features here require specific hardware (READ DOCS FIRST!)" diff --git a/docs/en/api-reference/storage/spi_flash_optional_feature.rst b/docs/en/api-reference/storage/spi_flash_optional_feature.rst index b6a7523891f..d79079bb258 100644 --- a/docs/en/api-reference/storage/spi_flash_optional_feature.rst +++ b/docs/en/api-reference/storage/spi_flash_optional_feature.rst @@ -28,28 +28,29 @@ Some features are not supported on all ESP chips and Flash chips. You can check Auto Suspend & Resume --------------------- -.. only:: esp32c3 +This feature is only supported on ESP32-C3 for now. + +The support for ESP32-S3 may be added in the future. - You can refer to :ref:`auto-suspend` for more information about this feature. The support list is as follows. +.. only:: esp32c3 -ESP Chips List: + List of Flash chips that support this feature: -1. ESP32C3 + 1. XM25QxxC series. -Flash Chips List: + .. attention:: -1. XM25QxxC series. + There are multiple limitations about the auto-suspend feature, please do read :ref:`auto-suspend` for more information before you enable this feature. Flash unique ID --------------- -Unique ID is not flash id, which means flash has 64-Bit unique ID for each device. The instruction to read the unique ID (4Bh) accesses a factory-set read-only 64-bit number that is unique to each flash device. This ID number helps you to recognize each single device. Not all flash vendors support this feature. If you try to read the unique ID on a chip which does not have this feature, the behavior is not determined. The support list is as follows. +This feature is supported on all Espressif chips. -ESP Chips Lists: +Unique ID is not flash id, which means flash has 64-Bit unique ID for each device. The instruction to read the unique ID (4Bh) accesses a factory-set read-only 64-bit number that is unique to each flash device. This ID number helps you to recognize each single device. Not all flash vendors support this feature. If you try to read the unique ID on a chip which does not have this feature, the behavior is not determined. The support list is as follows. -ALL -Flash Chips List: +List of Flash chips that support this feature: 1. ISSI 2. GD @@ -62,72 +63,73 @@ Flash Chips List: High performance mode --------------------- -.. note:: +This featuer is only supported on ESP32-S3 for now. - This section is provided for Dual mode (DOUT/DIO) and Quad mode (QIO/QOUT) flash chips. Octal flash used on ESP-chips support High performance mode by default so far, you can refer to the octal flash support list below. +The support for ESP32-S2, ESP32-C3 may be added in the future. -High performance mode (HPM) means that the SPI1 and flash chip works under high frequency. Usually, when the operating frequency of the flash is greater than 80 MHz, it is considered that the flash works under HPM. +.. only:: esp32s3 -As far as we acknowledged, there are more than three strategies for High Performance Mode (HPM) in typical SPI flash parts. For some flash chips, HPM is controlled by dummy cycle bit in the registers, while for other chips, it can be controlled by other bits (like HPM bit) in the register, or some special command. The difference in strategies requires the driver to explicitly add support for each chip. + .. note:: -.. attention:: + This section is provided for Dual mode (DOUT/DIO) and Quad mode (QIO/QOUT) flash chips. Octal flash used on ESP-chips support High performance mode by default so far, you can refer to the octal flash support list below. - It is hard to create several strategies to cover all situations, so all flash chips using HPM need to be supported explicitly. Therefore, if you try to use a flash not listed in :ref:`hpm_dc_support_list`, it might cause some error. So, when you try to use the flash chip beyond supported list, please test properly. + High performance mode (HPM) means that the SPI1 and flash chip works under high frequency. Usually, when the operating frequency of the flash is greater than 80 MHz, it is considered that the flash works under HPM. -Moreover, when the `Dummy Cycle adjustment` strategy is adopted by the flash chip, the flash remains in a state in which DC is different from the default value after a software reset. The sub mode of HPM that adjusts the dummy cycle to run at higher frequency in the application is called `HPM-DC`. `HPM-DC` feature needs a feature `DC Aware` to be enabled in the bootloader. Otherwise different DC value will forbid the 2nd bootloader from being boot up after reset. + As far as we acknowledged, there are more than three strategies for High Performance Mode (HPM) in typical SPI flash parts. For some flash chips, HPM is controlled by dummy cycle bit in the registers, while for other chips, it can be controlled by other bits (like HPM bit) in the register, or some special command. The difference in strategies requires the driver to explicitly add support for each chip. -To enable High Performance Mode: + .. attention:: -1. De-select :ref:`CONFIG_ESPTOOLPY_OCT_FLASH`. HPM is not used for Octal flash, enabling related options may bypass HPM functions. + It is hard to create several strategies to cover all situations, so all flash chips using HPM need to be supported explicitly. Therefore, if you try to use a flash not listed in :ref:`hpm_dc_support_list`, it might cause some error. So, when you try to use the flash chip beyond supported list, please test properly. -2. Enable ``CONFIG_SPI_FLASH_HPM_ENA`` option. + Moreover, when the `Dummy Cycle adjustment` strategy is adopted by the flash chip, the flash remains in a state in which DC is different from the default value after a software reset. The sub mode of HPM that adjusts the dummy cycle to run at higher frequency in the application is called `HPM-DC`. `HPM-DC` feature needs a feature `DC Aware` to be enabled in the bootloader. Otherwise different DC value will forbid the 2nd bootloader from being boot up after reset. -3. Switch Flash frequency to HPM ones. For example, ``CONFIG_ESPTOOLPY_FLASHFREQ_120M``. + To enable High Performance Mode: -4. Make sure the config option for `HPM-DC` feature (under ``CONFIG_SPI_FLASH_HPM_DC`` choices) is selected correctly according to whether the bootloader supports `DC Aware`. + 1. De-select :ref:`CONFIG_ESPTOOLPY_OCT_FLASH`. HPM is not used for Octal flash, enabling related options may bypass HPM functions. - - If bootloader supports `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_AUTO``. This allows the usage of flash chips that adopted `Dummy Cycle adjustment` strategy. + 2. Enable ``CONFIG_SPI_FLASH_HPM_ENA`` option. - - If bootloader doesn't support `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_DISABLE``. It avoid consequences caused by running HPM-DC with non-DC-aware bootloaders. But please avoid using flash chips that adopts `Dummy Cycle adjustment` strategy if ``CONFIG_SPI_FLASH_HPM_DC_DISABLE`` is selected. See list of flash models that adpot DC strategy below. + 3. Switch Flash frequency to HPM ones. For example, ``CONFIG_ESPTOOLPY_FLASHFREQ_120M``. -Check whether the bootloader supports `DC Aware` in the following way: + 4. Make sure the config option for `HPM-DC` feature (under ``CONFIG_SPI_FLASH_HPM_DC`` choices) is selected correctly according to whether the bootloader supports `DC Aware`. -- If you are starting a new project, it's suggested to enable `DC Aware` by selecting :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` option in the bootloader menu. Please note that, you won't be able to modify this option via OTA, because the support is in the bootloader. + - If bootloader supports `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_AUTO``. This allows the usage of flash chips that adopted `Dummy Cycle adjustment` strategy. -- If you are working on an existing project and want to update `HPM-DC` config option in the app via OTA, check the sdkconfig file used to build your bootloader: (Upgrading ESP-IDF version may make this file different from the one used by bootloader to build.) + - If bootloader doesn't support `DC Aware`, select ``CONFIG_SPI_FLASH_HPM_DC_DISABLE``. It avoid consequences caused by running HPM-DC with non-DC-aware bootloaders. But please avoid using flash chips that adopts `Dummy Cycle adjustment` strategy if ``CONFIG_SPI_FLASH_HPM_DC_DISABLE`` is selected. See list of flash models that adpot DC strategy below. - - For latest version (ESP-IDF v4.4.7+, v5.2 and above), if :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` is selected, the bootloader supports `DC Aware`. + Check whether the bootloader supports `DC Aware` in the following way: - - For versions in this range: (v4.4.4-v4.4.6, v5.0+, and v5.1+), if ``CONFIG_ESPTOOLPY_FLASHFREQ_120M`` is selected, the bootloader supports `DC Aware`. In this case, enable :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` to confirm this (though it will not affect bootloader in devices in the field). + - If you are starting a new project, it's suggested to enable `DC Aware` by selecting :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` option in the bootloader menu. Please note that, you won't be able to modify this option via OTA, because the support is in the bootloader. - - For versions below v4.4.4, the bootloader doesn't support `DC Aware`. + - If you are working on an existing project and want to update `HPM-DC` config option in the app via OTA, check the sdkconfig file used to build your bootloader: (Upgrading ESP-IDF version may make this file different from the one used by bootloader to build.) -ESP Chips List: + - For latest version (ESP-IDF v4.4.7+, v5.2 and above), if :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` is selected, the bootloader supports `DC Aware`. -1. ESP32S3 + - For versions in this range: (v4.4.4-v4.4.6, v5.0+, and v5.1+), if ``CONFIG_ESPTOOLPY_FLASHFREQ_120M`` is selected, the bootloader supports `DC Aware`. In this case, enable :ref:`CONFIG_BOOTLOADER_FLASH_DC_AWARE` to confirm this (though it will not affect bootloader in devices in the field). -(The SW support for other chips haven't been done yet) + - For versions below v4.4.4, the bootloader doesn't support `DC Aware`. -.. _hpm_dc_support_list: + .. _hpm_dc_support_list: -Quad Flash HPM support list -^^^^^^^^^^^^^^^^^^^^^^^^^^^ + Quad Flash HPM support list + ^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Flash chips that don't need HPM-DC: + Flash chips that don't need HPM-DC: -1. GD25Q64C (ID: 0xC84017) -2. GD25Q32C (ID: 0xC84016) -3. ZB25VQ32B (ID: 0x5E4016) -4. GD25LQ255E (ID: 0xC86019) + 1. GD25Q64C (ID: 0xC84017) + 2. GD25Q32C (ID: 0xC84016) + 3. ZB25VQ32B (ID: 0x5E4016) -Following flash chips also have HPM feature, but requires the bootloader to support `DC Aware`: + Following flash chips also have HPM feature, but requires the bootloader to support `DC Aware`: -1. GD25Q64E (ID: 0xC84017) -2. GD25Q128E (ID: 0xC84018) + 1. GD25Q64E (ID: 0xC84017) + 2. GD25Q128E (ID: 0xC84018) OPI flash support ----------------- +This feature is only supporetd on ESP32-S3 for now. + OPI flash means that the flash chip supports octal peripheral interface, which has octal I/O pins. Different octal flash has different configurations and different commands. Hence, it is necessary to carefully check the support list. .. only:: esp32s3 @@ -136,28 +138,23 @@ OPI flash means that the flash chip supports octal peripheral interface, which h To know how to configure menuconfig for a board with different Flash and PSRAM, please refer to the :ref:`SPI Flash and External SPI RAM Configuration ` -ESP Chips List: - -1. ESP32S3 - -Flash Chips List: + List of Flash chips that support this feature: -1. MX25UM25645G + 1. MX25UM25645G + 2. MX25UM12345G 32-bit Address Flash Chips -------------------------- -Most NOR flash chips used by Espressif chips use 24-bits address, which can cover 16 MBytes memory. However, for larger memory (usually equal to or larger than 16 MBytes), flash uses a 32-bits address to address larger memory. Regretfully, 32-bits address chips have vendor-specific commands, so we need to support the chips one by one. - -ESP Chips List: +This feature is supported on all Espressif chips (with various restrictions to application). -ALL ESP Chips support this. +Most NOR flash chips used by Espressif chips use 24-bits address, which can cover 16 MBytes memory. However, for larger memory (usually equal to or larger than 16 MBytes), flash uses a 32-bits address to address larger memory. Regretfully, 32-bits address chips have vendor-specific commands, so we need to support the chips one by one. -Flash Chips List: +List of Flash chips that support this feature: 1. W25Q256 2. GD25Q256 .. important:: - Over 16 MBytes space on flash mentioned above can be only used for ``data saving``, like file system. If your data/instructions over 16 MBytes spaces need to be mapped to MMU (so as to be accessed by the CPU), please upgrade to ESP-IDF v5.2 and read the latest docs. \ No newline at end of file + Over 16 MBytes space on flash mentioned above can be only used for ``data saving``, like file system. If your data/instructions over 16 MBytes spaces need to be mapped to MMU (so as to be accessed by the CPU), please upgrade to ESP-IDF v5.2 and read the latest docs. From 2a6797d016c92d1b0476bd22e76abcc8284fc928 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 2 Aug 2022 19:01:19 +0800 Subject: [PATCH 14/15] kconfig: support plain comment in the menu --- components/esp_lcd/Kconfig | 2 ++ tools/kconfig_new/gen_kconfig_doc.py | 21 +++++---------------- 2 files changed, 7 insertions(+), 16 deletions(-) diff --git a/components/esp_lcd/Kconfig b/components/esp_lcd/Kconfig index 6c48962affe..b00747ca9c4 100644 --- a/components/esp_lcd/Kconfig +++ b/components/esp_lcd/Kconfig @@ -1,4 +1,6 @@ menu "LCD and Touch Panel" + comment "LCD Touch Drivers are maintained in the IDF Component Registry" + menu "LCD Peripheral Configuration" config LCD_PANEL_IO_FORMAT_BUF_SIZE int "LCD panel io format buffer size" diff --git a/tools/kconfig_new/gen_kconfig_doc.py b/tools/kconfig_new/gen_kconfig_doc.py index 0ba78cb80d6..5d96e483095 100644 --- a/tools/kconfig_new/gen_kconfig_doc.py +++ b/tools/kconfig_new/gen_kconfig_doc.py @@ -7,21 +7,8 @@ # generated, allowing options to be referenced in other documents # (using :ref:`CONFIG_FOO`) # -# Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http:#www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -from __future__ import print_function - +# SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 import re import kconfiglib @@ -108,6 +95,8 @@ def node_is_invisible(item): return (False, None) def _visible(self, node): + if node.item == kconfiglib.COMMENT: + return (False, None) if isinstance(node.item, kconfiglib.Symbol) or isinstance(node.item, kconfiglib.Choice): dependencies = node.item.direct_dep # "depends on" for configs name_id = node.item.name @@ -159,7 +148,7 @@ def write_docs(config, visibility, filename): def node_is_menu(node): try: - return node.item == kconfiglib.MENU or node.is_menuconfig + return node.item in [kconfiglib.MENU, kconfiglib.COMMENT] or node.is_menuconfig except AttributeError: return False # not all MenuNodes have is_menuconfig for some reason From 8efc66495bb9a27c8326de42d857c34c2721d57a Mon Sep 17 00:00:00 2001 From: Rahul Tank Date: Fri, 2 Feb 2024 11:40:33 +0530 Subject: [PATCH 15/15] fix(nimble): Add adv interval min/max range check (v4.4) --- components/bt/host/nimble/nimble | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 2e8d2add8da..4fd8f684f8e 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 2e8d2add8dae7acbbf38b5925e5774fae9fb6af0 +Subproject commit 4fd8f684f8ecbaa32301644849157015a8beed66