Merge branch 'espressif:release/v4.4' into release/v4.4

.gitlab/ci/target-test.yml

@@ -782,8 +782,16 @@ UT_S3_FLASH:
     - ESP32S3_IDF
     - UT_T1_ESP_FLASH
 
+component_ut_test_ip101:
+  extends: .component_ut_esp32_template
+  image: $CI_DOCKER_REGISTRY/ubuntu-test-env
+  tags:
+    - ESP32
+    - eth_ip101
+
 component_ut_test_lan8720:
   extends: .component_ut_esp32_template
+  image: $CI_DOCKER_REGISTRY/ubuntu-test-env
   tags:
     - ESP32
-    - COMPONENT_UT_LAN8720
+    - eth_lan8720

.pre-commit-config.yaml

@@ -36,11 +36,12 @@ repos:
     hooks:
       - id: flake8
         args: ['--config=.flake8', '--tee', '--benchmark']
-  - repo: https://github.com/pycqa/isort
-    rev: 5.11.5  # python 3.7 compatible
+  - repo: https://github.com/asottile/reorder-python-imports
+    rev: v3.12.0
     hooks:
-      - id: isort
-        name: isort (python)
+      - id: reorder-python-imports
+        name: Reorder Python imports
+        args: [--py36-plus]
         exclude: >
           (?x)^(
               .*_pb2.py

components/bootloader/Kconfig.projbuild

@@ -62,34 +62,66 @@ menu "Bootloader config"
         default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
         default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
 
-    config BOOTLOADER_SPI_CUSTOM_WP_PIN
-        bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"
-        depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
-        default y if BOOTLOADER_SPI_WP_PIN != 7  # backwards compatibility, can remove in IDF 5
-        default n
-        help
-            This setting is only used if the SPI flash pins have been overridden by setting the eFuses
-            SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.
+    menu "Serial Flash Configurations"
+        config BOOTLOADER_SPI_CUSTOM_WP_PIN
+            bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"
+            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
+            default y if BOOTLOADER_SPI_WP_PIN != 7  # backwards compatibility, can remove in IDF 5
+            default n
+            help
+                This setting is only used if the SPI flash pins have been overridden by setting the eFuses
+                SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.
+
+                When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
+                ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used
+                for external SPIRAM if it is enabled.
+
+                If this config item is set to N (default), the correct WP pin will be automatically used for any
+                Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to
+                Y and specify the GPIO number connected to the WP.
+
+        config BOOTLOADER_SPI_WP_PIN
+            int "Custom SPI Flash WP Pin"
+            range 0 33
+            default 7
+            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
+            #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN  # backwards compatibility, can uncomment in IDF 5
+            help
+                The option "Use custom SPI Flash WP Pin" must be set or this value is ignored
 
-            When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
-            ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used
-            for external SPIRAM if it is enabled.
+                If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this
+                value to the GPIO number of the SPI flash WP pin.
 
-            If this config item is set to N (default), the correct WP pin will be automatically used for any
-            Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to
-            Y and specify the GPIO number connected to the WP.
+        config BOOTLOADER_FLASH_DC_AWARE
+            bool "Allow app adjust Dummy Cycle bits in SPI Flash for higher frequency (READ HELP FIRST)"
+            help
+                This will force 2nd bootloader to be loaded by DOUT mode, and will restore Dummy Cycle setting by
+                resetting the Flash
 
-    config BOOTLOADER_SPI_WP_PIN
-        int "Custom SPI Flash WP Pin"
-        range 0 33
-        default 7
-        depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
-        #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN  # backwards compatibility, can uncomment in IDF 5
-        help
-            The option "Use custom SPI Flash WP Pin" must be set or this value is ignored
+        config BOOTLOADER_FLASH_XMC_SUPPORT
+            bool "Enable the support for flash chips of XMC (READ DOCS FIRST)"
+            default y
+            help
+                Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
+                XMC chips will be forbidden to be used, when this option is disabled.
+
+                DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.
 
-            If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this
-            value to the GPIO number of the SPI flash WP pin.
+                comment "Features below require specific hardware (READ DOCS FIRST!)"
+
+        config BOOTLOADER_FLASH_32BIT_ADDR
+            bool
+            default y if ESPTOOLPY_FLASHSIZE_32MB || ESPTOOLPY_FLASHSIZE_64MB || ESPTOOLPY_FLASHSIZE_128MB
+            default n
+            help
+                This is a helper config for 32bits address flash. Invisible for users.
+
+        config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
+            bool
+            default y if ESPTOOLPY_OCT_FLASH && BOOTLOADER_FLASH_32BIT_ADDR
+            default n
+
+    endmenu
 
     choice BOOTLOADER_VDDSDIO_BOOST
         bool "VDDSDIO LDO voltage"
@@ -393,14 +425,6 @@ menu "Bootloader config"
             in this area of memory, you can increase it. It must be a multiple of 4 bytes.
             This area (rtc_retain_mem_t) is reserved and has access from the bootloader and an application.
 
-    config BOOTLOADER_FLASH_XMC_SUPPORT
-        bool "Enable the support for flash chips of XMC (READ HELP FIRST)"
-        default y
-        help
-            Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
-            XMC chips will be forbidden to be used, when this option is disabled.
-
-            DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.
 
 endmenu  # Bootloader
 

components/bootloader/sdkconfig.rename

@@ -23,3 +23,5 @@ CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE         CONFIG_SECURE_FLASH_
 
 # Secure Boot Scheme
 CONFIG_SECURE_BOOT_ENABLED                                  CONFIG_SECURE_BOOT_V1_ENABLED
+
+CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE                    CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH

components/bootloader_support/include/bootloader_flash_override.h

@@ -96,7 +96,7 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup
   */
 esp_err_t IRAM_ATTR __attribute__((weak)) bootloader_flash_unlock(void);
 
-#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
 /**
  * @brief Enable 32bits address flash(larger than 16MB) can map to cache.
  *

components/bootloader_support/src/bootloader_flash.c

@@ -487,7 +487,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
     return spi_to_esp_err(rc);
 }
 
-#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
 void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode)
 {
     esp_rom_opiflash_spi0rd_t cache_rd = {};

components/bootloader_support/src/esp32s3/bootloader_esp32s3.c

@@ -218,7 +218,7 @@ static esp_err_t bootloader_init_spi_flash(void)
     }
 #endif
 
-#if CONFIG_SPI_FLASH_HPM_ENABLE
+#if CONFIG_BOOTLOADER_FLASH_DC_AWARE
     // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot.
     bootloader_spi_flash_reset();
 #endif
@@ -228,7 +228,7 @@ static esp_err_t bootloader_init_spi_flash(void)
 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
     bootloader_enable_qio_mode();
 #endif
-#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
     bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
 #endif
     print_flash_info(&bootloader_image_hdr);

components/bt/controller/esp32c3/bt.c

@@ -763,19 +763,26 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles)
         return;
     }
 
-    // start a timer to wake up and acquire the pm_lock before modem_sleep awakes
     uint32_t us_to_sleep = btdm_lpcycles_2_hus(lpcycles, NULL) >> 1;
 
 #define BTDM_MIN_TIMER_UNCERTAINTY_US      (1800)
+#define BTDM_RTC_SLOW_CLK_RC_DRIFT_PERCENT 7
     assert(us_to_sleep > BTDM_MIN_TIMER_UNCERTAINTY_US);
     // allow a maximum time uncertainty to be about 488ppm(1/2048) at least as clock drift
     // and set the timer in advance
     uint32_t uncertainty = (us_to_sleep >> 11);
+#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+    if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) {
+        uncertainty = us_to_sleep * BTDM_RTC_SLOW_CLK_RC_DRIFT_PERCENT / 100;
+    }
+#endif
+
     if (uncertainty < BTDM_MIN_TIMER_UNCERTAINTY_US) {
         uncertainty = BTDM_MIN_TIMER_UNCERTAINTY_US;
     }
 
     assert (s_lp_stat.wakeup_timer_started == 0);
+    // start a timer to wake up and acquire the pm_lock before modem_sleep awakes
     if (esp_timer_start_once(s_btdm_slp_tmr, us_to_sleep - uncertainty) == ESP_OK) {
         s_lp_stat.wakeup_timer_started = 1;
     } else {
@@ -794,12 +801,12 @@ static void btdm_sleep_enter_phase2_wrapper(void)
             assert(0);
         }
 
-        if (s_lp_stat.pm_lock_released == 0) {
 #ifdef CONFIG_PM_ENABLE
+        if (s_lp_stat.pm_lock_released == 0) {
             esp_pm_lock_release(s_pm_lock);
-#endif
             s_lp_stat.pm_lock_released = 1;
         }
+#endif
     }
 }
 

components/esp32s3/Kconfig

@@ -307,7 +307,7 @@ menu "ESP32S3-Specific"
 
             config SPIRAM_SPEED_120M
                 depends on SPIRAM_MODE_QUAD
-                bool "120MHz clock speed"
+                bool "120MHz clock speed (READ DOCS FIRST)"
             config SPIRAM_SPEED_80M
                 bool "80MHz clock speed"
             config SPIRAM_SPEED_40M

components/esp_eth/test_apps/component_ut_test.py

@@ -19,6 +19,8 @@ def configure_eth_if(func):         # type: (typing.Any) -> typing.Any
     def inner(*args, **kwargs):     # type: (typing.Any, typing.Any) -> typing.Any
         # try to determine which interface to use
         netifs = os.listdir('/sys/class/net/')
+        # order matters - ETH NIC with the highest number is connected to DUT on CI runner
+        netifs.sort(reverse=True)
         target_if = ''
         print('detected interfaces: ' + str(netifs))
         for netif in netifs:
@@ -65,17 +67,19 @@ def send_eth_packet(so, mac):    # type: (socket.socket, str) -> None
 
 @configure_eth_if
 def recv_resp_poke(so, i):    # type: (socket.socket, int) -> None
-    so.settimeout(10)
+    so.settimeout(30)
     try:
-        eth_frame = Ether(so.recv(60))
-
-        if eth_frame.type == 0x2222 and eth_frame.load[0] == 0xfa:
-            if eth_frame.load[1] != i:
-                raise Exception('Missed Poke Packet')
-            eth_frame.dst = eth_frame.src
-            eth_frame.src = so.getsockname()[4]
-            eth_frame.load = bytes.fromhex('fb')    # POKE_RESP code
-            so.send(raw(eth_frame))
+        for _ in range(10):
+            eth_frame = Ether(so.recv(60))
+
+            if eth_frame.type == 0x2222 and eth_frame.load[0] == 0xfa:
+                if eth_frame.load[1] != i:
+                    raise Exception('Missed Poke Packet')
+                eth_frame.dst = eth_frame.src
+                eth_frame.src = so.getsockname()[4]
+                eth_frame.load = bytes.fromhex('fb')    # POKE_RESP code
+                so.send(raw(eth_frame))
+                break
     except Exception as e:
         raise e
 
@@ -145,16 +149,16 @@ def test_component_ut_esp_eth(env, appname):  # type: (tiny_test_fw.Env, str) ->
     ttfw_idf.ComponentUTResult.parse_result(stdout, test_format=TestFormat.UNITY_BASIC)
 
 
-# @ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_IP101', target=['esp32'])
-# def test_component_ut_esp_eth_ip101(env, _):  # type: (tiny_test_fw.Env, typing.Any) -> None
-#     test_component_ut_esp_eth(env, 'ip101')
+@ttfw_idf.idf_component_unit_test(env_tag='eth_ip101', target=['esp32'])
+def test_component_ut_esp_eth_ip101(env, _):  # type: (tiny_test_fw.Env, typing.Any) -> None
+    test_component_ut_esp_eth(env, 'ip101')
 
 
-@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_LAN8720', target=['esp32'])
+@ttfw_idf.idf_component_unit_test(env_tag='eth_lan8720', target=['esp32'])
 def test_component_ut_esp_eth_lan8720(env, _):  # type: (tiny_test_fw.Env, typing.Any) -> None
     test_component_ut_esp_eth(env, 'lan8720')
 
 
 if __name__ == '__main__':
-    # test_component_ut_esp_eth_ip101()
+    test_component_ut_esp_eth_ip101()
     test_component_ut_esp_eth_lan8720()