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Changes from NRAO #18

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merged 6 commits into from
May 8, 2023
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@mschiller-nrao mschiller-nrao commented Mar 25, 2023

  1. Implemented Twiddle generation in VHDL
  2. Adding files for Sigasi library mappings
  3. Fixed some compile issues in Questa
  4. Added gitlab CI configs (mostly for NRAO internal use)
  5. Added testbenches for Twiddle Generation
  6. A python module for FFT verification
  7. Rounding updates to implement round 2 even.

Sorry about the churn on this pull request... I wasn't happy with what I managed to do in GIT I had 1000's of changes as compared to your branch. Which I have no idea how happened.

…remote)

Squashed commit of the following:

commit 48df3a6a37865b486e4dae139dc9e57a1ee62577
Merge: 494bb57 c24d2b4
Author: Matthew Schiller <[email protected]>
Date:   Sat Mar 25 18:32:42 2023 -0400

    Remerging with NRAO local

commit c24d2b438c466679ffd76bfc4593a950c5068544
Author: Matthew Schiller <[email protected]>
Date:   Sat Mar 25 17:59:13 2023 -0400

    Fix typo in twiddlepackage
    disable known Manual test (set as manual)

commit 85e554e7fdb5393d78b40514e1a567089927a49a
Author: Matthew Schiller <[email protected]>
Date:   Sat Mar 25 17:47:28 2023 -0400

    Removing Magic file tests

commit dac6c73d5d2623c0dc9c0fd22a4942a04ef2b089
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 24 18:26:23 2023 -0400

    Fix for typo in LFS selections

commit 64c8b202b3b512637f856296f8646ff4fad58e38
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 24 16:32:33 2023 -0400

    REmoving text files that should've been in LFS

commit a9bb8dcaa1bd34d7a80f0e9e333ddcbc3d68f588
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 24 16:26:04 2023 -0400

    Setup LFS for twiddlepkg files
    Created Twiddle pkg files with stored VHDL twiddle results
    Implemented a twiddle generation testbench

commit 583f7775a42d8cea44119de20b857cb76bbb5ee7
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 24 09:56:17 2023 -0400

    Added plot titles

commit dfd959fe128e2ec83cc22385f08b8182e70b20cf
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 24 08:57:19 2023 -0400

    Fixed bug that broke in wb=4 mode.

commit 3caea80dfb290863dc4aa088a9de0c6bfec25c0b
Author: Matthew Schiller <[email protected]>
Date:   Thu Mar 23 15:17:35 2023 -0400

    Fix issue with type conversion in GHDL

commit 0c5f489f7fa796b5c145ce43f4c3ee9e89c3839a
Author: Matthew Schiller <[email protected]>
Date:   Thu Mar 23 15:04:26 2023 -0400

    Implemented Inferred Twiddle Factors
    Added Additional Rounding support
    Initial cut at a python model for the FFT (not verified or used yet)

commit 494bb579ea190e8094406994b6ba328fbe62e17e
Merge: 68ca652 1632d0c
Author: mschiller-nrao <[email protected]>
Date:   Tue Mar 21 09:01:49 2023 -0400

    Merge pull request #1 from mschiller-nrao/main

    Move into master

commit 71b13b54ea36a6579e9f5465a6a1fff2fccaec8f
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 21 08:57:10 2023 -0400

    Fix Python to allow MIF file generation for twids

commit 1632d0c5d72715afaa69fc97355c7f5926294ba5
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 21 08:57:10 2023 -0400

    Fix Python to allow MIF file generation for twids

commit 81885805ef0211d6b4d0de0a7c0ddf9822ea894a
Author: Matthew Schiller <[email protected]>
Date:   Mon Mar 20 13:11:19 2023 -0400

    Fixed rounding to use convergent round 2 even for signed values
    add sigasi project management files

commit 4e1f694e2dc0dbeef1aa6d766322331cfc117190
Author: Matthew Schiller <[email protected]>
Date:   Mon Mar 20 13:11:19 2023 -0400

    Fixed rounding to use convergent round 2 even for signed values
    add sigasi project management files

commit 68ca652e2940a25d7e57772b4caf5fc55caedb1e
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 14:19:06 2023 -0400

    Fix to set generics when operating in single mode.  Endian generics still must be set for Questa

commit 9a26642e5e09327096f6ef72926ed1b2937ed12c
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 14:19:06 2023 -0400

    Fix to set generics when operating in single mode.  Endian generics still must be set for Questa

commit f587e1aa143e3ea957d02c6b44f49238d3170853
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 13:47:34 2023 -0400

    Fixing missing generics.

commit 9c2d33ef7c16ee29caef0b0ceaab80b0f588110f
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 13:47:34 2023 -0400

    Fixing missing generics.

commit 424b6d567e0a082f1818d8cc79db3d33c74ca8e6
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 08:25:39 2023 -0400

    Fix Multiplier to work in Questa

commit 238555a06605219c0f4c888ec5ed3760e83cb7cd
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 08:25:39 2023 -0400

    Fix Multiplier to work in Questa

commit cbcceb9fa81b5db9dfd5a0b57a956a20d96eb6c1
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:58:35 2023 -0400

    Update .gitlab-ci.yml file

commit 94c01caf96b53ca0b278ae2b5ac33d47adfba7eb
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:58:35 2023 -0400

    Update .gitlab-ci.yml file

commit 3bf45a907b240e4c386219c75d43e0a882ec2c75
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:55:51 2023 -0400

    Update .gitlab-ci.yml file

commit 974fb7cbe99df41e83eed307aeca117ef1d86941
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:55:51 2023 -0400

    Update .gitlab-ci.yml file

commit 811e5e2ebda4aadf97499d4b338babaf38cb558b
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:53:30 2023 -0400

    Add virtual "RunQuesta" job that will always pass as the gatekeeper for other sims

commit 423a4d4611731bca5185523b432399e32628af61
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:53:30 2023 -0400

    Add virtual "RunQuesta" job that will always pass as the gatekeeper for other sims

commit dddb2d3b1cab9ee2a102738549ab7243dd4b6efb
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:46:36 2023 -0400

    fix config names for Questa

commit ff58e8883c23475c07ad1b2df4d0fa6cc44814d2
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:46:36 2023 -0400

    fix config names for Questa

commit f49494067f5c76006e8d4e323f034433d92074dc
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:45:36 2023 -0400

    Update .gitlab-ci.yml file

commit ba1a4a9f83622ce48f7397869a3d3edb30d71e59
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:45:36 2023 -0400

    Update .gitlab-ci.yml file

commit b6ac5b3539b6becfa572dbc29b6a484c2ccea175
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:20:19 2023 -0400

    Update .gitlab-ci.yml file

commit 7deaf9ce7c6f8b0f9a412aa0b8daa4e5c7e36a9c
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:20:19 2023 -0400

    Update .gitlab-ci.yml file

commit 7ad0a1b69f0294c1125d9bd5d04f84faf6b5ac9f
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:17:49 2023 -0400

    Update .gitlab-ci.yml file

commit 9d813ec9ef2d574dbbfe89fe34adcb53975c2e96
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:17:49 2023 -0400

    Update .gitlab-ci.yml file

commit f0c60d162c932032db6be8066775642bf9dde488
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:04:02 2023 -0400

    Changed Test names to allow Questa simulation to run

commit 7dd763df30a3e284db905780d322bd7c240c5db3
Author: Matthew Schiller <[email protected]>
Date:   Sun Mar 19 07:04:02 2023 -0400

    Changed Test names to allow Questa simulation to run

commit f789bdcec9c3520c204b0daf166abe33b1d24ee1
Author: Matthew Schiller <[email protected]>
Date:   Sat Mar 18 22:28:07 2023 -0400

    Update .gitlab-ci.yml file

commit d9db1bd06907d1ad6f558566b6ca4b4445ba7b4b
Author: Matthew Schiller <[email protected]>
Date:   Sat Mar 18 22:28:07 2023 -0400

    Update .gitlab-ci.yml file

commit 1106a2057dda51504ce4a80400781b90526ccdf7
Author: Matthew Schiller <[email protected]>
Date:   Sat Mar 18 22:22:03 2023 -0400

    Update .gitlab-ci.yml file

commit b4a109c4316a579870ca53b4c3052cc01d3c4376
Author: Matthew Schiller <[email protected]>
Date:   Sat Mar 18 22:22:03 2023 -0400

    Update .gitlab-ci.yml file

commit cc9b207ed0f6ba2dd3287055cfe6f76272c11823
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 18:47:01 2023 -0400

    Update .gitlab-ci.yml file

commit 19c73d4fb90c7bb4c0a3751b20f40a5a8f645397
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 18:47:01 2023 -0400

    Update .gitlab-ci.yml file

commit 84443302e1c3c05a74b49627f32e9b10fdaeba80
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 18:41:17 2023 -0400

    Add artifacts and reports

commit ecd0c422133880ceefd32a234534be2c79a4b0a6
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 18:41:17 2023 -0400

    Add artifacts and reports

commit a55e78420a530bdbb2c5a20f5c285254bba61d67
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 16:25:36 2023 -0400

    Working on getting Teros working

commit 423c5fac81e81901878f28766efb75488c72cdfa
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 16:25:36 2023 -0400

    Working on getting Teros working

commit 609d51f97f45a91fb6fc37dee0ae23666bddc516
Merge: 9eea9e6 297e0b8
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 13:08:45 2023 -0400

    Merge branch 'mschille-master-patch-81814' into 'master'

    Update technology/technology_select_pkg.vhd

    See merge request ngvlabackend/casper_dspdevel!1

commit b44ea5aaf84650851ef4734a0d81efda4dfeb82d
Merge: 8a68748 a464176
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 13:08:45 2023 -0400

    Merge branch 'mschille-master-patch-81814' into 'master'

    Update technology/technology_select_pkg.vhd

    See merge request ngvlabackend/casper_dspdevel!1

commit 297e0b842651fabe41861630da289e3376c09c54
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 13:08:04 2023 -0400

    Update technology/technology_select_pkg.vhd

commit a4641767708b80f6f63617d9d116ceb851e07a98
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 13:08:04 2023 -0400

    Update technology/technology_select_pkg.vhd

commit 9eea9e6a8db6c7ca062a3decaf02df4e1eac19c7
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 13:00:51 2023 -0400

    Update .gitlab-ci.yml file

commit 8a687484c3e6bb6bd9ea286c1258dc0ef23da50d
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 13:00:51 2023 -0400

    Update .gitlab-ci.yml file

commit 789b3d274907ff8b08ade40bf664e42f3d866bc1
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:46:54 2023 -0400

    Update .gitlab-ci.yml file

commit 7e4693f2a650178521a406bc3e87ea5da22d9ed8
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:46:54 2023 -0400

    Update .gitlab-ci.yml file

commit 81ffd160cdd1a4ccd3c1e4c3b21eadb38bbe72da
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:38:49 2023 -0400

    Update .gitlab-ci.yml file

commit c9d2142662e5ebc2f4c20e14bc51e4b16bd16b70
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:38:49 2023 -0400

    Update .gitlab-ci.yml file

commit 14ba2418d8b823f94a470f2cbbe1dada78bbba3e
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:35:06 2023 -0400

    Update .gitlab-ci.yml file

commit b35122fc630423b1440892db6a9b3d80f629da14
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:35:06 2023 -0400

    Update .gitlab-ci.yml file

commit e1a8e5930682eb1a655ac751ceb182e297140284
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:24:28 2023 -0400

    Update .gitlab-ci.yml file

commit ed482d98225dd3a7766dec63c4dc522218b3c433
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:24:28 2023 -0400

    Update .gitlab-ci.yml file

commit be26ade7dab84c6181d4db6cbb7c67e33f5f10ee
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:01:16 2023 -0400

    Update .gitlab-ci.yml file

commit 062314db243ec651345545c0f97122fb4dddb43a
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 12:01:16 2023 -0400

    Update .gitlab-ci.yml file

commit 203034639efd141af2335f530c4e6ef9b4ecc870
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 11:10:10 2023 -0400

    Fixed line endings

commit 61ff50604b473d2f5a2cca5a6879b1feb46652bc
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 11:10:10 2023 -0400

    Fixed line endings

commit 6069b2866cb92975b230827553fc5a315b9cdeeb
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 11:05:57 2023 -0400

    Fixes to allow simulations to pass

commit 15d7c2e940cd59eee5c89ae722e94f472f1f1f30
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 17 11:05:57 2023 -0400

    Fixes to allow simulations to pass

commit 5acf40496bdbc0e701faef3cc51df6e84f1438e8
Merge: e4a8cc8 598a133
Author: Andrew Martens <[email protected]>
Date:   Tue Dec 6 17:50:00 2022 +0200

    Merge branch 'master' of github.com:talonmyburgh/casper_dspdevel

commit 598a1338ec68943e18ea9fe4083647320a07212e
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 3 14:27:27 2022 +0200

    ** remove dsp48 vacc from unit test - requires UNISIM

commit ec8c40c40c1478d1ff95cd37bd9988ccf012361c
Author: radonnachie <[email protected]>
Date:   Tue Nov 1 17:56:11 2022 +0200

    * workflows/test files_changed

commit 4b3c8a13d4ff28a35d67a8254ccebeabe495ab51
Author: radonnachie <[email protected]>
Date:   Tue Nov 1 17:54:01 2022 +0200

    ^ casper_delay/run.py misc lib

commit 74b9921f0edd9b77efdbe9d2fe307d573179f055
Author: radonnachie <[email protected]>
Date:   Tue Nov 1 17:50:24 2022 +0200

    + workflows/test use container ghdl/vunit:llvm-master

commit 626ec8f6787c24961e65aebc9c195488ee0e4f18
Author: radonnachie <[email protected]>
Date:   Tue Nov 1 13:27:03 2022 +0200

    + workflows/test Update git step

commit a733dc70145e2a8650db5e52d89b81581b9cf96e
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 12:17:08 2022 +0200

    ** using v2 checkout actions and recursive submodules

commit 8c868ae4c9aa98020b4a64cfc35b63a949f9123d
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 12:11:07 2022 +0200

    ** install git from new ppa

commit 831fe1fe1c6d180d2df1740982dad34b1c962adb
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 12:06:56 2022 +0200

    ** sudo

commit d127694873d2134849e8de38b3350f73bd86b0b8
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 12:05:59 2022 +0200

    ** manually switch git ppa

commit 292c179e45cf262ec6c0e247b4de71b40c1ee5f7
Author: radonnachie <[email protected]>
Date:   Tue Nov 1 12:03:53 2022 +0200

    ^ misc/tb_sample_and_hold

commit 1f27185af5701bc0563502e8720810b840027954
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 11:53:31 2022 +0200

    ** actual version 3

commit 46180e945987fc9667d3a2c07987866de86e9efc
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 11:52:24 2022 +0200

    ** version 3 and manual submodule update

commit 5c0c4bb8c20638188597230ac9a0ee841150f09a
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 11:45:52 2022 +0200

    ** try version 3

commit acd0d22f425f0d88c023ad6de19622f82ebb9621
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 11:40:41 2022 +0200

    ** manually submodule the repositories

commit f48291c3f918163d256e3adca2106e83e515ecdd
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 11:34:02 2022 +0200

    ** fetch depth 0

commit fa15be5e4af06f84568aef146a9f840fa9cec222
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 1 11:31:55 2022 +0200

    ** submodule recursive update clone

commit c02d3fc99048682a572e60d4bf5d12b9c5b5cde5
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 12:39:14 2022 +0200

    v .github/workflows/test WIP

commit 4dc4ca528e2207cf980411ce5977921b0927367b
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 12:37:22 2022 +0200

    * .github/workflows/test update git

commit 396f3e4642f1f12f463bd2e0443e16a8fcacd6f8
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 12:25:37 2022 +0200

    * .github/workflows/test WIP

commit 50bd903ee492d475631120174856c3452192af35
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 12:22:54 2022 +0200

    ^ .github/workflows/test.yml pip install numpy

commit 93c764ed2ccfe0bac6aa5f648a984b664c3f2af8
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:59:36 2022 +0200

    ^ .github/workflows/test.yml pip install numpy

commit 5d0111feb53c0a92727b14e911c72de8a73a862a
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:54:30 2022 +0200

    ^ .github/workflows/test.yml pip3 install numpy

commit a5c5e2fc2ea3c74eff8007c49764701d94b1dfbf
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:52:01 2022 +0200

    ^ .github/workflows/test.yml filter tests

commit 85c94fe2f2923ee0fe48bd27373e29a8b6093542
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:50:28 2022 +0200

    ^ .github/workflows/test.yml pip3 install numpy

commit 9f08d7b7277a3a1bee2882ef627044dbc012d507
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:47:59 2022 +0200

    ^ .github/workflows/test.yml checkout submodule, pip install numpy

commit 60af97d79e62c00a4dd9abdd2e48c26f14137ff4
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:44:47 2022 +0200

    ^ misc/run.py

commit 155902a4aea82be98f4f90c24fbd4b74a1be1c5b
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:32:43 2022 +0200

    + README badges, trigger tests: accs, delay, filter, flow_ctrl, misc

commit abdebb5dd994440fe708d673f10aaf1145a44fd2
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:29:07 2022 +0200

    + github/workflows/test: accs, delay, filter, flow_ctrl, misc

commit dd73cae98b12afb631cc34a5d68589dde6f9959e
Author: RocketRoss <[email protected]>
Date:   Wed Sep 7 11:18:17 2022 +0200

    + docs accum, delay, flow_control, misc: ^ wb_fft refs

commit 09cd4b8000d7c846eff5d0bab3673143f80a83b8
Author: RocketRoss <[email protected]>
Date:   Thu Sep 1 13:14:21 2022 +0200

    v .github\workflows\test if changed

commit 6435a745b0dc1bceb88099f252143e931cf85cdf
Author: RocketRoss <[email protected]>
Date:   Thu Sep 1 12:19:49 2022 +0200

    * github/workflows/test all

commit 89e04d10872e6bda005fc30d92c47b035f3a3c5e
Author: radonnachie <[email protected]>
Date:   Wed Aug 10 16:29:12 2022 +0200

    ++ DELAYS delay_complex simulink block

commit 53b2ffb8d957c0545f13b756b9e3cf7606ddbce9
Author: radonnachie <[email protected]>
Date:   Wed Aug 10 16:26:21 2022 +0200

    ^ delay_complex c_to_ri/ri_to_c always ASYNC

commit d8124dba00362ed6fb2e79f1019835abbd14e06a
Author: radonnachie <[email protected]>
Date:   Wed Aug 10 15:17:36 2022 +0200

    ++ delay_complex and tb

commit d31342899c045c6f56c31c3b8f88165d948b580c
Author: radonnachie <[email protected]>
Date:   Wed Aug 10 12:48:48 2022 +0200

    ~ wrappers/munge_config.m

commit 2ab09ec41ee135f5dca5b8fdc418083a21919d42
Author: radonnachie <[email protected]>
Date:   Tue Jun 21 12:27:29 2022 +0200

    *+ flow_control/bus_create unique generation

commit 01f6de248b9f876513b9cff9deb8f4cb02ccf540
Author: radonnachie <[email protected]>
Date:   Tue Jun 21 12:06:09 2022 +0200

    + docs/flow_control, docs/misc
    - munge, bus_create/expand, pulse_ext

commit 99ea68bca78c668852a33ce75d0dd0dd844b2c01
Author: radonnachie <[email protected]>
Date:   Sun Jun 12 21:03:53 2022 +0200

    ++ flow_control/bus_create simulink arbitrary

commit aee2380e1aa68b4eac630e3649bbf3efae3a65a7
Author: talonmyburgh <[email protected]>
Date:   Fri Jul 1 14:22:16 2022 +0200

    ++ Sample and hold module - untested

commit dac929696724f19d5c7b418228c564cc4c44affe
Author: talonmyburgh <[email protected]>
Date:   Wed Jun 22 22:41:07 2022 +0200

    ** fixeruppers and constraints

commit e96e455d07f31a441e9965fc72e5526741983749
Author: talonmyburgh <[email protected]>
Date:   Wed Jun 22 21:59:47 2022 +0200

    ^^ corrected if statement

commit 29e12924e3cf90e1acd702a36c43b110ae70a50e
Author: talonmyburgh <[email protected]>
Date:   Wed Jun 22 20:57:23 2022 +0200

    ** signed mask parameter is checkbox

commit cb10ae410b32c7cf2e03b7ce749586356d60a5cf
Author: talonmyburgh <[email protected]>
Date:   Tue Jun 21 17:15:30 2022 +0200

    ++ documentation for vector accumulator blocks.

commit b32a8d26caa5d7801d7800f0838bbefd58b736fa
Author: talonmyburgh <[email protected]>
Date:   Tue Jun 21 16:40:35 2022 +0200

    ++ Simulink block for dsp48e block. Crashes Simulink

commit 0047712574cb5ef24ccc272f7046e36b0d88e5d3
Author: talonmyburgh <[email protected]>
Date:   Tue Jun 21 16:40:10 2022 +0200

    ++ dsp48e_bram_vacc. Passes tb in Vivado

commit 934336877b417e1b3ceb8d30c6ae45f7c92ee526
Author: talonmyburgh <[email protected]>
Date:   Tue Jun 21 16:39:57 2022 +0200

    **company and name

commit f1b85fd1a6bf887a229ef24366b2e95eaa55ea97
Author: talonmyburgh <[email protected]>
Date:   Sat Jun 18 14:00:01 2022 +0200

    ++addr_bram_vacc added to library

commit da868826428b96f75ffcf5c310acfa0f14d68da6
Author: talonmyburgh <[email protected]>
Date:   Thu Jun 16 23:07:10 2022 +0200

    ** Use different path

commit 9672350285c644b675edb05e7625981e0d12ec17
Author: talonmyburgh <[email protected]>
Date:   Thu Jun 16 23:06:48 2022 +0200

    ^^ working simulink block

commit a5684438d6bd1ba677b78e6e4fe1581a08aa84cd
Author: talonmyburgh <[email protected]>
Date:   Thu Jun 16 23:06:36 2022 +0200

    ** use common_counter for synch rst

commit 4b1519655f7dc61173aee55894f9018d71dc8b73
Author: talonmyburgh <[email protected]>
Date:   Wed Jun 15 20:01:51 2022 +0200

    ** or on test checking

commit 1621262a2cfdd3a60555fa5b05c5fc91f0bd1049
Author: talonmyburgh <[email protected]>
Date:   Wed Jun 15 20:01:21 2022 +0200

    ++ started simulink block for addr_bram_vacc

commit a0b9892fac2d453644c963036573f8896cf19267
Author: talonmyburgh <[email protected]>
Date:   Wed Jun 15 20:00:56 2022 +0200

    ^^ Working regression testing

commit dd38c183766cb92f71d7735146defcd3f43e65c7
Author: talonmyburgh <[email protected]>
Date:   Tue Jun 14 23:33:25 2022 +0200

    ** neatenings

commit 0807e26e8877fa48eee1ead5ac15a2ed0731f3ac
Author: talonmyburgh <[email protected]>
Date:   Tue Jun 14 23:33:08 2022 +0200

    ++ regression testing for addr_bram_vacc - not passing

commit c93ef6a48b20aac4e73362520f2e9c09bc452158
Author: talonmyburgh <[email protected]>
Date:   Tue Jun 14 22:46:49 2022 +0200

    ^* working addr_bram_vacc

commit 020cf6cd7ccf181fba9997412049ae5370c3d758
Author: radonnachie <[email protected]>
Date:   Sun Jun 12 20:05:25 2022 +0200

    * misc/pulse_ext low after extension if rising_edge extension

commit 64a9c07f1c5c37da0ebf01013afed9681a87e7e2
Author: radonnachie <[email protected]>
Date:   Sun Jun 12 20:04:56 2022 +0200

    ^ counter/free_run_up reset in sensitivity list

commit e85ecdbf96975e6c5a00c3149dba5e80ba9ae2ed
Author: radonnachie <[email protected]>
Date:   Sun Jun 12 16:01:07 2022 +0200

    ++ flow_control/bus_create vhdl, vunit.
    - this only tests one bitwidth for each expansion/slice

commit b3d9d5b82bb2ccca4e9df8ef98346bd0f9c2fe20
Author: radonnachie <[email protected]>
Date:   Sun Jun 12 15:44:03 2022 +0200

    ~ flow_control/bus_expand g_divisions generic

commit c6eb528c09813fb4385e663f62298febbabf1f16
Author: talonmyburgh <[email protected]>
Date:   Fri Jun 10 16:54:22 2022 +0200

    ++ addr_bram_vacc - does not work as yet

commit 97ad32d8cfd78fa992707ef4374faa6c6fb7efae
Author: radonnachie <[email protected]>
Date:   Sun Jun 12 14:00:25 2022 +0200

    ++ flow_control/bus_expand simulink arbitrary

commit 8eef8c4d824034275ac38391da2906fdc9db049a
Author: radonnachie <[email protected]>
Date:   Sat Jun 11 18:28:36 2022 +0200

    ++ flow_control/bus_expand vhdl, vunit.
    - this only tests one bitwidth for each expansion/slice

commit 7ebbaaa3c83e46766e3c13f2234d1c74d6088a5e
Author: radonnachie <[email protected]>
Date:   Sat Jun 11 18:19:46 2022 +0200

    ^ misc/pulse_ext, update all

commit 5c8f443eab9b7df54f4fe322fcbb40cf9baef1fb
Author: radonnachie <[email protected]>
Date:   Sat Jun 11 17:36:10 2022 +0200

    * @author/company

commit 0abcd38758e81ad208b6c6d0db9e011a5a14191f
Author: radonnachie <[email protected]>
Date:   Fri Jun 10 13:07:45 2022 +0200

    * pulse_ext_blk/config, MISC update

commit beb8dce01b819ada0f65b1b4b342f3e570639641
Author: radonnachie <[email protected]>
Date:   Fri Jun 10 12:11:43 2022 +0200

    ** misc/pulse_ext better match casper block
    - default rising_edge detect assumes/forces i_pulse of 1 clk width
    - kept falling_edge detect as generic switch

commit 34ce1fcb9264bc89cc6acc1213c6ead1b2a7507c
Author: radonnachie <[email protected]>
Date:   Fri Jun 10 12:09:20 2022 +0200

    ** casper_counter/free_run_up_counter asynchronous reset
    - to match the common_counter

commit 96eb9ff1d5a2bdb51156a69e7bc1f56770b2d578
Author: radonnachie <[email protected]>
Date:   Tue Jun 7 10:18:38 2022 +0200

    *+ hdl_library add FLOW_CONTROL

commit c576ba885b1b9631ad3d07dd2d0e52957d5bef0c
Author: radonnachie <[email protected]>
Date:   Tue Jun 7 10:18:27 2022 +0200

    *+ MISC pulse_ext add

commit f14fbc1ab66f0d6fc3804db14b1df8b50a1ab15a
Author: radonnachie <[email protected]>
Date:   Tue Jun 7 10:17:45 2022 +0200

    + FLOW_CONTROL lib

commit 9eb81af02141a31ae897025860382a283dd7a74b
Author: radonnachie <[email protected]>
Date:   Tue Jun 7 10:17:32 2022 +0200

    ++ pulse_ext_blk/config

commit bd9211e969fdd64f1e1bdbcff4015befb09b6bf9
Author: radonnachie <[email protected]>
Date:   Tue Jun 7 10:17:00 2022 +0200

    *+ flow_control/munge_blk neater errors

commit e55dca67671fe5330b0297eb357cda40a0436f7a
Author: radonnachie <[email protected]>
Date:   Mon Jun 6 18:27:56 2022 +0200

    ++ misc/pulse_ext VHDL and VUnit

commit 36cf206fbaf0e87db9553a324345bb4a26cc664e
Author: radonnachie <[email protected]>
Date:   Mon Jun 6 17:11:28 2022 +0200

    ++ casper_flow_control/munge

commit 4c26ef08b033e3fc8a0e05207f29f72cce1ab8cb
Author: talonmyburgh <[email protected]>
Date:   Fri Jun 3 21:45:11 2022 +0200

    ++ documenation for armed_trigger

commit 92a21ca7c82fc5b908df5730e355ed70b5b4fd64
Author: talonmyburgh <[email protected]>
Date:   Fri Jun 3 21:42:07 2022 +0200

    ++ armed trigger Simulink block

commit 37c78f53228810759ffd15ea6eea99f08e94661e
Author: talonmyburgh <[email protected]>
Date:   Fri Jun 3 21:41:48 2022 +0200

    ++ armed_trigger regression testing

commit dce0542606484c3f479ec15d1f3b8ab8512d8472
Author: talonmyburgh <[email protected]>
Date:   Fri Jun 3 21:41:22 2022 +0200

    ^* module working correctly

commit fd855f83cce74a4844813190ea5a195650e66426
Author: talonmyburgh <[email protected]>
Date:   Thu Jun 2 12:23:40 2022 +0200

    ++ edge detect documentation

commit 344f0bbc5c1d9b628904f1d20ff59bb193621d0c
Author: talonmyburgh <[email protected]>
Date:   Thu Jun 2 12:23:25 2022 +0200

    ++ edge detect Simulink block

commit 4b9973a0866fd323c2fa84239c6ade397ee02c23
Author: talonmyburgh <[email protected]>
Date:   Thu Jun 2 12:22:57 2022 +0200

    ^* working regression testing

commit 3c531ef46afd2991e6b48a31bb9f68f41327cd01
Author: talonmyburgh <[email protected]>
Date:   Tue May 31 20:34:08 2022 +0200

    ++ regression testing - failing

commit 3358069520ed41e58e5a2b80ea356696fb44d660
Author: talonmyburgh <[email protected]>
Date:   Tue May 31 20:33:54 2022 +0200

    ^* working edge_detect module

commit cef7c73c6bbf85d3fb888397fb41d9af287df228
Author: talonmyburgh <[email protected]>
Date:   Mon May 30 11:31:54 2022 +0200

    ++unfinished edge detection module

commit b5030b3c47a54487fc2028728ff0ef64fa02453b
Author: talonmyburgh <[email protected]>
Date:   Fri May 27 18:50:12 2022 +0200

    ++ armed trigger HDL module - not working as yet

commit fac26b8d9150dba9efb19b0b98f04da1679061c3
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:42:31 2022 +0200

    ++Documented bit_reverse block

commit 1159c51a010c01d63531eab4cdd8c0c363658a82
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:42:19 2022 +0200

    ++bit reverse to MISC library

commit 78b5d5bdafc1e90b0dc739c0768582997618732e
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:42:05 2022 +0200

    ^^ initialisation mask

commit b319267cea59caa2684bdee79c121f465500526d
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:41:43 2022 +0200

    ++bit_reverse simulink block

commit ff5ba155929b8135c4bb1d356a6eadc9a942da3a
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:41:20 2022 +0200

    -- common_pkg_lib

commit f8e37cb0c03bf8eadc06c48d94da2cc343e56f32
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:40:51 2022 +0200

    ++Reg testing for bit_reverse

commit f16d828b26850c6301008801d82f4963a6f39527
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:40:34 2022 +0200

    ++bit_reverse module

commit 8c7efbaa97c741e765c745e94c4d1df17882c8b7
Author: talonmyburgh <[email protected]>
Date:   Thu May 19 10:40:16 2022 +0200

    ++ bit_reverse function

commit 5210f1309a25b22d56818c5ea16c409ee9f5ec88
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:22:54 2022 +0200

    ++ ri_to_c and c_to_ri documentation

commit d59bbc4dc6b30c5346dea69fb8466687a69cc536
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:22:36 2022 +0200

    ++ Added ri_to_c and c_to_ri blocks to library

commit ca6ed919f41db0135de1533fbc8462ce8b04fb1a
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:21:43 2022 +0200

    ++ ri_to_c Simulink block

commit 9faec6e92835b35c302e7e3fee649a29e8141470
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:21:27 2022 +0200

    ++ c_to_ri Simulink block

commit 72465d69abfc4d3abd619690abc4eeec9054f08f
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:21:07 2022 +0200

    ++ Regression testing for c_to_ri HDL block

commit 9b5ecb13c6aebb1318fa28ae3a94005692560fd8
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:20:48 2022 +0200

    ++ Regression testing for ri_to_c block

commit 8baf6cd84e0589810a21014e8c1bd237c3102571
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:20:17 2022 +0200

    ++ c_to_ri HDL block

commit 2cd412de3b0890c91e7d0f27cfcd1e8913157b63
Author: talonmyburgh <[email protected]>
Date:   Wed May 18 14:20:02 2022 +0200

    ++ ri_to_c HDL block

commit ab926ce7ce7935086d9ce7c5f3cb00d038258dd2
Author: talonmyburgh <[email protected]>
Date:   Thu May 12 15:45:18 2022 +0200

    ** Correctly compile the xpm ram modules for reg testing

commit ff7ad12ac6096a23c5a9b79996bb85c98a7a34b7
Author: talonmyburgh <[email protected]>
Date:   Thu May 12 15:44:14 2022 +0200

    ** Cleaned delay_bram_prog module

commit ea00749203bb5bacdba78cd7687af1c4f5bffe1d
Author: talonmyburgh <[email protected]>
Date:   Thu May 12 15:43:54 2022 +0200

    ++ Simulink block for delay_bram_prog_dp module

commit 4aa9fc0ac1ac3dda95130fe66b900d605b658ff3
Author: talonmyburgh <[email protected]>
Date:   Thu May 12 15:43:19 2022 +0200

    ++ Regression testing for delay_bram_prog_dp module

commit 79efe25f7e6be1ddd7eecf51cb6fa45a70f38ecc
Author: talonmyburgh <[email protected]>
Date:   Thu May 12 15:42:55 2022 +0200

    ++ Created delay_bram_prog_dp hdl module

commit 674a976f6ff23324d71744fcaaa37f58b1897bf7
Author: talonmyburgh <[email protected]>
Date:   Wed May 4 16:07:59 2022 +0200

    ++ Simulink block for delay_bram_prog and added to lib

commit 6825ce9363170f7870046b7b701d09a4a0d2081c
Author: talonmyburgh <[email protected]>
Date:   Wed May 4 16:07:36 2022 +0200

    ++ Regression testing for delay_bram_prog

commit 81998ca8044d42e0deef08ccf50893ade361af35
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 15 20:49:39 2022 +0200

    ** comment change

commit d491edb0934b480d5032e830e497bb695ea1fc29
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 15 20:49:26 2022 +0200

    ++ unfinished block wrapper for delay_bram_prog

commit 2ec115f7785e1d18c1e8bab444a7ab127cc5a758
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 15 20:49:04 2022 +0200

    ++ delay_bram_prog module

commit 402efe1d54972b4e1c9121634e6e4d58dad9dbbf
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 15 20:48:44 2022 +0200

    ++ free running simpler counter

commit 3c297540dbd3b44bb7abe3ce44b56fbd8440608d
Author: talonmyburgh <[email protected]>
Date:   Wed Apr 13 13:10:11 2022 +0200

    ++ Delay library documentation

commit 2d12ee6bbef84427ebdf91b5a6e7b30014b5cdd7
Author: talonmyburgh <[email protected]>
Date:   Wed Apr 13 13:09:50 2022 +0200

    ++ delay bram en plus Simulink block and added to library

commit 64a0e322079d573abf4736f3d457308afd6e2676
Author: talonmyburgh <[email protected]>
Date:   Wed Apr 13 13:09:18 2022 +0200

    ++ delay bram en plus regression testing

commit 1665b248ffa495b8f63910fc92fc0f26c87ac444
Author: talonmyburgh <[email protected]>
Date:   Wed Apr 13 13:08:49 2022 +0200

    ++ delay bram en plus module created

commit 0d96c06931f8024007c5271a73663d59c751c924
Author: talonmyburgh <[email protected]>
Date:   Wed Apr 13 13:08:25 2022 +0200

    ** Block parameter constraints and minor fixes

commit 576874b1a791b6584f45ee629e8d2f846d39a1ad
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 8 17:22:43 2022 +0200

    ++ DELAYS library in CASPER_HDL_Blockset

commit 83a0976405ef943211d95eb772227e433e3f4a49
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 8 17:22:29 2022 +0200

    ++ Simulink block for delay_bram block

commit 64ce07cc17c97f1129f5c9d47465b4e299c61b34
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 8 17:22:15 2022 +0200

    ++ reg testing for delay_bram and delay_bram_async

commit a5ef215260d96f5469e8d7161e9945c48e845e6e
Author: talonmyburgh <[email protected]>
Date:   Fri Apr 8 17:21:56 2022 +0200

    ++ delay_bram and delay_bram_async with tb

commit d433e80a5bc24c24d42b5b2b1f96f31dbaab3ffb
Author: talonmyburgh <[email protected]>
Date:   Tue Dec 21 11:24:32 2021 +0200

    ** minor changes

commit fb3975fd4f9f1abe77ad84d337191795dbc295d9
Author: talonmyburgh <[email protected]>
Date:   Wed Dec 15 14:56:53 2021 +0200

    ^+ Working ri_to_c block and added MISC library.

commit 297b3d8481db8312ab4df2a1655a8f1e51dbe0fe
Author: talonmyburgh <[email protected]>
Date:   Tue Dec 14 18:42:00 2021 +0200

    ++ Created ri_to_c block (uses concat).

commit 5a0ea9d425a0287b1de3a89f5673e04e904c0eaa
Author: talonmyburgh <[email protected]>
Date:   Thu Sep 1 12:53:56 2022 +0200

    ^* pfb configuration fixed for par twid generation

commit 91048bdbd33a4d2cfe21fe7414912f5dc8f142e2
Author: talonmyburgh <[email protected]>
Date:   Wed Aug 31 16:41:31 2022 +0200

    ** vivado project fix

commit a3846e01f508ad214aa14d62f59c095ef3ba75cf
Author: talonmyburgh <[email protected]>
Date:   Tue Aug 23 19:02:14 2022 +0200

    ~~ nof points constraint on FFT

commit 66a6b7a9e0a9d465f03b86537d419fb823576006
Author: talonmyburgh <[email protected]>
Date:   Fri Aug 19 16:24:47 2022 +0200

    ** a whole lot.
    fixed case of wb_factor=1 mask break

commit 236ec6f49c3b785b6d8e4254342031870c34cde7
Author: talonmyburgh <[email protected]>
Date:   Thu Aug 4 22:14:12 2022 +0200

    ^* Optimised parallel twiddle package generation -> mask speedup

commit f5a955ff4c4131b9799db7c8262ae540578b92c5
Author: talonmyburgh <[email protected]>
Date:   Sun Jul 17 15:00:52 2022 +0200

    ^^ fixed reg test and updated vivado projects

commit 8236badc721bc774aff70d41e5fb7a8909c28995
Author: talonmyburgh <[email protected]>
Date:   Sun Jul 17 14:30:08 2022 +0200

    ++ g_alt_output to switch output data arrangement.
    ** formatting and cleanup.

commit ba4b2774f2d6f0bccb7ea7c622ca27618b4e89db
Author: talonmyburgh <[email protected]>
Date:   Fri Jul 15 13:28:52 2022 +0200

    ^^overflow detection fixed -> no ovflw when in_sel='1'

commit 27a2db6dc38b62e3845aa146128b32fa18f648bc
Author: talonmyburgh <[email protected]>
Date:   Fri Jul 15 13:28:42 2022 +0200

    **formatting and refactoring

commit 6e28d091ee4450ac9ab559dd61098846eb1f53c0
Merge: 3de9dd9 9d6098d
Author: Talon <[email protected]>
Date:   Wed Jul 13 13:34:40 2022 +0200

    Merge pull request #9 from talonmyburgh/picking_cherries

    Picking cherries

commit 3de9dd9ea7a3410985d95eee6bb2e5f5dba579b4
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 16:26:24 2022 +0200

    ** Mask constraints and Prompts

commit b22ffa544ea30d13e972568254690ec623e84a99
Author: Talon <[email protected]>
Date:   Fri Mar 4 16:00:12 2022 +0200

    Merge pull request #8 from talonmyburgh/wb_stream_dev

    Wb stream dev merge. WBPFB block now has support for multiple streams

commit 1e335fb737bc662a43fccdf7f4fd6223132b87ac
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 15:27:39 2022 +0200

    ^* nof_points is a power of 2 parameter in the FFT and PFB now

commit 1ab4823e9edfbea253f5ff5e0f6e3e9348c1edc8
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 14:34:05 2022 +0200

    *^ pipeline and pfb tests pass now.
    ~* Unneeded files removed
    ** Tests run when files change only.
    ++ Commenting

commit 16aa91bad5b764c63845e9dc459c36bbf6e6945f
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:47:15 2022 +0200

    *~ twiddle_offset and noted point size is 2^nof_points

commit 55f90988bf7eb00b04d98656a9a7acb4d2387869
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:44:47 2022 +0200

    ** new_rTwoWeights -> rTwoWeights

commit 498dfe395d365f9ed037af99a5f60e4d0b01e72f
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:43:57 2022 +0200

    ~~ twiddle_offset and stage_offset

commit d0ba353fcfac76643713185401c0f0f783d3c0f4
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 17:40:14 2022 +0200

    ** Updated block appearance in library

commit 043a1ed945264a0edd260b4beab210305ef78d47
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 17:35:16 2022 +0200

    ^* variable wb_stream works. Tested for streams=1

commit 4c156003e009cebd162acef3d75e927da34af0cd
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 13:09:40 2022 +0200

    ** Unecessary generics removed

commit 2587c11c23e8112c46c9a35b8e8088956aeabf63
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 09:07:34 2022 +0200

    ^^ Issue with ports being incorrectly generated over wb_factor 8

commit cfba9255a6886ce7b41bfd201294ce4d8e7b5b5d
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 08:58:17 2022 +0200

    ^* Included support for wb_stream>1. Getting zeros in Simulink Simulation

commit 3bd83b9f12683f3a4744636228d4867efa3f9e27
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 25 09:58:20 2022 +0200

    **Rearrange and alter default values

commit 202f07760095b39d4dd8a8662b0c9fa3e9a731bf
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 25 09:57:59 2022 +0200

    ~~ Remove data representation and twiddle offset

commit 9d6098d00c1d107b927f5870866896fa09f2494b
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 16:26:24 2022 +0200

    ** Mask constraints and Prompts

commit 216061160f532bbc05c974e02f7120c3d10a0d97
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 15:27:39 2022 +0200

    ^* nof_points is a power of 2 parameter in the FFT and PFB now

commit 117b9c349e3a4af5786e002cbface398471229f2
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 14:34:05 2022 +0200

    *^ pipeline and pfb tests pass now.
    ~* Unneeded files removed
    ** Tests run when files change only.
    ++ Commenting

commit 0aed168cfbcb0d79fd7a188fde8037fe7b8983d7
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:47:15 2022 +0200

    *~ twiddle_offset and noted point size is 2^nof_points

commit 7044e01ae7b41fd529d5398dabb8f6506c038e49
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:44:47 2022 +0200

    ** new_rTwoWeights -> rTwoWeights

commit f6401cebbde1e4de9fe7bf8c56c6d643dc35bc07
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:43:57 2022 +0200

    ~~ twiddle_offset and stage_offset

commit 647116c221e9983928dbe65e8a9eefcd099cfc4e
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 17:40:14 2022 +0200

    ** Updated block appearance in library

commit c038108197fddcc867317ccfede8675444ff1bff
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 17:35:16 2022 +0200

    ^* variable wb_stream works. Tested for streams=1

commit 31b5d359df1ae153b1fe722a8c64b4bf1fdcfc82
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 13:09:40 2022 +0200

    ** Unecessary generics removed

commit d281b8ad2b85b481b27fbc6155d61058621ec92b
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 09:07:34 2022 +0200

    ^^ Issue with ports being incorrectly generated over wb_factor 8

commit fc47bcc780179acd139867440387759b59998d8f
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 08:58:17 2022 +0200

    ^* Included support for wb_stream>1. Getting zeros in Simulink Simulation

commit ed1dfce4447988e1cb3cdd409d9046993e3113aa
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 25 09:58:20 2022 +0200

    **Rearrange and alter default values

commit 7e4ce04a92c451d333419ad46a2228b073c11e9f
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 25 09:57:59 2022 +0200

    ~~ Remove data representation and twiddle offset

commit e4a8cc80857d5c44b40a4f3370d7ebea06a87d1c
Merge: abbffaa 6a86aa3
Author: Andrew Martens <[email protected]>
Date:   Tue May 31 18:07:18 2022 +0200

    Merge branch 'inplace_fft_pipe_reorder' into merge_test

commit 6a86aa327a413c9204f731f4f236de4dac5fc302
Author: Andrew Martens <[email protected]>
Date:   Sun Mar 27 09:46:18 2022 +0200

    testbenches fix

    pipeline and wideband fixes
    removed commented out tests
    fixed alignment and format

commit 7023d83f93ff0af637aeffc24a5b79ce2a0e3660
Author: Andrew Martens <[email protected]>
Date:   Fri Mar 18 14:29:35 2022 +0200

    Testbench integration

    - included new parameter into fft package
    - added generic changes to wide and pipelined FFT
    - added new testbench entries for pipelined and wideband FFTs

commit abbffaa3dfeb7a97899972820f215665e1817fd3
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 16:26:24 2022 +0200

    ** Mask constraints and Prompts

commit 2fe6638bc61573c8c8c010fc5b949919f72ce5f1
Merge: ad0fed6 e31742f
Author: Talon <[email protected]>
Date:   Fri Mar 4 16:00:12 2022 +0200

    Merge pull request #8 from talonmyburgh/wb_stream_dev

    Wb stream dev merge. WBPFB block now has support for multiple streams

commit e31742f4d640a482602b518e3c57875a4365eba3
Merge: b9596b8 ad0fed6
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 15:33:59 2022 +0200

    >< master into wb_stream_dev

commit ad0fed674b3a344a84cafa58e80a15364d86f253
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 15:27:39 2022 +0200

    ^* nof_points is a power of 2 parameter in the FFT and PFB now

commit e2cfbd3a2aa035921a2c4ac068a6b8c5851189e3
Author: talonmyburgh <[email protected]>
Date:   Fri Mar 4 14:34:05 2022 +0200

    *^ pipeline and pfb tests pass now.
    ~* Unneeded files removed
    ** Tests run when files change only.
    ++ Commenting

commit c657068a32e6e46853d49b47ab7c3db62b63f042
Author: Andrew Martens <[email protected]>
Date:   Fri Mar 4 10:23:15 2022 +0200

    Start of generic fix

    Generics may not be compatible. Local constants created to override
    requested generics to ensure operation is always correct.

commit 845d0e73496bf6b7fc0fb5669f5642e82cdb8a80
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:47:15 2022 +0200

    *~ twiddle_offset and noted point size is 2^nof_points

commit 4e9414178ea1cdf19ca079a52a964a21f3d7fa6f
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:44:47 2022 +0200

    ** new_rTwoWeights -> rTwoWeights

commit 992ec608c20ec70509917334c01ea8ee26db0e62
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 22:43:57 2022 +0200

    ~~ twiddle_offset and stage_offset

commit b9596b83767725045c2f021542a10f7571c19bce
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 17:40:14 2022 +0200

    ** Updated block appearance in library

commit e94ec9a886cb7c9e011c1d1cd13deb75371bb670
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 17:35:16 2022 +0200

    ^* variable wb_stream works. Tested for streams=1

commit 0aaf68751cbdd6f2771914e0f1d124901dd60cf7
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 13:09:40 2022 +0200

    ** Unecessary generics removed

commit 53d1baab872232821d23f6de593ada9b604c2191
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 09:07:34 2022 +0200

    ^^ Issue with ports being incorrectly generated over wb_factor 8

commit 1be3911aee90abc4b8864933ce505cbe0943df7f
Author: talonmyburgh <[email protected]>
Date:   Thu Mar 3 08:58:17 2022 +0200

    ^* Included support for wb_stream>1. Getting zeros in Simulink Simulation

commit fd7d3d7e06edfa8cd92da416260e2cf1b6fa8029
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 25 09:58:20 2022 +0200

    **Rearrange and alter default values

commit 48a375a6b30f347967ccce2b53e181ad9a176cd5
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 25 09:57:59 2022 +0200

    ~~ Remove data representation and twiddle offset

commit 9a42e50a4f1fa4842f6e0e6b519190b8be1f073a
Author: Andrew Martens <[email protected]>
Date:   Wed Feb 23 17:37:30 2022 +0200

    <feat> in place reorder/separate buffer option

    In place buffer generic option added to reorder/separate block for
    pipeline FFT. This halves the amount of BRAM required when compared
    to standard double buffer option.

    The output valid signal does not stay high in a continuous block
    as previously so not guaranteed to be backwards compatible.

commit cf0bb0413756ae4ed2e8549e782b14214e13659b
Merge: 0edc2d8 9afd147
Author: Talon <[email protected]>
Date:   Tue Feb 22 19:56:41 2022 +0200

    Merge pull request #6 from talonmyburgh/bram_optimisations

    Bram optimisations

commit 9afd1471c43cb62365cefb8680c0daa817029417
Merge: 3e9df7a 0edc2d8
Author: Talon <[email protected]>
Date:   Tue Feb 22 18:30:21 2022 +0200

    Merge branch 'master' into bram_optimisations

commit 3e9df7a988e202a3c101ba7946c89c2e548e2116
Author: talonmyburgh <[email protected]>
Date:   Mon Feb 21 21:09:23 2022 +0200

    **Neatened and Updated PFB and FFT Masks

commit 7cca840832d8e82ac12be2a46ee662c5185eed33
Author: talonmyburgh <[email protected]>
Date:   Sat Feb 19 14:53:09 2022 +0200

    ** supports new ROM pipeline twiddles in Simulink.
    Passes Simulink simulation

commit cb5cafc42b8324463e60e0c39dd85c4f5676b2de
Author: talonmyburgh <[email protected]>
Date:   Sat Feb 19 14:52:25 2022 +0200

    ^* PFB library display

commit 784f234a3729516c6c2113a5140e9573dbca4e70
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 18 12:35:44 2022 +0200

    ^* regression testing for pfb passing

commit 677e6ebe77ec5e68cf7dc8cb15b04ef9cfea6c0d
Author: talonmyburgh <[email protected]>
Date:   Wed Feb 16 18:14:03 2022 +0200

    ** default for twiddle_stem_path is from r2sdfpkg

commit f2aa99f322240abd29ab180cd65a82b2f18cb0cc
Author: talonmyburgh <[email protected]>
Date:   Wed Feb 16 17:33:22 2022 +0200

    **Add new weight testing to the regression testing - not working.

commit a25b1a0bbdc673a10af634084f0a4983390bfd7b
Author: talonmyburgh <[email protected]>
Date:   Wed Feb 16 16:07:21 2022 +0200

    ** PFB tb work in Vivado with bram-optimisation

commit 8b36ef82807d86fb42d926aff77bf05c1f3abe23
Author: talonmyburgh <[email protected]>
Date:   Wed Feb 16 09:39:21 2022 +0200

    ~* Replaced rTwoWeights with new ROM rTwoWeights

commit 50a884749a0efae31819a303d778e101071e8917
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 11 17:43:54 2022 +0200

    ++ Support for parallel twiddle package generation via mask

commit 9f14bfea6cc7da132378ddb43d9019304966e68d
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 11 17:43:26 2022 +0200

    ** Comment

commit b5fd9e6c3f5b073f8fa1a4bffff375ddf3072e35
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 11 17:43:10 2022 +0200

    ** Moved and joined for simplicity

commit e14a3b590d27ac5d755f803b6ecf011026c3766a
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 11 17:42:28 2022 +0200

    ~~ Unused pkg

commit f3d6b83e3ff2af37195ac47629d062df6c602a71
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 11 17:42:00 2022 +0200

    ~~ Unecessary class field

commit 1a6e51a4a38cbdf1bb1112042b40f9b9aa836740
Author: talonmyburgh <[email protected]>
Date:   Thu Feb 10 19:56:54 2022 +0200

    *^ r2sdf_fft reg testing fix

commit 78a0cfa384ba15624dc67b51bdfee3c81f4ceeed
Author: talonmyburgh <[email protected]>
Date:   Thu Feb 10 19:53:20 2022 +0200

    ** file stem for coef twid file generated and passed down

commit c2bf883cda7102c73f27889068c5538ff32fdf3e
Author: talonmyburgh <[email protected]>
Date:   Thu Feb 10 19:51:16 2022 +0200

    ++ twid files for 128 point tests

commit 2be157e66c682415f8babddc4ae74f0f7f5baf56
Author: talonmyburgh <[email protected]>
Date:   Sat Feb 5 14:56:44 2022 +0200

    ^^ Indexing with np.int -> int for older python versions

commit 2bbc27ed49d86a738001fe35c2657319c7237ab4
Author: talonmyburgh <[email protected]>
Date:   Sat Feb 5 14:13:28 2022 +0200

    ^* FFT block successfully simulates with new twids

commit 7093e40c7b6e61109649cdfe9ebb6f448c3edce5
Author: talonmyburgh <[email protected]>
Date:   Sat Feb 5 12:57:18 2022 +0200

    ^* parameter display of FFT block

commit 90aaa7339658b2c546256ba85c363018efa89691
Author: talonmyburgh <[email protected]>
Date:   Sat Feb 5 12:35:51 2022 +0200

    +* Added bram optimisation to FFT Simulink block

commit d04394ffa870576c4ec12c755d2be576ee788407
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 4 14:07:38 2022 +0200

    ** wb_fft VUnit sim failing

commit 961e312b9d491aea82ed7d34e29c68ed36b3d62a
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 4 14:06:56 2022 +0200

    +* twiddle file name convention & twids for tb

commit 08cf54bd00662938b8e7a427658c065ddc981a95
Author: talonmyburgh <[email protected]>
Date:   Fri Feb 4 14:05:40 2022 +0200

    ^* Vivado simulation of r2sdf and wb FFT passes

commit 0edc2d849c8d689f600743dd91ed7b18d58f968c
Author: RocketRoss <[email protected]>
Date:   Fri Feb 4 12:56:08 2022 +0200

    ^ wb_slim_fft_top update names

commit 7592c4d4ae551255d39fe5298731905ae5d280f5
Author: talonmyburgh <[email protected]>
Date:   Thu Feb 3 18:20:17 2022 +0200

    ^* r2sdf_fft passes tests in Vivado. Fails in GHDL

commit 8fa38a791da82672beddb581099c7fa33f20b5cd
Author: talonmyburgh <[email protected]>
Date:   Wed Feb 2 19:24:37 2022 +0200

    ** Failing r2sdf_fft tb

commit 03c8b480cbd36c739104add1e65b1063e85eef59
Author: talonmyburgh <[email protected]>
Date:   Wed Feb 2 19:02:57 2022 +0200

    +* Wideband and r2sdf_fft synth with new ceoff rom

commit aec88f40db7961e897e7fa0c36849d4cd26815d9
Author: Andrew Martens <[email protected]>
Date:   Mon Jan 31 00:24:11 2022 +0200

    twiddle generation fix

    Works with 0 based stage indices. Also wraps properly
    for wideband factors that are larger than the number of
    coefficients in a stage.

commit dbfe219be536ca01ca3a9c51da0000dff273ae0b
Author: talonmyburgh <[email protected]>
Date:   Sun Jan 30 13:44:08 2022 +0200

    *^ Fixed so that files are written out re,im,re,im.

commit 2a52bad798239942d74c693a98efb6273063c1e8
Author: Andrew Martens <[email protected]>
Date:   Sat Jan 29 17:46:52 2022 +0200

    stage coefficients for BRAM initial values

commit 96cc7097f7fef862230c5ebd5727a57136644f50
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 13:33:24 2022 +0200

    ** make use of new weights entity

commit 0952c3ae3aaa99242117483c06a6ac3bdb04f29e
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 13:32:49 2022 +0200

    *^ add/fix initialisation of generics

commit 5eb1f0fc9cb8943b8538b84f73d2417f80eaf02f
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 13:31:51 2022 +0200

    ** rename coef_w to twid_w

commit b50fecc57bab577e9cbe3612d2e7648bd25ec897
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 13:31:18 2022 +0200

    ^^ Fix rom init

commit fb5cfdc9be765d1020212641e8b9fa4dbaac25b4
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 13:30:29 2022 +0200

    +* include new twiddle width constant

commit 59473def613734a9cf6575b2138d81f6eeb92874
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 13:29:47 2022 +0200

    ** Set up roms correctly

commit 422bcf863dd40df85bbc6ad290013a5fd3ef2142
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 12:03:01 2022 +0200

    ++ Create file for coefficient generation.
    - Stem goes into constant in sdf_pkg

commit 1408339ea1474404b1816190bbc851b9c828ac94
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 12:02:05 2022 +0200

    ** Use new weights module and pass up generics

commit e6d492044928ab15c935969fcc94566d2c912a42
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 12:00:54 2022 +0200

    ** Modify rTwoWeights to use rom for twids

commit e9be4cd777afc31a450818c469d59fae8a57b39d
Author: talonmyburgh <[email protected]>
Date:   Fri Jan 21 11:57:34 2022 +0200

    ++ Created common rom modules (dual/single port)

commit ffe741753e0e4debbac4111e2badfdeeef6f7950
Author: talonmyburgh <[email protected]>
Date:   Mon Jan 17 10:31:05 2022 +0200

    ++ dual port ROMs for twiddle storage

commit ec7c4dc1ae465737f5d0aca33c6251b868cda44f
Author: talonmyburgh <[email protected]>
Date:   Thu Jan 13 16:32:04 2022 +0200

    ^* unsigned fixed point type on filter block

commit f0b254b2fad6d6fe692cee2465990ebeae380380
Author: RocketRoss <[email protected]>
Date:   Tue Jan 11 19:14:57 2022 +0200

    * trigger all tests

commit 1025100e7dce71ce39d7fd5add96a5472bd4e24b
Author: talonmyburgh <[email protected]>
Date:   Fri Nov 26 09:03:03 2021 +0200

    *^ PFB vivproject update.

commit 2c2187dbcd166bee85a6f494fb93fb0b1fd3da43
Merge: 1e85a68 d991d45
Author: Talon <[email protected]>
Date:   Fri Nov 26 08:26:33 2021 +0200

    Merge pull request #5 from talonmyburgh/casper_wbpfb_vunit_generics

    Casper wbpfb vunit generics

commit 1e17799d1455e8388617f131e59806c87a32a0f7
Author: Andrew Martens <[email protected]>
Date:   Thu Nov 25 23:15:41 2021 +0200

    rough in place reorder for pipeline FFT

    * Checked manually i.e automated testing using existing testbenches not working yet as first spectrum
    zeros.
    * All generic permutations not supported by inorder reorder yet e.g channels not 0,
    separate = false etc. Only tested on real inputs needing to be in normal
    order and separated.
    * Parameter controlling choice of in place reorder not propagated
    upwards yet - currently hardcoded in fft_reorder_sepa_pipe.

commit d991d450b4e3c86fa85901c6644647a846523e8e
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 25 18:06:37 2021 +0200

    ++ CI for wbpfb
    - readme shows badge
    - test.yml launches test
    - generic_dicts alters diff_margin of one test
    - run.py has package mangling
    - tb is fixed to not fail incorrectly

commit d56bf77f25cc577a631b5e7de12febc4c523a58b
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 25 18:03:30 2021 +0200

    ++ package mangling to fft test

commit b0e784b8e95da498e24bbed6250026fe02e75bdd
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 25 18:02:51 2021 +0200

    +* package mangling in filter run.py & ignore pycache

commit 1e85a68f47f55b25d7b0faf7e023ff903a14b65c
Author: RocketRoss <[email protected]>
Date:   Thu Nov 25 16:09:57 2021 +0200

    *^ wrappers update fil and wpfb scripts

commit a4b89e8aee7f314efc618a7156e240675934c2b6
Author: RocketRoss <[email protected]>
Date:   Thu Nov 25 15:13:59 2021 +0200

    +* casper_wbpfb generic_dicts.py for run.py

commit ca999a10f3c923c3edda593f4cd60e2c8266cf6c
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 25 14:51:48 2021 +0200

    ** Pad mem values for hread in pfb

commit d77286d61a6ef69ba617247ea9cdaf46111a62dd
Author: RocketRoss <[email protected]>
Date:   Thu Nov 25 14:15:33 2021 +0200

    ** casper_wbpfb tb/tb_tb_vu run.py
    - fix RAM filepaths in run.py
    - add defaults to tb_tb_vu
    - fix test_pass logic in tb

commit 09f611ca33b9e1b40fd9cc80fcf4b62055ed96f8
Author: RocketRoss <[email protected]>
Date:   Thu Nov 25 12:12:28 2021 +0200

    ^ casper_wbpfb tb_tb_vu and run.py. Tests fail

commit e0a748a7f20c3be09c59e2b1cd0be276cf7c2dff
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 25 10:50:38 2021 +0200

    +* Regression testing for wbpfb. Not finished

commit 6c404e65c3439f9fc5d460480e413add333b9c5d
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 23 19:17:21 2021 +0200

    ** Force wide filter run

commit 4d555e1856e37467012a290df91906136c97e428
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 23 18:58:14 2021 +0200

    ++ CI for wide prefilter

commit ea512606f49d2037dc18c70768f209182b82ab0a
Author: RocketRoss <[email protected]>
Date:   Tue Nov 23 18:40:25 2021 +0200

    ^ casper_wb_fft_config ~~casper_~~common_add_sub

commit 23ea26e5da606d64980470a1b51afd77b27ec129
Author: RocketRoss <[email protected]>
Date:   Tue Nov 23 14:03:50 2021 +0200

    ^ test.yml single_filter_report path

commit 166c972307e3da58b84e7a86996f622eb5ce6e43
Author: RocketRoss <[email protected]>
Date:   Tue Nov 23 14:02:28 2021 +0200

    * test.yml single_filter if files_changed, fix filter.svg path

commit 3c0d2043e3f5ed8d30ffb8678aba42a2ca16daa7
Author: RocketRoss <[email protected]>
Date:   Tue Nov 23 13:58:33 2021 +0200

    * xpm_vhdl

commit 87e5804ed84dc2b3528646110bfd7c3eb543962d
Author: RocketRoss <[email protected]>
Date:   Tue Nov 23 13:46:26 2021 +0200

    + README single_filter, force test

commit f10d343a26daa5fb0e86255d1c5198005b79632b
Author: RocketRoss <[email protected]>
Date:   Tue Nov 23 13:00:14 2021 +0200

    + test.yml casper_filter single

commit 64884d57949022b4e98bd53d3e0dd0553f582712
Author: RocketRoss <[email protected]>
Date:   Tue Nov 23 12:55:11 2021 +0200

    ^^ casper_filter file_prefix, nof_chan, ~tb_end_mm

commit dc0e02a6fa80c1b5816e939e8fa217a20fd67c1e
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 23 12:02:53 2021 +0200

    ~~ unecessary tb files for fft.

commit 18b23eca1ffb6c93a84382e42bf2a3b7c65b5c8f
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 23 12:01:24 2021 +0200

    ** Improve layout of ram vunit script

commit 5852f9898e65f912c44b6bb82e1842e444b625ef
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 23 12:00:46 2021 +0200

    ** Pad hex values in mem generation

commit 645b2eb3f93c960bf562b6ed58f41f8a2d1c6fbb
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 23 11:44:08 2021 +0200

    ** pad hex values in generated mem files.

commit b3c339f08fa1dfdb4888ed2fe886ccf69687b89a
Author: talonmyburgh <[email protected]>
Date:   Mon Nov 22 16:28:24 2021 +0200

    *+ fil_ppf CI WIP

commit 5fbcc5346b35107ba9daa16a7f5315b0ccc57cef
Author: talonmyburgh <[email protected]>
Date:   Mon Nov 22 12:26:57 2021 +0200

    ~* Remove all fft case will find optimal option later.

commit cfb74739c9b19d72d2d8049f99b672402e57da11
Author: talonmyburgh <[email protected]>
Date:   Fri Nov 19 16:38:29 2021 +0200

    **Force run of wide and all CI FFT options

commit 963f1a34df457ffd01519472f78c72bd882a511f
Author: talonmyburgh <[email protected]>
Date:   Fri Nov 19 16:14:10 2021 +0200

    ~~ Previous way of test assertion

commit 4cb650460e374b6accf9a924b0b01fed74a50f9d
Author: talonmyburgh <[email protected]>
Date:   Fri Nov 19 16:13:44 2021 +0200

    **Changed test_msg size to 80 chars

commit fae1f56d0a97dd18b0e1f47bdb340ce4522fa439
Author: talonmyburgh <[email protected]>
Date:   Fri Nov 19 16:13:20 2021 +0200

    ++Regression testing for wide fft

commit 2a1b0b556d52ba56c32b680763a1e685b04d9f9b
Author: talonmyburgh <[email protected]>
Date:   Fri Nov 19 16:12:35 2021 +0200

    ++Wide and All FFT CI options

commit 45dac58ab89bde347ad0950f1fa24eaf7e80d5a9
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 10:12:12 2021 +0200

    *^ test.yml par_fft files changed, trigger

commit bec623b873e3d3f412b3a5dc1bfbeb1c7dfe25b7
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 10:06:25 2021 +0200

    * tb_fft_r2_par add verify_proc, test.yml uniform

commit f0d432d3ccf352f4b2ef28aaea7df8de16a08946
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 10:02:39 2021 +0200

    v* test.yml single vunit cmd, mcode for par_fft

commit 7eff250171f3da2f90a8d6b389525f1bfe2342de
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 10:00:23 2021 +0200

    * test.yml list vunit cmds

commit 02a6988156ababd273d8450b97ef3da01f4c6e48
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 09:54:55 2021 +0200

    ^ test.yml comment

commit a270750aac62498a8de4ddbf73f2934427937579
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 09:52:17 2021 +0200

    * test.yml  ghdl --version before run.py

commit 5ad0f460fdebbd85f6e6777fcff3c25f2c2772b1
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 09:36:13 2021 +0200

    * test.yml uniform colors, ~~ed~~ing, fix failing

commit 8ae0bc06ec382886a5bca888d426b96eec66b2e6
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 09:35:17 2021 +0200

    + README par/pipe fft badges

commit 9b2af92604998fb0dba29804bee3e4d40e5539d3
Author: RocketRoss <[email protected]>
Date:   Fri Nov 19 09:34:47 2021 +0200

    * casper_wb_fft --ieee-asserts=disable-at-0

commit 91baef1e25aa23238cf7a38e6b7bb42bdc322232
Author: RocketRoss <[email protected]>
Date:   Thu Nov 18 22:54:33 2021 +0200

    *^ common_pkg is_all body.. oops

commit 3377c70137094c05286a633fa2faa00a95bf86c7
Author: RocketRoss <[email protected]>
Date:   Thu Nov 18 22:51:11 2021 +0200

    *^ test.yml fix fft tests

commit b2a64dadda6955e5c2e5e33caf1154be54972765
Author: RocketRoss <[email protected]>
Date:   Thu Nov 18 22:47:41 2021 +0200

    * test.yml trigger fft tests

commit eab5ee374fbbbcd33acfe52e7256206f4816f080
Author: RocketRoss <[email protected]>
Date:   Thu Nov 18 22:47:10 2021 +0200

    * test.yml neaten fft file_changed seciton

commit eda7b11605383c0ab13e0832229a933fee1d9f94
Author: RocketRoss <[email protected]>
Date:   Thu Nov 18 22:41:23 2021 +0200

    *+ common_pkg is_all, r2_par ovflw
    - is_all enables checking any slv is all of a value (avoids 32bit limit of TO_SINT alternative for == 0)
    - r2_par uses this to collapse stage ovflw values

commit ce9196ec0820c5924be8cc586cffe9ad7518ac51
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 18 22:35:54 2021 +0200

    ++ Regression testing for parallel FFT.
    run.py accepts args to dictate which tests to run.

commit 4d14760760e14af33228c10d4e6442de7a21c9c1
Merge: 6e619db 876f5c8
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 18 18:47:44 2021 +0200

    Merge branch 'master' of https://github.com/talonmyburgh/casper_dspdevel

commit 6e619dbf3aa666bd270089f5451ed3249e4dac86
Author: talonmyburgh <[email protected]>
Date:   Thu Nov 18 18:47:31 2021 +0200

    ++ Reg testing for par_fft.
    Tests fail due to bound check in vhdl

commit 876f5c82ea1c48fc2b855b86b2dbac9edd99bf2b
Author: Ross Donnachie <[email protected]>
Date:   Thu Nov 18 11:44:14 2021 +0200

    *+ README.md, docs badge, categorise badges

commit 6123403f67e03a06fd625acdb272933b730edd99
Author: RocketRoss <[email protected]>
Date:   Wed Nov 17 12:31:15 2021 +0200

    * test.yml if files_changed reinstated

commit 40fc084ce10d314f742e87777558cb0f8fb6d248
Author: RocketRoss <[email protected]>
Date:   Wed Nov 17 12:29:17 2021 +0200

    *+ test.yml correct badge colors, embed in README

commit 6967c502f768736d98bf586ef99b8e75fe10e988
Author: RocketRoss <[email protected]>
Date:   Wed Nov 17 12:22:22 2021 +0200

    *^ test.yml generate badge per entity

commit ce0fcbd4f0e317aeb74228f30cab31ab8a88a875
Author: RocketRoss <[email protected]>
Date:   Wed Nov 17 12:09:52 2021 +0200

    *+ test.yml generate badge per entity
    - redact if files_changed to trigger test

commit c0020a7c3d83ff1295395c4a1131634f183a2d86
Author: talonmyburgh <[email protected]>
Date:   Tue Nov 16 21:35:33 2021 +0200

    ++ pipeline fft reg testing

commit 8b2b21bb0a9d60544fc4b91041d31fc5f5e9d0e9
Author: talonmyburgh <[email protected]>…
…use size.

Test is disabled by default due to run time, but could be added to ci (new argument to r2sdf run.py to run test)

Squashed commit of the following:

commit 9a06831
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 13:54:18 2023 -0400

    Further improvements to execution time
    reduced data processed by fix_point model

commit dde760b
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 11:24:29 2023 -0400

    Compiling the VHDL for turned off testbenches still allowed the VHDL to run

commit 59ffb93
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:57:30 2023 -0400

    More syntax error fixage

commit 7303de1
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:35:11 2023 -0400

    Fixed syntax error

commit 3bb66e9
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:27:34 2023 -0400

    Due to long run time in GHDL, the bitaccurate and twiddle tests are now manually run and turned off unless a command line argument is passed

commit 3981e58
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 21:05:44 2023 -0400

    Reduce Execution time for r2sdf

commit 9978344
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 19:57:44 2023 -0400

    Fix for stack memory usage in GHDL

commit c7479e8
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 19:36:06 2023 -0400

    This is still going to break but I want the error

commit ddc6cc3
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 18:47:24 2023 -0400

    Added command line for GHDL in docker image, sicne vunit doesn't seem to place it in the right place

commit 943c336
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 18:30:42 2023 -0400

    Updates to max stack

commit fe0b915
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 17:51:16 2023 -0400

    Try 3

commit 8598fd0
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 17:48:07 2023 -0400

    Fix for type issues, try 2

commit 4bb0832
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:19:39 2023 -0400

    There was an type ambiguity in other files when we overloaded gen_twiddle_factor, removed overloading

commit 6194b73
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:17:47 2023 -0400

    Disabling scipy since not in the Docker image

commit b3d0f84
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:11:09 2023 -0400

    Implemented a Real Twiddles output in twiddles pkf
    Implemented a fixed point bit accurate model for the r2sdf_fft in r2sdf_fft_py module.

    Added a testbench using ngVLA proposed size.  Still need to implement in wbfft though
@mschiller-nrao
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r2sdf Bit accurate model implemented in new r2sdf testbench!

Added fixed point simulation of the fft_r2_wide in the configuration I'd likely use on ngVLA!   also removed the requirement to rewrite fft_gncrcs_intrfcs_pkg, with some more changes to matlab/python the generics could now
be set directly to the underlying synthesizable code (see how I did it in the tb_vu_wb_fft_vfmodel.vhd file which overrides the constants set by matlab in the fft_gncrcs_intrgcs_pkg

Squashed commit of the following:

commit cebf54c
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 31 10:36:05 2023 -0400

    Fix to use generic types to allow better configurability from generics

commit 16a8e63
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 31 10:03:49 2023 -0400

    Implemented partial support for elimination of "rewrite" of fft_gncrcs_intrfcs_pkg.vhd by matlab/python

    With 2-d arrays it should be possible to keep fft_r2_wide/fft_r2_par fully generic.  While Synthesizable VHDL blocks should be fixed up, I didn't ripout the matlab support
    So what will happen is matlab will likely rewrite the pkg file and those settings become the default, but if you want to set them from a higher level
    vhdl file it should work.   Seems to work for tb_bu_wb_fft_vfmodel.vhd which is the fixed point bit-accurate model configured for ngVLAs sizes

commit fa17175
Merge: 9a06831 cffba16
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 15:27:41 2023 -0400

    Make our branches the same again
    Merge branch 'github'

commit 9a06831
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 13:54:18 2023 -0400

    Further improvements to execution time
    reduced data processed by fix_point model

commit dde760b
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 11:24:29 2023 -0400

    Compiling the VHDL for turned off testbenches still allowed the VHDL to run

commit 59ffb93
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:57:30 2023 -0400

    More syntax error fixage

commit 7303de1
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:35:11 2023 -0400

    Fixed syntax error

commit 3bb66e9
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:27:34 2023 -0400

    Due to long run time in GHDL, the bitaccurate and twiddle tests are now manually run and turned off unless a command line argument is passed

commit 3981e58
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 21:05:44 2023 -0400

    Reduce Execution time for r2sdf

commit 9978344
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 19:57:44 2023 -0400

    Fix for stack memory usage in GHDL

commit c7479e8
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 19:36:06 2023 -0400

    This is still going to break but I want the error

commit ddc6cc3
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 18:47:24 2023 -0400

    Added command line for GHDL in docker image, sicne vunit doesn't seem to place it in the right place

commit 943c336
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 18:30:42 2023 -0400

    Updates to max stack

commit fe0b915
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 17:51:16 2023 -0400

    Try 3

commit 8598fd0
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 17:48:07 2023 -0400

    Fix for type issues, try 2

commit 4bb0832
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:19:39 2023 -0400

    There was an type ambiguity in other files when we overloaded gen_twiddle_factor, removed overloading

commit 6194b73
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:17:47 2023 -0400

    Disabling scipy since not in the Docker image

commit b3d0f84
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:11:09 2023 -0400

    Implemented a Real Twiddles output in twiddles pkf
    Implemented a fixed point bit accurate model for the r2sdf_fft in r2sdf_fft_py module.

    Added a testbench using ngVLA proposed size.  Still need to implement in wbfft though
1) Implemented AgileX (intel) and Versal support, both require different complex multiplier implementations
2) Implemented some support for not having testbenches rewrite the fft_interfaces file, my bit accurate testbenches use this support, but I didn't update the older testbenches to use it

These now work the way NGVLA wants them for now.  However:
Reordering for the ngVLA configuration (wb_factor=16, points=8192) doesn't seem to work properly.

Some testbenches still fail if you use a mode other than "xpm" "legacy" xilinx.   However Agilex/Versal both work for the ngVLA configuration, so I didn't go back to fix the minor issues (eg casper_multiply testbench).

The issue I think is that Agilex/versal and possibly stratixIV all require different multiplier pipelines.  The fixes I put in for the ngVLA configuration may have fixed those though

Squashed commit of the following:

commit 677688a
Author: Matthew Schiller <[email protected]>
Date:   Tue Apr 4 08:46:48 2023 -0400

    Git ignore'ing vivado files

commit 75711b0
Author: Matthew Schiller <[email protected]>
Date:   Tue Apr 4 08:22:31 2023 -0400

    Added support for Versal.   Versal uses XPM for memory, but uses a inferred complex multiplier

commit 086663f
Author: Matthew Schiller <[email protected]>
Date:   Tue Apr 4 08:00:01 2023 -0400

    Update to fix reorder for wideband pfb.   I still contend that wideband reorder isn't working quite right, but disabling it here didn't help.

commit 10033c4
Author: Matthew Schiller <[email protected]>
Date:   Mon Apr 3 15:20:42 2023 -0400

    Reverting to Xilinx default for sims,

    Some test cases don't work for Intel

commit 1dbd540
Author: Matthew Schiller <[email protected]>
Date:   Mon Apr 3 15:07:34 2023 -0400

    Fix python bugs

commit 6f9f0b0
Merge: cebf54c b93be43
Author: Matthew Schiller <[email protected]>
Date:   Mon Apr 3 15:02:18 2023 -0400

    Merge branch 'github'

commit b93be43
Author: Matthew Schiller <[email protected]>
Date:   Mon Apr 3 14:52:37 2023 -0400

    Updates to support AgileX

commit cebf54c
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 31 10:36:05 2023 -0400

    Fix to use generic types to allow better configurability from generics

commit 16a8e63
Author: Matthew Schiller <[email protected]>
Date:   Fri Mar 31 10:03:49 2023 -0400

    Implemented partial support for elimination of "rewrite" of fft_gncrcs_intrfcs_pkg.vhd by matlab/python

    With 2-d arrays it should be possible to keep fft_r2_wide/fft_r2_par fully generic.  While Synthesizable VHDL blocks should be fixed up, I didn't ripout the matlab support
    So what will happen is matlab will likely rewrite the pkg file and those settings become the default, but if you want to set them from a higher level
    vhdl file it should work.   Seems to work for tb_bu_wb_fft_vfmodel.vhd which is the fixed point bit-accurate model configured for ngVLAs sizes

commit fa17175
Merge: 9a06831 cffba16
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 15:27:41 2023 -0400

    Make our branches the same again
    Merge branch 'github'

commit 9a06831
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 13:54:18 2023 -0400

    Further improvements to execution time
    reduced data processed by fix_point model

commit dde760b
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 11:24:29 2023 -0400

    Compiling the VHDL for turned off testbenches still allowed the VHDL to run

commit 59ffb93
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:57:30 2023 -0400

    More syntax error fixage

commit 7303de1
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:35:11 2023 -0400

    Fixed syntax error

commit 3bb66e9
Author: Matthew Schiller <[email protected]>
Date:   Wed Mar 29 10:27:34 2023 -0400

    Due to long run time in GHDL, the bitaccurate and twiddle tests are now manually run and turned off unless a command line argument is passed

commit 3981e58
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 21:05:44 2023 -0400

    Reduce Execution time for r2sdf

commit 9978344
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 19:57:44 2023 -0400

    Fix for stack memory usage in GHDL

commit c7479e8
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 19:36:06 2023 -0400

    This is still going to break but I want the error

commit ddc6cc3
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 18:47:24 2023 -0400

    Added command line for GHDL in docker image, sicne vunit doesn't seem to place it in the right place

commit 943c336
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 18:30:42 2023 -0400

    Updates to max stack

commit fe0b915
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 17:51:16 2023 -0400

    Try 3

commit 8598fd0
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 17:48:07 2023 -0400

    Fix for type issues, try 2

commit 4bb0832
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:19:39 2023 -0400

    There was an type ambiguity in other files when we overloaded gen_twiddle_factor, removed overloading

commit 6194b73
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:17:47 2023 -0400

    Disabling scipy since not in the Docker image

commit b3d0f84
Author: Matthew Schiller <[email protected]>
Date:   Tue Mar 28 16:11:09 2023 -0400

    Implemented a Real Twiddles output in twiddles pkf
    Implemented a fixed point bit accurate model for the r2sdf_fft in r2sdf_fft_py module.

    Added a testbench using ngVLA proposed size.  Still need to implement in wbfft though
@mschiller-nrao
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This is my last checkin for a bit, have to get back to document writing. But the ngVLA configurations are working with versal and agileX support.

Features implemented:

  1. Versal/AgileX complex multiplier (the new dsps support special modes for complex multiplies)
  2. Inferred Twiddles
  3. Bit accurate model is implemented

Features still planned for "someday" on ngVLA:

  1. DIF/DIT support (eg ability to take bit-revorder inputs)
  2. Fix reorder support for wb_factor=16, 8192 points, which appears to not work currently
  3. IFFT support (pretty trivial)
  4. Possibly elimination of XPM/AlteraMF memories for inferred versions.

But those will have to wait for a later time (and a later pull-request)

@talonmyburgh
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Created origin/pre-nrao-merge branch to retain state pre merge from NRAO. Will address bugs if/when they crop up.

@talonmyburgh talonmyburgh merged commit 8bd704c into talonmyburgh:master May 8, 2023
@talonmyburgh
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@mschiller-nrao having issue with Vivado support for:

use ieee.fixed_float_types.all;
use ieee.fixed_pkg.all;

Inside of common_pkg.vhd.

Appears that this functionality is not supported in Vivado's 2008 feature set. I've tried this solution but had no luck.

Unfortunately due to how integrated CASPER is with Vivado, if Vivado won't support it, we need to implement a manual workaround. Any ideas? Otherwise I can give it a whirl.

@talonmyburgh
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Could try something like:

function round_even (x : real) return integer is
begin
    if x >= 0.0 then
        return integer(x + 0.5);
    else
        return integer(x - 0.5);
    end if;
end function round_even;

and have an additional overload-type function that accepts slv input?

@mschiller-nrao
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mschiller-nrao commented May 8, 2023 via email

@talonmyburgh
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Ah... been using Vivado 2020.1 since that has good compatability with MATLAB 2019a and the casper toolflow.

I have been loading the file as VHDL-2008. Must just be the Vivado version :/

@mschiller-nrao
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mschiller-nrao commented May 8, 2023 via email

@talonmyburgh
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Preaching to the crowd here :') If I could place and route with nextpnr I'd do away with Vivado all together.

Thanks. I'll add you as a contributor so you can push directly to this repository.

@talonmyburgh
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Some actions also failed to successfully run. Will address those soon too!

@mschiller-nrao
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mschiller-nrao commented May 8, 2023

I'm not surprised, I never got github actions (something about github secrets that I didn't understand and didn't take the time to figure out) to work on my forked repo. So I couldn't test them (there's some weirdness on Actions and forked repos on github).

But those should be fixable, since internally the code works on gitlab.

image

The only thing I never got to work was the casper_delay tests, but those were broken in my test environment when I forked... So I assumed they were broken in github actions too.... But if not... Ugh more tool problems.

@talonmyburgh
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Nah the casper_delay had some known issues - not your stuff :)

@talonmyburgh
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@mschiller-nrao can I leave it for you to add the necessary files from here to this repository to make the fixed point stuff work?

Best method may just be to submodule it into the repository - which I'm happy to do if you agree? We had to do some submoduling of XPM libraries for GHDL.

@mschiller-nrao
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mschiller-nrao commented May 8, 2023

Yeah I'll have to download 2020.1 (which is slowly downloading...) to be sure I get it right... But if you want to just hold off, I should be able to address this in the next 24 hours or so.

@talonmyburgh
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No rush. Thank you!

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mschiller-nrao commented May 9, 2023

Ugh I hate tool problem...

Good news: My Test design works
Bad News: I didn't change anything...... (other than selecting a random ultrascale+ part and using vivado 2020.1)

I'm hoping the problem is I have it in "versal" mode using the new tech_select_package files I added. Hopefully it'll break in "xpm" mode which is what I assume you are using....... Let me try that.

(I have c_test_select_default = 3, in this test build, and I'm going to change it back to 1)

image

@mschiller-nrao
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Ugh so in my VHDL only test design it seems to always work.... So that's fun...
project_1_test_casper.xpr.zip

A Vivado archive of the project is attached if you want to try buidling it on your machine to rule out something there.

I guess the next step is trying to figure out how your fancy matlab stuff works.. But I don't think I have the right matlab version =c(
I've

@mschiller-nrao
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And I don't have a copy of simulink......... =c( I might be stuck @talonmyburgh I don't seem to be able to replicate the problem.

Assuming I'm at the same version of Vivado (see screencapture above) I think we're looking at a project file settings... is all your casper VHDL files set to 2008? or just a few of them?

@talonmyburgh
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talonmyburgh commented May 9, 2023

@mschiller-nrao Just a few of them we made VHDL2008. @mschiller-nrao could you try with the committed Vivado projects:

And try synthesize those? I had issue synthesizing the wbfft project (as is) then changed common_pkg.vhd to be VHDL2008 and still had issue.

Sorry I have not documented the locations of these project files - probably would've made your life easier

@mschiller-nrao
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mschiller-nrao commented May 11, 2023 via email

@mschiller-nrao
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Alright I fixed one:
image

Those files were the ones that needed to be 2008, but there was also some type non-sense because I made one of the types more generic with a record of unconstrained std_logic_vector.

But with unconstrained std_logic_vector the top level (ish) needs to declare the size in the signal declaration. That should be fixed too.. so your top level declares the proper sizes i wb_fft.

I'll look at fixing the other ones and then check this all in.

@talonmyburgh
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Thanks a tonne @mschiller-nrao !

@mschiller-nrao
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mschiller-nrao commented May 12, 2023 via email

@talonmyburgh
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talonmyburgh commented May 15, 2023

Oh yikes! Don't worry I made a branch pre the changes so I'm working off of that. I can attempt to make some fixes to the master branch but am constrained for time with my own project.
Hope you get better soon!

@mschiller-nrao
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there testbench works again on on my machine

@talonmyburgh
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Thanks @mschiller-nrao I'm surprised/pleased you're already back at it. I hope you are healing well.

Please shout if there is anything you need from me to get things working. I understand Github Actions are a pain and occasionally with run for a while due to scheduling. I'd maybe recommend branching, testing locally and then occasionally adding PR's so we don't use up our action minutes - though I don't imagine we will.

@mschiller-nrao
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mschiller-nrao commented May 19, 2023 via email

@mschiller-nrao
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mschiller-nrao commented May 19, 2023 via email

@talonmyburgh
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Excellent thanks!

Also feel free to approve your own PR's when you see fit. Arguably more important than VUnit support is the Vivado 2020.1 project support that we have... so please try maintain that.

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