From 5f636a1566f0a848c5d884b84a348e7b45da398f Mon Sep 17 00:00:00 2001 From: Tom De Rybel Date: Thu, 16 Dec 2021 16:05:31 +0100 Subject: [PATCH 1/4] Added more documented and explicit memory.x examples for all STM32H7xx current device families. --- Cargo.toml | 23 ++++-- memory_723_725_730_733_735.x | 105 ++++++++++++++++++++++++++++ memory_742.x | 107 ++++++++++++++++++++++++++++ memory_743_750_753.x | 114 ++++++++++++++++++++++++++++++ memory_745_747_755_757.x | 131 +++++++++++++++++++++++++++++++++++ memory_7A3_7B0_7B3.x | 125 +++++++++++++++++++++++++++++++++ 6 files changed, 599 insertions(+), 6 deletions(-) create mode 100644 memory_723_725_730_733_735.x create mode 100644 memory_742.x create mode 100644 memory_743_750_753.x create mode 100644 memory_745_747_755_757.x create mode 100644 memory_7A3_7B0_7B3.x diff --git a/Cargo.toml b/Cargo.toml index 0ccff33a..28c2a9f5 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -103,16 +103,27 @@ rt = ["stm32h7/rt"] usb_hs = ["synopsys-usb-otg", "synopsys-usb-otg/hs"] stm32h742 = ["stm32h7/stm32h743", "device-selected", "rm0433"] stm32h743 = ["stm32h7/stm32h743", "device-selected", "rm0433"] -stm32h753 = ["stm32h7/stm32h753", "device-selected", "rm0433"] stm32h750 = ["stm32h7/stm32h743", "device-selected", "rm0433"] +stm32h753 = ["stm32h7/stm32h753", "device-selected", "rm0433"] stm32h742v = ["stm32h7/stm32h743v", "device-selected", "revision_v", "rm0433"] stm32h743v = ["stm32h7/stm32h743v", "device-selected", "revision_v", "rm0433"] -stm32h753v = ["stm32h7/stm32h753v", "device-selected", "revision_v", "rm0433"] stm32h750v = ["stm32h7/stm32h743v", "device-selected", "revision_v", "rm0433"] -stm32h747cm7 = ["stm32h7/stm32h747cm7", "device-selected", "revision_v", "rm0399", "cm7", "dsi", "smps"] -stm32h7b3 = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455", "smps"] -stm32h7b0 = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455", "smps"] -stm32h7a3 = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455", "smps"] +stm32h753v = ["stm32h7/stm32h753v", "device-selected", "revision_v", "rm0433"] +stm32h745cm7 = ["stm32h7/stm32h747cm7", "device-selected", "revision_v", "rm0399", "cm7", "smps"] +stm32h747cm7 = ["stm32h7/stm32h747cm7", "device-selected", "revision_v", "rm0399", "cm7", "smps", "dsi"] +stm32h755cm7 = ["stm32h7/stm32h747cm7", "device-selected", "revision_v", "rm0399", "cm7", "smps"] +stm32h757cm7 = ["stm32h7/stm32h747cm7", "device-selected", "revision_v", "rm0399", "cm7", "smps", "dsi"] +stm32h7a3 = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455"] +stm32h7a3q = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455", "smps"] # SMPS is only available on STM32H7A3xIxxQ and STM32H7A3xGxxQ versions. +stm32h7b0 = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455"] +stm32h7b0q = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455", "smps"] # SMPS is only available on STM32H7B0xIxxQ versions. +stm32h7b3 = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455"] +stm32h7b3q = ["stm32h7/stm32h7b3", "device-selected", "revision_v", "rm0455", "smps"] # SMPS is only available on STM32H7B3xIxxQ versions. +stm32h723 = ["stm32h7/stm32h735", "device-selected", "revision_v", "rm0468"] +stm32h725 = ["stm32h7/stm32h735", "device-selected", "revision_v", "rm0468", "smps"] +stm32h730 = ["stm32h7/stm32h735", "device-selected", "revision_v", "rm0468"] +stm32h730q = ["stm32h7/stm32h735", "device-selected", "revision_v", "rm0468", "smps"] # SMPS is only available on STM32H730xxxxQ versions. +stm32h733 = ["stm32h7/stm32h735", "device-selected", "revision_v", "rm0468"] stm32h735 = ["stm32h7/stm32h735", "device-selected", "revision_v", "rm0468", "smps"] # Flags for examples log-itm = [] diff --git a/memory_723_725_730_733_735.x b/memory_723_725_730_733_735.x new file mode 100644 index 00000000..44d1b951 --- /dev/null +++ b/memory_723_725_730_733_735.x @@ -0,0 +1,105 @@ +MEMORY +{ + /* This file is intended for parts in the STM32H735 family. (RM0468) */ + /* - FLASH and RAM are mandatory memory sections. */ + /* - The sum of all non-FLASH sections must add to 564k total device RAM. */ + /* - The FLASH section size must match your device, see table below. */ + + /* FLASH */ + /* Select the appropriate FLASH size for your device. */ + /* - STM32H730xB 128K */ + /* - STM32H723xE/725xE 512K */ + /* - STM32H723xG/725xG/733xG/735xG 1M */ + FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M + + /* Data TCM */ + /* - Two contiguous 64KB RAMs. */ + /* - Used for interrupt handlers, stacks and general RAM. */ + /* - Zero wait-states. */ + /* - The DTCM is taken as the origin of the base ram. (See below.) */ + /* This is also where the interrupt table and such will live, */ + /* which is required for deterministic performance. */ + DTCM : ORIGIN = 0x20000000, LENGTH = 128K + + /* Instruction TCM */ + /* - Used for latency-critical interrupt handlers etc. */ + /* - Zero wait-states. */ + ITCM : ORIGIN = 0x00000000, LENGTH = 64K + + /* AXI SRAM */ + /* - AXISRAM is in D1 and accessible by all system masters except BDMA. */ + /* - Suitable for application data not stored in DTCM. */ + /* - Zero wait-states. */ + /* - The 192k of extra shared RAM is fully allotted to the AXI SRAM by default. */ + /* This results in: 64k for ITCM and 320k (128k + 192k) for AXI SRAM. */ + /* This can be re-configured via the TCM_AXI_SHARED[1,0] register when more */ + /* ITCM is required. */ + AXISRAM : ORIGIN = 0x24000000, LENGTH = 320K + + /* AHB SRAM */ + /* - SRAM1-2 are in D2 and accessible by all system masters except BDMA, LTDC */ + /* and SDMMC1. Suitable for use as DMA buffers. */ + /* - SRAM4 is in D3 and additionally accessible by the BDMA. Used for BDMA */ + /* buffers, for storing application data in lower-power modes. */ + /* - Zero wait-states. */ + SRAM1 : ORIGIN = 0x30000000, LENGTH = 16K + SRAM2 : ORIGIN = 0x30040000, LENGTH = 16K + SRAM4 : ORIGIN = 0x38000000, LENGTH = 16K + + /* Backup SRAM */ + /* Used to store data during low-power sleeps. */ + BSRAM : ORIGIN = 0x38800000, LENGTH = 4K +} + +/* +/* Assign the memory regions defined above for use. */ +/* + +/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */ +REGION_ALIAS(FLASH, FLASH1); +REGION_ALIAS(RAM, DTCM); + +/* The location of the stack can be overridden using the `_stack_start` symbol. */ +/* - Set the stack location at the end of RAM, using all remaining space. */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* The location of the .text section can be overridden using the */ +/* `_stext` symbol. By default it will place after .vector_table. */ +/* _stext = ORIGIN(FLASH) + 0x40c; */ + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */ +/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */ +SECTIONS { + .itcm (NOLOAD) : ALIGN(8) { + *(.itcm .itcm.*); + . = ALIGN(8); + } > ITCM + + .axisram (NOLOAD) : ALIGN(8) { + *(.axisram .axisram.*); + . = ALIGN(8); + } > AXISRAM + + .sram1 (NOLOAD) : ALIGN(4) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM1 + + .sram2 (NOLOAD) : ALIGN(4) { + *(.sram2 .sram2.*); + . = ALIGN(4); + } > SRAM2 + + .sram4 (NOLOAD) : ALIGN(4) { + *(.sram4 .sram4.*); + . = ALIGN(4); + } > SRAM4 + + .bsram (NOLOAD) : ALIGN(4) { + *(.bsram .bsram.*); + . = ALIGN(4); + } > BSRAM + +} INSERT AFTER .bss; diff --git a/memory_742.x b/memory_742.x new file mode 100644 index 00000000..264b29cd --- /dev/null +++ b/memory_742.x @@ -0,0 +1,107 @@ +MEMORY +{ + /* This file is intended for parts in the STM32H742/742v families. (RM0433) */ + /* - FLASH and RAM are mandatory memory sections. */ + /* - The sum of all non-FLASH sections must add to 692K total device RAM. */ + /* - The FLASH section size must match your device, see table below. */ + + /* FLASH */ + /* Flash is divided in two independent banks. */ + /* Select the appropriate FLASH size for your device. */ + /* - STM32H742xG 1M (512K + 512K) */ + /* - STM32H742xI 2M ( 1M + 1M) */ + FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M + FLASH2 : ORIGIN = 0x08100000, LENGTH = 1M + + /* Data TCM */ + /* - Two contiguous 64KB RAMs. */ + /* - Used for interrupt handlers, stacks and general RAM. */ + /* - Zero wait-states. */ + /* - The DTCM is taken as the origin of the base ram. (See below.) */ + /* This is also where the interrupt table and such will live, */ + /* which is required for deterministic performance. */ + DTCM : ORIGIN = 0x20000000, LENGTH = 128K + + /* Instruction TCM */ + /* - Used for latency-critical interrupt handlers etc. */ + /* - Zero wait-states. */ + ITCM : ORIGIN = 0x00000000, LENGTH = 64K + + /* AXI SRAM */ + /* - AXISRAM is in D1 and accessible by all system masters except BDMA. */ + /* - Suitable for application data not stored in DTCM. */ + /* - Zero wait-states. */ + AXISRAM : ORIGIN = 0x24000000, LENGTH = 384K + + /* AHB SRAM */ + /* - SRAM1-2 are in D2 and accessible by all system masters except BDMA. */ + /* Suitable for use as DMA buffers. */ + /* - SRAM4 is in D3 and additionally accessible by the BDMA. Used for BDMA */ + /* buffers, for storing application data in lower-power modes. */ + /* - Zero wait-states. */ + SRAM1 : ORIGIN = 0x30000000, LENGTH = 32K + SRAM2 : ORIGIN = 0x30020000, LENGTH = 16K + SRAM4 : ORIGIN = 0x38000000, LENGTH = 64K + + /* Backup SRAM */ + /* Used to store data during low-power sleeps. */ + BSRAM : ORIGIN = 0x38800000, LENGTH = 4K +} + +/* +/* Assign the memory regions defined above for use. */ +/* + +/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */ +REGION_ALIAS(FLASH, FLASH1); +REGION_ALIAS(RAM, DTCM); + +/* The location of the stack can be overridden using the `_stack_start` symbol. */ +/* - Set the stack location at the end of RAM, using all remaining space. */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* The location of the .text section can be overridden using the */ +/* `_stext` symbol. By default it will place after .vector_table. */ +/* _stext = ORIGIN(FLASH) + 0x40c; */ + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */ +/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */ +SECTIONS { + .flash2 (NOLOAD) : ALIGN(4) { + *(.flash2 .flash2.*); + . = ALIGN(4); + } > FLASH2 + + .itcm (NOLOAD) : ALIGN(8) { + *(.itcm .itcm.*); + . = ALIGN(8); + } > ITCM + + .axisram (NOLOAD) : ALIGN(8) { + *(.axisram .axisram.*); + . = ALIGN(8); + } > AXISRAM + + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM1 + + .sram2 (NOLOAD) : ALIGN(8) { + *(.sram2 .sram2.*); + . = ALIGN(4); + } > SRAM2 + + .sram4 (NOLOAD) : ALIGN(4) { + *(.sram4 .sram4.*); + . = ALIGN(4); + } > SRAM4 + + .bsram (NOLOAD) : ALIGN(4) { + *(.bsram .bsram.*); + . = ALIGN(4); + } > BSRAM + +} INSERT AFTER .bss; diff --git a/memory_743_750_753.x b/memory_743_750_753.x new file mode 100644 index 00000000..08d1b3a3 --- /dev/null +++ b/memory_743_750_753.x @@ -0,0 +1,114 @@ +MEMORY +{ + /* This file is intended for parts in the STM32H743/743v/753/753v families (RM0433), */ + /* with the exception of the STM32H742/742v parts which have a different RAM layout. */ + /* - FLASH and RAM are mandatory memory sections. */ + /* - The sum of all non-FLASH sections must add to 1060K total device RAM. */ + /* - The FLASH section size must match your device, see table below. */ + + /* FLASH */ + /* Flash is divided in two independent banks (except 750xB). */ + /* Select the appropriate FLASH size for your device. */ + /* - STM32H750xB 128K (only FLASH1) */ + /* - STM32H750xB 1M (512K + 512K) */ + /* - STM32H743xI/753xI 2M ( 1M + 1M) */ + FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M + FLASH2 : ORIGIN = 0x08100000, LENGTH = 1M + + /* Data TCM */ + /* - Two contiguous 64KB RAMs. */ + /* - Used for interrupt handlers, stacks and general RAM. */ + /* - Zero wait-states. */ + /* - The DTCM is taken as the origin of the base ram. (See below.) */ + /* This is also where the interrupt table and such will live, */ + /* which is required for deterministic performance. */ + DTCM : ORIGIN = 0x20000000, LENGTH = 128K + + /* Instruction TCM */ + /* - Used for latency-critical interrupt handlers etc. */ + /* - Zero wait-states. */ + ITCM : ORIGIN = 0x00000000, LENGTH = 64K + + /* AXI SRAM */ + /* - AXISRAM is in D1 and accessible by all system masters except BDMA. */ + /* - Suitable for application data not stored in DTCM. */ + /* - Zero wait-states. */ + AXISRAM : ORIGIN = 0x24000000, LENGTH = 512K + + /* AHB SRAM */ + /* - SRAM1-3 are in D2 and accessible by all system masters except BDMA. */ + /* Suitable for use as DMA buffers. */ + /* - SRAM4 is in D3 and additionally accessible by the BDMA. Used for BDMA */ + /* buffers, for storing application data in lower-power modes. */ + /* - Zero wait-states. */ + SRAM1 : ORIGIN = 0x30000000, LENGTH = 128K + SRAM2 : ORIGIN = 0x30020000, LENGTH = 128K + SRAM3 : ORIGIN = 0x30040000, LENGTH = 32K + SRAM4 : ORIGIN = 0x38000000, LENGTH = 64K + + /* Backup SRAM */ + BSRAM : ORIGIN = 0x38800000, LENGTH = 4K +} + +/* +/* Assign the memory regions defined above for use. */ +/* + +/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */ +REGION_ALIAS(FLASH, FLASH1); +REGION_ALIAS(RAM, DTCM); + +/* The location of the stack can be overridden using the `_stack_start` symbol. */ +/* - Set the stack location at the end of RAM, using all remaining space. */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* The location of the .text section can be overridden using the */ +/* `_stext` symbol. By default it will place after .vector_table. */ +/* _stext = ORIGIN(FLASH) + 0x40c; */ + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */ +/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */ +SECTIONS { + .flash2 (NOLOAD) : ALIGN(4) { + *(.flash2 .flash2.*); + . = ALIGN(4); + } > FLASH2 + + .itcm (NOLOAD) : ALIGN(8) { + *(.itcm .itcm.*); + . = ALIGN(8); + } > ITCM + + .axisram (NOLOAD) : ALIGN(8) { + *(.axisram .axisram.*); + . = ALIGN(8); + } > AXISRAM + + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM1 + + .sram2 (NOLOAD) : ALIGN(8) { + *(.sram2 .sram2.*); + . = ALIGN(4); + } > SRAM2 + + .sram3 (NOLOAD) : ALIGN(4) { + *(.sram3 .sram3.*); + . = ALIGN(4); + } > SRAM3 + + .sram4 (NOLOAD) : ALIGN(4) { + *(.sram4 .sram4.*); + . = ALIGN(4); + } > SRAM4 + + .bsram (NOLOAD) : ALIGN(4) { + *(.bsram .bsram.*); + . = ALIGN(4); + } > BSRAM + +} INSERT AFTER .bss; diff --git a/memory_745_747_755_757.x b/memory_745_747_755_757.x new file mode 100644 index 00000000..7398bc4f --- /dev/null +++ b/memory_745_747_755_757.x @@ -0,0 +1,131 @@ +MEMORY +{ + /* This file is intended for parts in the STM32H747 family. (RM0399) */ + /* - These are dual-core parts, having both a CM7 (primary) and CM4 core. */ + /* - FLASH and RAM are mandatory memory sections. */ + /* - The sum of all non-FLASH sections must add to 1060k total device RAM. */ + /* - The FLASH section size must match your device, see table below. */ + + /* FLASH */ + /* Flash is divided in two independent banks. */ + /* Select the appropriate FLASH sizes for your device. */ + /* - STM32H745xG/747xG 1M (512K + 512K) */ + /* - STM32H745xI/747xI/755xI/757xI 2M ( 1M + 1M) */ + FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M + FLASH2 : ORIGIN = 0x08100000, LENGTH = 1M + + /* Data TCM */ + /* - Two contiguous 64KB RAMs. */ + /* - Used for interrupt handlers, stacks and general RAM. */ + /* - Only accessible to the Cortex-M7 core. */ + /* - Zero wait-states. */ + /* - The DTCM is taken as the origin of the base ram. (See below.) */ + /* This is also where the interrupt table and such will live, */ + /* which is required for deterministic performance. */ + DTCM : ORIGIN = 0x20000000, LENGTH = 128K + + /* Instruction TCM */ + /* - Used for latency-critical interrupt handlers etc. */ + /* - Zero wait-states. */ + ITCM : ORIGIN = 0x00000000, LENGTH = 64K + + /* AXI SRAM */ + /* - Accessible by all system masters except BDMA. */ + /* - Suitable for application data not stored in DTCM. */ + /* - Zero wait-states. */ + AXISRAM : ORIGIN = 0x24000000, LENGTH = 512K + + /* AHB SRAM */ + /* - SRAM1-3 are in D2 and accessible by all system masters except BDMA. */ + /* Suitable for use as DMA buffers. */ + /* - SRAM4 is in D3 and additionally accessible by the BDMA. Used for BDMA */ + /* buffers, for storing application data in lower-power modes, or for */ + /* sharing data between the Cortex-M4 and Cortex-M7 cores. */ + /* - Zero wait-states. */ + SRAM1 : ORIGIN = 0x30000000, LENGTH = 128K + SRAM2 : ORIGIN = 0x30020000, LENGTH = 128K + SRAM3 : ORIGIN = 0x30040000, LENGTH = 32K + SRAM4 : ORIGIN = 0x38000000, LENGTH = 64K + + /* Backup SRAM */ + /* Used to store data during low-power sleeps. */ + BSRAM : ORIGIN = 0x38800000, LENGTH = 4K +} + +/* +/* Assign the memory regions defined above for use. */ +/* + +/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */ +/* - These definitions concern only the CM7 core (CPU1). */ +/* - The CM4 core (CPU2) is set-up separately in the various other sections, below. */ +REGION_ALIAS(FLASH, FLASH1); +REGION_ALIAS(RAM, DTCM); + +/* The location of the stack can be overridden using the `_stack_start` symbol. */ +/* - Set the CM7 core (CPU1) stack location at the end of RAM, using all remaining space. */ +/* - Set the CM4 core (CPU2) stack location in SRAM2, using the whole memory bank. */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); +_cpu2_stack_start = ORIGIN(SRAM2) + LENGTH(SRAM2); + +/* The location of the .text section can be overridden using the */ +/* `_stext` symbol. By default it will place after .vector_table. */ +/* _stext = ORIGIN(FLASH) + 0x40c; */ + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */ +/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */ +/* - The SRAM1 and SRAM2 sections are commonly used as the stack and heap for */ +/* the CM4 core in dual core versions and may thus have to be omitted from */ +/* this list. */ +SECTIONS { + .flash2 : ALIGN(4) { + LONG(_cpu2_stack_start); + KEEP(*(.flash2.reset_vector)); + KEEP(*(.flash2.vector_table)); + *(.flash2 .flash2.*); + . = ALIGN(4); + } > FLASH2 + + /*.itcm (NOLOAD) : ALIGN(8) { */ + /* *(.itcm .itcm.*); */ + /* . = ALIGN(8); */ + /* } > ITCM */ + + .itcm : ALIGN(4) { + *(.itcm .itcm.*); + . = ALIGN(4); + } > ITCM AT > FLASH + + .axisram (NOLOAD) : ALIGN(8) { + *(.axisram .axisram.*); + . = ALIGN(8); + } > AXISRAM + + .sram1 (NOLOAD) : ALIGN(4) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM1 + + .sram2 (NOLOAD) : ALIGN(4) { + *(.sram2 .sram2.*); + . = ALIGN(4); + } > SRAM2 + + .sram3 (NOLOAD) : ALIGN(4) { + *(.sram3 .sram3.*); + . = ALIGN(4); + } > SRAM3 + + .sram4 (NOLOAD) : ALIGN(4) { + *(.sram4 .sram4.*); + . = ALIGN(4); + } > SRAM4 + + .bsram (NOLOAD) : ALIGN(4) { + *(.bsram .bsram.*); + . = ALIGN(4); + } > BSRAM + +} INSERT AFTER .bss; diff --git a/memory_7A3_7B0_7B3.x b/memory_7A3_7B0_7B3.x new file mode 100644 index 00000000..521d70bd --- /dev/null +++ b/memory_7A3_7B0_7B3.x @@ -0,0 +1,125 @@ +MEMORY +{ + /* This file is intended for parts in the STM32H7B3 family. (RM0455) */ + /* - FLASH and RAM are mandatory memory sections. */ + /* - The sum of all non-FLASH sections must add to 1380K total device RAM. */ + /* - The FLASH section size must match your device, see table below. */ + + /* FLASH */ + /* Flash is divided in two independent banks (except 7B0xB). */ + /* Select the appropriate FLASH size for your device. */ + /* - STM32H7B0xB 128K (only FLASH1) */ + /* - STM32H7A3xG/7B3xG 1M (512K + 512K) */ + /* - STM32H7A3xI/7B3xI 2M ( 1M + 1M) */ + FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M + FLASH2 : ORIGIN = 0x08100000, LENGTH = 1M + + /* Data TCM */ + /* - Two contiguous 64KB RAMs. */ + /* - Used for interrupt handlers, stacks and general RAM. */ + /* - Zero wait-states. */ + /* - The DTCM is taken as the origin of the base ram. (See below.) */ + /* This is also where the interrupt table and such will live, */ + /* which is required for deterministic performance. */ + DTCM : ORIGIN = 0x20000000, LENGTH = 128K + + /* Instruction TCM */ + /* - Used for latency-critical interrupt handlers etc. */ + /* - Zero wait-states. */ + ITCM : ORIGIN = 0x00000000, LENGTH = 64K + + /* AXI SRAM */ + /* - AXISRAM1-3 are mapped in the CPU domain (CD). */ + /* - Accessible by all system masters except BDMA1 and BDMA2. */ + /* - Suitable for application data not stored in DTCM. */ + /* - Zero wait-states. */ + AXISRAM1 : ORIGIN = 0x24000000, LENGTH = 256K + AXISRAM2 : ORIGIN = 0x24040000, LENGTH = 384K + AXISRAM3 : ORIGIN = 0x240A0000, LENGTH = 384K + + /* AHB SRAM */ + /* - AHBSRAM1-2 are mapped in the CPU domain (CD). */ + /* - Accessible by all system masters except BDMA2. */ + /* - Suitable for use as DMA buffers. */ + /* - Zero wait-states. */ + AHBSRAM1 : ORIGIN = 0x30000000, LENGTH = 64K + AHBSRAM2 : ORIGIN = 0x30010000, LENGTH = 64K + + /* SRD SRAM */ + /* - Mapped in the Smart Run Domain (SRD). */ + /* - Accessible by most system masters through SRD */ + /* domain AHB matrix. */ + SRDSRAM : ORIGIN = 0x38000000, LENGTH = 32K + + /* Backup SRAM */ + /* Used to store data during low-power sleeps. */ + BSRAM : ORIGIN = 0x38800000, LENGTH = 4K +} + +/* +/* Assign the memory regions defined above for use. */ +/* + +/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */ +REGION_ALIAS(FLASH, FLASH1); +REGION_ALIAS(RAM, DTCM); + +/* The location of the stack can be overridden using the `_stack_start` symbol. */ +/* - Set the stack location at the end of RAM, using all remaining space. */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* The location of the .text section can be overridden using the */ +/* `_stext` symbol. By default it will place after .vector_table. */ +/* _stext = ORIGIN(FLASH) + 0x40c; */ + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */ +/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */ +SECTIONS { + .flash2 (NOLOAD) : ALIGN(4) { + *(.flash2 .flash2.*); + . = ALIGN(4); + } > FLASH2 + + .itcm (NOLOAD) : ALIGN(8) { + *(.itcm .itcm.*); + . = ALIGN(8); + } > ITCM + + .axisram1 (NOLOAD) : ALIGN(8) { + *(.axisram1 .axisram1.*); + . = ALIGN(8); + } > AXISRAM1 + + .axisram2 (NOLOAD) : ALIGN(8) { + *(.axisram2 .axisram2.*); + . = ALIGN(8); + } > AXISRAM2 + + .axisram3 (NOLOAD) : ALIGN(8) { + *(.axisram3 .axisram3.*); + . = ALIGN(8); + } > AXISRAM3 + + .ahbsram1 (NOLOAD) : ALIGN(4) { + *(.ahbsram1 .ahbsram1.*); + . = ALIGN(4); + } > AHBSRAM1 + + .ahbsram2 (NOLOAD) : ALIGN(4) { + *(.ahbsram2 .ahbsram2.*); + . = ALIGN(4); + } > AHBSRAM2 + + .srdsram (NOLOAD) : ALIGN(4) { + *(.srdsram .srdsram.*); + . = ALIGN(4); + } > SRDSRAM + + .bsram (NOLOAD) : ALIGN(4) { + *(.bsram .bsram.*); + . = ALIGN(4); + } > BSRAM + +} INSERT AFTER .bss; From 1bf52d5673f6f743c4155eb62358e2858a54c4ab Mon Sep 17 00:00:00 2001 From: Tom De Rybel Date: Thu, 16 Dec 2021 16:09:20 +0100 Subject: [PATCH 2/4] Removed "INSERT AFTER .bss" to match stm32-rs#263 fix. --- memory_723_725_730_733_735.x | 2 +- memory_742.x | 2 +- memory_743_750_753.x | 2 +- memory_745_747_755_757.x | 2 +- memory_7A3_7B0_7B3.x | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/memory_723_725_730_733_735.x b/memory_723_725_730_733_735.x index 44d1b951..6fa47d2a 100644 --- a/memory_723_725_730_733_735.x +++ b/memory_723_725_730_733_735.x @@ -102,4 +102,4 @@ SECTIONS { . = ALIGN(4); } > BSRAM -} INSERT AFTER .bss; +}; diff --git a/memory_742.x b/memory_742.x index 264b29cd..600f5158 100644 --- a/memory_742.x +++ b/memory_742.x @@ -104,4 +104,4 @@ SECTIONS { . = ALIGN(4); } > BSRAM -} INSERT AFTER .bss; +}; diff --git a/memory_743_750_753.x b/memory_743_750_753.x index 08d1b3a3..40d04350 100644 --- a/memory_743_750_753.x +++ b/memory_743_750_753.x @@ -111,4 +111,4 @@ SECTIONS { . = ALIGN(4); } > BSRAM -} INSERT AFTER .bss; +}; diff --git a/memory_745_747_755_757.x b/memory_745_747_755_757.x index 7398bc4f..82bb5e36 100644 --- a/memory_745_747_755_757.x +++ b/memory_745_747_755_757.x @@ -128,4 +128,4 @@ SECTIONS { . = ALIGN(4); } > BSRAM -} INSERT AFTER .bss; +}; diff --git a/memory_7A3_7B0_7B3.x b/memory_7A3_7B0_7B3.x index 521d70bd..2af1d514 100644 --- a/memory_7A3_7B0_7B3.x +++ b/memory_7A3_7B0_7B3.x @@ -122,4 +122,4 @@ SECTIONS { . = ALIGN(4); } > BSRAM -} INSERT AFTER .bss; +}; From 4f6c6a145fce5ea253d468dac5201e2cd21403c1 Mon Sep 17 00:00:00 2001 From: Tom De Rybel Date: Fri, 17 Dec 2021 11:51:48 +0100 Subject: [PATCH 3/4] Improved the documentation for the H735 series regarding ITCM - AXISRAM memory configuration. --- memory_723_725_730_733_735.x | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/memory_723_725_730_733_735.x b/memory_723_725_730_733_735.x index 6fa47d2a..c899499c 100644 --- a/memory_723_725_730_733_735.x +++ b/memory_723_725_730_733_735.x @@ -22,19 +22,20 @@ MEMORY DTCM : ORIGIN = 0x20000000, LENGTH = 128K /* Instruction TCM */ - /* - Used for latency-critical interrupt handlers etc. */ - /* - Zero wait-states. */ - ITCM : ORIGIN = 0x00000000, LENGTH = 64K + /* - More memory can be assigned to ITCM. See AXI SRAM notes, below. */ + /* - Used for latency-critical interrupt handlers etc. */ + /* - Zero wait-states. */ + ITCM : ORIGIN = 0x00000000, LENGTH = 64K + 0K /* AXI SRAM */ /* - AXISRAM is in D1 and accessible by all system masters except BDMA. */ /* - Suitable for application data not stored in DTCM. */ /* - Zero wait-states. */ /* - The 192k of extra shared RAM is fully allotted to the AXI SRAM by default. */ - /* This results in: 64k for ITCM and 320k (128k + 192k) for AXI SRAM. */ + /* As a result: 64k (64k + 0k) for ITCM and 320k (128k + 192k) for AXI SRAM. */ /* This can be re-configured via the TCM_AXI_SHARED[1,0] register when more */ /* ITCM is required. */ - AXISRAM : ORIGIN = 0x24000000, LENGTH = 320K + AXISRAM : ORIGIN = 0x24000000, LENGTH = 128K + 192K /* AHB SRAM */ /* - SRAM1-2 are in D2 and accessible by all system masters except BDMA, LTDC */ From ba6cabca6f8b01a52bd867d9db4d5012383fa44c Mon Sep 17 00:00:00 2001 From: Tom De Rybel Date: Mon, 20 Dec 2021 11:28:36 +0100 Subject: [PATCH 4/4] Added documentation on how to use the family-specific memory.x files. --- README.md | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/README.md b/README.md index 8b1df11f..3b6b7d86 100644 --- a/README.md +++ b/README.md @@ -28,13 +28,13 @@ Collaboration on this crate is highly welcome, as are pull requests! Supported Configurations ------------------------ -* __stm32h743v__ (Revision V: stm32h743, stm32h742, stm32h750) -* __stm32h753v__ -* __stm32h747cm7__ (stm32h747, stm32h757) -* __stm32h7b3__ -* __stm32h7b0__ +* __stm32h743v__ (Revision V: stm32h742, stm32h743, stm32h750) +* __stm32h753v__ (Revision V: stm32h753 +* __stm32h747cm7__ (stm32h745, stm32h747, stm32h755, stm32h757) * __stm32h7a3__ -* __stm32h735__ (stm32h725, stm32h735) +* __stm32h7b0__ +* __stm32h7b3__ +* __stm32h735__ (stm32h723, stm32h725, stm32h730, stm32h733, stm32h735) #### Old revision STM32H742/743/750/753 parts @@ -46,8 +46,37 @@ revision (Revision Y) are supported by feature gates without the 'v' suffix. (__stm32h743__, __stm32h753__) #### Dual core parts (Cortex M7 + Cortex M4) + On dual core parts, currently only the Cortex M7 core is supported. +#### Family-specific memory.x + +Each H7 device family has a somewhat different memory layout. To make starting +a project easier, a specific example memory.x file is included for each family. +You can use these to replace the memory.x included in this crate for the examples. + +The memory layout for each device family is specified in their respective +reference manual (RM). The table below relates the various parts to their +applicable memory.x and reference manual. + +RM | memory.x | Applicable devices +-------|------------------------------|---------------------------------------- +RM0399 | memory_745_747_755_757.x | stm32h745, stm32h747, stm32h755, stm32h757 +RM0433 | memory_742.x | stm32h742 +RM0433 | memory_743_750_753.x | stm32h743, stm32h750, stm32h753 +RM0455 | memory_7A3_7B0_7B3.x | stm32h7a3, stm32h7b0, stm32h7b3 +RM0468 | memory_723_725_730_733_735.x | stm32h723, stm32h725, stm32h730, stm32h733, stm32h735 + +To use these files, substitute memory.x by the applicable one and update the +flash memory size as indicated below. + +⚠️: If you use [flip-link](https://github.com/knurling-rs/flip-link) for stack +overflow protection, there is one more change to make. Flip-link does not (yet) +support the use of region aliases and expects an entry called RAM in the MEMORY +block. The work-around is to comment-out the "REGION_ALIAS(RAM, DTCM)" line and +manually substitute the RAM label in the respective MEMORY entry. Eg: replace +DTCM by RAM. + #### Flash memory size By default this crate assumes a 2Mbyte flash size. To set a smaller limit for