diff --git a/src/crc.rs b/src/crc.rs index b6253235..867e1168 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -37,7 +37,6 @@ impl Crc { // manual says unit must be reset (or DR read) before change of polynomial // (technically only in case of ongoing calculation, but DR is buffered) - //NOTE(unsafe) Only valid bit patterns are written self.reg.cr().modify(|_, w| { w.polysize() .set(config.poly.polysize()) @@ -124,7 +123,6 @@ impl Crc { /// /// The IDR is not involved with CRC calculation. pub fn set_idr(&mut self, value: u32) { - //NOTE(unsafe) All bit patterns are valid self.reg.idr().write(|w| w.idr().set(value)); } diff --git a/src/dma/bdma.rs b/src/dma/bdma.rs index 695da7c3..a0e40df3 100644 --- a/src/dma/bdma.rs +++ b/src/dma/bdma.rs @@ -353,7 +353,6 @@ where #[inline(always)] fn set_priority(&mut self, priority: config::Priority) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -464,7 +463,6 @@ where #[inline(always)] fn set_number_of_transfers(&mut self, value: u16) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) All bit patterns are valid for ndt unsafe { Self::stream().ndtr().write(|w| w.ndt().set(value)); } diff --git a/src/dma/dma.rs b/src/dma/dma.rs index 2140ca9c..a37224fb 100644 --- a/src/dma/dma.rs +++ b/src/dma/dma.rs @@ -352,7 +352,6 @@ impl StreamX { #[inline(always)] fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .fcr() @@ -372,7 +371,6 @@ impl StreamX { #[inline(always)] fn set_memory_burst(&mut self, memory_burst: config::BurstMode) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -383,7 +381,6 @@ impl StreamX { #[inline(always)] fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -514,7 +511,6 @@ where #[inline(always)] fn set_priority(&mut self, priority: config::Priority) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) We only write valid bit patterns unsafe { Self::stream() .cr() @@ -643,7 +639,6 @@ where #[inline(always)] fn set_number_of_transfers(&mut self, value: u16) { //NOTE(unsafe) We only access the registers that belongs to the StreamX - //NOTE(unsafe) All bit pattern for ndt are valid unsafe { Self::stream().ndtr().write(|w| w.ndt().set(value)); } diff --git a/src/rcc/rec.rs b/src/rcc/rec.rs index 2b5ebf9b..9de147de 100644 --- a/src/rcc/rec.rs +++ b/src/rcc/rec.rs @@ -76,8 +76,6 @@ use super::Rcc; use crate::stm32::{rcc, RCC}; use cortex_m::interrupt; -//const X: stm32h7::stm32h743v::rcc::d1ccipr::FMCSEL = (); - /// A trait for Resetting, Enabling and Disabling a single peripheral pub trait ResetEnable { /// Enable this peripheral diff --git a/src/rtc.rs b/src/rtc.rs index 6a8fb707..70ca8d39 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -230,7 +230,6 @@ impl Rtc { "Invalid RTC prescaler value" ); - //NOTE(unsafe) Only valid bit patterns are writte, values are checked above rtc.prer().write(|w| { w.prediv_s() .set(u16(s_pre - 1).unwrap()) @@ -259,7 +258,6 @@ impl Rtc { /// /// Panics if `reg` is greater than 31. pub fn write_backup_reg(&mut self, reg: u8, value: u32) { - //NOTE(unsafe) All bit patterns are valid self.reg.bkpr(reg as usize).write(|w| w.bkp().set(value)); } @@ -286,7 +284,6 @@ impl Rtc { let st = second / 10; let su = second % 10; - //NOTE(unsafe) Only valid bit patterns are written self.reg.tr().write(|w| { w.pm() .clear_bit() diff --git a/src/system_watchdog.rs b/src/system_watchdog.rs index a568d0fb..170d037e 100644 --- a/src/system_watchdog.rs +++ b/src/system_watchdog.rs @@ -162,9 +162,7 @@ impl WatchdogEnable for SystemWindowWatchdog { // write the config values, matching the set timeout the most self.wwdg.cfr().modify(|_, w| w.wdgtb().set(wdgtb)); - self.wwdg.cfr().modify(|_, w| w.w().set(self.down_counter)); - self.wwdg.cr().modify(|_, w| w.t().set(self.down_counter)); // For some reason, setting the t value makes the early wakeup pending. // That's bad behaviour, so lets turn it off again. diff --git a/src/timer.rs b/src/timer.rs index 766fab2c..6bfdfd2e 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -116,7 +116,7 @@ impl GetClk for LPTIM3 { // unsafe: read only let srdccipr = &unsafe { &*stm32::RCC::ptr() }.srdccipr(); - match srdccipr.read().lptim3sel().set() { + match srdccipr.read().lptim3sel().bits() { 0 => Some(clocks.pclk4()), 1 => clocks.pll2_p_ck(), 2 => clocks.pll3_r_ck(), @@ -452,7 +452,6 @@ macro_rules! hal { let div = self.clk / frequency.raw(); let psc = u16(div - 1).unwrap(); - //NOTE(unsafe) All bit patterns are valid self.tim.psc().write(|w| w.psc().set(psc)); let counter_max = u32(<$cntType>::MAX);