From 6ed4d9494a560de0a889dac3d60ce5c7097294f8 Mon Sep 17 00:00:00 2001 From: Diego Barrios Romero Date: Sun, 26 Jul 2020 13:03:23 +0200 Subject: [PATCH] Adapt to embedded-hal 1.0.0-alpha.1 --- Cargo.toml | 11 +++---- examples/adc.rs | 2 +- examples/adc12.rs | 4 +-- examples/blinky.rs | 10 +++---- examples/blinky_random.rs | 6 ++-- examples/blinky_timer.rs | 14 ++++----- examples/dac.rs | 2 +- examples/i2c.rs | 2 +- examples/pwm.rs | 12 ++++---- examples/rtic.rs | 4 +-- examples/rtic_timers.rs | 10 +++---- examples/serial.rs | 4 +-- examples/spi.rs | 6 ++-- examples/temperature.rs | 7 +++-- examples/watchdog.rs | 2 +- src/adc.rs | 14 ++++----- src/dac.rs | 2 +- src/delay.rs | 30 ++++++++++++------- src/gpio.rs | 62 +++++++++++++++++++-------------------- src/i2c.rs | 6 ++-- src/lib.rs | 3 -- src/pwm.rs | 41 ++++++++++++++++---------- src/pwr.rs | 4 +-- src/qei.rs | 17 ++++++----- src/rng.rs | 2 +- src/sai/pdm.rs | 6 ++-- src/serial.rs | 31 +++++++++++--------- src/spi.rs | 4 +-- src/timer.rs | 13 ++++---- src/watchdog.rs | 9 ++++-- 30 files changed, 181 insertions(+), 159 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index a385ed6cc..89af398ad 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,18 +22,16 @@ features = ["stm32h743", "rt"] targets = ["thumbv7em-none-eabihf"] [dependencies] -embedded-hal = "0.2.4" +embedded-hal = "=1.0.0-alpha.1" cortex-m = "^0.6.2" cortex-m-rt = "^0.6.12" stm32h7 = "0.11.0" -void = { version = "1.0.2", default-features = false } cast = { version = "0.2.3", default-features = false } -nb = "0.1.2" +nb = "1" paste = "0.1.18" [dependencies.bare-metal] -version = "0.2.5" -features = ["const-fn"] +version = "1" [dev-dependencies] panic-itm = "~0.4.1" @@ -41,8 +39,6 @@ cortex-m-rtic = "0.5.3" cortex-m-log = { version = "~0.6", features = ["itm"] } [features] -default = ["unproven"] -unproven = ["embedded-hal/unproven"] device-selected = [] revision_v = [] singlecore = [] @@ -89,3 +85,4 @@ required-features = ["revision_v"] [[example]] name = "qspi" required-features = ["quadspi"] + diff --git a/examples/adc.rs b/examples/adc.rs index 2bdd98b2e..5b4c6a9fb 100644 --- a/examples/adc.rs +++ b/examples/adc.rs @@ -73,7 +73,7 @@ fn main() -> ! { let mut channel = gpioc.pc0.into_analog(); // ANALOG IN 10 loop { - let data: u32 = adc1.read(&mut channel).unwrap(); + let data: u32 = adc1.try_read(&mut channel).unwrap(); // voltage = reading * (vref/resolution) println!( log, diff --git a/examples/adc12.rs b/examples/adc12.rs index 9bd204867..540ddaedb 100644 --- a/examples/adc12.rs +++ b/examples/adc12.rs @@ -67,8 +67,8 @@ fn main() -> ! { let mut channel_pc3 = gpioc.pc3.into_analog(); // AIN 13 loop { - let data_pc2: u32 = adc1.read(&mut channel_pc2).unwrap(); - let data_pc3: u32 = adc2.read(&mut channel_pc3).unwrap(); + let data_pc2: u32 = adc1.try_read(&mut channel_pc2).unwrap(); + let data_pc3: u32 = adc2.try_read(&mut channel_pc3).unwrap(); // voltage = reading * (vref/resolution) println!(log, "ADC readings: {} {}", data_pc2, data_pc3); } diff --git a/examples/blinky.rs b/examples/blinky.rs index 0e1c6a01f..3232ea6be 100644 --- a/examples/blinky.rs +++ b/examples/blinky.rs @@ -6,7 +6,7 @@ extern crate panic_itm; use cortex_m_rt::entry; -use stm32h7xx_hal::hal::digital::v2::OutputPin; +use stm32h7xx_hal::hal::digital::OutputPin; use stm32h7xx_hal::{pac, prelude::*}; use cortex_m_log::println; @@ -44,11 +44,11 @@ fn main() -> ! { loop { loop { - led.set_high().unwrap(); - delay.delay_ms(500_u16); + led.try_set_high().unwrap(); + delay.try_delay_ms(500_u16).unwrap(); - led.set_low().unwrap(); - delay.delay_ms(500_u16); + led.try_set_low().unwrap(); + delay.try_delay_ms(500_u16).unwrap(); } } } diff --git a/examples/blinky_random.rs b/examples/blinky_random.rs index d9f72c2e2..1ffc6db13 100644 --- a/examples/blinky_random.rs +++ b/examples/blinky_random.rs @@ -6,7 +6,7 @@ extern crate panic_itm; use cortex_m_rt::entry; -use stm32h7xx_hal::hal::digital::v2::ToggleableOutputPin; +use stm32h7xx_hal::hal::digital::ToggleableOutputPin; use stm32h7xx_hal::{pac, prelude::*}; use cortex_m_log::println; @@ -61,8 +61,8 @@ fn main() -> ! { // acceptable for your application. let period = random % 200_u32; - led.toggle().unwrap(); - delay.delay_ms(period); + led.try_toggle().unwrap(); + delay.try_delay_ms(period).unwrap(); } Err(err) => println!(log, "RNG error: {:?}", err), } diff --git a/examples/blinky_timer.rs b/examples/blinky_timer.rs index 51cadf6e7..a4bd6bf84 100644 --- a/examples/blinky_timer.rs +++ b/examples/blinky_timer.rs @@ -9,7 +9,7 @@ extern crate panic_itm; extern crate nb; use cortex_m_rt::entry; -use stm32h7xx_hal::hal::digital::v2::{OutputPin, ToggleableOutputPin}; +use stm32h7xx_hal::hal::digital::{OutputPin, ToggleableOutputPin}; use stm32h7xx_hal::{pac, prelude::*}; use cortex_m_log::println; @@ -41,7 +41,7 @@ fn main() -> ! { // Configure PE1 as output. let mut led = gpioe.pe1.into_push_pull_output(); - led.set_low().unwrap(); + led.try_set_low().unwrap(); // Get the delay provider. let mut delay = cp.SYST.delay(ccdr.clocks); @@ -52,14 +52,14 @@ fn main() -> ! { loop { for _ in 0..5 { // 20ms wait with timer - led.toggle().unwrap(); - timer.start(20.ms()); - block!(timer.wait()).ok(); + led.try_toggle().unwrap(); + timer.try_start(20.ms()).unwrap(); + block!(timer.try_wait()).ok(); // Delay for 500ms. Timer must operate correctly on next // use. - led.toggle().unwrap(); - delay.delay_ms(500_u16); + led.try_toggle().unwrap(); + delay.try_delay_ms(500_u16).unwrap(); } } } diff --git a/examples/dac.rs b/examples/dac.rs index 75b684248..e7502c921 100644 --- a/examples/dac.rs +++ b/examples/dac.rs @@ -7,7 +7,7 @@ extern crate panic_itm; use cortex_m::asm; use cortex_m_rt::entry; -use stm32h7xx_hal::hal::Direction; +use stm32h7xx_hal::hal::qei::Direction; use stm32h7xx_hal::{pac, prelude::*}; use stm32h7xx_hal::traits::DacOut; diff --git a/examples/i2c.rs b/examples/i2c.rs index c822c6d14..1e45e7448 100644 --- a/examples/i2c.rs +++ b/examples/i2c.rs @@ -41,6 +41,6 @@ fn main() -> ! { let mut buf = [0x60]; loop { buf[0] = 0x11; - i2c.write_read(0x76, &buf.clone(), &mut buf).unwrap(); + i2c.try_write_read(0x76, &buf.clone(), &mut buf).unwrap(); } } diff --git a/examples/pwm.rs b/examples/pwm.rs index c494e731d..556eccb20 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -51,23 +51,23 @@ fn main() -> ! { .pwm(pins, 10.khz(), ccdr.peripheral.TIM1, &ccdr.clocks); // Output PWM on PA8 - let max = pwm.get_max_duty(); - pwm.set_duty(max / 2); + let max = pwm.try_get_max_duty().unwrap(); + pwm.try_set_duty(max / 2).unwrap(); println!(log, "50%"); - pwm.enable(); + pwm.try_enable().unwrap(); asm::bkpt(); println!(log, "25%"); - pwm.set_duty(max / 4); + pwm.try_set_duty(max / 4).unwrap(); asm::bkpt(); println!(log, "12.5%"); - pwm.set_duty(max / 8); + pwm.try_set_duty(max / 8).unwrap(); asm::bkpt(); println!(log, "100%"); - pwm.set_duty(max); + pwm.try_set_duty(max).unwrap(); asm::bkpt(); loop {} diff --git a/examples/rtic.rs b/examples/rtic.rs index 918ed1216..ebd6b8be2 100644 --- a/examples/rtic.rs +++ b/examples/rtic.rs @@ -6,7 +6,7 @@ extern crate panic_itm; extern crate rtic; -use stm32h7xx_hal::hal::digital::v2::ToggleableOutputPin; +use stm32h7xx_hal::hal::digital::ToggleableOutputPin; use rtic::app; use stm32h7xx_hal::gpio::{gpioc::PC13, gpioi::PI13}; @@ -52,6 +52,6 @@ const APP: () = { #[task(binds = EXTI15_10, resources = [button, led])] fn button_click(ctx: button_click::Context) { ctx.resources.button.clear_interrupt_pending_bit(); - ctx.resources.led.toggle().unwrap(); + ctx.resources.led.try_toggle().unwrap(); } }; diff --git a/examples/rtic_timers.rs b/examples/rtic_timers.rs index 61c88b6e0..9178d7efb 100644 --- a/examples/rtic_timers.rs +++ b/examples/rtic_timers.rs @@ -7,7 +7,7 @@ extern crate panic_itm; extern crate rtic; -use stm32h7xx_hal::hal::digital::v2::ToggleableOutputPin; +use stm32h7xx_hal::hal::digital::ToggleableOutputPin; use rtic::app; use stm32h7xx_hal::gpio::gpioi::{PI12, PI13, PI14, PI15}; @@ -86,24 +86,24 @@ const APP: () = { #[task(binds = TIM1_UP, resources = [led1, timer1])] fn timer1_tick(ctx: timer1_tick::Context) { ctx.resources.timer1.clear_irq(); - ctx.resources.led1.toggle().unwrap(); + ctx.resources.led1.try_toggle().unwrap(); } #[task(binds = TIM2, resources = [led2, timer2])] fn timer2_tick(ctx: timer2_tick::Context) { ctx.resources.timer2.clear_irq(); - ctx.resources.led2.toggle().unwrap(); + ctx.resources.led2.try_toggle().unwrap(); } #[task(binds = TIM8_BRK_TIM12, resources = [led3, timer3])] fn timer3_tick(ctx: timer3_tick::Context) { ctx.resources.timer3.clear_irq(); - ctx.resources.led3.toggle().unwrap(); + ctx.resources.led3.try_toggle().unwrap(); } #[task(binds = TIM17, resources = [led4, timer4])] fn timer4_tick(ctx: timer4_tick::Context) { ctx.resources.timer4.clear_irq(); - ctx.resources.led4.toggle().unwrap(); + ctx.resources.led4.try_toggle().unwrap(); } }; diff --git a/examples/serial.rs b/examples/serial.rs index 362d120c6..974a57f6e 100644 --- a/examples/serial.rs +++ b/examples/serial.rs @@ -62,7 +62,7 @@ fn main() -> ! { loop { // Echo what is received on the serial link. - let received = block!(rx.read()).unwrap(); - block!(tx.write(received)).ok(); + let received = block!(rx.try_read()).unwrap(); + block!(tx.try_write(received)).ok(); } } diff --git a/examples/spi.rs b/examples/spi.rs index b0c707de7..2a58d3af2 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -56,12 +56,12 @@ fn main() -> ! { ); // Write fixed data - spi.write(&[0x11u8, 0x22, 0x33]).unwrap(); + spi.try_write(&[0x11u8, 0x22, 0x33]).unwrap(); // Echo what is received on the SPI let mut received = 0; loop { - block!(spi.send(received)).ok(); - received = block!(spi.read()).unwrap(); + block!(spi.try_send(received)).ok(); + received = block!(spi.try_read()).unwrap(); } } diff --git a/examples/temperature.rs b/examples/temperature.rs index 5bd94f8b7..4d44070b2 100644 --- a/examples/temperature.rs +++ b/examples/temperature.rs @@ -58,14 +58,15 @@ fn main() -> ! { // Setup Temperature Sensor on the disabled ADC let mut channel = adc::Temperature::new(); channel.enable(&adc3); - delay.delay_us(25_u16); + delay.try_delay_us(25_u16).unwrap(); let mut adc3 = adc3.enable(); let vdda = 2.500; // Volts loop { - let word: u32 = - adc3.read(&mut channel).expect("Temperature read failed."); + let word: u32 = adc3 + .try_read(&mut channel) + .expect("Temperature read failed."); // Average slope let cal = (110.0 - 30.0) diff --git a/examples/watchdog.rs b/examples/watchdog.rs index 58a8ff1c1..4e7eeb363 100644 --- a/examples/watchdog.rs +++ b/examples/watchdog.rs @@ -46,7 +46,7 @@ fn main() -> ! { // Enable the watchdog with a limit of 100 ms and wait forever // -> restart the chip - watchdog.start(100.ms()); + watchdog.try_start(100.ms()).unwrap(); loop {} } diff --git a/src/adc.rs b/src/adc.rs index 5661189dc..bea8c6ee7 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -6,6 +6,7 @@ use crate::hal::adc::{Channel, OneShot}; use crate::hal::blocking::delay::DelayUs; +use core::convert::Infallible; use core::marker::PhantomData; use crate::stm32::{ADC1, ADC2, ADC3, ADC3_COMMON}; @@ -159,10 +160,7 @@ macro_rules! adc_pins { $( impl Channel<$ADC> for $input { type ID = u8; - - fn channel() -> u8 { - $chan - } + const CHANNEL: Self::ID = $chan; } )+ }; @@ -438,7 +436,7 @@ macro_rules! adc_hal { w.deeppwd().clear_bit() .advregen().set_bit() ); - delay.delay_us(10_u8); + delay.try_delay_us(10_u8).unwrap(); // infallible } /// Enables Deeppowerdown-mode and disables voltage regulator @@ -768,10 +766,10 @@ macro_rules! adc_hal { WORD: From, PIN: Channel<$ADC, ID = u8>, { - type Error = (); + type Error = Infallible; - fn read(&mut self, _pin: &mut PIN) -> nb::Result { - let res = self.convert(PIN::channel()); + fn try_read(&mut self, _pin: &mut PIN) -> nb::Result { + let res = self.convert(PIN::CHANNEL); Ok(res.into()) } } diff --git a/src/dac.rs b/src/dac.rs index 293b001a0..7a2a9e7e2 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -109,7 +109,7 @@ macro_rules! dac { let mut trim = 0; while true { dac.ccr.modify(|_, w| unsafe { w.$trim().bits(trim) }); - delay.delay_us(64_u32); + delay.try_delay_us(64_u32).ok(); // infallible if dac.sr.read().$cal_flag().bit() { break; } diff --git a/src/delay.rs b/src/delay.rs index 155341b32..a6977e21c 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -1,6 +1,7 @@ //! Delays use cast::u32; +use core::convert::Infallible; use cortex_m::peripheral::syst::SystClkSource; use cortex_m::peripheral::SYST; @@ -38,25 +39,29 @@ impl Delay { } impl DelayMs for Delay { - fn delay_ms(&mut self, ms: u32) { - self.delay_us(ms * 1_000); + type Error = Infallible; + fn try_delay_ms(&mut self, ms: u32) -> Result<(), Self::Error> { + self.try_delay_us(ms * 1_000) } } impl DelayMs for Delay { - fn delay_ms(&mut self, ms: u16) { - self.delay_ms(u32(ms)); + type Error = Infallible; + fn try_delay_ms(&mut self, ms: u16) -> Result<(), Self::Error> { + self.try_delay_ms(u32(ms)) } } impl DelayMs for Delay { - fn delay_ms(&mut self, ms: u8) { - self.delay_ms(u32(ms)); + type Error = Infallible; + fn try_delay_ms(&mut self, ms: u8) -> Result<(), Self::Error> { + self.try_delay_ms(u32(ms)) } } impl DelayUs for Delay { - fn delay_us(&mut self, us: u32) { + type Error = Infallible; + fn try_delay_us(&mut self, us: u32) -> Result<(), Self::Error> { // The SysTick Reload Value register supports values between 1 and 0x00FFFFFF. const MAX_RVR: u32 = 0x00FF_FFFF; @@ -93,17 +98,20 @@ impl DelayUs for Delay { self.syst.disable_counter(); } + Ok(()) } } impl DelayUs for Delay { - fn delay_us(&mut self, us: u16) { - self.delay_us(u32(us)) + type Error = Infallible; + fn try_delay_us(&mut self, us: u16) -> Result<(), Self::Error> { + self.try_delay_us(u32(us)) } } impl DelayUs for Delay { - fn delay_us(&mut self, us: u8) { - self.delay_us(u32(us)) + type Error = Infallible; + fn try_delay_us(&mut self, us: u8) -> Result<(), Self::Error> { + self.try_delay_us(u32(us)) } } diff --git a/src/gpio.rs b/src/gpio.rs index e1b597394..13f87322b 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -112,8 +112,8 @@ macro_rules! gpio { pub mod $gpiox { use core::marker::PhantomData; - use embedded_hal::digital::v2::{InputPin, OutputPin, - StatefulOutputPin, toggleable}; + use embedded_hal::digital::{InputPin, OutputPin, + StatefulOutputPin, toggleable}; use crate::rcc::{rec, ResetEnable}; use crate::stm32::$GPIOX; @@ -124,7 +124,7 @@ macro_rules! gpio { AF2, AF3, AF4, AF5, AF6, AF7, AF8, AF9, AF10, AF11, AF12, AF13, AF14, AF15, Analog, Edge, ExtiPin, }; - use crate::Never; + use core::convert::Infallible; /// GPIO parts pub struct Parts { @@ -162,9 +162,9 @@ macro_rules! gpio { } impl OutputPin for $PXx> { - type Error = Never; + type Error = Infallible; - fn set_high(&mut self) -> Result<(), Never> { + fn try_set_high(&mut self) -> Result<(), Infallible> { // NOTE(unsafe) atomic write to a stateless // register unsafe { (*$GPIOX::ptr()).bsrr @@ -173,7 +173,7 @@ macro_rules! gpio { Ok(()) } - fn set_low(&mut self) -> Result<(), Never> { + fn try_set_low(&mut self) -> Result<(), Infallible> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*$GPIOX::ptr()).bsrr .write(|w| w.bits(1 << (self.i + 16))) } @@ -183,11 +183,11 @@ macro_rules! gpio { } impl StatefulOutputPin for $PXx> { - fn is_set_high(&self) -> Result { - self.is_set_low().map(|v| !v) + fn try_is_set_high(&self) -> Result { + self.try_is_set_low().map(|v| !v) } - fn is_set_low(&self) -> Result { + fn try_is_set_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).odr .read().bits() & (1 << self.i) } == 0) @@ -197,13 +197,13 @@ macro_rules! gpio { impl toggleable::Default for $PXx> {} impl InputPin for $PXx> { - type Error = Never; + type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr .read().bits() & (1 << self.i) } == 0) @@ -211,13 +211,13 @@ macro_rules! gpio { } impl InputPin for $PXx> { - type Error = Never; + type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr .read().bits() & (1 << self.i) } == 0) @@ -626,9 +626,9 @@ macro_rules! gpio { } impl OutputPin for $PXi> { - type Error = Never; + type Error = Infallible; - fn set_high(&mut self) -> Result<(), Never> { + fn try_set_high(&mut self) -> Result<(), Infallible> { // NOTE(unsafe) atomic write to a stateless // register unsafe { (*$GPIOX::ptr()).bsrr @@ -637,7 +637,7 @@ macro_rules! gpio { Ok(()) } - fn set_low(&mut self) -> Result<(), Never> { + fn try_set_low(&mut self) -> Result<(), Infallible> { // NOTE(unsafe) atomic write to a stateless // register unsafe { (*$GPIOX::ptr()).bsrr @@ -648,11 +648,11 @@ macro_rules! gpio { } impl StatefulOutputPin for $PXi> { - fn is_set_high(&self) -> Result { - self.is_set_low().map(|v| !v) + fn try_is_set_high(&self) -> Result { + self.try_is_set_low().map(|v| !v) } - fn is_set_low(&self) -> Result { + fn try_is_set_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).odr .read().bits() & (1 << $i) } == 0) @@ -662,13 +662,13 @@ macro_rules! gpio { impl toggleable::Default for $PXi> {} impl InputPin for $PXi> { - type Error = Never; + type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr .read().bits() & (1 << $i) } == 0) @@ -676,13 +676,13 @@ macro_rules! gpio { } impl InputPin for $PXi> { - type Error = Never; + type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr .read().bits() & (1 << $i) } == 0) diff --git a/src/i2c.rs b/src/i2c.rs index 25ef4d226..9f12979d4 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -325,7 +325,7 @@ macro_rules! i2c { impl Write for I2c<$I2CX> { type Error = Error; - fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> { + fn try_write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> { // TODO support transfers of more than 255 bytes assert!(bytes.len() < 256 && bytes.len() > 0); @@ -369,7 +369,7 @@ macro_rules! i2c { impl WriteRead for I2c<$I2CX> { type Error = Error; - fn write_read( + fn try_write_read( &mut self, addr: u8, bytes: &[u8], @@ -444,7 +444,7 @@ macro_rules! i2c { impl Read for I2c<$I2CX> { type Error = Error; - fn read( + fn try_read( &mut self, addr: u8, buffer: &mut [u8], diff --git a/src/lib.rs b/src/lib.rs index 323a492b5..7bde6c891 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -40,9 +40,6 @@ extern crate paste; -#[derive(Debug)] -pub enum Never {} - #[cfg(not(feature = "device-selected"))] compile_error!( "This crate requires one of the following device features enabled: diff --git a/src/pwm.rs b/src/pwm.rs index 01a33fdff..37eb0ce22 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -39,6 +39,7 @@ //! c0.enable() //! ``` //! +use core::convert::Infallible; use core::marker::PhantomData; use core::mem::MaybeUninit; @@ -554,19 +555,21 @@ macro_rules! tim_pin_hal { $ccrx:ident, $typ:ident),)+ ) => { $( - impl hal::PwmPin for Pwm<$TIMX, $CH> { + impl hal::pwm::PwmPin for Pwm<$TIMX, $CH> { type Duty = $typ; + type Error = Infallible; // You may not access self in the following methods! // See unsafe above - fn disable(&mut self) { + fn try_disable(&mut self) -> Result<(), Self::Error> { let tim = unsafe { &*$TIMX::ptr() }; tim.ccer.modify(|_, w| w.$ccxe().clear_bit()); + Ok(()) } - fn enable(&mut self) { + fn try_enable(&mut self) -> Result<(), Self::Error> { let tim = unsafe { &*$TIMX::ptr() }; tim.$ccmrx_output().modify(|_, w| @@ -576,24 +579,26 @@ macro_rules! tim_pin_hal { .pwm_mode1() // PWM Mode ); tim.ccer.modify(|_, w| w.$ccxe().set_bit()); + Ok(()) } - fn get_duty(&self) -> Self::Duty { + fn try_get_duty(&self) -> Result { let tim = unsafe { &*$TIMX::ptr() }; - tim.$ccrx.read().ccr().bits() + Ok(tim.$ccrx.read().ccr().bits()) } - fn get_max_duty(&self) -> Self::Duty { + fn try_get_max_duty(&self) -> Result { let tim = unsafe { &*$TIMX::ptr() }; - tim.arr.read().arr().bits() + Ok(tim.arr.read().arr().bits()) } - fn set_duty(&mut self, duty: Self::Duty) { + fn try_set_duty(&mut self, duty: Self::Duty) -> Result<(), Self::Error> { let tim = unsafe { &*$TIMX::ptr() }; tim.$ccrx.write(|w| w.ccr().bits(duty)); + Ok(()) } } )+ @@ -695,44 +700,48 @@ macro_rules! lptim_hal { unsafe { MaybeUninit::::uninit().assume_init() } } - impl hal::PwmPin for Pwm<$TIMX, C1> { + impl hal::pwm::PwmPin for Pwm<$TIMX, C1> { type Duty = u16; + type Error = Infallible; // You may not access self in the following methods! // See unsafe above - fn disable(&mut self) { + fn try_disable(&mut self) -> Result<(), Self::Error>{ let tim = unsafe { &*$TIMX::ptr() }; // LPTIM only has one output, so we disable the // entire timer tim.cr.modify(|_, w| w.enable().disabled()); + Ok(()) } - fn enable(&mut self) { + fn try_enable(&mut self) -> Result<(), Self::Error>{ let tim = unsafe { &*$TIMX::ptr() }; tim.cr.modify(|_, w| w.cntstrt().start().enable().enabled()); + Ok(()) } - fn get_duty(&self) -> u16 { + fn try_get_duty(&self) -> Result{ let tim = unsafe { &*$TIMX::ptr() }; - tim.cmp.read().cmp().bits() + Ok(tim.cmp.read().cmp().bits()) } - fn get_max_duty(&self) -> u16 { + fn try_get_max_duty(&self)-> Result { let tim = unsafe { &*$TIMX::ptr() }; - tim.arr.read().arr().bits() + Ok(tim.arr.read().arr().bits()) } - fn set_duty(&mut self, duty: u16) { + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { let tim = unsafe { &*$TIMX::ptr() }; tim.cmp.write(|w| w.cmp().bits(duty)); while !tim.isr.read().cmpok().is_set() {} tim.icr.write(|w| w.cmpokcf().clear()); + Ok(()) } } )+ diff --git a/src/pwr.rs b/src/pwr.rs index 49d3bc453..b161a7a75 100644 --- a/src/pwr.rs +++ b/src/pwr.rs @@ -249,7 +249,7 @@ impl Pwr { // Enable overdrive for maximum clock // Syscfgen required to set enable overdrive - #[cfg(feature = "revision_v")] + /*#[cfg(feature = "revision_v")] if self.enable_vos0 { unsafe { &(*RCC::ptr()).apb4enr.modify(|_, w| w.syscfgen().enabled()) @@ -264,7 +264,7 @@ impl Pwr { }; while self.rb.d3cr.read().vosrdy().bit_is_clear() {} return VoltageScale::Scale0; - } + }*/ VoltageScale::Scale1 } diff --git a/src/qei.rs b/src/qei.rs index 4d28dcf9d..5b055314b 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -1,6 +1,8 @@ //! # Quadrature Encoder Interface -use crate::hal::{self, Direction}; + +use crate::hal::{self, qei::Direction}; use crate::rcc::{rec, ResetEnable}; +use core::convert::Infallible; use crate::gpio::gpioa::{PA0, PA1, PA15, PA5, PA6, PA7, PA8, PA9}; use crate::gpio::gpiob::{PB0, PB13, PB14, PB3, PB4, PB5, PB6, PB7}; @@ -207,18 +209,19 @@ macro_rules! tim_hal { } } - impl hal::Qei for Qei<$TIM> { + impl hal::qei::Qei for Qei<$TIM> { type Count = $bits; + type Error = Infallible; - fn count(&self) -> $bits { - self.tim.cnt.read().bits() as $bits + fn try_count(&self) -> Result<$bits, Self::Error> { + Ok(self.tim.cnt.read().bits() as $bits) } - fn direction(&self) -> Direction { + fn try_direction(&self) -> Result { if self.tim.cr1.read().dir().bit_is_clear() { - hal::Direction::Upcounting + Ok(Direction::Upcounting) } else { - hal::Direction::Downcounting + Ok(Direction::Downcounting) } } } diff --git a/src/rng.rs b/src/rng.rs index 98789d94e..01a74fb37 100644 --- a/src/rng.rs +++ b/src/rng.rs @@ -86,7 +86,7 @@ impl Rng { impl rng::Read for Rng { type Error = ErrorKind; - fn read(&mut self, buffer: &mut [u8]) -> Result<(), Self::Error> { + fn try_read(&mut self, buffer: &mut [u8]) -> Result<(), Self::Error> { self.fill(buffer) } } diff --git a/src/sai/pdm.rs b/src/sai/pdm.rs index 60875fa2d..7c2355e1c 100644 --- a/src/sai/pdm.rs +++ b/src/sai/pdm.rs @@ -15,15 +15,13 @@ //! let _ = block!(sai.read_data()).unwrap(); //! ``` -use core::convert::TryInto; +use core::convert::{Infallible, TryInto}; use crate::rcc::{rec, CoreClocks, ResetEnable}; use crate::sai::{GetClkSAI, Sai, SaiChannel, INTERFACE}; use crate::stm32::{SAI1, SAI4}; use crate::time::Hertz; -use crate::Never; - use crate::gpio::gpiob::PB2; use crate::gpio::gpioc::{PC1, PC5}; use crate::gpio::gpiod::PD6; @@ -196,7 +194,7 @@ macro_rules! hal { } impl Sai<$SAIX, PDM> { /// Read a single data word (one 'slot') - pub fn read_data(&mut self) -> nb::Result { + pub fn read_data(&mut self) -> nb::Result { while self.interface.invalid_countdown > 0 { // Check for words to read if self.rb.cha.sr.read().freq().bit_is_clear() { diff --git a/src/serial.rs b/src/serial.rs index 47efdb333..131710965 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -1,5 +1,6 @@ //! Serial +use core::convert::Infallible; use core::fmt; use core::marker::PhantomData; use core::ptr; @@ -36,8 +37,6 @@ use crate::gpio::{Alternate, AF11, AF14, AF4, AF6, AF7, AF8}; use crate::rcc::{rec, CoreClocks, ResetEnable}; use crate::time::Hertz; -use crate::Never; - /// Serial error #[derive(Debug)] pub enum Error { @@ -546,18 +545,18 @@ macro_rules! usart { impl serial::Read for Serial<$USARTX> { type Error = Error; - fn read(&mut self) -> nb::Result { + fn try_read(&mut self) -> nb::Result { let mut rx: Rx<$USARTX> = Rx { _usart: PhantomData, }; - rx.read() + rx.try_read() } } impl serial::Read for Rx<$USARTX> { type Error = Error; - fn read(&mut self) -> nb::Result { + fn try_read(&mut self) -> nb::Result { // NOTE(unsafe) atomic read with no side effects let isr = unsafe { (*$USARTX::ptr()).isr.read() }; @@ -585,20 +584,20 @@ macro_rules! usart { } impl serial::Write for Serial<$USARTX> { - type Error = Never; + type Error = Infallible; - fn flush(&mut self) -> nb::Result<(), Never> { + fn try_flush(&mut self) -> nb::Result<(), Infallible> { let mut tx: Tx<$USARTX> = Tx { _usart: PhantomData, }; - tx.flush() + tx.try_flush() } - fn write(&mut self, byte: u8) -> nb::Result<(), Never> { + fn try_write(&mut self, byte: u8) -> nb::Result<(), Infallible> { let mut tx: Tx<$USARTX> = Tx { _usart: PhantomData, }; - tx.write(byte) + tx.try_write(byte) } } @@ -613,9 +612,9 @@ macro_rules! usart { // framing errors (which only occur in SmartCard // mode); neither of these apply to our hardware // configuration - type Error = Never; + type Error = Infallible; - fn flush(&mut self) -> nb::Result<(), Never> { + fn try_flush(&mut self) -> nb::Result<(), Infallible> { // NOTE(unsafe) atomic read with no side effects let isr = unsafe { (*$USARTX::ptr()).isr.read() }; @@ -626,7 +625,7 @@ macro_rules! usart { } } - fn write(&mut self, byte: u8) -> nb::Result<(), Never> { + fn try_write(&mut self, byte: u8) -> nb::Result<(), Infallible> { // NOTE(unsafe) atomic read with no side effects let isr = unsafe { (*$USARTX::ptr()).isr.read() }; @@ -721,7 +720,11 @@ where Tx: serial::Write, { fn write_str(&mut self, s: &str) -> fmt::Result { - let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last(); + let _ = s + .as_bytes() + .iter() + .map(|c| block!(self.try_write(*c))) + .last(); Ok(()) } } diff --git a/src/spi.rs b/src/spi.rs index 57ca9f924..3cc3af068 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -589,7 +589,7 @@ macro_rules! spi { impl hal::spi::FullDuplex<$TY> for Spi<$SPIX, $TY> { type Error = Error; - fn read(&mut self) -> nb::Result<$TY, Error> { + fn try_read(&mut self) -> nb::Result<$TY, Error> { let sr = self.spi.sr.read(); Err(if sr.ovr().is_overrun() { @@ -612,7 +612,7 @@ macro_rules! spi { }) } - fn send(&mut self, byte: $TY) -> nb::Result<(), Error> { + fn try_send(&mut self, byte: $TY) -> nb::Result<(), Error> { let sr = self.spi.sr.read(); Err(if sr.ovr().is_overrun() { diff --git a/src/timer.rs b/src/timer.rs index 6901e611b..e1977d4a1 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -3,6 +3,7 @@ // TODO: on the h7x3 at least, only TIM2, TIM3, TIM4, TIM5 can support 32 bits. // TIM1 is 16 bit. +use core::convert::Infallible; use core::marker::PhantomData; use crate::hal::timer::{CountDown, Periodic}; @@ -14,7 +15,6 @@ use crate::stm32::{ use cast::{u16, u32}; use nb; -use void::Void; use crate::rcc::{rec, CoreClocks, ResetEnable}; use crate::stm32; @@ -143,9 +143,10 @@ macro_rules! hal { impl Periodic for Timer<$TIMX> {} impl CountDown for Timer<$TIMX> { + type Error = Infallible; type Time = Hertz; - fn start(&mut self, timeout: T) + fn try_start(&mut self, timeout: T) -> Result<(), Self::Error> where T: Into, { @@ -167,10 +168,12 @@ macro_rules! hal { self.tim.egr.write(|w| w.ug().set_bit()); // Start counter - self.resume() + self.resume(); + + Ok(()) } - fn wait(&mut self) -> nb::Result<(), Void> { + fn try_wait(&mut self) -> nb::Result<(), Infallible> { if self.tim.sr.read().uif().bit_is_clear() { Err(nb::Error::WouldBlock) } else { @@ -212,7 +215,7 @@ macro_rules! hal { tim, timeout: Hertz(0), }; - timer.start(timeout); + timer.try_start(timeout).unwrap(); // infallible timer } diff --git a/src/watchdog.rs b/src/watchdog.rs index d87aff337..8efee5870 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -4,6 +4,7 @@ use crate::hal::watchdog::{Watchdog, WatchdogEnable}; use crate::rcc::Ccdr; use crate::time::{Hertz, MilliSeconds}; use cast::u8; +use core::convert::Infallible; /// Select Window Watchdog hardware based on core #[cfg(any(feature = "singlecore"))] @@ -35,20 +36,23 @@ impl SystemWindowWatchdog { } impl Watchdog for SystemWindowWatchdog { + type Error = Infallible; /// Feeds the watchdog in order to avoid a reset, only executes properly if the watchdog /// has already been started aka. the down_counter is not 0 anymore - fn feed(&mut self) { + fn try_feed(&mut self) -> Result<(), Self::Error> { // if this value is 0 it is assumed that the watchdog has not yet been started assert!(self.down_counter != 0); self.wwdg.cr.modify(|_, w| w.t().bits(self.down_counter)); + Ok(()) } } impl WatchdogEnable for SystemWindowWatchdog { + type Error = Infallible; type Time = MilliSeconds; /// Starts the watchdog with a given timeout period, if this period is out of bounds the function /// is going to panic - fn start(&mut self, period: T) + fn try_start(&mut self, period: T) -> Result<(), Self::Error> where T: Into, { @@ -84,5 +88,6 @@ impl WatchdogEnable for SystemWindowWatchdog { self.wwdg.cr.modify(|_, w| w.t().bits(self.down_counter)); // enable the watchdog self.wwdg.cr.modify(|_, w| w.wdga().set_bit()); + Ok(()) } }