diff --git a/src/adc.rs b/src/adc.rs index 44b49b98..07e0ba98 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,5 +1,5 @@ //! Analog to digital converter configuration. -//! https://github.com/stm32-rs/stm32l4xx-hal/blob/master/src/adc.rs +//! #![deny(missing_docs)] @@ -310,7 +310,8 @@ pub mod config { pub enum ClockMode { /// (Asynchronous clock mode), adc_ker_ck. generated at product level (refer to Section 6: Reset and clock control (RCC) Asynchronous, - /// (Synchronous clock mode). adc_hclk/1 This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle. + /// (Synchronous clock mode). adc_hclk/1 + /// This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE\[3:0\] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle. Synchronous_Div_1, /// Synchronous clock mode. adc_hclk/2 Synchronous_Div_2, @@ -1166,9 +1167,9 @@ impl Conversion { !self.is_active() } - /// Converts from Conversion to Option. + /// Converts from `Conversion` to `Option`. /// - /// Converts self into an Option, consuming self, and discarding the adc, if it is stopped. + /// Converts self into an `Option`, consuming self, and discarding the adc, if it is stopped. #[inline(always)] pub fn active(self) -> Option> { match self { @@ -1177,9 +1178,9 @@ impl Conversion { } } - /// Converts from Conversion to Option. + /// Converts from `Conversion` to `Option`. /// - /// Converts self into an Option, consuming self, and discarding the adc, if it is still active. + /// Converts self into an `Option`, consuming self, and discarding the adc, if it is still active. #[inline(always)] pub fn stopped(self) -> Option> { match self { diff --git a/src/delay.rs b/src/delay.rs index c6eaa9b9..417208b6 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -1,9 +1,9 @@ //! Delay providers //! //! There are currently two delay providers. In general you should prefer to use -//! [Delay](Delay), however if you do not have access to `SYST` you can use -//! [DelayFromCountDownTimer](DelayFromCountDownTimer) with any timer that -//! implements the [CountDown](embedded_hal::timer::CountDown) trait. This can be +//! [Delay], however if you do not have access to `SYST` you can use +//! [DelayFromCountDownTimer] with any timer that +//! implements the [CountDown](embedded_hal_old::timer::CountDown) trait. This can be //! useful if you're using [RTIC](https://rtic.rs)'s schedule API, which occupies //! the `SYST` peripheral. //! diff --git a/src/dma.rs b/src/dma.rs index d05b6e00..d1033762 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -13,7 +13,7 @@ //! instructions in DMA controller configuration. //! //! Adapted from -//! https://github.com/stm32-rs/stm32h7xx-hal/blob/master/src/dma/mod.rs +//! use core::fmt::Debug; diff --git a/src/dma/traits.rs b/src/dma/traits.rs index d33a965e..214cc17a 100644 --- a/src/dma/traits.rs +++ b/src/dma/traits.rs @@ -1,7 +1,7 @@ //! Traits for DMA types //! //! Adapted from -//! https://github.com/stm32-rs/stm32f4xx-hal/blob/master/src/dma/traits.rs +//! use super::*; diff --git a/src/pwm.rs b/src/pwm.rs index 76592fe7..e25d8a82 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -1405,7 +1405,7 @@ macro_rules! tim_hal { $( impl PwmBuilder<$TIMX, PINS, CHANNEL, FaultDisabled, COMP, $typ> { /// Configure a break pin that will disable PWM when activated (active level based on polarity argument) - /// Note: not all timers have fault inputs; FaultPins is only implemented for valid pins/timers. + /// Note: not all timers have fault inputs; `FaultPins` is only implemented for valid pins/timers. pub fn with_break_pin>(self, _pin: P, polarity: Polarity) -> PwmBuilder<$TIMX, PINS, CHANNEL, FaultEnabled, COMP, $typ> { PwmBuilder { _tim: PhantomData,