diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.c b/drivers/gpu/drm/msm/sde/sde_hw_top.c
index beb0613033b89..44906a7e04fa1 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.c
@@ -387,6 +387,10 @@ void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
 {
 	struct sde_hw_blk_reg_map c;
 	u32 ubwc_version;
+	u32 reg = m->mdp[0].ubwc_static |
+		(m->mdp[0].ubwc_swizzle & 0x1) |
+		((m->mdp[0].highest_bank_bit & 0x3) << 4) |
+		((m->macrotile_mode & 0x1) << 12);
 
 	if (!mdp || !m)
 		return;
@@ -394,24 +398,25 @@ void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
 	/* force blk offset to zero to access beginning of register region */
 	c = mdp->hw;
 	c.blk_off = 0x0;
-	ubwc_version = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);
+	/* 630 doesn't seem to have the UBWC version register */
+	//ubwc_version = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);
+	ubwc_version = m->ubwc_version;
 
-	if (IS_UBWC_20_SUPPORTED(ubwc_version)) {
-		SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
-	} else if (IS_UBWC_30_SUPPORTED(ubwc_version)) {
-		u32 reg = m->mdp[0].ubwc_static |
-			(m->mdp[0].ubwc_swizzle & 0x1) |
-			((m->mdp[0].highest_bank_bit & 0x3) << 4) |
-			((m->macrotile_mode & 0x1) << 12);
-
-		if (IS_UBWC_30_SUPPORTED(m->ubwc_version))
-			reg |= BIT(10);
-		if (IS_UBWC_10_SUPPORTED(m->ubwc_version))
+	switch(ubwc_version) {
+		case 0x10000000:
 			reg |= BIT(8);
-
-		SDE_REG_WRITE(&c, UBWC_STATIC, reg);
-	} else {
-		SDE_ERROR("Unsupported UBWC version 0x%08x\n", ubwc_version);
+			SDE_REG_WRITE(&c, UBWC_STATIC, reg);
+			break;
+		case 0x20000000:
+			SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
+			break;
+		case 0x30000000:
+			reg |= BIT(10);
+			SDE_REG_WRITE(&c, UBWC_STATIC, reg);
+			break;
+		default:
+			SDE_ERROR("Unsupported UBWC version 0x%08x\n", ubwc_version);
+			break;
 	}
 }