From 296920a07d9ebb42fdad918b96b5ecc4a044d778 Mon Sep 17 00:00:00 2001 From: Lakshmi Narayana Kalavala Date: Fri, 7 Dec 2018 16:17:33 -0800 Subject: [PATCH] drm/msm/sde: fix watchdog vsync timer configuration Fix the incorrect values for the watchdog vsync timer with proper hexadecimal values. Change-Id: Iddaf36018a7f6521f7da32349afd64c5ebe79060 Signed-off-by: Dhaval Patel Signed-off-by: Lakshmi Narayana Kalavala --- drivers/gpu/drm/msm/sde/sde_hw_mdss.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h index 9b4e03d65098d..7174a5d303d9e 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h @@ -89,11 +89,11 @@ enum sde_format_flags { #define SDE_VSYNC_SOURCE_INTF_1 4 #define SDE_VSYNC_SOURCE_INTF_2 5 #define SDE_VSYNC_SOURCE_INTF_3 6 -#define SDE_VSYNC_SOURCE_WD_TIMER_4 11 -#define SDE_VSYNC_SOURCE_WD_TIMER_3 12 -#define SDE_VSYNC_SOURCE_WD_TIMER_2 13 -#define SDE_VSYNC_SOURCE_WD_TIMER_1 14 -#define SDE_VSYNC_SOURCE_WD_TIMER_0 15 +#define SDE_VSYNC_SOURCE_WD_TIMER_4 0x11 +#define SDE_VSYNC_SOURCE_WD_TIMER_3 0x12 +#define SDE_VSYNC_SOURCE_WD_TIMER_2 0x13 +#define SDE_VSYNC_SOURCE_WD_TIMER_1 0x14 +#define SDE_VSYNC_SOURCE_WD_TIMER_0 0x15 enum sde_hw_blk_type { SDE_HW_BLK_TOP = 0,