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@ruck314 ruck314 released this 02 Oct 22:32
· 166 commits to main since this release
v2.51.0
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Pull Requests Since v2.50.0

Unlabeled

  1. #1195 - adding Pgp4RxLiteLowSpeed.vhd
  2. #1204 - introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment
  3. #1194 - adding userCLk to SelectioDeserUltraScale.vhd
  4. #1203 - _Qsfp.py Update
  5. #1199 - Updates to AxiLiteSaciMaster.vhd & SaciMaster2.vhd
  6. #1197 - Increased range of SACI_NUM_CHIPS_G to support more than 4 chips
  7. #1200 - Pgp4RxLiteLowSpeedLane.vhd Update
  8. #1198 - Update RstSync.vhd

Pull Request Details

adding userCLk to SelectioDeserUltraScale.vhd
Author: Larry Ruckman [email protected]
Date: Mon Sep 23 10:27:09 2024 -0700
Pull: #1194 (27 additions, 8 deletions, 1 files changed)
Branch: slaclab/ruckman/SelectioDeserUltraScale

Notes:

Description

  • mapping CLKOUT1 to userClk, which is a useful optional clock reference

adding Pgp4RxLiteLowSpeed.vhd
Author: Larry Ruckman [email protected]
Date: Thu Sep 26 09:52:31 2024 -0700
Pull: #1195 (803 additions, 0 deletions, 5 files changed)
Branch: slaclab/Pgp4RxLiteLowSpeed

Notes:

Description

  • Designed for receiving unidirectional PGP4-lite from ASIC using the FPGA's SelectIO (LVDS I/O)

Increased range of SACI_NUM_CHIPS_G to support more than 4 chips
Author: Larry Ruckman [email protected]
Date: Tue Oct 1 08:05:37 2024 -0700
Pull: #1197 (7 additions, 7 deletions, 1 files changed)
Branch: slaclab/saci_6_chip

Notes:

Description

The AxiLiteSaciMaster currently has a fixed limit of four ASICs ("chips"). This has been increased to six to work with a new readout system with that many ASICs.

Details

The new 3x2 Readout (https://confluence.slac.stanford.edu/x/eKRxG) seems to be first system to use more than four ASICs with a common SACI interfaces. There is no mention why only four chips were allowed previously. The hardware will arrive in a couple of weeks with which we can test running SACI with six chips, but from the code alone I don't see any reason why more than four would not work.

Update RstSync.vhd
Author: Larry Ruckman [email protected]
Date: Wed Sep 25 09:59:04 2024 -0700
Pull: #1198 (5 additions, 2 deletions, 1 files changed)
Branch: slaclab/RstSync-std_logic

Notes:

Description

  • Using "std_logic" instead of "sl" for generics due to issues with SystemVerilog handling VHDL subtype on generics properly

Updates to AxiLiteSaciMaster.vhd & SaciMaster2.vhd
Author: Larry Ruckman [email protected]
Date: Fri Sep 27 12:31:21 2024 -0700
Pull: #1199 (22 additions, 8 deletions, 2 files changed)
Branch: slaclab/AxiLiteSaciMaster-asicRstL-aware

Notes:

Description

Pgp4RxLiteLowSpeedLane.vhd Update
Author: Larry Ruckman [email protected]
Date: Mon Sep 30 09:13:03 2024 -0700
Pull: #1200 (7 additions, 2 deletions, 1 files changed)
Branch: slaclab/Pgp4RxLiteLowSpeedLane

Notes:

Description

  • Mask off the Valid to the RX protocol until the gearbox is locked

_Qsfp.py Update
Author: Larry Ruckman [email protected]
Date: Wed Oct 2 11:03:34 2024 -0700
Pull: #1203 (31 additions, 0 deletions, 1 files changed)
Branch: slaclab/Qsfp-TxDisable

Notes:

Description

introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment
Author: Larry Ruckman [email protected]
Date: Tue Oct 1 19:27:41 2024 -0700
Pull: #1204 (164 additions, 121 deletions, 15 files changed)
Branch: slaclab/pgp4lite-rstPolarity

Notes:

introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment

(ASIC designs usually employ an active-LOW reset/i.e. a rstN/enable signal)

add RST_POLARITY_G to all modules.

note that I also added RST_POLARITY_G to RX-related modules because I use them in my local behavioral simulation (no receiver in ASICs are foreseen). Since the RST_POLARITY_G generic default values are consistent, the changes in the TX/RX modules hopefully should not have impact on existing designs.

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