From f4ccc95ddc6dd3153860635196fd22c695b079f5 Mon Sep 17 00:00:00 2001 From: Julian Mendez Date: Fri, 23 Jun 2023 14:41:42 -0700 Subject: [PATCH 01/32] fix Delay3PatchFSM: init issue (JIRA ESSURF-24) --- .../general/rtl/Delaye3PatchFsm.vhd | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd index f3c647180a..568e268838 100644 --- a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd +++ b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd @@ -49,6 +49,7 @@ architecture rtl of Delaye3PatchFsm is type StateType is ( IDLE_S, + CHECK_CNT_S, LOAD_S, WAIT_S); @@ -84,15 +85,17 @@ begin v.Load := '0'; -- Check for load request - if (LOAD = '1') then - -- Update the target delay value - v.dlyTarget := CNTVALUEIN; - end if; - -- Main state machine case r.state is ---------------------------------------------------------------------- when IDLE_S => + if (LOAD = '1') then + -- Update the target delay value on load request + v.dlyTarget := CNTVALUEIN; + v.state := CHECK_CNT_S; + end if; + + when CHECK_CNT_S => -- Check if load target different from current output if (v.dlyTarget /= CNTVALUEOUT) then -- Check if we should increment the value @@ -104,6 +107,10 @@ begin end if; -- Next state v.state := LOAD_S; + + else + v.state := IDLE_S; + end if; ---------------------------------------------------------------------- when LOAD_S => @@ -121,7 +128,7 @@ begin -- Reset the counter v.waitCnt := (others => '0'); -- Next state - v.state := IDLE_S; + v.state := CHECK_CNT_S; end if; ---------------------------------------------------------------------- end case; From c1d6fa31b0895407ac40b51db3b085b70d2e2f66 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sat, 24 Jun 2023 14:37:33 -0700 Subject: [PATCH 02/32] adding enAdcTile/enDacTile arg to _RfDataConverter.py --- python/surf/xilinx/_RfDataConverter.py | 34 ++++++++++++++------------ 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/python/surf/xilinx/_RfDataConverter.py b/python/surf/xilinx/_RfDataConverter.py index 3496a14458..f70e61d4fb 100644 --- a/python/surf/xilinx/_RfDataConverter.py +++ b/python/surf/xilinx/_RfDataConverter.py @@ -20,7 +20,9 @@ class RfDataConverter(pr.Device): def __init__( self, - gen3 = True, # True if using RFSoC GEN3 Hardware + gen3 = True, # True if using RFSoC GEN3 Hardware + enAdcTile = [True,True,True,True], + enDacTile = [True,True,True,True], **kwargs): super().__init__(**kwargs) @@ -104,22 +106,24 @@ def __init__( )) for i in range(4): - self.add(xil.RfTile( - name = f'dacTile[{i}]', - isAdc = False, - gen3 = gen3, - offset = 0x04000 + 0x4000*i, - expand = False, - )) + if enDacTile[i]: + self.add(xil.RfTile( + name = f'dacTile[{i}]', + isAdc = False, + gen3 = gen3, + offset = 0x04000 + 0x4000*i, + expand = False, + )) for i in range(4): - self.add(xil.RfTile( - name = f'adcTile[{i}]', - isAdc = True, - gen3 = gen3, - offset = 0x14000 + 0x4000*i, - expand = False, - )) + if enAdcTile[i]: + self.add(xil.RfTile( + name = f'adcTile[{i}]', + isAdc = True, + gen3 = gen3, + offset = 0x14000 + 0x4000*i, + expand = False, + )) def Init(self, dynamicNco=False): From 7ce7d63ec79d810e335b8dabb7bc37651a314181 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 27 Jun 2023 07:35:03 -0700 Subject: [PATCH 03/32] code clean up --- xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd index 568e268838..3f7f95b18c 100644 --- a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd +++ b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd @@ -94,12 +94,12 @@ begin v.dlyTarget := CNTVALUEIN; v.state := CHECK_CNT_S; end if; - + ---------------------------------------------------------------------- when CHECK_CNT_S => -- Check if load target different from current output - if (v.dlyTarget /= CNTVALUEOUT) then + if (r.dlyTarget /= CNTVALUEOUT) then -- Check if we should increment the value - if (v.dlyTarget > CNTVALUEOUT) then + if (r.dlyTarget > CNTVALUEOUT) then v.dlyValue := CNTVALUEOUT + 1; -- Else decrement the value else @@ -107,10 +107,8 @@ begin end if; -- Next state v.state := LOAD_S; - else v.state := IDLE_S; - end if; ---------------------------------------------------------------------- when LOAD_S => From f92629ad47d18670e9e3277d4dfd48327383fd5a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 2 Jul 2023 11:28:40 -0700 Subject: [PATCH 04/32] adding test_LineCode8b10bTb.py --- protocols/line-codes/tb/LineCode8b10bTb.vhd | 87 ++++++++++ protocols/sugoi/ruckus.tcl | 5 +- ruckus.tcl | 2 +- tests/test_LineCode8b10bTb.py | 167 ++++++++++++++++++++ 4 files changed, 257 insertions(+), 4 deletions(-) create mode 100644 protocols/line-codes/tb/LineCode8b10bTb.vhd create mode 100644 tests/test_LineCode8b10bTb.py diff --git a/protocols/line-codes/tb/LineCode8b10bTb.vhd b/protocols/line-codes/tb/LineCode8b10bTb.vhd new file mode 100644 index 0000000000..d0866cf4fb --- /dev/null +++ b/protocols/line-codes/tb/LineCode8b10bTb.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Line Code 8B10B: https://en.wikipedia.org/wiki/8b/10b_encoding +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: 8B10B Line Code Test bed for cocoTB +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity LineCode8b10bTb is + generic ( + TPD_G : time := 1 ns; + NUM_BYTES_G : positive := 1); + port ( + -- Clock and Reset + clk : in sl; + rst : in sl; + -- Encoder Interface + validIn : in sl; + dataIn : in slv(NUM_BYTES_G*8-1 downto 0); + dataKIn : in slv(NUM_BYTES_G-1 downto 0); + -- Decoder Interface + validOut : out sl; + dataOut : out slv(NUM_BYTES_G*8-1 downto 0); + dataKOut : out slv(NUM_BYTES_G-1 downto 0); + codeErr : out slv(NUM_BYTES_G-1 downto 0); + dispErr : out slv(NUM_BYTES_G-1 downto 0)); +end entity LineCode8b10bTb; + +architecture mapping of LineCode8b10bTb is + + signal validEncode : sl; + signal dataEncode : slv(NUM_BYTES_G*10-1 downto 0); + +begin + + U_Encoder : entity surf.Encoder8b10b + generic map ( + TPD_G => TPD_G, + NUM_BYTES_G => NUM_BYTES_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + FLOW_CTRL_EN_G => true) + port map ( + clk => clk, + clkEn => '1', + rst => rst, + validIn => validIn, + readyIn => open, + dataIn => dataIn, + dataKIn => dataKIn, + validOut => validEncode, + readyOut => validEncode, + dataOut => dataEncode); + + U_Decoder : entity surf.Decoder8b10b + generic map ( + TPD_G => TPD_G, + NUM_BYTES_G => NUM_BYTES_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false) + port map ( + clk => clk, + clkEn => '1', + rst => rst, + validIn => validEncode, + dataIn => dataEncode, + validOut => validOut, + dataOut => dataOut, + dataKOut => dataKOut, + codeErr => codeErr, + dispErr => dispErr); + +end mapping; diff --git a/protocols/sugoi/ruckus.tcl b/protocols/sugoi/ruckus.tcl index 8dc6a28f5c..e46029c62f 100644 --- a/protocols/sugoi/ruckus.tcl +++ b/protocols/sugoi/ruckus.tcl @@ -4,13 +4,12 @@ source $::env(RUCKUS_PROC_TCL) # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" -# Load Simulation -loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" - # Check for non-zero Vivado version (in-case non-Vivado project) if { $::env(VIVADO_VERSION) > 0.0} { loadSource -lib surf -dir "$::DIR_PATH/rtl/7Series" loadSource -lib surf -dir "$::DIR_PATH/rtl/UltraScale" + # Load Simulation (includes library UNISIM) + loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" } else { loadSource -lib surf -dir "$::DIR_PATH/rtl/dummy" } diff --git a/ruckus.tcl b/ruckus.tcl index c136ab983e..6238316e6b 100644 --- a/ruckus.tcl +++ b/ruckus.tcl @@ -3,7 +3,7 @@ source $::env(RUCKUS_PROC_TCL) # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { - if { [SubmoduleCheck {ruckus} {4.8.2} ] < 0 } {exit -1} + if { [SubmoduleCheck {ruckus} {4.8.4} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0" diff --git a/tests/test_LineCode8b10bTb.py b/tests/test_LineCode8b10bTb.py new file mode 100644 index 0000000000..ca29f0be6b --- /dev/null +++ b/tests/test_LineCode8b10bTb.py @@ -0,0 +1,167 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +# test_DspComparator +from cocotb_test.simulator import run +import pytest +import glob +import os + +@cocotb.coroutine +def dut_init(dut): + + # Initialize the inputs + dut.rst.value = 1 + dut.validIn.value = 0 + dut.dataIn.value = 0 + dut.dataKIn.value = 0 + + # Start clock (200 MHz) in a separate thread + cocotb.start_soon(Clock(dut.clk, 5.0, units='ns').start()) + + # Wait 5 clock cycle + for i in range(5): + yield RisingEdge(dut.clk) + + # De-assert the reset + dut.rst.value = 0 + + # Wait 1 clock cycle + yield RisingEdge(dut.clk) + +@cocotb.coroutine +def load_value(dut, dataIn, dataKIn): + + # Load the values + dut.dataIn.value = dataIn + dut.dataKIn.value = dataKIn + + # Assert valid flag + dut.validIn.value = 1 + + # Wait 1 clock cycle + yield RisingEdge(dut.clk) + + # De-assert valid flag + dut.validIn.value = 0 + + # Wait for the result + while ( dut.validOut.value != 1 ): + yield RisingEdge(dut.clk) + + +def check_result(dut, dataIn, dataKIn): + # Check (dataIn = dataOut) or (dataKIn = dataKOut) result + if (dataIn != dut.dataOut.value) or (dataKIn != dut.dataKOut.value): + dut._log.error( f'dataIn={hex(dataIn)},dataKIn={hex(dataKIn)} but got dataOut={hex(dut.dataOut.value)},dataKOut={hex(dut.dataKOut.value)}') + assert False + + # Check (codeErr = 0) or (dispErr = 0) result + if (dut.codeErr.value != 0) or (dut.dispErr.value != 0): + dut._log.error( f'ERROR: codeErr={hex(dut.codeErr.value)},dispErr={hex(dut.dispErr.value)}') + assert False + +@cocotb.test() +def dut_tb(dut): + + # Initialize the DUT + yield dut_init(dut) + + # Read the parameters back from the DUT to set up our model + width = dut.NUM_BYTES_G.value.integer + dut._log.info( f'Found NUM_BYTES_G={width}' ) + + # Sweep through all possible combinations of data codes + dataKIn = 0 + for dataIn in range(2**(8*width)): + + # Load the values + yield load_value(dut, dataIn, dataKIn) + + # Check the results for errors + check_result(dut, dataIn, dataKIn) + + # Sweep through the defined Control Code Constants + dataKIn = 1 + controlCodes = [ + 0x1C, # K28.0, 0x1C + 0x3C, # K28.1, 0x3C (Comma) + 0x5C, # K28.2, 0x5C + 0x7C, # K28.3, 0x7C + 0x9C, # K28.4, 0x9C + 0xBC, # K28.5, 0xBC (Comma) + 0xDC, # K28.6, 0xDC + 0xFC, # K28.7, 0xFC (Comma) + 0xF7, # K23.7, 0xF7 + 0xFB, # K27.7, 0xFB + 0xFD, # K29.7, 0xFD + 0xFE, # K30.7, 0xFE + ] + for dataIn in controlCodes: + + # Load the values + yield load_value(dut, dataIn, dataKIn) + + # Check the results for errors + check_result(dut, dataIn, dataKIn) + + dut._log.info("DUT: Passed") + +tests_dir = os.path.dirname(__file__) +tests_module = 'LineCode8b10bTb' + +@pytest.mark.parametrize( + "parameters", [ + {'NUM_BYTES_G': '1'}, # Test 1 byte interface + {'NUM_BYTES_G': '2'}, # Test 2 byte interface + ]) +def test_LineCode8b10bTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}.' + ",".join((f"{key}={value}" for key, value in parameters.items())), + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # Dump waveform to file ($ gtkwave sim_build/LineCode8b10bTb.NUM_BYTES_G\=1/LineCode8b10bTb.vcd) + sim_args =[f'--vcd={tests_module}.vcd'], + ) From 64b0510ed063933d0b37a8f1e6a4affedcf99d8f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 2 Jul 2023 12:35:05 -0700 Subject: [PATCH 05/32] adding adding test_LineCode10b12bTb.py --- protocols/line-codes/rtl/Code10b12bPkg.vhd | 2 +- protocols/line-codes/tb/LineCode10b12bTb.vhd | 87 ++++++++++ tests/test_LineCode10b12bTb.py | 171 +++++++++++++++++++ 3 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 protocols/line-codes/tb/LineCode10b12bTb.vhd create mode 100644 tests/test_LineCode10b12bTb.py diff --git a/protocols/line-codes/rtl/Code10b12bPkg.vhd b/protocols/line-codes/rtl/Code10b12bPkg.vhd index 67c2e2cdbd..87115cf5b5 100644 --- a/protocols/line-codes/rtl/Code10b12bPkg.vhd +++ b/protocols/line-codes/rtl/Code10b12bPkg.vhd @@ -34,7 +34,7 @@ package Code10b12bPkg is constant K_28_19_C : slv(9 downto 0) := b"10011_11100"; -- 0x27C -> 0x4FC, 0xB03 -- These symbols are not commas but can be used for control sequences - -- Technically any K.28.x character is a valid k-char but these are preffered + -- Technically any K.28.x character is a valid k-char but these are preferred constant K_28_5_C : slv(9 downto 0) := b"00101_11100"; -- 0x0BC -> 0x683, 0x97C constant K_28_6_C : slv(9 downto 0) := b"00110_11100"; -- 0x0DC -> 0x643, 0x9BC constant K_28_9_C : slv(9 downto 0) := b"01001_11100"; -- 0x13C -> 0x583, 0xA7C diff --git a/protocols/line-codes/tb/LineCode10b12bTb.vhd b/protocols/line-codes/tb/LineCode10b12bTb.vhd new file mode 100644 index 0000000000..dc01d09038 --- /dev/null +++ b/protocols/line-codes/tb/LineCode10b12bTb.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- Title : Line Code 10B12B: https://confluence.slac.stanford.edu/x/QndODQ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: 10B12B Line Code Test bed for cocoTB +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity LineCode10b12bTb is + generic ( + TPD_G : time := 1 ns); + port ( + -- Clock and Reset + clk : in sl; + rst : in sl; + -- Encoder Interface + validIn : in sl; + dataIn : in slv(9 downto 0); + dataKIn : in sl; + -- Decoder Interface + validOut : out sl; + dataOut : out slv(9 downto 0); + dataKOut : out sl; + codeErr : out sl; + dispErr : out sl); +end entity LineCode10b12bTb; + +architecture mapping of LineCode10b12bTb is + + signal validEncode : sl; + signal dataEncode : slv(11 downto 0); + +begin + + U_Encoder : entity surf.Encoder10b12b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + USE_CLK_EN_G => false, + FLOW_CTRL_EN_G => true) + port map ( + clk => clk, + clkEn => '1', + rst => rst, + validIn => validIn, + readyIn => open, + dataIn => dataIn, + dataKIn => dataKIn, + validOut => validEncode, + readyOut => validEncode, + dataOut => dataEncode, + dispOut => open); + + U_Decoder : entity surf.Decoder10b12b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + USE_CLK_EN_G => false) + port map ( + clk => clk, + clkEn => '1', + rst => rst, + validIn => validEncode, + dataIn => dataEncode, + validOut => validOut, + dataOut => dataOut, + dataKOut => dataKOut, + codeError => codeErr, + dispError => dispErr); + +end mapping; diff --git a/tests/test_LineCode10b12bTb.py b/tests/test_LineCode10b12bTb.py new file mode 100644 index 0000000000..a34e3fbfee --- /dev/null +++ b/tests/test_LineCode10b12bTb.py @@ -0,0 +1,171 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +# test_DspComparator +from cocotb_test.simulator import run +import pytest +import glob +import os + +@cocotb.coroutine +def dut_init(dut): + + # Initialize the inputs + dut.rst.value = 1 + dut.validIn.value = 0 + dut.dataIn.value = 0 + dut.dataKIn.value = 0 + + # Start clock (200 MHz) in a separate thread + cocotb.start_soon(Clock(dut.clk, 5.0, units='ns').start()) + + # Wait 5 clock cycle + for i in range(5): + yield RisingEdge(dut.clk) + + # De-assert the reset + dut.rst.value = 0 + + # Wait 1 clock cycle + yield RisingEdge(dut.clk) + +@cocotb.coroutine +def load_value(dut, dataIn, dataKIn): + + # Load the values + dut.dataIn.value = dataIn + dut.dataKIn.value = dataKIn + + # Assert valid flag + dut.validIn.value = 1 + + # Wait 1 clock cycle + yield RisingEdge(dut.clk) + + # De-assert valid flag + dut.validIn.value = 0 + + # Wait for the result + while ( dut.validOut.value != 1 ): + yield RisingEdge(dut.clk) + + +def check_result(dut, dataIn, dataKIn): + # Check (dataIn = dataOut) or (dataKIn = dataKOut) result + if (dataIn != dut.dataOut.value) or (dataKIn != dut.dataKOut.value): + dut._log.error( f'dataIn={hex(dataIn)},dataKIn={hex(dataKIn)} but got dataOut={hex(dut.dataOut.value)},dataKOut={hex(dut.dataKOut.value)}') + assert False + + # Check (codeErr = 0) or (dispErr = 0) result + if (dut.codeErr.value != 0) or (dut.dispErr.value != 0): + dut._log.error( f'ERROR: codeErr={hex(dut.codeErr.value)},dispErr={hex(dut.dispErr.value)}') + assert False + +@cocotb.test() +def dut_tb(dut): + + # Initialize the DUT + yield dut_init(dut) + + # Sweep through all possible combinations of data codes + dataKIn = 0 + for dataIn in range(2**10): + + # Load the values + yield load_value(dut, dataIn, dataKIn) + + # Check the results for errors + check_result(dut, dataIn, dataKIn) + + # Sweep through the defined Control Code Constants + dataKIn = 1 + controlCodes = [ + # These symbols are commas, sequences that can be used for word alignment + 0x07C, # 0x07C -> 0x8FC, 0x703 + 0x17C, # 0x17C -> 0x2FC, 0xD03 + 0x27C, # 0x27C -> 0x4FC, 0xB03 + # These symbols are not commas but can be used for control sequences + # Technically any K.28.x character is a valid k-char but these are preferred + 0x0BC, # 0x0BC -> 0x683, 0x97C + 0x0DC, # 0x0DC -> 0x643, 0x9BC + 0x13C, # 0x13C -> 0x583, 0xA7C + 0x15C, # 0x15C -> 0xABC, 0x543 + 0x19C, # 0x19C -> 0x4C3, 0xB3C + 0x1BC, # 0x1BC -> 0x37C, 0xC83 + 0x1DC, # 0x1DC -> 0x3BC, 0xC43 + 0x23C, # 0x23C -> 0x383, 0xC7C + 0x25C, # 0x25C -> 0x343, 0xCBC + 0x29C, # 0x29C -> 0x2C3, 0xD3C + 0x2BC, # 0x2BC -> 0x57C, 0xA83 + 0x2DC, # 0x2DC -> 0x5BC, 0xA43 + 0x33C, # 0x33C -> 0x67C, 0x983 + 0x35C, # 0x35C -> 0x6BC, 0x943 + ] + for dataIn in controlCodes: + + # Load the values + yield load_value(dut, dataIn, dataKIn) + + # Check the results for errors + check_result(dut, dataIn, dataKIn) + + dut._log.info("DUT: Passed") + +tests_dir = os.path.dirname(__file__) +tests_module = 'LineCode10b12bTb' + +@pytest.mark.parametrize( + "parameters", [ + None + ]) +def test_LineCode10b12bTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}.', + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys', '-fexplicit'], + ) From 0f83a8e580944cccc80f76da1a6c84afe0754e3f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 3 Jul 2023 08:37:36 -0700 Subject: [PATCH 06/32] Encoder12b14b.vhd bug fix: missing readyOut in sensitivity list --- protocols/line-codes/rtl/Encoder12b14b.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/line-codes/rtl/Encoder12b14b.vhd b/protocols/line-codes/rtl/Encoder12b14b.vhd index e6a5a6e234..608aed8340 100644 --- a/protocols/line-codes/rtl/Encoder12b14b.vhd +++ b/protocols/line-codes/rtl/Encoder12b14b.vhd @@ -67,7 +67,7 @@ architecture rtl of Encoder12b14b is begin - comb : process (dataIn, dataKIn, dispIn, r, rst, validIn) is + comb : process (dataIn, dataKIn, dispIn, r, readyOut, rst, validIn) is variable v : RegType; variable dispInTmp : slv(1 downto 0); variable invalidK : sl; From ea775c4769801f9b4cf6a448b29170a9b2c1c6c0 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 3 Jul 2023 08:47:53 -0700 Subject: [PATCH 07/32] adding adding test_LineCode12b14bTb.py --- protocols/line-codes/tb/LineCode12b14bTb.vhd | 90 ++++++++++ tests/test_LineCode10b12bTb.py | 5 +- tests/test_LineCode12b14bTb.py | 180 +++++++++++++++++++ tests/test_LineCode8b10bTb.py | 2 +- 4 files changed, 275 insertions(+), 2 deletions(-) create mode 100644 protocols/line-codes/tb/LineCode12b14bTb.vhd create mode 100644 tests/test_LineCode12b14bTb.py diff --git a/protocols/line-codes/tb/LineCode12b14bTb.vhd b/protocols/line-codes/tb/LineCode12b14bTb.vhd new file mode 100644 index 0000000000..964e4861dd --- /dev/null +++ b/protocols/line-codes/tb/LineCode12b14bTb.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------- +-- Title : Line Code 12B14B: https://confluence.slac.stanford.edu/x/6AJODQ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: 12B14B Line Code Test bed for cocoTB +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity LineCode12b14bTb is + generic ( + TPD_G : time := 1 ns); + port ( + -- Clock and Reset + clk : in sl; + rst : in sl; + -- Encoder Interface + validIn : in sl; + dataIn : in slv(11 downto 0); + dataKIn : in sl; + -- Decoder Interface + validOut : out sl; + dataOut : out slv(11 downto 0); + dataKOut : out sl; + codeErr : out sl; + dispErr : out sl); +end entity LineCode12b14bTb; + +architecture mapping of LineCode12b14bTb is + + signal validEncode : sl; + signal dataEncode : slv(13 downto 0); + +begin + + U_Encoder : entity surf.Encoder12b14b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + DEBUG_DISP_G => false, + FLOW_CTRL_EN_G => true) + port map ( + clk => clk, + clkEn => '1', + rst => rst, + validIn => validIn, + readyIn => open, + dataIn => dataIn, + dispIn => "00", -- Used if DEBUG_DISP_G=true + dataKIn => dataKIn, + validOut => validEncode, + readyOut => validEncode, + dataOut => dataEncode, + dispOut => open); + + U_Decoder : entity surf.Decoder12b14b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + DEBUG_DISP_G => false) + port map ( + clk => clk, + clkEn => '1', + rst => rst, + validIn => validEncode, + dataIn => dataEncode, + dispIn => "00", -- Used if DEBUG_DISP_G=true + validOut => validOut, + dataOut => dataOut, + dataKOut => dataKOut, + codeError => codeErr, + dispError => dispErr, + dispOut => open); + +end mapping; diff --git a/tests/test_LineCode10b12bTb.py b/tests/test_LineCode10b12bTb.py index a34e3fbfee..a87dac1f2f 100644 --- a/tests/test_LineCode10b12bTb.py +++ b/tests/test_LineCode10b12bTb.py @@ -70,7 +70,7 @@ def check_result(dut, dataIn, dataKIn): # Check (codeErr = 0) or (dispErr = 0) result if (dut.codeErr.value != 0) or (dut.dispErr.value != 0): - dut._log.error( f'ERROR: codeErr={hex(dut.codeErr.value)},dispErr={hex(dut.dispErr.value)}') + dut._log.error( f'ERROR - dataIn={hex(dataIn)},dataKIn={hex(dataKIn)}: codeErr={hex(dut.codeErr.value)},dispErr={hex(dut.dispErr.value)}') assert False @cocotb.test() @@ -168,4 +168,7 @@ def test_LineCode10b12bTb(parameters): # use of synopsys package "std_logic_arith" needs the -fsynopsys option # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys', '-fexplicit'], + + # Dump waveform to file ($ gtkwave sim_build/LineCode12b14bTb./LineCode12b14bTb.vcd) + sim_args =[f'--vcd={tests_module}.vcd'], ) diff --git a/tests/test_LineCode12b14bTb.py b/tests/test_LineCode12b14bTb.py new file mode 100644 index 0000000000..59aa3d20b1 --- /dev/null +++ b/tests/test_LineCode12b14bTb.py @@ -0,0 +1,180 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +# test_DspComparator +from cocotb_test.simulator import run +import pytest +import glob +import os + +@cocotb.coroutine +def dut_init(dut): + + # Initialize the inputs + dut.rst.value = 1 + dut.validIn.value = 0 + dut.dataIn.value = 0 + dut.dataKIn.value = 0 + + # Start clock (200 MHz) in a separate thread + cocotb.start_soon(Clock(dut.clk, 5.0, units='ns').start()) + + # Wait 5 clock cycle + for i in range(5): + yield RisingEdge(dut.clk) + + # De-assert the reset + dut.rst.value = 0 + + # Wait 1 clock cycle + yield RisingEdge(dut.clk) + +@cocotb.coroutine +def load_value(dut, dataIn, dataKIn): + + # Load the values + dut.dataIn.value = dataIn + dut.dataKIn.value = dataKIn + + # Assert valid flag + dut.validIn.value = 1 + + # Wait 1 clock cycle + yield RisingEdge(dut.clk) + + # De-assert valid flag + dut.validIn.value = 0 + + # Wait for the result + while ( dut.validOut.value != 1 ): + yield RisingEdge(dut.clk) + + +def check_result(dut, dataIn, dataKIn): + # Check (dataIn = dataOut) or (dataKIn = dataKOut) result + if (dataIn != dut.dataOut.value) or (dataKIn != dut.dataKOut.value): + dut._log.error( f'dataIn={hex(dataIn)},dataKIn={hex(dataKIn)} but got dataOut={hex(dut.dataOut.value)},dataKOut={hex(dut.dataKOut.value)}') + assert False + + # Check (codeErr = 0) or (dispErr = 0) result + if (dut.codeErr.value != 0) or (dut.dispErr.value != 0): + dut._log.error( f'ERROR - dataIn={hex(dataIn)},dataKIn={hex(dataKIn)}: codeErr={hex(dut.codeErr.value)},dispErr={hex(dut.dispErr.value)}') + assert False + +@cocotb.test() +def dut_tb(dut): + + # Initialize the DUT + yield dut_init(dut) + + # Sweep through all possible combinations of data codes + dataKIn = 0 + for dataIn in range(2**12): + + # Load the values + yield load_value(dut, dataIn, dataKIn) + + # Check the results for errors + check_result(dut, dataIn, dataKIn) + + # Sweep through the defined Control Code Constants + dataKIn = 1 + controlCodes = [ + # ------------------------------------------------------------------------------------------------- + # -- Constants for K codes + # -- These are intended for public use + # ------------------------------------------------------------------------------------------------- + 0x078, # constant K_120_0_C : slv(11 downto 0) := "000001111000"; + 0x0F8, # constant K_120_1_C : slv(11 downto 0) := "000011111000"; + 0x178, # constant K_120_2_C : slv(11 downto 0) := "000101111000"; + 0x1F8, # constant K_120_3_C : slv(11 downto 0) := "000111111000"; + 0x278, # constant K_120_4_C : slv(11 downto 0) := "001001111000"; + 0x3F8, # constant K_120_7_C : slv(11 downto 0) := "001111111000"; + 0x478, # constant K_120_8_C : slv(11 downto 0) := "010001111000"; + 0x5F8, # constant K_120_11_C : slv(11 downto 0) := "010111111000"; + # -- constant K_120_15_C : slv(11 downto 0) := "011111111000"; + 0x878, # constant K_120_16_C : slv(11 downto 0) := "100001111000"; + 0x9F8, # constant K_120_19_C : slv(11 downto 0) := "100111111000"; + 0xBF8, # constant K_120_23_C : slv(11 downto 0) := "101111111000"; + 0xC78, # constant K_120_24_C : slv(11 downto 0) := "110001111000"; + 0xDF8, # constant K_120_27_C : slv(11 downto 0) := "110111111000"; + 0xEF8, # constant K_120_29_C : slv(11 downto 0) := "111011111000"; + 0xF78, # constant K_120_30_C : slv(11 downto 0) := "111101111000"; + 0xFF8, # constant K_120_31_C : slv(11 downto 0) := "111111111000"; + # -- constant K_55_15_C : slv(11 downto 0) := "011110110111"; + # -- constant K_57_15_C : slv(11 downto 0) := "011110111001"; + # -- constant K_87_15_C : slv(11 downto 0) := "011111010111"; + # -- constant K_93_15_C : slv(11 downto 0) := "011111011101"; + # -- constant K_117_15_C : slv(11 downto 0) := "011111110101"; + ] + for dataIn in controlCodes: + + # Load the values + yield load_value(dut, dataIn, dataKIn) + + # Check the results for errors + check_result(dut, dataIn, dataKIn) + + dut._log.info("DUT: Passed") + +tests_dir = os.path.dirname(__file__) +tests_module = 'LineCode12b14bTb' + +@pytest.mark.parametrize( + "parameters", [ + None + ]) +def test_LineCode12b14bTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}.', + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys', '-fexplicit'], + + # Dump waveform to file ($ gtkwave sim_build/LineCode12b14bTb./LineCode12b14bTb.vcd) + sim_args =[f'--vcd={tests_module}.vcd'], + ) diff --git a/tests/test_LineCode8b10bTb.py b/tests/test_LineCode8b10bTb.py index ca29f0be6b..4da7ca93ba 100644 --- a/tests/test_LineCode8b10bTb.py +++ b/tests/test_LineCode8b10bTb.py @@ -70,7 +70,7 @@ def check_result(dut, dataIn, dataKIn): # Check (codeErr = 0) or (dispErr = 0) result if (dut.codeErr.value != 0) or (dut.dispErr.value != 0): - dut._log.error( f'ERROR: codeErr={hex(dut.codeErr.value)},dispErr={hex(dut.dispErr.value)}') + dut._log.error( f'ERROR - dataIn={hex(dataIn)},dataKIn={hex(dataKIn)}: codeErr={hex(dut.codeErr.value)},dispErr={hex(dut.dispErr.value)}') assert False @cocotb.test() From 2044adc8c20e37d0c62a223e0008b2cb86ed914f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 3 Jul 2023 11:57:31 -0700 Subject: [PATCH 08/32] SUGOI sim includes library UNISIM --- protocols/sugoi/ruckus.tcl | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/protocols/sugoi/ruckus.tcl b/protocols/sugoi/ruckus.tcl index 8dc6a28f5c..e46029c62f 100644 --- a/protocols/sugoi/ruckus.tcl +++ b/protocols/sugoi/ruckus.tcl @@ -4,13 +4,12 @@ source $::env(RUCKUS_PROC_TCL) # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" -# Load Simulation -loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" - # Check for non-zero Vivado version (in-case non-Vivado project) if { $::env(VIVADO_VERSION) > 0.0} { loadSource -lib surf -dir "$::DIR_PATH/rtl/7Series" loadSource -lib surf -dir "$::DIR_PATH/rtl/UltraScale" + # Load Simulation (includes library UNISIM) + loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" } else { loadSource -lib surf -dir "$::DIR_PATH/rtl/dummy" } From cb03b3567635b4fe897a35673eb1828497e09e12 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 3 Jul 2023 12:44:58 -0700 Subject: [PATCH 09/32] adding AxiStreamFifoV2IpIntegrator.vhd --- .../AxiStreamFifoV2IpIntegrator.vhd | 253 ++++++++++++++++++ 1 file changed, 253 insertions(+) create mode 100644 axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd diff --git a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd new file mode 100644 index 0000000000..df7bc052cd --- /dev/null +++ b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd @@ -0,0 +1,253 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Integrator Wrapper for surf.AxiStreamFifoV2 +------------------------------------------------------------------------------- +-- TCL Command: create_bd_cell -type module -reference AxiStreamFifoV2IpIntegrator AxiStreamFifoV2_0 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity AxiStreamFifoV2IpIntegrator is + generic ( + -- IP Integrator Slave AXI Stream Configuration + S_INTERFACENAME : string := "S_AXIS"; + S_HAS_TLAST : natural range 0 to 1 := 1; + S_HAS_TKEEP : natural range 0 to 1 := 1; + S_HAS_TSTRB : natural range 0 to 1 := 0; + S_HAS_TREADY : natural range 0 to 1 := 1; + S_TUSER_WIDTH : natural range 1 to 8 := 2; + S_TID_WIDTH : natural range 1 to 8 := 1; + S_TDEST_WIDTH : natural range 1 to 8 := 1; + S_TDATA_NUM_BYTES : natural range 1 to 128 := 1; + + -- IP Integrator Master AXI Stream Configuration + M_INTERFACENAME : string := "M_AXIS"; + M_HAS_TLAST : natural range 0 to 1 := 1; + M_HAS_TKEEP : natural range 0 to 1 := 1; + M_HAS_TSTRB : natural range 0 to 1 := 0; + M_HAS_TREADY : natural range 0 to 1 := 1; + M_TUSER_WIDTH : natural range 1 to 8 := 2; + M_TID_WIDTH : natural range 1 to 8 := 1; + M_TDEST_WIDTH : natural range 1 to 8 := 1; + M_TDATA_NUM_BYTES : natural range 1 to 128 := 1; + + -- General Configurations + RST_ASYNC : boolean := false; + INT_PIPE_STAGES : natural range 0 to 16 := 0; -- Internal FIFO setting + PIPE_STAGES : natural range 0 to 16 := 1; + VALID_BURST_MODE : boolean := false; -- only used in VALID_THOLD_G>1 + VALID_THOLD : integer range 0 to (2**24) := 1; -- =1 = normal operation + -- =0 = only when frame ready + -- >1 = only when frame ready or # entries + + -- FIFO configurations + GEN_SYNC_FIFO : boolean := false; + FIFO_ADDR_WIDTH : integer range 4 to 48 := 9; + FIFO_FIXED_THRESH : boolean := true; + FIFO_PAUSE_THRESH : integer range 1 to (2**24) := 1; + SYNTH_MODE : string := "inferred"; + MEMORY_TYPE : string := "block"; + + -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM" + -- WIDE uses wider of slave / master. NARROW uses narrower. + -- CUSOTM uses passed FIFO_DATA_WIDTH_G + INT_WIDTH_SELECT : string := "WIDE"; + INT_DATA_WIDTH : natural range 1 to 16 := 16; + + -- If VALID_THOLD_G /=1, FIFO that stores on tLast txns can be smaller. + -- Set to 0 for same size as primary fifo (default) + -- Set >4 for custom size. + -- Use at own risk. Overflow of tLast fifo is not checked + LAST_FIFO_ADDR_WIDTH : integer range 0 to 48 := 0; + + -- Index = 0 is output, index = n is input + CASCADE_PAUSE_SEL : integer range 0 to (2**24) := 0; + CASCADE_SIZE : integer range 1 to (2**24) := 1); + port ( + -- IP Integrator Slave AXI Stream Interface + S_AXIS_ACLK : in std_logic := '0'; + S_AXIS_ARESETN : in std_logic := '0'; + S_AXIS_TVALID : in std_logic := '0'; + S_AXIS_TDATA : in std_logic_vector((8*S_TDATA_NUM_BYTES)-1 downto 0) := (others => '0'); + S_AXIS_TSTRB : in std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0) := (others => '0'); + S_AXIS_TKEEP : in std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0) := (others => '0'); + S_AXIS_TLAST : in std_logic := '0'; + S_AXIS_TDEST : in std_logic_vector(S_TDEST_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TID : in std_logic_vector(S_TID_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TUSER : in std_logic_vector(S_TUSER_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TREADY : out std_logic; + -- IP Integrator Master AXI Stream Interface + M_AXIS_ACLK : in std_logic := '0'; + M_AXIS_ARESETN : in std_logic := '0'; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector((8*S_TDATA_NUM_BYTES)-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TKEEP : out std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(S_TDEST_WIDTH-1 downto 0); + M_AXIS_TID : out std_logic_vector(S_TID_WIDTH-1 downto 0); + M_AXIS_TUSER : out std_logic_vector(S_TUSER_WIDTH-1 downto 0); + M_AXIS_TREADY : in std_logic := '1'; + -- Misc. Interfaces + fifoPauseThresh : in std_logic_vector(FIFO_ADDR_WIDTH-1 downto 0) := (others => '1'); + fifoWrCnt : out std_logic_vector(FIFO_ADDR_WIDTH-1 downto 0); + fifoFull : out std_logic; + sAxisPause : out std_logic; + sAxisOverflow : out std_logic; + sAxisIdle : out std_logic; + mTLastTUser : out std_logic_vector(7 downto 0)); +end AxiStreamFifoV2IpIntegrator; + +architecture mapping of AxiStreamFifoV2IpIntegrator is + + constant S_AXI_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => ite(S_HAS_TSTRB = 1, true, false), + TDATA_BYTES_C => S_TDATA_NUM_BYTES, + TDEST_BITS_C => S_TDEST_WIDTH, + TID_BITS_C => S_TID_WIDTH, + TKEEP_MODE_C => ite(S_HAS_TKEEP = 1, TKEEP_NORMAL_C, TKEEP_FIXED_C), + TUSER_BITS_C => S_TUSER_WIDTH, + TUSER_MODE_C => TUSER_NORMAL_C); + + constant M_AXI_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => ite(M_HAS_TSTRB = 1, true, false), + TDATA_BYTES_C => M_TDATA_NUM_BYTES, + TDEST_BITS_C => M_TDEST_WIDTH, + TID_BITS_C => M_TID_WIDTH, + TKEEP_MODE_C => ite(M_HAS_TKEEP = 1, TKEEP_NORMAL_C, TKEEP_FIXED_C), + TUSER_BITS_C => M_TUSER_WIDTH, + TUSER_MODE_C => TUSER_NORMAL_C); + + signal sAxisClk : sl := '0'; + signal sAxisRst : sl := '0'; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal sAxisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; + + signal mAxisClk : sl := '0'; + signal mAxisRst : sl := '0'; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => S_INTERFACENAME, + HAS_TLAST => S_HAS_TLAST, + HAS_TKEEP => S_HAS_TKEEP, + HAS_TSTRB => S_HAS_TSTRB, + HAS_TREADY => S_HAS_TREADY, + TUSER_WIDTH => S_TUSER_WIDTH, + TID_WIDTH => S_TID_WIDTH, + TDEST_WIDTH => S_TDEST_WIDTH, + TDATA_NUM_BYTES => S_TDATA_NUM_BYTES) + port map ( + -- IP Integrator AXI Stream Interface + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_ARESETN => S_AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TSTRB => S_AXIS_TSTRB, + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => S_AXIS_TDEST, + S_AXIS_TID => S_AXIS_TID, + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => sAxisClk, + axisRst => sAxisRst, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + U_AxiStreamFifoV2 : entity surf.AxiStreamFifoV2 + generic map ( + RST_ASYNC_G => RST_ASYNC, + INT_PIPE_STAGES_G => INT_PIPE_STAGES, + PIPE_STAGES_G => PIPE_STAGES, + SLAVE_READY_EN_G => ite(S_HAS_TREADY = 1, true, false), + VALID_THOLD_G => VALID_THOLD, + VALID_BURST_MODE_G => VALID_BURST_MODE, + GEN_SYNC_FIFO_G => GEN_SYNC_FIFO, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH, + FIFO_FIXED_THRESH_G => FIFO_FIXED_THRESH, + FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH, + SYNTH_MODE_G => SYNTH_MODE, + MEMORY_TYPE_G => MEMORY_TYPE, + INT_WIDTH_SELECT_G => INT_WIDTH_SELECT, + INT_DATA_WIDTH_G => INT_DATA_WIDTH, + LAST_FIFO_ADDR_WIDTH_G => LAST_FIFO_ADDR_WIDTH, + CASCADE_PAUSE_SEL_G => CASCADE_PAUSE_SEL, + CASCADE_SIZE_G => CASCADE_SIZE, + SLAVE_AXI_CONFIG_G => S_AXI_CONFIG_C, + MASTER_AXI_CONFIG_G => M_AXI_CONFIG_C) + port map ( + -- Slave Port + sAxisClk => sAxisClk, + sAxisRst => sAxisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCtrl => sAxisCtrl, + -- FIFO status & config + fifoPauseThresh => fifoPauseThresh, + fifoWrCnt => fifoWrCnt, + fifoFull => fifoFull, + -- Master Port + mAxisClk => mAxisClk, + mAxisRst => mAxisRst, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + mTLastTUser => mTLastTUser); + + sAxisPause <= sAxisCtrl.pause; + sAxisOverflow <= sAxisCtrl.overflow; + sAxisIdle <= sAxisCtrl.idle; + + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => M_INTERFACENAME, + HAS_TLAST => M_HAS_TLAST, + HAS_TKEEP => M_HAS_TKEEP, + HAS_TSTRB => M_HAS_TSTRB, + HAS_TREADY => M_HAS_TREADY, + TUSER_WIDTH => M_TUSER_WIDTH, + TID_WIDTH => M_TID_WIDTH, + TDEST_WIDTH => M_TDEST_WIDTH, + TDATA_NUM_BYTES => M_TDATA_NUM_BYTES) + port map ( + -- IP Integrator AXI Stream Interface + M_AXIS_ACLK => M_AXIS_ACLK, + M_AXIS_ARESETN => M_AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TSTRB => M_AXIS_TSTRB, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => M_AXIS_TDEST, + M_AXIS_TID => M_AXIS_TID, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => mAxisClk, + axisRst => mAxisRst, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + +end mapping; From 96b2c836d3377e2e421a3e0625fd66424b006f4a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 3 Jul 2023 13:19:13 -0700 Subject: [PATCH 10/32] starting to add test_AxiStreamFifoV2IpIntegrator.py --- axi/axi-stream/ruckus.tcl | 6 +- tests/test_AxiStreamFifoV2IpIntegrator.py | 150 ++++++++++++++++++++++ 2 files changed, 151 insertions(+), 5 deletions(-) create mode 100644 tests/test_AxiStreamFifoV2IpIntegrator.py diff --git a/axi/axi-stream/ruckus.tcl b/axi/axi-stream/ruckus.tcl index ef1310c738..bd040298c4 100644 --- a/axi/axi-stream/ruckus.tcl +++ b/axi/axi-stream/ruckus.tcl @@ -3,11 +3,7 @@ source $::env(RUCKUS_PROC_TCL) # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" - -# Check for non-zero Vivado version (in-case non-Vivado project) -if { $::env(VIVADO_VERSION) > 0.0} { - loadSource -lib surf -dir "$::DIR_PATH/ip_integrator" -} +loadSource -lib surf -dir "$::DIR_PATH/ip_integrator" # Load Simulation loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" diff --git a/tests/test_AxiStreamFifoV2IpIntegrator.py b/tests/test_AxiStreamFifoV2IpIntegrator.py new file mode 100644 index 0000000000..b501f0385d --- /dev/null +++ b/tests/test_AxiStreamFifoV2IpIntegrator.py @@ -0,0 +1,150 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import logging +import random +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamMonitor + +# test_AxiStreamFifoV2IpIntegrator +from cocotb_test.simulator import run +import pytest +import glob +import os + +class TB: + def __init__(self, dut): + + # Pointer to DUT object + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Start S_AXIS_ACLK clock (200 MHz) in a separate thread + cocotb.start_soon(Clock(dut.S_AXIS_ACLK, 5.0, units='ns').start()) + + # Start M_AXIS_ACLK clock (200 MHz) in a separate thread + cocotb.start_soon(Clock(dut.M_AXIS_ACLK, 5.0, units='ns').start()) + + # Setup the AXI stream source + self.source = AxiStreamSource( + bus = AxiStreamBus.from_prefix(dut, "S_AXIS"), + clock = dut.S_AXIS_ACLK, + reset = dut.S_AXIS_ARESETN, + reset_active_level = False, + ) + + # Setup the AXI stream sink + self.sink = AxiStreamSink( + bus = AxiStreamBus.from_prefix(dut, "M_AXIS"), + clock = dut.M_AXIS_ACLK, + reset = dut.M_AXIS_ARESETN, + reset_active_level = False, + ) + + def set_idle_generator(self, generator=None): + if generator: + self.source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.sink.set_pause_generator(generator()) + + async def s_cycle_reset(self): + self.dut.S_AXIS_ARESETN.setimmediatevalue(0) + await RisingEdge(self.dut.S_AXIS_ACLK) + await RisingEdge(self.dut.S_AXIS_ACLK) + self.dut.S_AXIS_ARESETN.value = 0 + await RisingEdge(self.dut.S_AXIS_ACLK) + await RisingEdge(self.dut.S_AXIS_ACLK) + self.dut.S_AXIS_ARESETN.value = 1 + await RisingEdge(self.dut.S_AXIS_ACLK) + await RisingEdge(self.dut.S_AXIS_ACLK) + + async def m_cycle_reset(self): + self.dut.M_AXIS_ARESETN.setimmediatevalue(0) + await RisingEdge(self.dut.M_AXIS_ACLK) + await RisingEdge(self.dut.M_AXIS_ACLK) + self.dut.M_AXIS_ARESETN.value = 0 + await RisingEdge(self.dut.M_AXIS_ACLK) + await RisingEdge(self.dut.M_AXIS_ACLK) + self.dut.M_AXIS_ARESETN.value = 1 + await RisingEdge(self.dut.M_AXIS_ACLK) + await RisingEdge(self.dut.M_AXIS_ACLK) + +async def dut_tb(dut): + + # Initialize the DUT + tb = TB(dut) + + # Reset DUT + await tb.s_cycle_reset() + await tb.m_cycle_reset() + +if cocotb.SIM_NAME: + factory = TestFactory(dut_tb) + factory.generate_tests() + +tests_dir = os.path.dirname(__file__) +tests_module = 'AxiStreamFifoV2IpIntegrator' + +@pytest.mark.parametrize( + "parameters", [ + {'S_TDATA_NUM_BYTES': '1', }, + ]) +def test_AxiStreamFifoV2IpIntegrator(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}', + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # -frelaxed-rules option to allow IP integrator attributes + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], + + # Select a simulator + simulator="ghdl", + + # # Dump waveform to file ($ gtkwave sim_build/AxiStreamFifoV2IpIntegrator/AxiStreamFifoV2IpIntegrator.vcd) + # sim_args =[f'--vcd={tests_module}.vcd'], + ) From 7639ef3eb15c75f6e0eb11966691ccb4b2139447 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 3 Jul 2023 15:38:41 -0700 Subject: [PATCH 11/32] minor fixes to test_AxiVersionIpIntegrator.py --- .../AxiStreamFifoV2IpIntegrator.vhd | 12 +-- tests/test_AxiStreamFifoV2IpIntegrator.py | 102 +++++++++++++----- tests/test_AxiVersionIpIntegrator.py | 6 +- 3 files changed, 85 insertions(+), 35 deletions(-) diff --git a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd index df7bc052cd..bf1eb81b7e 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd @@ -96,13 +96,13 @@ entity AxiStreamFifoV2IpIntegrator is M_AXIS_ACLK : in std_logic := '0'; M_AXIS_ARESETN : in std_logic := '0'; M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector((8*S_TDATA_NUM_BYTES)-1 downto 0); - M_AXIS_TSTRB : out std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0); - M_AXIS_TKEEP : out std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TDATA : out std_logic_vector((8*M_TDATA_NUM_BYTES)-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector(M_TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TKEEP : out std_logic_vector(M_TDATA_NUM_BYTES-1 downto 0); M_AXIS_TLAST : out std_logic; - M_AXIS_TDEST : out std_logic_vector(S_TDEST_WIDTH-1 downto 0); - M_AXIS_TID : out std_logic_vector(S_TID_WIDTH-1 downto 0); - M_AXIS_TUSER : out std_logic_vector(S_TUSER_WIDTH-1 downto 0); + M_AXIS_TDEST : out std_logic_vector(M_TDEST_WIDTH-1 downto 0); + M_AXIS_TID : out std_logic_vector(M_TID_WIDTH-1 downto 0); + M_AXIS_TUSER : out std_logic_vector(M_TUSER_WIDTH-1 downto 0); M_AXIS_TREADY : in std_logic := '1'; -- Misc. Interfaces fifoPauseThresh : in std_logic_vector(FIFO_ADDR_WIDTH-1 downto 0) := (others => '1'); diff --git a/tests/test_AxiStreamFifoV2IpIntegrator.py b/tests/test_AxiStreamFifoV2IpIntegrator.py index b501f0385d..e35d7ca460 100644 --- a/tests/test_AxiStreamFifoV2IpIntegrator.py +++ b/tests/test_AxiStreamFifoV2IpIntegrator.py @@ -9,14 +9,14 @@ ############################################################################## # dut_tb +import itertools import logging -import random import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge from cocotb.regression import TestFactory -from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamMonitor +from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink # test_AxiStreamFifoV2IpIntegrator from cocotb_test.simulator import run @@ -35,25 +35,25 @@ def __init__(self, dut): # Start S_AXIS_ACLK clock (200 MHz) in a separate thread cocotb.start_soon(Clock(dut.S_AXIS_ACLK, 5.0, units='ns').start()) - + # Start M_AXIS_ACLK clock (200 MHz) in a separate thread - cocotb.start_soon(Clock(dut.M_AXIS_ACLK, 5.0, units='ns').start()) + cocotb.start_soon(Clock(dut.M_AXIS_ACLK, 5.0, units='ns').start()) # Setup the AXI stream source self.source = AxiStreamSource( - bus = AxiStreamBus.from_prefix(dut, "S_AXIS"), - clock = dut.S_AXIS_ACLK, + bus = AxiStreamBus.from_prefix(dut, "S_AXIS"), + clock = dut.S_AXIS_ACLK, reset = dut.S_AXIS_ARESETN, reset_active_level = False, ) - + # Setup the AXI stream sink self.sink = AxiStreamSink( - bus = AxiStreamBus.from_prefix(dut, "M_AXIS"), - clock = dut.M_AXIS_ACLK, + bus = AxiStreamBus.from_prefix(dut, "M_AXIS"), + clock = dut.M_AXIS_ACLK, reset = dut.M_AXIS_ARESETN, reset_active_level = False, - ) + ) def set_idle_generator(self, generator=None): if generator: @@ -73,7 +73,7 @@ async def s_cycle_reset(self): self.dut.S_AXIS_ARESETN.value = 1 await RisingEdge(self.dut.S_AXIS_ACLK) await RisingEdge(self.dut.S_AXIS_ACLK) - + async def m_cycle_reset(self): self.dut.M_AXIS_ARESETN.setimmediatevalue(0) await RisingEdge(self.dut.M_AXIS_ACLK) @@ -83,28 +83,78 @@ async def m_cycle_reset(self): await RisingEdge(self.dut.M_AXIS_ACLK) self.dut.M_AXIS_ARESETN.value = 1 await RisingEdge(self.dut.M_AXIS_ACLK) - await RisingEdge(self.dut.M_AXIS_ACLK) + await RisingEdge(self.dut.M_AXIS_ACLK) -async def dut_tb(dut): +async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): - # Initialize the DUT tb = TB(dut) - # Reset DUT + id_count = 2**len(tb.source.bus.tid) + + cur_id = 1 + await tb.s_cycle_reset() await tb.m_cycle_reset() + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for test_data in [payload_data(x) for x in payload_lengths()]: + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id + test_frame.tdest = cur_id + await tb.source.send(test_frame) + + test_frames.append(test_frame) + + cur_id = (cur_id + 1) % id_count + + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + +def size_list(): + return list(range(1, 32+1)) + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + if cocotb.SIM_NAME: - factory = TestFactory(dut_tb) + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) factory.generate_tests() tests_dir = os.path.dirname(__file__) tests_module = 'AxiStreamFifoV2IpIntegrator' -@pytest.mark.parametrize( - "parameters", [ - {'S_TDATA_NUM_BYTES': '1', }, - ]) +############################################################################## + +paramSweep = [] +for sTdataByte in ['2','6']: + for mTdataByte in ['2','6']: + tmpDict = { + "M_TDATA_NUM_BYTES": mTdataByte, + "S_TDATA_NUM_BYTES": sTdataByte, + } + paramSweep.append(tmpDict) + +############################################################################## + +@pytest.mark.parametrize("parameters", paramSweep) def test_AxiStreamFifoV2IpIntegrator(parameters): # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun @@ -132,19 +182,19 @@ def test_AxiStreamFifoV2IpIntegrator(parameters): parameters = parameters, # The directory used to compile the tests. (default: sim_build) - sim_build = f'{tests_dir}/sim_build/{tests_module}', + sim_build = f'{tests_dir}/sim_build/{tests_module}.' + ",".join((f"{key}={value}" for key, value in parameters.items())), # A dictionary of extra environment variables set in simulator process. extra_env=parameters, + # Select a simulator + simulator="ghdl", + # use of synopsys package "std_logic_arith" needs the -fsynopsys option # -frelaxed-rules option to allow IP integrator attributes # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], - # Select a simulator - simulator="ghdl", - - # # Dump waveform to file ($ gtkwave sim_build/AxiStreamFifoV2IpIntegrator/AxiStreamFifoV2IpIntegrator.vcd) - # sim_args =[f'--vcd={tests_module}.vcd'], + # Dump waveform to file ($ gtkwave sim_build/AxiStreamFifoV2IpIntegrator/AxiStreamFifoV2IpIntegrator.vcd) + sim_args =[f'--vcd={tests_module}.vcd'], ) diff --git a/tests/test_AxiVersionIpIntegrator.py b/tests/test_AxiVersionIpIntegrator.py index eb4a668f42..520ea76dc6 100644 --- a/tests/test_AxiVersionIpIntegrator.py +++ b/tests/test_AxiVersionIpIntegrator.py @@ -123,13 +123,13 @@ def test_AxiVersionIpIntegrator(parameters): # A dictionary of extra environment variables set in simulator process. extra_env=parameters, + # Select a simulator + simulator="ghdl", + # use of synopsys package "std_logic_arith" needs the -fsynopsys option # -frelaxed-rules option to allow IP integrator attributes vhdl_compile_args = ['-fsynopsys','-frelaxed-rules'], - # Select a simulator - simulator="ghdl", - # Dump waveform to file ($ gtkwave sim_build/AxiVersionIpIntegrator/AxiVersionIpIntegrator.vcd) sim_args =[f'--vcd={tests_module}.vcd'], ) From 2085284e2ac83eb659e5e817f8d9fa04cfafb970 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 3 Jul 2023 15:41:16 -0700 Subject: [PATCH 12/32] updating ruckus submodule lock due to cocoTB/GHDL deps --- ruckus.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ruckus.tcl b/ruckus.tcl index c136ab983e..6238316e6b 100644 --- a/ruckus.tcl +++ b/ruckus.tcl @@ -3,7 +3,7 @@ source $::env(RUCKUS_PROC_TCL) # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { - if { [SubmoduleCheck {ruckus} {4.8.2} ] < 0 } {exit -1} + if { [SubmoduleCheck {ruckus} {4.8.4} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0" From dea525736b6538f30299b028da11ebb02225e69a Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Thu, 6 Jul 2023 14:14:10 -0700 Subject: [PATCH 13/32] Remove MemoryDevices from surf --- python/surf/devices/microchip/_Axi24LC64FT.py | 12 +++++++++--- python/surf/devices/micron/_DdrSpd.py | 15 +++++++-------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/python/surf/devices/microchip/_Axi24LC64FT.py b/python/surf/devices/microchip/_Axi24LC64FT.py index d2c532d6c5..dab5e6993c 100644 --- a/python/surf/devices/microchip/_Axi24LC64FT.py +++ b/python/surf/devices/microchip/_Axi24LC64FT.py @@ -28,9 +28,15 @@ def __init__(self, # Variables ############################## if (instantiate): - pr.MemoryDevice( + self.add(pr.RemoteVariable( name = "Mem", description = "Memory Array", size = (4*nelms), - # nelms = nelms, - ) + numValues = nelms, + valueBits = 32, + valueStride = 32, + bitSize = 32 * nelms, + # mode = "RO", + )) + + diff --git a/python/surf/devices/micron/_DdrSpd.py b/python/surf/devices/micron/_DdrSpd.py index b5d119e59b..889b685072 100644 --- a/python/surf/devices/micron/_DdrSpd.py +++ b/python/surf/devices/micron/_DdrSpd.py @@ -24,16 +24,15 @@ def __init__( self, **kwargs): super().__init__(description=description, hidden=hidden, **kwargs) - ############################## - # Variables - ############################## if (instantiate): - pr.MemoryDevice( + self.add(pr.RemoteVariable( name = "Mem", description = "Memory Array", size = (4*nelms), - # nelms = nelms, + numValues = nelms, + valueBits = 32, + valueStride = 32, + bitSize = 32 * nelms, # mode = "RO", - wordBitSize = 8, - # bitSize = 8, - ) + )) + From 5e68d0e1e8ddc6096143a660f7972554bb1f7c10 Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Thu, 6 Jul 2023 14:26:57 -0700 Subject: [PATCH 14/32] Remove legacy support' --- .../surf/devices/micron/_AxiMicronMt28ew.py | 242 ++-- python/surf/devices/micron/_AxiMicronN25Q.py | 188 ++- python/surf/devices/micron/_AxiMicronP30.py | 249 ++-- python/surf/devices/silabs/_Si5324.py | 52 +- python/surf/devices/silabs/_Si5326.py | 52 +- python/surf/devices/silabs/_Si5345Lite.py | 16 +- python/surf/devices/silabs/_Si5394Lite.py | 17 +- python/surf/devices/ti/_Adc32Rf45.py | 1173 ++++++----------- python/surf/devices/ti/_Lmx2615.py | 53 +- 9 files changed, 750 insertions(+), 1292 deletions(-) diff --git a/python/surf/devices/micron/_AxiMicronMt28ew.py b/python/surf/devices/micron/_AxiMicronMt28ew.py index 66c94aeef3..99e7b1f8a4 100644 --- a/python/surf/devices/micron/_AxiMicronMt28ew.py +++ b/python/surf/devices/micron/_AxiMicronMt28ew.py @@ -28,16 +28,8 @@ def __init__(self, hidden = True, **kwargs): - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (0x1 << 12) - super().__init__( description = description, - size = size, hidden = hidden, **kwargs) @@ -48,76 +40,74 @@ def __init__(self, ############################## # Setup variables ############################## - if self._useVars: - - self.add(pr.RemoteVariable(name='DataWrBus', - offset=0x0, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='AddrBus', - offset=0x4, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='DataRdBus', - offset=0x8, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='TranSize', - offset=0x80, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='BurstTran', - offset=0x84, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='BurstData', - offset=0x400, - base=pr.UInt, - bitSize=32*256, - bitOffset=0, - numValues=256, - valueBits=32, - valueStride=32, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) + self.add(pr.RemoteVariable(name='DataWrBus', + offset=0x0, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='AddrBus', + offset=0x4, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='DataRdBus', + offset=0x8, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='TranSize', + offset=0x80, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='BurstTran', + offset=0x84, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='BurstData', + offset=0x400, + base=pr.UInt, + bitSize=32*256, + bitOffset=0, + numValues=256, + valueBits=32, + valueStride=32, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) @self.command(value='',description="Load the .MCS into PROM",) def LoadMcsFile(arg): @@ -203,16 +193,10 @@ def writeProm(self): # Reset the PROM self._resetCmd() # Create a burst data array - if self._useVars: - dataArray = self.BurstData.get(read=False) - else: - dataArray = [0] * 256 + dataArray = self.BurstData.get(read=False) # Set the block transfer size - if self._useVars: - self.TranSize.set(0xFF) - else: - self._rawWrite(0x80,0xFF,tryCount=self._tryCount) # Deprecated + self.TranSize.set(0xFF) # Setup the status bar with click.progressbar( @@ -238,17 +222,10 @@ def writeProm(self): # Check for the last byte if ( cnt == 256 ): - if self._useVars: - # Write burst data - self.BurstData.set(dataArray) - # Start a burst transfer - self.BurstTran.set(0x7FFFFFFF&addr) - - else: - # Write burst data - self._rawWrite(offset=0x400, data=dataArray,tryCount=self._tryCount) # Deprecated - # Start a burst transfer - self._rawWrite(offset=0x84, data=0x7FFFFFFF&addr,tryCount=self._tryCount) # Deprecated + # Write burst data + self.BurstData.set(dataArray) + # Start a burst transfer + self.BurstTran.set(0x7FFFFFFF&addr) # Check for leftover data if (cnt != 256): @@ -256,17 +233,10 @@ def writeProm(self): for i in range(cnt, 256): dataArray[i] = 0xFFFF - if self._useVars: - # Write burst data - self.BurstData.set(dataArray) - # Start a burst transfer - self.BurstTran.set(0x7FFFFFFF&addr) - - else: - # Write burst data - self._rawWrite(offset=0x400, data=dataArray,tryCount=self._tryCount) # Deprecated - # Start a burst transfer - self._rawWrite(offset=0x84, data=0x7FFFFFFF&addr,tryCount=self._tryCount) # Deprecated + # Write burst data + self.BurstData.set(dataArray) + # Start a burst transfer + self.BurstTran.set(0x7FFFFFFF&addr) # Close the status bar bar.update(self._mcs.size) @@ -275,16 +245,10 @@ def verifyProm(self): # Reset the PROM self._resetCmd() - if self._useVars: - # Set the data bus - self.DataWrBus.set(0xFFFFFFFF) - # Set the block transfer size - self.TranSize.set(0xFF) - else: - # Set the data bus - self._rawWrite(offset=0x0, data=0xFFFFFFFF,tryCount=self._tryCount) # Deprecated - # Set the block transfer size - self._rawWrite(offset=0x80, data=0xFF,tryCount=self._tryCount) # Deprecated + # Set the data bus + self.DataWrBus.set(0xFFFFFFFF) + # Set the block transfer size + self.TranSize.set(0xFF) # Setup the status bar with click.progressbar( @@ -301,18 +265,12 @@ def verifyProm(self): # Throttle down printf rate bar.update(0x1FF) - if self._useVars: - # Start a burst transfer - self.BurstTran.set(0x80000000|addr) + # Start a burst transfer + self.BurstTran.set(0x80000000|addr) - # Get the data - dataArray = self.BurstData.get() + # Get the data + dataArray = self.BurstData.get() - else: - # Start a burst transfer - self._rawWrite(offset=0x84, data=0x80000000|addr,tryCount=self._tryCount) # Deprecated - # Get the data - dataArray = self._rawRead(offset=0x400,numWords=256,tryCount=self._tryCount) # Deprecated else: # Get the data for MCS file data |= (int(self._mcs.entry[i][1]) << 8) @@ -327,26 +285,14 @@ def verifyProm(self): # Generic FLASH write Command def _writeToFlash(self, addr, data): - if self._useVars: - # Set the data bus - self.DataWrBus.set(data) - # Set the address bus and initiate the transfer - self.AddrBus.set(addr&0x7FFFFFFF) - else: - # Set the data bus - self._rawWrite(offset=0x0, data=data,tryCount=self._tryCount) # Deprecated - # Set the address bus and initiate the transfer - self._rawWrite(offset=0x4,data=addr&0x7FFFFFFF,tryCount=self._tryCount) # Deprecated + # Set the data bus + self.DataWrBus.set(data) + # Set the address bus and initiate the transfer + self.AddrBus.set(addr&0x7FFFFFFF) # Generic FLASH read Command def _readFromFlash(self, addr): - if self._useVars: - # Set the address - self.AddrBus.set(addr|0x80000000) - # Get the read data - return self.DataRdBus.get()&0xFFFF - else: - # Set the address - self._rawWrite(offset=0x4, data=addr|0x80000000,tryCount=self._tryCount) # Deprecated - # Get the read data - return (self._rawRead(offset=0x8,tryCount=self._tryCount)&0xFFFF) # Deprecated + # Set the address + self.AddrBus.set(addr|0x80000000) + # Get the read data + return self.DataRdBus.get()&0xFFFF diff --git a/python/surf/devices/micron/_AxiMicronN25Q.py b/python/surf/devices/micron/_AxiMicronN25Q.py index 783d40e70e..0bdb3db7c7 100644 --- a/python/surf/devices/micron/_AxiMicronN25Q.py +++ b/python/surf/devices/micron/_AxiMicronN25Q.py @@ -29,16 +29,8 @@ def __init__(self, hidden = True, **kwargs): - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (0x1 << 10) - super().__init__( description = description, - size = size, hidden = hidden, **kwargs) @@ -50,75 +42,73 @@ def __init__(self, ############################## # Setup variables ############################## - if self._useVars: - - self.add(pr.RemoteVariable( - name = 'PasswordLock', - offset = 0x00, - base = pr.UInt, - bitSize = 32, - bitOffset = 0, - retryCount = tryCount, - updateNotify= False, - bulkOpEn = False, - hidden = True, - verify = False, - )) - - self.add(pr.RemoteVariable( - name = 'ModeReg', - offset = 0x04, - base = pr.UInt, - bitSize = 32, - bitOffset = 0, - retryCount = tryCount, - updateNotify= False, - bulkOpEn = False, - hidden = True, - verify = False, - )) - - self.add(pr.RemoteVariable( - name = 'AddrReg', - offset = 0x08, - base = pr.UInt, - bitSize = 32, - bitOffset = 0, - retryCount = tryCount, - updateNotify= False, - bulkOpEn = False, - hidden = True, - verify = False, - )) - - self.add(pr.RemoteVariable( - name = 'CmdReg', - offset = 0x0C, - base = pr.UInt, - bitSize = 32, - bitOffset = 0, - retryCount = tryCount, - updateNotify= False, - bulkOpEn = False, - hidden = True, - verify = False, - )) - - self.add(pr.RemoteVariable( - name = 'DataReg', - offset = 0x200, - base = pr.UInt, - bitSize = 32*64, - bitOffset = 0, - numValues = 64, - valueBits = 32, - valueStride = 32, - retryCount = tryCount, - updateNotify= False, - bulkOpEn = False, - hidden = True, - verify = False, - )) + self.add(pr.RemoteVariable( + name = 'PasswordLock', + offset = 0x00, + base = pr.UInt, + bitSize = 32, + bitOffset = 0, + retryCount = tryCount, + updateNotify= False, + bulkOpEn = False, + hidden = True, + verify = False, + )) + + self.add(pr.RemoteVariable( + name = 'ModeReg', + offset = 0x04, + base = pr.UInt, + bitSize = 32, + bitOffset = 0, + retryCount = tryCount, + updateNotify= False, + bulkOpEn = False, + hidden = True, + verify = False, + )) + + self.add(pr.RemoteVariable( + name = 'AddrReg', + offset = 0x08, + base = pr.UInt, + bitSize = 32, + bitOffset = 0, + retryCount = tryCount, + updateNotify= False, + bulkOpEn = False, + hidden = True, + verify = False, + )) + + self.add(pr.RemoteVariable( + name = 'CmdReg', + offset = 0x0C, + base = pr.UInt, + bitSize = 32, + bitOffset = 0, + retryCount = tryCount, + updateNotify= False, + bulkOpEn = False, + hidden = True, + verify = False, + )) + + self.add(pr.RemoteVariable( + name = 'DataReg', + offset = 0x200, + base = pr.UInt, + bitSize = 32*64, + bitOffset = 0, + numValues = 64, + valueBits = 32, + valueStride = 32, + retryCount = tryCount, + updateNotify= False, + bulkOpEn = False, + hidden = True, + verify = False, + )) ############################## # Constants @@ -253,10 +243,7 @@ def writeProm(self): wordCnt = 0 byteCnt = 0 # Create a burst data array - if self._useVars: - dataArray = self.getDataReg(read=False) - else: - dataArray = [0] * 64 + dataArray = self.getDataReg(read=False) # Setup the status bar with click.progressbar( length = self._mcs.size, @@ -441,46 +428,25 @@ def waitForFlashReady(self): break ######################################### - # All the rawWrite and rawRead commands # + # Command wrappers ######################################### def setModeReg(self): - if self._useVars: - if (self._addrMode): - self.ModeReg.set(value=0x1) - else: - self.ModeReg.set(value=0x0) + if (self._addrMode): + self.ModeReg.set(value=0x1) else: - if (self._addrMode): - self._rawWrite(offset=0x04,data=0x1,tryCount=self._tryCount) # Deprecated - else: - self._rawWrite(offset=0x04,data=0x0,tryCount=self._tryCount) # Deprecated + self.ModeReg.set(value=0x0) def setAddrReg(self,value): - if self._useVars: - self.AddrReg.set(value=value) - else: - self._rawWrite(offset=0x08,data=value,tryCount=self._tryCount) # Deprecated + self.AddrReg.set(value=value) def setCmdReg(self,value): - if self._useVars: - self.CmdReg.set(value=value) - else: - self._rawWrite(offset=0x0C,data=value,tryCount=self._tryCount) # Deprecated + self.CmdReg.set(value=value) def getCmdReg(self): - if self._useVars: - return self.CmdReg.get() - else: - return (self._rawRead(offset=0x0C,tryCount=self._tryCount)) # Deprecated + return self.CmdReg.get() def setDataReg(self,values): - if self._useVars: - self.DataReg.set(values) - else: - self._rawWrite(offset=0x200,data=values,tryCount=self._tryCount) # Deprecated + self.DataReg.set(values) def getDataReg(self,read=True): - if self._useVars: - return self.DataReg.get(read=read) - else: - return (self._rawRead(offset=0x200,numWords=64,tryCount=self._tryCount)) # Deprecated + return self.DataReg.get(read=read) diff --git a/python/surf/devices/micron/_AxiMicronP30.py b/python/surf/devices/micron/_AxiMicronP30.py index a9865f505f..089bc2a690 100644 --- a/python/surf/devices/micron/_AxiMicronP30.py +++ b/python/surf/devices/micron/_AxiMicronP30.py @@ -28,16 +28,8 @@ def __init__(self, hidden = True, **kwargs): - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (0x1 << 12) - super().__init__( description = description, - size = size, hidden = hidden, **kwargs) @@ -48,76 +40,74 @@ def __init__(self, ############################## # Setup variables ############################## - if self._useVars: - - self.add(pr.RemoteVariable(name='DataWrBus', - offset=0x0, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='AddrBus', - offset=0x4, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='DataRdBus', - offset=0x8, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='TranSize', - offset=0x80, - base=pr.UInt, - bitSize=8, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='BurstTran', - offset=0x84, - base=pr.UInt, - bitSize=32, - bitOffset=0, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) - - self.add(pr.RemoteVariable(name='BurstData', - offset=0x400, - base=pr.UInt, - bitSize=32*256, - bitOffset=0, - numValues=256, - valueBits=32, - valueStride=32, - retryCount=tryCount, - updateNotify=False, - bulkOpEn=False, - hidden=True, - verify=False)) + self.add(pr.RemoteVariable(name='DataWrBus', + offset=0x0, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='AddrBus', + offset=0x4, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='DataRdBus', + offset=0x8, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='TranSize', + offset=0x80, + base=pr.UInt, + bitSize=8, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='BurstTran', + offset=0x84, + base=pr.UInt, + bitSize=32, + bitOffset=0, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) + + self.add(pr.RemoteVariable(name='BurstData', + offset=0x400, + base=pr.UInt, + bitSize=32*256, + bitOffset=0, + numValues=256, + valueBits=32, + valueStride=32, + retryCount=tryCount, + updateNotify=False, + bulkOpEn=False, + hidden=True, + verify=False)) @self.command(value='',description="Load the .MCS into PROM",) def LoadMcsFile(arg): @@ -207,16 +197,10 @@ def _eraseCmd(self, address): def writeProm(self): # Create a burst data array - if self._useVars: - dataArray = self.BurstData.get(read=False) - else: - dataArray = [0] * 256 + dataArray = self.BurstData.get(read=False) # Set the block transfer size - if self._useVars: - self.TranSize.set(0xFF) - else: - self._rawWrite(0x80,0xFF,tryCount=self._tryCount) # Deprecated + self.TranSize.set(0xFF) # Setup the status bar with click.progressbar( @@ -242,50 +226,30 @@ def writeProm(self): # Check for the last byte if ( cnt == 256 ): - if self._useVars: - # Write burst data - self.BurstData.set(dataArray) - # Start a burst transfer - self.BurstTran.set(0x7FFFFFFF&addr) - - else: - # Write burst data - self._rawWrite(offset=0x400, data=dataArray,tryCount=self._tryCount) # Deprecated - # Start a burst transfer - self._rawWrite(offset=0x84, data=0x7FFFFFFF&addr,tryCount=self._tryCount) # Deprecated + # Write burst data + self.BurstData.set(dataArray) + # Start a burst transfer + self.BurstTran.set(0x7FFFFFFF&addr) if (cnt != 256): # Fill the rest of the data array with ones for i in range(cnt, 256): dataArray[i] = 0xFFFF - if self._useVars: - # Write burst data - self.BurstData.set(dataArray) - # Start a burst transfer - self.BurstTran.set(0x7FFFFFFF&addr) - - else: - # Write burst data - self._rawWrite(offset=0x400, data=dataArray,tryCount=self._tryCount) # Deprecated - # Start a burst transfer - self._rawWrite(offset=0x84, data=0x7FFFFFFF&addr,tryCount=self._tryCount) # Deprecated + # Write burst data + self.BurstData.set(dataArray) + # Start a burst transfer + self.BurstTran.set(0x7FFFFFFF&addr) # Close the status bar bar.update(self._mcs.size) def verifyProm(self): - if self._useVars: - # Set the data bus - self.DataWrBus.set(0xFFFFFFFF) - # Set the block transfer size - self.TranSize.set(0xFF) - else: - # Set the data bus - self._rawWrite(offset=0x0, data=0xFFFFFFFF,tryCount=self._tryCount) # Deprecated - # Set the block transfer size - self._rawWrite(offset=0x80, data=0xFF,tryCount=self._tryCount) # Deprecated + # Set the data bus + self.DataWrBus.set(0xFFFFFFFF) + # Set the block transfer size + self.TranSize.set(0xFF) # Setup the status bar with click.progressbar( @@ -302,18 +266,11 @@ def verifyProm(self): # Throttle down printf rate bar.update(0x1FF) - if self._useVars: - # Start a burst transfer - self.BurstTran.set(0x80000000|addr) - - # Get the data - dataArray = self.BurstData.get() + # Start a burst transfer + self.BurstTran.set(0x80000000|addr) - else: - # Start a burst transfer - self._rawWrite(offset=0x84, data=0x80000000|addr,tryCount=self._tryCount) # Deprecated - # Get the data - dataArray = self._rawRead(offset=0x400,numWords=256,tryCount=self._tryCount) # Deprecated + # Get the data + dataArray = self.BurstData.get() else: # Get the data for MCS file @@ -329,30 +286,16 @@ def verifyProm(self): # Generic FLASH write Command def _writeToFlash(self, addr, cmd, data): - if self._useVars: - # Set the data bus - self.DataWrBus.set(((cmd&0xFFFF)<< 16) | (data&0xFFFF)) - # Set the address bus and initiate the transfer - self.AddrBus.set(addr&0x7FFFFFFF) - else: - # Set the data bus - self._rawWrite(offset=0x0, data=((cmd&0xFFFF)<< 16) | (data&0xFFFF),tryCount=self._tryCount) # Deprecated - # Set the address bus and initiate the transfer - self._rawWrite(offset=0x4,data=addr&0x7FFFFFFF,tryCount=self._tryCount) # Deprecated + # Set the data bus + self.DataWrBus.set(((cmd&0xFFFF)<< 16) | (data&0xFFFF)) + # Set the address bus and initiate the transfer + self.AddrBus.set(addr&0x7FFFFFFF) # Generic FLASH read Command def _readFromFlash(self, addr, cmd): - if self._useVars: - # Set the data bus - self.DataWrBus.set(((cmd&0xFFFF)<< 16) | 0xFF) - # Set the address - self.AddrBus.set(addr|0x80000000) - # Get the read data - return self.DataRdBus.get()&0xFFFF - else: - # Set the data bus - self._rawWrite(offset=0x0, data=((cmd&0xFFFF)<< 16) | 0xFF,tryCount=self._tryCount) # Deprecated - # Set the address - self._rawWrite(offset=0x4, data=addr|0x80000000,tryCount=self._tryCount) # Deprecated - # Get the read data - return (self._rawRead(offset=0x8,tryCount=self._tryCount)&0xFFFF) # Deprecated + # Set the data bus + self.DataWrBus.set(((cmd&0xFFFF)<< 16) | 0xFF) + # Set the address + self.AddrBus.set(addr|0x80000000) + # Get the read data + return self.DataRdBus.get()&0xFFFF diff --git a/python/surf/devices/silabs/_Si5324.py b/python/surf/devices/silabs/_Si5324.py index 098667a2f7..4e28209150 100644 --- a/python/surf/devices/silabs/_Si5324.py +++ b/python/surf/devices/silabs/_Si5324.py @@ -15,34 +15,25 @@ class Si5324(pr.Device): def __init__(self,**kwargs): + super().__init__(**kwargs) - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (0x100 << 2) # 1KB - - super().__init__(size=size, **kwargs) - - if self._useVars: - self.add(pr.RemoteVariable( - name = "DataBlock", - description = "", - offset = 0, - bitSize = 32 * 0x100, - bitOffset = 0, - numValues = 0x100, - valueBits = 32, - valueStride = 32, - updateNotify = True, - bulkOpEn = True, - overlapEn = True, - verify = True, - hidden = True, - base = pr.UInt, - mode = "RW", - )) + self.add(pr.RemoteVariable( + name = "DataBlock", + description = "", + offset = 0, + bitSize = 32 * 0x100, + bitOffset = 0, + numValues = 0x100, + valueBits = 32, + valueStride = 32, + updateNotify = True, + bulkOpEn = True, + overlapEn = True, + verify = True, + hidden = True, + base = pr.UInt, + mode = "RW", + )) self.add(pr.LocalVariable( name = "TxtFilePath", @@ -1147,8 +1138,5 @@ def LoadTxtFile(arg): )) def _setValue(self,offset,data): - if self._useVars: - # Note: index is byte index (not word index) - self.DataBlock.set(value=data,index=(offset%0x400)>>2) - else: - self._rawWrite(offset,data) # Deprecated + # Note: index is byte index (not word index) + self.DataBlock.set(value=data,index=(offset%0x400)>>2) diff --git a/python/surf/devices/silabs/_Si5326.py b/python/surf/devices/silabs/_Si5326.py index ea9453a734..288efdc247 100644 --- a/python/surf/devices/silabs/_Si5326.py +++ b/python/surf/devices/silabs/_Si5326.py @@ -15,34 +15,25 @@ class Si5326(pr.Device): def __init__(self,**kwargs): + super().__init__(**kwargs) - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (0x100 << 2) # 1KB - - super().__init__(size=size, **kwargs) - - if self._useVars: - self.add(pr.RemoteVariable( - name = "DataBlock", - description = "", - offset = 0, - bitSize = 32 * 0x100, - bitOffset = 0, - numValues = 0x100, - valueBits = 32, - valueStride = 32, - updateNotify = True, - bulkOpEn = True, - overlapEn = True, - verify = True, - hidden = True, - base = pr.UInt, - mode = "RW", - )) + self.add(pr.RemoteVariable( + name = "DataBlock", + description = "", + offset = 0, + bitSize = 32 * 0x100, + bitOffset = 0, + numValues = 0x100, + valueBits = 32, + valueStride = 32, + updateNotify = True, + bulkOpEn = True, + overlapEn = True, + verify = True, + hidden = True, + base = pr.UInt, + mode = "RW", + )) self.add(pr.LocalVariable( name = "TxtFilePath", @@ -1214,8 +1205,5 @@ def LoadTxtFile(arg): )) def _setValue(self,offset,data): - if self._useVars: - # Note: index is byte index (not word index) - self.DataBlock.set(value=data,index=(offset%0x400)>>2) - else: - self._rawWrite(offset,data) # Deprecated + # Note: index is byte index (not word index) + self.DataBlock.set(value=data,index=(offset%0x400)>>2) diff --git a/python/surf/devices/silabs/_Si5345Lite.py b/python/surf/devices/silabs/_Si5345Lite.py index a704ee24d2..66573f4f69 100644 --- a/python/surf/devices/silabs/_Si5345Lite.py +++ b/python/surf/devices/silabs/_Si5345Lite.py @@ -22,14 +22,7 @@ def __init__(self, liteVersion = True, **kwargs): - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (0x1000 << 2) # 16KB - - super().__init__(size=size, **kwargs) + super().__init__(**kwargs) self.add(pr.LocalVariable( name = "CsvFilePath", @@ -117,8 +110,5 @@ def LoadCsvFile(arg): )) def _setValue(self,offset,data): - if self._useVars: - # Note: index is byte index (not word index) - self._pages[offset // 0x400].DataBlock.set(value=data,index=(offset%0x400)>>2) - else: - self._rawWrite(offset,data) # Deprecated + # Note: index is byte index (not word index) + self._pages[offset // 0x400].DataBlock.set(value=data,index=(offset%0x400)>>2) diff --git a/python/surf/devices/silabs/_Si5394Lite.py b/python/surf/devices/silabs/_Si5394Lite.py index 0ef716bec7..6dd967d704 100644 --- a/python/surf/devices/silabs/_Si5394Lite.py +++ b/python/surf/devices/silabs/_Si5394Lite.py @@ -23,15 +23,7 @@ def __init__(self, liteVersion = True, **kwargs): - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - # self._useVars = False - - if self._useVars: - size = 0 - else: - size = 0x10000 # 64KB - - super().__init__(size=size, **kwargs) + super().__init__(**kwargs) self.add(pr.LocalVariable( name = "CsvFilePath", @@ -129,8 +121,5 @@ def LoadCsvFile(arg): )) def _setValue(self,offset,data): - if self._useVars: - # Note: index is byte index (not word index) - self._pages[offset // 0x400].DataBlock.set(value=data,index=(offset%0x400)>>2) - else: - self._rawWrite(offset,data) # Deprecated + # Note: index is byte index (not word index) + self._pages[offset // 0x400].DataBlock.set(value=data,index=(offset%0x400)>>2) diff --git a/python/surf/devices/ti/_Adc32Rf45.py b/python/surf/devices/ti/_Adc32Rf45.py index bc9abf9322..ecb8dbdf6e 100644 --- a/python/surf/devices/ti/_Adc32Rf45.py +++ b/python/surf/devices/ti/_Adc32Rf45.py @@ -18,17 +18,7 @@ class Adc32Rf45(pr.Device): def __init__( self, verify=True, **kwargs): - - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (0x1 << 19) - - super().__init__( - size = size, - **kwargs) + super().__init__(**kwargs) ################ # Base addresses @@ -57,36 +47,33 @@ def __init__( self, verify=True, **kwargs): ################## # General Register ################## - - if self._useVars: - - self.add(pr.RemoteVariable(name='GeneralAddr0', - offset = generalAddr + (4*0x0000), # 0x00000 - 0x00FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - overlapEn = True, - verify = False)) - - self.add(pr.RemoteVariable(name='GeneralAddr4', - offset = generalAddr + (4*0x4000), # 0x08000 - 0x08FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - overlapEn = False, - verify = False)) + self.add(pr.RemoteVariable(name='GeneralAddr0', + offset = generalAddr + (4*0x0000), # 0x00000 - 0x00FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + overlapEn = True, + verify = False)) + + self.add(pr.RemoteVariable(name='GeneralAddr4', + offset = generalAddr + (4*0x4000), # 0x08000 - 0x08FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + overlapEn = False, + verify = False)) self.add(pr.RemoteCommand( name = "RESET", @@ -110,148 +97,139 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", hidden = True, - overlapEn = (not self._useVars), )) ################## # Offset Corrector ################## - if self._useVars: - - self.add(pr.RemoteVariable(name='OffsetCorrectorA', - offset = offsetCorrector + chA, # 0x04000 - 0x04FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - self.add(pr.RemoteVariable(name='OffsetCorrectorB', - offset = offsetCorrector + chB, # 0x24000 - 0x24FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) + self.add(pr.RemoteVariable(name='OffsetCorrectorA', + offset = offsetCorrector + chA, # 0x04000 - 0x04FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + verify = False)) + + self.add(pr.RemoteVariable(name='OffsetCorrectorB', + offset = offsetCorrector + chB, # 0x24000 - 0x24FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + verify = False)) ################## # Main Digital ################## - if self._useVars: - - self.add(pr.RemoteVariable(name='MainDigitalA', - offset = mainDigital + chA, # 0x0C000 - 0x0CFFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - self.add(pr.RemoteVariable(name='MainDigitalB', - offset = mainDigital + chB, # 0x2C000 - 0x2CFFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) + self.add(pr.RemoteVariable(name='MainDigitalA', + offset = mainDigital + chA, # 0x0C000 - 0x0CFFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + verify = False)) + + self.add(pr.RemoteVariable(name='MainDigitalB', + offset = mainDigital + chB, # 0x2C000 - 0x2CFFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + verify = False)) ################## # JSESD Digital ################## - if self._useVars: - - self.add(pr.RemoteVariable(name='JesdDigitalA', - offset = jesdDigital + chA, # 0x10000 - 0x10FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - self.add(pr.RemoteVariable(name='JesdDigitalB', - offset = jesdDigital + chB, # 0x30000 - 0x30FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) + self.add(pr.RemoteVariable(name='JesdDigitalA', + offset = jesdDigital + chA, # 0x10000 - 0x10FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + verify = False)) + + self.add(pr.RemoteVariable(name='JesdDigitalB', + offset = jesdDigital + chB, # 0x30000 - 0x30FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + verify = False)) ################## # Raw Interface ################## - if self._useVars: - - self.add(pr.RemoteVariable(name='RawInterface0', - offset = rawInterface + (4*0x0000), # 0x40000 - 0x40FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - overlapEn = False, - verify = False)) - - self.add(pr.RemoteVariable(name='RawInterface4', - offset = rawInterface + (4*0x4000), # 0x50000 - 0x50FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - overlapEn = False, - verify = False)) - - self.add(pr.RemoteVariable(name='RawInterface6', - offset = rawInterface + (4*0x6000), # 0x58000 - 0x58FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - overlapEn = False, - verify = False)) + self.add(pr.RemoteVariable(name='RawInterface0', + offset = rawInterface + (4*0x0000), # 0x40000 - 0x40FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + overlapEn = False, + verify = False)) + + self.add(pr.RemoteVariable(name='RawInterface4', + offset = rawInterface + (4*0x4000), # 0x50000 - 0x50FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + overlapEn = False, + verify = False)) + + self.add(pr.RemoteVariable(name='RawInterface6', + offset = rawInterface + (4*0x6000), # 0x58000 - 0x58FFF + base = pr.UInt, + bitSize = 32*0x400, # 4KBytes + bitOffset = 0, + numValues = 0x400, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + hidden = True, + overlapEn = False, + verify = False)) ############# # Master Page @@ -265,7 +243,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -277,7 +254,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -289,7 +265,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -301,7 +276,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -315,7 +289,6 @@ def __init__( self, verify=True, **kwargs): value = 0x1, hidden = True, verify = False, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -329,7 +302,6 @@ def __init__( self, verify=True, **kwargs): value = 0x1, hidden = True, verify = False, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -341,7 +313,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -353,7 +324,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -365,7 +335,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -377,7 +346,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -389,7 +357,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -401,7 +368,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -413,7 +379,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -425,7 +390,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -437,7 +401,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) # ########## @@ -452,7 +415,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) self.add(pr.RemoteVariable( @@ -464,7 +426,6 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", verify = verify, - overlapEn = (not self._useVars), )) @@ -473,565 +434,286 @@ def __init__( self, verify=True, **kwargs): ############################## @self.command(description = "Device Initiation") def Init(): - if self._useVars: - self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select - self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier - self.GeneralAddr0.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero - self.GeneralAddr0.set(value=0x00,index=0x020) - self.JesdDigitalA.set(value=0x00,index=0x03E) - self.JesdDigitalB.set(value=0x00,index=0x03E) - - self.IL_Config_Nyq1_ChA() - self.IL_Config_Nyq1_ChB() + self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select + self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier + self.GeneralAddr0.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero + self.GeneralAddr0.set(value=0x00,index=0x020) + self.JesdDigitalA.set(value=0x00,index=0x03E) + self.JesdDigitalB.set(value=0x00,index=0x03E) - time.sleep(0.250) + self.IL_Config_Nyq1_ChA() + self.IL_Config_Nyq1_ChB() - self.SetNLTrim() + time.sleep(0.250) - time.sleep(0.250) + self.SetNLTrim() - self.JESD_DDC_config() + time.sleep(0.250) - time.sleep(0.250) + self.JESD_DDC_config() - self.OffsetCorrectorA.set(value=0xA2,index=0x068) #... freeze offset estimation - self.OffsetCorrectorB.set(value=0xA2,index=0x068) #... freeze offset estimation + time.sleep(0.250) - self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select - self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier - self.GeneralAddr0.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero - self.GeneralAddr0.set(value=0x00,index=0x020) + self.OffsetCorrectorA.set(value=0xA2,index=0x068) #... freeze offset estimation + self.OffsetCorrectorB.set(value=0xA2,index=0x068) #... freeze offset estimation - self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select - self.JesdDigitalA.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF - self.JesdDigitalB.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF + self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select + self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier + self.GeneralAddr0.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero + self.GeneralAddr0.set(value=0x00,index=0x020) - self.JesdDigitalA.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF - self.JesdDigitalB.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF + self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select + self.JesdDigitalA.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF + self.JesdDigitalB.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF - self.GeneralAddr0.set(value=0x10,index=0x020) # PDN_SYSREF = 0x1 + self.JesdDigitalA.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF + self.JesdDigitalB.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF - else: - self._rawWrite(generalAddr + (4*0x0012),0x04) # write 4 to address 12 page select # Deprecated - self._rawWrite(generalAddr + (4*0x0056),0x00) # sysref dis - check this was written earlier # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x00) # sysref dis - whether it has to be zero # Deprecated - self._rawWrite(generalAddr + (4*0x0020),0x00) # Deprecated - self._rawWrite(jesdDigital + chA + (4*0x03E),0x00) # Deprecated - self._rawWrite(jesdDigital + chB + (4*0x03E),0x00) # Deprecated - - self.IL_Config_Nyq1_ChA() - self.IL_Config_Nyq1_ChB() - - time.sleep(0.250) - - self.SetNLTrim() - - time.sleep(0.250) - - self.JESD_DDC_config() - - time.sleep(0.250) - - self._rawWrite(offsetCorrector + chA + (4*0x068),0xA2) #... freeze offset estimation # Deprecated - self._rawWrite(offsetCorrector + chB + (4*0x068),0xA2) #... freeze offset estimation # Deprecated - - self._rawWrite(generalAddr + (4*0x0012),0x04) # write 4 to address 12 page select # Deprecated - self._rawWrite(generalAddr + (4*0x0056),0x00) # sysref dis - check this was written earlier # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x00) # sysref dis - whether it has to be zero # Deprecated - self._rawWrite(generalAddr + (4*0x0020),0x00) # Deprecated - - self._rawWrite(generalAddr + (4*0x0012),0x04) # write 4 to address 12 page select # Deprecated - self._rawWrite(jesdDigital + chA + (4*0x03E),0x40) #... MASK CLKDIV SYSREF # Deprecated - self._rawWrite(jesdDigital + chB + (4*0x03E),0x40) #... MASK CLKDIV SYSREF # Deprecated - - self._rawWrite(jesdDigital + chA + (4*0x03E),0x60) #... MASK CLKDIV SYSREF + MASK NCO SYSREF # Deprecated - self._rawWrite(jesdDigital + chB + (4*0x03E),0x60) #... MASK CLKDIV SYSREF + MASK NCO SYSREF # Deprecated - - self._rawWrite(generalAddr + (4*0x0020),0x10) # PDN_SYSREF = 0x1 # Deprecated + self.GeneralAddr0.set(value=0x10,index=0x020) # PDN_SYSREF = 0x1 @self.command() def Powerup_AnalogConfig(): - if self._useVars: - self.GeneralAddr0.set(value=0x81,index=0x000) # Global software reset. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config - self.GeneralAddr0.set(value=0xFF,index=0x011) # Select ADC page. - self.GeneralAddr0.set(value=0xC0,index=0x022) # Analog trims start here. - self.GeneralAddr0.set(value=0x80,index=0x032) # ... - self.GeneralAddr0.set(value=0x08,index=0x033) # ... - self.GeneralAddr0.set(value=0x03,index=0x042) # ... - self.GeneralAddr0.set(value=0x03,index=0x043) # ... - self.GeneralAddr0.set(value=0x58,index=0x045) # ... - self.GeneralAddr0.set(value=0xC4,index=0x046) # ... - self.GeneralAddr0.set(value=0x01,index=0x047) # ... - self.GeneralAddr0.set(value=0x01,index=0x053) # ... - self.GeneralAddr0.set(value=0x08,index=0x054) # ... - self.GeneralAddr0.set(value=0x05,index=0x064) # ... - self.GeneralAddr0.set(value=0x84,index=0x072) # ... - self.GeneralAddr0.set(value=0x80,index=0x08C) # ... - self.GeneralAddr0.set(value=0x80,index=0x097) # ... - self.GeneralAddr0.set(value=0x38,index=0x0F0) # ... - self.GeneralAddr0.set(value=0xBF,index=0x0F1) # Analog trims ended here. - self.GeneralAddr0.set(value=0x00,index=0x011) # Disable ADC Page - self.GeneralAddr0.set(value=0x04,index=0x012) # Select Master Page - self.GeneralAddr0.set(value=0x01,index=0x025) # Global Analog Trims start here. - self.GeneralAddr0.set(value=0x40,index=0x026) #... - self.GeneralAddr0.set(value=0x80,index=0x027) #... - self.GeneralAddr0.set(value=0x40,index=0x029) #... - self.GeneralAddr0.set(value=0x80,index=0x02A) #... - self.GeneralAddr0.set(value=0x40,index=0x02C) #... - self.GeneralAddr0.set(value=0x80,index=0x02D) #... - self.GeneralAddr0.set(value=0x40,index=0x02F) #... - self.GeneralAddr0.set(value=0x01,index=0x034) #... - self.GeneralAddr0.set(value=0x01,index=0x03F) #... - self.GeneralAddr0.set(value=0x50,index=0x039) #... - self.GeneralAddr0.set(value=0x28,index=0x03B) #... - self.GeneralAddr0.set(value=0x80,index=0x040) #... - self.GeneralAddr0.set(value=0x40,index=0x042) #... - self.GeneralAddr0.set(value=0x80,index=0x043) #... - self.GeneralAddr0.set(value=0x40,index=0x045) #... - self.GeneralAddr0.set(value=0x80,index=0x046) #... - self.GeneralAddr0.set(value=0x40,index=0x048) #... - self.GeneralAddr0.set(value=0x80,index=0x049) #... - self.GeneralAddr0.set(value=0x40,index=0x04B) #... - self.GeneralAddr0.set(value=0x60,index=0x053) #... - self.GeneralAddr0.set(value=0x02,index=0x059) #... - self.GeneralAddr0.set(value=0x08,index=0x05B) #... - self.GeneralAddr0.set(value=0x07,index=0x05C) #... - self.GeneralAddr0.set(value=0x10,index=0x057) # Register control for SYSREF --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x00,index=0x057) # Give SYSREF control back to device pin --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier - self.GeneralAddr0.set(value=0x00,index=0x020) # Pdn sysref = 0 - self.GeneralAddr0.set(value=0x00,index=0x012) # Master page disabled - self.GeneralAddr0.set(value=0xFF,index=0x011) # Select ADC Page - self.GeneralAddr0.set(value=0x07,index=0x083) # Additioanal Analog trims - self.GeneralAddr0.set(value=0x00,index=0x05C) #... - self.GeneralAddr0.set(value=0x01,index=0x05C) #... - self.GeneralAddr0.set(value=0x00,index=0x011) #Disable ADC Page. Power up Analog writes end here. Program appropriate -->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config - - self.GeneralAddr4.set(value=0x00,index=0x001) #DC corrector Bandwidth settings - self.GeneralAddr4.set(value=0x00,index=0x002) #... - self.GeneralAddr4.set(value=0x00,index=0x003) #... - self.RawInterface4.set(value=0x61,index=0x004) #... - self.RawInterface6.set(value=0x22,index=0x068) #... - self.RawInterface4.set(value=0x01,index=0x003) #... - self.RawInterface6.set(value=0x22,index=0x068) #... - else: - self._rawWrite(generalAddr + (4*0x0000),0x81) # Global software reset. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config # Deprecated - self._rawWrite(generalAddr + (4*0x0011),0xFF) # Select ADC page. # Deprecated - self._rawWrite(generalAddr + (4*0x0022),0xC0) # Analog trims start here. # Deprecated - self._rawWrite(generalAddr + (4*0x0032),0x80) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0033),0x08) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0042),0x03) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0043),0x03) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0045),0x58) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0046),0xC4) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0047),0x01) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0053),0x01) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0054),0x08) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0064),0x05) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0072),0x84) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x008C),0x80) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x0097),0x80) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x00F0),0x38) # ... # Deprecated - self._rawWrite(generalAddr + (4*0x00F1),0xBF) # Analog trims ended here. # Deprecated - self._rawWrite(generalAddr + (4*0x0011),0x00) # Disable ADC Page # Deprecated - self._rawWrite(generalAddr + (4*0x0012),0x04) # Select Master Page # Deprecated - self._rawWrite(generalAddr + (4*0x0025),0x01) # Global Analog Trims start here. # Deprecated - self._rawWrite(generalAddr + (4*0x0026),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0027),0x80) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0029),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x002A),0x80) #... # Deprecated - self._rawWrite(generalAddr + (4*0x002C),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x002D),0x80) #... # Deprecated - self._rawWrite(generalAddr + (4*0x002F),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0034),0x01) #... # Deprecated - self._rawWrite(generalAddr + (4*0x003F),0x01) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0039),0x50) #... # Deprecated - self._rawWrite(generalAddr + (4*0x003B),0x28) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0040),0x80) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0042),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0043),0x80) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0045),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0046),0x80) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0048),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0049),0x80) #... # Deprecated - self._rawWrite(generalAddr + (4*0x004B),0x40) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0053),0x60) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0059),0x02) #... # Deprecated - self._rawWrite(generalAddr + (4*0x005B),0x08) #... # Deprecated - self._rawWrite(generalAddr + (4*0x005c),0x07) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x10) # Register control for SYSREF --these lines are added in revision SBAA226C. # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x18) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x10) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x18) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x10) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. # Deprecated - self._rawWrite(generalAddr + (4*0x0057),0x00) # Give SYSREF control back to device pin --these lines are added in revision SBAA226C. # Deprecated - self._rawWrite(generalAddr + (4*0x0056),0x00) # sysref dis - check this was written earlier # Deprecated - self._rawWrite(generalAddr + (4*0x0020),0x00) # Pdn sysref = 0 # Deprecated - self._rawWrite(generalAddr + (4*0x0012),0x00) # Master page disabled # Deprecated - self._rawWrite(generalAddr + (4*0x0011),0xFF) # Select ADC Page # Deprecated - self._rawWrite(generalAddr + (4*0x0083),0x07) # Additioanal Analog trims # Deprecated - self._rawWrite(generalAddr + (4*0x005C),0x00) #... # Deprecated - self._rawWrite(generalAddr + (4*0x005C),0x01) #... # Deprecated - self._rawWrite(generalAddr + (4*0x0011),0x00) #Disable ADC Page. Power up Analog writes end here. Program appropriate -->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config # Deprecated - self._rawWrite(rawInterface + (4*0x4001),0x00) #DC corrector Bandwidth settings # Deprecated - self._rawWrite(rawInterface + (4*0x4002),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4003),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4004),0x61) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6068),0x22) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4003),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6068),0x22) #... # Deprecated + self.GeneralAddr0.set(value=0x81,index=0x000) # Global software reset. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config + self.GeneralAddr0.set(value=0xFF,index=0x011) # Select ADC page. + self.GeneralAddr0.set(value=0xC0,index=0x022) # Analog trims start here. + self.GeneralAddr0.set(value=0x80,index=0x032) # ... + self.GeneralAddr0.set(value=0x08,index=0x033) # ... + self.GeneralAddr0.set(value=0x03,index=0x042) # ... + self.GeneralAddr0.set(value=0x03,index=0x043) # ... + self.GeneralAddr0.set(value=0x58,index=0x045) # ... + self.GeneralAddr0.set(value=0xC4,index=0x046) # ... + self.GeneralAddr0.set(value=0x01,index=0x047) # ... + self.GeneralAddr0.set(value=0x01,index=0x053) # ... + self.GeneralAddr0.set(value=0x08,index=0x054) # ... + self.GeneralAddr0.set(value=0x05,index=0x064) # ... + self.GeneralAddr0.set(value=0x84,index=0x072) # ... + self.GeneralAddr0.set(value=0x80,index=0x08C) # ... + self.GeneralAddr0.set(value=0x80,index=0x097) # ... + self.GeneralAddr0.set(value=0x38,index=0x0F0) # ... + self.GeneralAddr0.set(value=0xBF,index=0x0F1) # Analog trims ended here. + self.GeneralAddr0.set(value=0x00,index=0x011) # Disable ADC Page + self.GeneralAddr0.set(value=0x04,index=0x012) # Select Master Page + self.GeneralAddr0.set(value=0x01,index=0x025) # Global Analog Trims start here. + self.GeneralAddr0.set(value=0x40,index=0x026) #... + self.GeneralAddr0.set(value=0x80,index=0x027) #... + self.GeneralAddr0.set(value=0x40,index=0x029) #... + self.GeneralAddr0.set(value=0x80,index=0x02A) #... + self.GeneralAddr0.set(value=0x40,index=0x02C) #... + self.GeneralAddr0.set(value=0x80,index=0x02D) #... + self.GeneralAddr0.set(value=0x40,index=0x02F) #... + self.GeneralAddr0.set(value=0x01,index=0x034) #... + self.GeneralAddr0.set(value=0x01,index=0x03F) #... + self.GeneralAddr0.set(value=0x50,index=0x039) #... + self.GeneralAddr0.set(value=0x28,index=0x03B) #... + self.GeneralAddr0.set(value=0x80,index=0x040) #... + self.GeneralAddr0.set(value=0x40,index=0x042) #... + self.GeneralAddr0.set(value=0x80,index=0x043) #... + self.GeneralAddr0.set(value=0x40,index=0x045) #... + self.GeneralAddr0.set(value=0x80,index=0x046) #... + self.GeneralAddr0.set(value=0x40,index=0x048) #... + self.GeneralAddr0.set(value=0x80,index=0x049) #... + self.GeneralAddr0.set(value=0x40,index=0x04B) #... + self.GeneralAddr0.set(value=0x60,index=0x053) #... + self.GeneralAddr0.set(value=0x02,index=0x059) #... + self.GeneralAddr0.set(value=0x08,index=0x05B) #... + self.GeneralAddr0.set(value=0x07,index=0x05C) #... + self.GeneralAddr0.set(value=0x10,index=0x057) # Register control for SYSREF --these lines are added in revision SBAA226C. + self.GeneralAddr0.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. + self.GeneralAddr0.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. + self.GeneralAddr0.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. + self.GeneralAddr0.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. + self.GeneralAddr0.set(value=0x00,index=0x057) # Give SYSREF control back to device pin --these lines are added in revision SBAA226C. + self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier + self.GeneralAddr0.set(value=0x00,index=0x020) # Pdn sysref = 0 + self.GeneralAddr0.set(value=0x00,index=0x012) # Master page disabled + self.GeneralAddr0.set(value=0xFF,index=0x011) # Select ADC Page + self.GeneralAddr0.set(value=0x07,index=0x083) # Additioanal Analog trims + self.GeneralAddr0.set(value=0x00,index=0x05C) #... + self.GeneralAddr0.set(value=0x01,index=0x05C) #... + self.GeneralAddr0.set(value=0x00,index=0x011) #Disable ADC Page. Power up Analog writes end here. Program appropriate -->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config + + self.GeneralAddr4.set(value=0x00,index=0x001) #DC corrector Bandwidth settings + self.GeneralAddr4.set(value=0x00,index=0x002) #... + self.GeneralAddr4.set(value=0x00,index=0x003) #... + self.RawInterface4.set(value=0x61,index=0x004) #... + self.RawInterface6.set(value=0x22,index=0x068) #... + self.RawInterface4.set(value=0x01,index=0x003) #... + self.RawInterface6.set(value=0x22,index=0x068) #... @self.command(description = "Set IL ChA") def IL_Config_Nyq1_ChA(): - if self._useVars: - self.MainDigitalA.set(value=0x01,index=0x044) # Program global settings for Interleaving Corrector - self.MainDigitalA.set(value=0x04,index=0x068) # - self.MainDigitalA.set(value=0xC0,index=0x0FF) #... - self.MainDigitalA.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A - self.MainDigitalA.set(value=0x03,index=0x0A9) #... - self.MainDigitalA.set(value=0x77,index=0x0AB) #... - self.MainDigitalA.set(value=0x01,index=0x0AC) #... - self.MainDigitalA.set(value=0x77,index=0x0AD) #... - self.MainDigitalA.set(value=0x01,index=0x0AE) #... - self.MainDigitalA.set(value=0x0F,index=0x096) #... - self.MainDigitalA.set(value=0x26,index=0x097) #... - self.MainDigitalA.set(value=0x0C,index=0x08F) #... - self.MainDigitalA.set(value=0x08,index=0x08C) #... - self.MainDigitalA.set(value=0x0F,index=0x080) #... - self.MainDigitalA.set(value=0xCB,index=0x081) #... - self.MainDigitalA.set(value=0x03,index=0x07D) #... - self.MainDigitalA.set(value=0x75,index=0x056) #... - self.MainDigitalA.set(value=0x75,index=0x057) #... - self.MainDigitalA.set(value=0x00,index=0x053) #... - self.MainDigitalA.set(value=0x03,index=0x04B) #... - self.MainDigitalA.set(value=0x80,index=0x049) #... - self.MainDigitalA.set(value=0x26,index=0x043) #... - self.MainDigitalA.set(value=0x01,index=0x05E) #... - self.MainDigitalA.set(value=0x38,index=0x042) #... - self.MainDigitalA.set(value=0x04,index=0x05A) #... - self.MainDigitalA.set(value=0x20,index=0x071) #... - self.MainDigitalA.set(value=0x00,index=0x062) #... - self.MainDigitalA.set(value=0x00,index=0x098) #... - self.MainDigitalA.set(value=0x08,index=0x099) #... - self.MainDigitalA.set(value=0x08,index=0x09C) #... - self.MainDigitalA.set(value=0x20,index=0x09D) #... - self.MainDigitalA.set(value=0x03,index=0x0BE) #... - self.MainDigitalA.set(value=0x00,index=0x069) #... - self.MainDigitalA.set(value=0x10,index=0x045) #... - self.MainDigitalA.set(value=0x64,index=0x08D) #... - self.MainDigitalA.set(value=0x20,index=0x08B) #... - self.MainDigitalA.set(value=0x00,index=0x000) # Dig Core reset - self.MainDigitalA.set(value=0x01,index=0x000) #... - self.MainDigitalA.set(value=0x00,index=0x000) #... - else: - self._rawWrite(mainDigital + chA + (4*0x044),0x01) # Program global settings for Interleaving Corrector # Deprecated - self._rawWrite(mainDigital + chA + (4*0x068),0x04) # # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0FF),0xC0) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0A2),0x08) # Progam nyquist zone 1 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0A9),0x03) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0AB),0x77) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0AC),0x01) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0AD),0x77) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0AE),0x01) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x096),0x0F) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x097),0x26) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x08F),0x0C) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x08C),0x08) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x080),0x0F) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x081),0xCB) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x07D),0x03) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x056),0x75) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x057),0x75) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x053),0x00) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x04B),0x03) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x049),0x80) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x043),0x26) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x05E),0x01) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x042),0x38) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x05A),0x04) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x071),0x20) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x062),0x00) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x098),0x00) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x099),0x08) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x09C),0x08) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x09D),0x20) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x0BE),0x03) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x069),0x00) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x045),0x10) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x08D),0x64) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x08B),0x20) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x000),0x00) # Dig Core reset # Deprecated - self._rawWrite(mainDigital + chA + (4*0x000),0x01) #... # Deprecated - self._rawWrite(mainDigital + chA + (4*0x000),0x00) #... # Deprecated + self.MainDigitalA.set(value=0x01,index=0x044) # Program global settings for Interleaving Corrector + self.MainDigitalA.set(value=0x04,index=0x068) # + self.MainDigitalA.set(value=0xC0,index=0x0FF) #... + self.MainDigitalA.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A + self.MainDigitalA.set(value=0x03,index=0x0A9) #... + self.MainDigitalA.set(value=0x77,index=0x0AB) #... + self.MainDigitalA.set(value=0x01,index=0x0AC) #... + self.MainDigitalA.set(value=0x77,index=0x0AD) #... + self.MainDigitalA.set(value=0x01,index=0x0AE) #... + self.MainDigitalA.set(value=0x0F,index=0x096) #... + self.MainDigitalA.set(value=0x26,index=0x097) #... + self.MainDigitalA.set(value=0x0C,index=0x08F) #... + self.MainDigitalA.set(value=0x08,index=0x08C) #... + self.MainDigitalA.set(value=0x0F,index=0x080) #... + self.MainDigitalA.set(value=0xCB,index=0x081) #... + self.MainDigitalA.set(value=0x03,index=0x07D) #... + self.MainDigitalA.set(value=0x75,index=0x056) #... + self.MainDigitalA.set(value=0x75,index=0x057) #... + self.MainDigitalA.set(value=0x00,index=0x053) #... + self.MainDigitalA.set(value=0x03,index=0x04B) #... + self.MainDigitalA.set(value=0x80,index=0x049) #... + self.MainDigitalA.set(value=0x26,index=0x043) #... + self.MainDigitalA.set(value=0x01,index=0x05E) #... + self.MainDigitalA.set(value=0x38,index=0x042) #... + self.MainDigitalA.set(value=0x04,index=0x05A) #... + self.MainDigitalA.set(value=0x20,index=0x071) #... + self.MainDigitalA.set(value=0x00,index=0x062) #... + self.MainDigitalA.set(value=0x00,index=0x098) #... + self.MainDigitalA.set(value=0x08,index=0x099) #... + self.MainDigitalA.set(value=0x08,index=0x09C) #... + self.MainDigitalA.set(value=0x20,index=0x09D) #... + self.MainDigitalA.set(value=0x03,index=0x0BE) #... + self.MainDigitalA.set(value=0x00,index=0x069) #... + self.MainDigitalA.set(value=0x10,index=0x045) #... + self.MainDigitalA.set(value=0x64,index=0x08D) #... + self.MainDigitalA.set(value=0x20,index=0x08B) #... + self.MainDigitalA.set(value=0x00,index=0x000) # Dig Core reset + self.MainDigitalA.set(value=0x01,index=0x000) #... + self.MainDigitalA.set(value=0x00,index=0x000) #... @self.command() def IL_Config_Nyq1_ChB(): - if self._useVars: - self.MainDigitalB.set(value=0x80,index=0x049) # Special setting for chB - self.MainDigitalB.set(value=0x20,index=0x042) # Special setting for chB - self.MainDigitalB.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chB, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A - self.MainDigitalB.set(value=0x00,index=0x003) # Main digital page selected for chA - self.MainDigitalB.set(value=0x00,index=0x000) #... - self.MainDigitalB.set(value=0x01,index=0x000) #... - self.MainDigitalB.set(value=0x00,index=0x000) #... - else: - self._rawWrite(mainDigital + chB + (4*0x049),0x80) # Special setting for chB # Deprecated # Deprecated - self._rawWrite(mainDigital + chB + (4*0x042),0x20) # Special setting for chB # Deprecated # Deprecated - self._rawWrite(mainDigital + chB + (4*0x0A2),0x08) # Progam nyquist zone 1 for chB, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A # Deprecated - self._rawWrite(mainDigital + chB + (4*0x003),0x00) # Main digital page selected for chA # Deprecated - self._rawWrite(mainDigital + chB + (4*0x000),0x00) #... # Deprecated - self._rawWrite(mainDigital + chB + (4*0x000),0x01) #... # Deprecated - self._rawWrite(mainDigital + chB + (4*0x000),0x00) #... # Deprecated + self.MainDigitalB.set(value=0x80,index=0x049) # Special setting for chB + self.MainDigitalB.set(value=0x20,index=0x042) # Special setting for chB + self.MainDigitalB.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chB, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A + self.MainDigitalB.set(value=0x00,index=0x003) # Main digital page selected for chA + self.MainDigitalB.set(value=0x00,index=0x000) #... + self.MainDigitalB.set(value=0x01,index=0x000) #... + self.MainDigitalB.set(value=0x00,index=0x000) #... @self.command(description = "Set nonlinear trims") def SetNLTrim(): - if self._useVars: - # Nonlinearity trims - self.RawInterface4.set(value=0x00,index=0x003) #chA Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config - self.RawInterface4.set(value=0x20,index=0x004) #... - self.RawInterface4.set(value=0xF8,index=0x002) #... - self.RawInterface6.set(value=0xF5,index=0x03C) #... - self.RawInterface6.set(value=0x01,index=0x03D) #... - self.RawInterface6.set(value=0xF0,index=0x03E) #... - self.RawInterface6.set(value=0x0C,index=0x03F) #... - self.RawInterface6.set(value=0x0A,index=0x040) #... - self.RawInterface6.set(value=0xFE,index=0x041) #... - self.RawInterface6.set(value=0xF5,index=0x053) #... - self.RawInterface6.set(value=0x01,index=0x054) #... - self.RawInterface6.set(value=0xEE,index=0x055) #... - self.RawInterface6.set(value=0x0E,index=0x056) #... - self.RawInterface6.set(value=0x0B,index=0x057) #... - self.RawInterface6.set(value=0xFE,index=0x058) #... - self.RawInterface6.set(value=0xF4,index=0x06A) #... - self.RawInterface6.set(value=0x01,index=0x06B) #... - self.RawInterface6.set(value=0xF0,index=0x06C) #... - self.RawInterface6.set(value=0x0B,index=0x06D) #... - self.RawInterface6.set(value=0x09,index=0x06E) #... - self.RawInterface6.set(value=0xFE,index=0x06F) #... - self.RawInterface6.set(value=0xF5,index=0x081) #... - self.RawInterface6.set(value=0x01,index=0x082) #... - self.RawInterface6.set(value=0xEE,index=0x083) #... - self.RawInterface6.set(value=0x0D,index=0x084) #... - self.RawInterface6.set(value=0x0A,index=0x085) #... - self.RawInterface6.set(value=0xFE,index=0x086) #... - self.RawInterface6.set(value=0xFD,index=0x098) #... - self.RawInterface6.set(value=0x00,index=0x099) #... - self.RawInterface6.set(value=0x00,index=0x09A) #... - self.RawInterface6.set(value=0x00,index=0x09B) #... - self.RawInterface6.set(value=0x00,index=0x09C) #... - self.RawInterface6.set(value=0x00,index=0x09D) #... - self.RawInterface6.set(value=0xFF,index=0x0AF) #... - self.RawInterface6.set(value=0x00,index=0x0B0) #... - self.RawInterface6.set(value=0x01,index=0x0B1) #... - self.RawInterface6.set(value=0xFF,index=0x0B2) #... - self.RawInterface6.set(value=0xFF,index=0x0B3) #... - self.RawInterface6.set(value=0x00,index=0x0B4) #... - self.RawInterface6.set(value=0xFE,index=0x0C6) #... - self.RawInterface6.set(value=0x00,index=0x0C7) #... - self.RawInterface6.set(value=0x00,index=0x0C8) #... - self.RawInterface6.set(value=0x02,index=0x0C9) #... - self.RawInterface6.set(value=0x00,index=0x0CA) #... - self.RawInterface6.set(value=0x00,index=0x0CB) #... - self.RawInterface6.set(value=0xFF,index=0x0DD) #... - self.RawInterface6.set(value=0x00,index=0x0DE) #... - self.RawInterface6.set(value=0x02,index=0x0DF) #... - self.RawInterface6.set(value=0x00,index=0x0E0) #... - self.RawInterface6.set(value=0xFE,index=0x0E1) #... - self.RawInterface6.set(value=0x00,index=0x0E2) #... - self.RawInterface6.set(value=0x00,index=0x0F4) #... - self.RawInterface6.set(value=0x00,index=0x0F5) #... - self.RawInterface6.set(value=0x01,index=0x0FB) #... - self.RawInterface6.set(value=0x01,index=0x0FC) #... - self.RawInterface4.set(value=0x00,index=0x003) #chB Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config - self.RawInterface4.set(value=0x20,index=0x004) #... - self.RawInterface4.set(value=0xF9,index=0x002) #... - self.RawInterface6.set(value=0xF4,index=0x074) #... - self.RawInterface6.set(value=0x01,index=0x075) #... - self.RawInterface6.set(value=0xEF,index=0x076) #... - self.RawInterface6.set(value=0x0C,index=0x077) #... - self.RawInterface6.set(value=0x0A,index=0x078) #... - self.RawInterface6.set(value=0xFE,index=0x079) #... - self.RawInterface6.set(value=0xF4,index=0x08B) #... - self.RawInterface6.set(value=0x01,index=0x08C) #... - self.RawInterface6.set(value=0xEE,index=0x08D) #... - self.RawInterface6.set(value=0x0D,index=0x08E) #... - self.RawInterface6.set(value=0x0A,index=0x08F) #... - self.RawInterface6.set(value=0xFE,index=0x090) #... - self.RawInterface6.set(value=0xF4,index=0x0A2) #... - self.RawInterface6.set(value=0x01,index=0x0A3) #... - self.RawInterface6.set(value=0xEF,index=0x0A4) #... - self.RawInterface6.set(value=0x0C,index=0x0A5) #... - self.RawInterface6.set(value=0x0A,index=0x0A6) #... - self.RawInterface6.set(value=0xFE,index=0x0A7) #... - self.RawInterface6.set(value=0xF4,index=0x0B9) #... - self.RawInterface6.set(value=0x01,index=0x0BA) #... - self.RawInterface6.set(value=0xEF,index=0x0BB) #... - self.RawInterface6.set(value=0x0D,index=0x0BC) #... - self.RawInterface6.set(value=0x0A,index=0x0BD) #... - self.RawInterface6.set(value=0xFE,index=0x0BE) #... - self.RawInterface6.set(value=0xFF,index=0x0D0) #... - self.RawInterface6.set(value=0x00,index=0x0D1) #... - self.RawInterface6.set(value=0xFF,index=0x0D2) #... - self.RawInterface6.set(value=0x01,index=0x0D3) #... - self.RawInterface6.set(value=0x00,index=0x0D4) #... - self.RawInterface6.set(value=0x00,index=0x0D5) #... - self.RawInterface6.set(value=0xFF,index=0x0E7) #... - self.RawInterface6.set(value=0x00,index=0x0E8) #... - self.RawInterface6.set(value=0x01,index=0x0E9) #... - self.RawInterface6.set(value=0x00,index=0x0EA) #... - self.RawInterface6.set(value=0x00,index=0x0EB) #... - self.RawInterface6.set(value=0x00,index=0x0EC) #... - self.RawInterface6.set(value=0xFE,index=0x0FE) #... - self.RawInterface6.set(value=0x00,index=0x0FF) #... - self.RawInterface4.set(value=0xFA,index=0x002) #... - self.RawInterface6.set(value=0xFF,index=0x000) #... - self.RawInterface6.set(value=0x02,index=0x001) #... - self.RawInterface6.set(value=0x01,index=0x002) #... - self.RawInterface6.set(value=0x00,index=0x003) #... - self.RawInterface6.set(value=0xFF,index=0x015) #... - self.RawInterface6.set(value=0x00,index=0x016) #... - self.RawInterface6.set(value=0x01,index=0x017) #... - self.RawInterface6.set(value=0x00,index=0x018) #... - self.RawInterface6.set(value=0xFF,index=0x019) #... - self.RawInterface6.set(value=0x00,index=0x01A) #... - self.RawInterface6.set(value=0x00,index=0x02C) #... - self.RawInterface6.set(value=0x00,index=0x02D) #... - self.RawInterface6.set(value=0x01,index=0x033) #... - self.RawInterface6.set(value=0x01,index=0x034) #... - self.RawInterface4.set(value=0x00,index=0x002) #... - self.RawInterface4.set(value=0x00,index=0x003) #... - self.RawInterface4.set(value=0x68,index=0x004) #... - self.RawInterface6.set(value=0x00,index=0x068) #... - self.RawInterface0.set(value=0x00,index=0x011) #... - self.RawInterface0.set(value=0x04,index=0x012) #... - self.RawInterface0.set(value=0x87,index=0x05c) #... - self.RawInterface0.set(value=0x00,index=0x012) #... - else: - # Nonlinearity trims - self._rawWrite(rawInterface + (4*0x4003),0x00) #chA Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config # Deprecated - self._rawWrite(rawInterface + (4*0x4004),0x20) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4002),0xF8) #... # Deprecated - self._rawWrite(rawInterface + (4*0x603C),0xF5) #... # Deprecated - self._rawWrite(rawInterface + (4*0x603D),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x603E),0xF0) #... # Deprecated - self._rawWrite(rawInterface + (4*0x603F),0x0C) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6040),0x0A) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6041),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6053),0xF5) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6054),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6055),0xEE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6056),0x0E) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6057),0x0B) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6058),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x606A),0xF4) #... # Deprecated - self._rawWrite(rawInterface + (4*0x606B),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x606C),0xF0) #... # Deprecated - self._rawWrite(rawInterface + (4*0x606D),0x0B) #... # Deprecated - self._rawWrite(rawInterface + (4*0x606E),0x09) #... # Deprecated - self._rawWrite(rawInterface + (4*0x606F),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6081),0xF5) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6082),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6083),0xEE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6084),0x0D) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6085),0x0A) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6086),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6098),0xFD) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6099),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x609A),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x609B),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x609C),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x609D),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60AF),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60B0),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60B1),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60B2),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60B3),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60B4),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60C6),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60C7),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60C8),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60C9),0x02) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60CA),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60CB),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60DD),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60DE),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60DF),0x02) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60E0),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60E1),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60E2),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60F4),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60F5),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60FB),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60FC),0x01) #... # Deprecated - - self._rawWrite(rawInterface + (4*0x4003),0x00) #chB Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config # Deprecated - self._rawWrite(rawInterface + (4*0x4004),0x20) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4002),0xF9) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6074),0xF4) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6075),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6076),0xEF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6077),0x0C) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6078),0x0A) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6079),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x608B),0xF4) #... # Deprecated - self._rawWrite(rawInterface + (4*0x608C),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x608D),0xEE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x608E),0x0D) #... # Deprecated - self._rawWrite(rawInterface + (4*0x608F),0x0A) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6090),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60A2),0xF4) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60A3),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60A4),0xEF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60A5),0x0C) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60A6),0x0A) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60A7),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60B9),0xF4) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60BA),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60BB),0xEF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60BC),0x0D) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60BD),0x0A) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60BE),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60D0),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60D1),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60D2),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60D3),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60D4),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60D5),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60E7),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60E8),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60E9),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60EA),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60EB),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60EC),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60FE),0xFE) #... # Deprecated - self._rawWrite(rawInterface + (4*0x60FF),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4002),0xFA) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6000),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6001),0x02) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6002),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6003),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6015),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6016),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6017),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6018),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6019),0xFF) #... # Deprecated - self._rawWrite(rawInterface + (4*0x601A),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x602C),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x602D),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6033),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6034),0x01) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4002),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4003),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x4004),0x68) #... # Deprecated - self._rawWrite(rawInterface + (4*0x6068),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x0011),0x00) #... # Deprecated - self._rawWrite(rawInterface + (4*0x0012),0x04) #... # Deprecated - self._rawWrite(rawInterface + (4*0x005c),0x87) #... # Deprecated - self._rawWrite(rawInterface + (4*0x0012),0x00) #... # Deprecated + # Nonlinearity trims + self.RawInterface4.set(value=0x00,index=0x003) #chA Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config + self.RawInterface4.set(value=0x20,index=0x004) #... + self.RawInterface4.set(value=0xF8,index=0x002) #... + self.RawInterface6.set(value=0xF5,index=0x03C) #... + self.RawInterface6.set(value=0x01,index=0x03D) #... + self.RawInterface6.set(value=0xF0,index=0x03E) #... + self.RawInterface6.set(value=0x0C,index=0x03F) #... + self.RawInterface6.set(value=0x0A,index=0x040) #... + self.RawInterface6.set(value=0xFE,index=0x041) #... + self.RawInterface6.set(value=0xF5,index=0x053) #... + self.RawInterface6.set(value=0x01,index=0x054) #... + self.RawInterface6.set(value=0xEE,index=0x055) #... + self.RawInterface6.set(value=0x0E,index=0x056) #... + self.RawInterface6.set(value=0x0B,index=0x057) #... + self.RawInterface6.set(value=0xFE,index=0x058) #... + self.RawInterface6.set(value=0xF4,index=0x06A) #... + self.RawInterface6.set(value=0x01,index=0x06B) #... + self.RawInterface6.set(value=0xF0,index=0x06C) #... + self.RawInterface6.set(value=0x0B,index=0x06D) #... + self.RawInterface6.set(value=0x09,index=0x06E) #... + self.RawInterface6.set(value=0xFE,index=0x06F) #... + self.RawInterface6.set(value=0xF5,index=0x081) #... + self.RawInterface6.set(value=0x01,index=0x082) #... + self.RawInterface6.set(value=0xEE,index=0x083) #... + self.RawInterface6.set(value=0x0D,index=0x084) #... + self.RawInterface6.set(value=0x0A,index=0x085) #... + self.RawInterface6.set(value=0xFE,index=0x086) #... + self.RawInterface6.set(value=0xFD,index=0x098) #... + self.RawInterface6.set(value=0x00,index=0x099) #... + self.RawInterface6.set(value=0x00,index=0x09A) #... + self.RawInterface6.set(value=0x00,index=0x09B) #... + self.RawInterface6.set(value=0x00,index=0x09C) #... + self.RawInterface6.set(value=0x00,index=0x09D) #... + self.RawInterface6.set(value=0xFF,index=0x0AF) #... + self.RawInterface6.set(value=0x00,index=0x0B0) #... + self.RawInterface6.set(value=0x01,index=0x0B1) #... + self.RawInterface6.set(value=0xFF,index=0x0B2) #... + self.RawInterface6.set(value=0xFF,index=0x0B3) #... + self.RawInterface6.set(value=0x00,index=0x0B4) #... + self.RawInterface6.set(value=0xFE,index=0x0C6) #... + self.RawInterface6.set(value=0x00,index=0x0C7) #... + self.RawInterface6.set(value=0x00,index=0x0C8) #... + self.RawInterface6.set(value=0x02,index=0x0C9) #... + self.RawInterface6.set(value=0x00,index=0x0CA) #... + self.RawInterface6.set(value=0x00,index=0x0CB) #... + self.RawInterface6.set(value=0xFF,index=0x0DD) #... + self.RawInterface6.set(value=0x00,index=0x0DE) #... + self.RawInterface6.set(value=0x02,index=0x0DF) #... + self.RawInterface6.set(value=0x00,index=0x0E0) #... + self.RawInterface6.set(value=0xFE,index=0x0E1) #... + self.RawInterface6.set(value=0x00,index=0x0E2) #... + self.RawInterface6.set(value=0x00,index=0x0F4) #... + self.RawInterface6.set(value=0x00,index=0x0F5) #... + self.RawInterface6.set(value=0x01,index=0x0FB) #... + self.RawInterface6.set(value=0x01,index=0x0FC) #... + self.RawInterface4.set(value=0x00,index=0x003) #chB Non Linearity Trims for Nyq1. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config + self.RawInterface4.set(value=0x20,index=0x004) #... + self.RawInterface4.set(value=0xF9,index=0x002) #... + self.RawInterface6.set(value=0xF4,index=0x074) #... + self.RawInterface6.set(value=0x01,index=0x075) #... + self.RawInterface6.set(value=0xEF,index=0x076) #... + self.RawInterface6.set(value=0x0C,index=0x077) #... + self.RawInterface6.set(value=0x0A,index=0x078) #... + self.RawInterface6.set(value=0xFE,index=0x079) #... + self.RawInterface6.set(value=0xF4,index=0x08B) #... + self.RawInterface6.set(value=0x01,index=0x08C) #... + self.RawInterface6.set(value=0xEE,index=0x08D) #... + self.RawInterface6.set(value=0x0D,index=0x08E) #... + self.RawInterface6.set(value=0x0A,index=0x08F) #... + self.RawInterface6.set(value=0xFE,index=0x090) #... + self.RawInterface6.set(value=0xF4,index=0x0A2) #... + self.RawInterface6.set(value=0x01,index=0x0A3) #... + self.RawInterface6.set(value=0xEF,index=0x0A4) #... + self.RawInterface6.set(value=0x0C,index=0x0A5) #... + self.RawInterface6.set(value=0x0A,index=0x0A6) #... + self.RawInterface6.set(value=0xFE,index=0x0A7) #... + self.RawInterface6.set(value=0xF4,index=0x0B9) #... + self.RawInterface6.set(value=0x01,index=0x0BA) #... + self.RawInterface6.set(value=0xEF,index=0x0BB) #... + self.RawInterface6.set(value=0x0D,index=0x0BC) #... + self.RawInterface6.set(value=0x0A,index=0x0BD) #... + self.RawInterface6.set(value=0xFE,index=0x0BE) #... + self.RawInterface6.set(value=0xFF,index=0x0D0) #... + self.RawInterface6.set(value=0x00,index=0x0D1) #... + self.RawInterface6.set(value=0xFF,index=0x0D2) #... + self.RawInterface6.set(value=0x01,index=0x0D3) #... + self.RawInterface6.set(value=0x00,index=0x0D4) #... + self.RawInterface6.set(value=0x00,index=0x0D5) #... + self.RawInterface6.set(value=0xFF,index=0x0E7) #... + self.RawInterface6.set(value=0x00,index=0x0E8) #... + self.RawInterface6.set(value=0x01,index=0x0E9) #... + self.RawInterface6.set(value=0x00,index=0x0EA) #... + self.RawInterface6.set(value=0x00,index=0x0EB) #... + self.RawInterface6.set(value=0x00,index=0x0EC) #... + self.RawInterface6.set(value=0xFE,index=0x0FE) #... + self.RawInterface6.set(value=0x00,index=0x0FF) #... + self.RawInterface4.set(value=0xFA,index=0x002) #... + self.RawInterface6.set(value=0xFF,index=0x000) #... + self.RawInterface6.set(value=0x02,index=0x001) #... + self.RawInterface6.set(value=0x01,index=0x002) #... + self.RawInterface6.set(value=0x00,index=0x003) #... + self.RawInterface6.set(value=0xFF,index=0x015) #... + self.RawInterface6.set(value=0x00,index=0x016) #... + self.RawInterface6.set(value=0x01,index=0x017) #... + self.RawInterface6.set(value=0x00,index=0x018) #... + self.RawInterface6.set(value=0xFF,index=0x019) #... + self.RawInterface6.set(value=0x00,index=0x01A) #... + self.RawInterface6.set(value=0x00,index=0x02C) #... + self.RawInterface6.set(value=0x00,index=0x02D) #... + self.RawInterface6.set(value=0x01,index=0x033) #... + self.RawInterface6.set(value=0x01,index=0x034) #... + self.RawInterface4.set(value=0x00,index=0x002) #... + self.RawInterface4.set(value=0x00,index=0x003) #... + self.RawInterface4.set(value=0x68,index=0x004) #... + self.RawInterface6.set(value=0x00,index=0x068) #... + self.RawInterface0.set(value=0x00,index=0x011) #... + self.RawInterface0.set(value=0x04,index=0x012) #... + self.RawInterface0.set(value=0x87,index=0x05c) #... + self.RawInterface0.set(value=0x00,index=0x012) #... @self.command() def JESD_DDC_config(): @@ -1092,39 +774,20 @@ def JESD_DDC_config(): @self.command(description = "Digital Reset") def DigRst(): - if self._useVars: - # Wait for 50 ms for the device to estimate the interleaving errors - time.sleep(0.250) # TODO: Optimize this timeout - self.JesdDigitalA.set(value=0x00,index=0x000) # clear reset - self.JesdDigitalB.set(value=0x00,index=0x000) # clear reset - self.JesdDigitalA.set(value=0x01,index=0x000) # CHA digital reset - self.JesdDigitalB.set(value=0x01,index=0x000) # CHB digital reset - self.JesdDigitalA.set(value=0x00,index=0x000) # clear reset - self.JesdDigitalB.set(value=0x00,index=0x000) # clear reset - - # Wait for 50 ms for the device to estimate the interleaving errors - time.sleep(0.250) # TODO: Optimize this timeout - self.MainDigitalA.set(value=0x00,index=0x000) # clear reset - self.MainDigitalB.set(value=0x00,index=0x000) # clear reset - self.MainDigitalA.set(value=0x01,index=0x000) # CHA digital reset - self.MainDigitalB.set(value=0x01,index=0x000) # CHB digital reset - self.MainDigitalA.set(value=0x00,index=0x000) # clear reset - self.MainDigitalB.set(value=0x00,index=0x000) # clear reset - else: - # Wait for 50 ms for the device to estimate the interleaving errors - time.sleep(0.250) # TODO: Optimize this timeout - self._rawWrite(jesdDigital + chA + (4*0x000),0x00) # clear reset # Deprecated - self._rawWrite(jesdDigital + chB + (4*0x000),0x00) # clear reset # Deprecated - self._rawWrite(jesdDigital + chA + (4*0x000),0x01) # CHA digital reset # Deprecated - self._rawWrite(jesdDigital + chB + (4*0x000),0x01) # CHB digital reset # Deprecated - self._rawWrite(jesdDigital + chA + (4*0x000),0x00) # clear reset # Deprecated - self._rawWrite(jesdDigital + chB + (4*0x000),0x00) # clear reset # Deprecated - - # Wait for 50 ms for the device to estimate the interleaving errors - time.sleep(0.250) # TODO: Optimize this timeout - self._rawWrite(mainDigital + chA + (4*0x000),0x00) # clear reset # Deprecated - self._rawWrite(mainDigital + chB + (4*0x000),0x00) # clear reset # Deprecated - self._rawWrite(mainDigital + chA + (4*0x000),0x01) # CHA digital reset # Deprecated - self._rawWrite(mainDigital + chB + (4*0x000),0x01) # CHB digital reset # Deprecated - self._rawWrite(mainDigital + chA + (4*0x000),0x00) # clear reset # Deprecated - self._rawWrite(mainDigital + chB + (4*0x000),0x00) # clear reset # Deprecated + # Wait for 50 ms for the device to estimate the interleaving errors + time.sleep(0.250) # TODO: Optimize this timeout + self.JesdDigitalA.set(value=0x00,index=0x000) # clear reset + self.JesdDigitalB.set(value=0x00,index=0x000) # clear reset + self.JesdDigitalA.set(value=0x01,index=0x000) # CHA digital reset + self.JesdDigitalB.set(value=0x01,index=0x000) # CHB digital reset + self.JesdDigitalA.set(value=0x00,index=0x000) # clear reset + self.JesdDigitalB.set(value=0x00,index=0x000) # clear reset + + # Wait for 50 ms for the device to estimate the interleaving errors + time.sleep(0.250) # TODO: Optimize this timeout + self.MainDigitalA.set(value=0x00,index=0x000) # clear reset + self.MainDigitalB.set(value=0x00,index=0x000) # clear reset + self.MainDigitalA.set(value=0x01,index=0x000) # CHA digital reset + self.MainDigitalB.set(value=0x01,index=0x000) # CHB digital reset + self.MainDigitalA.set(value=0x00,index=0x000) # clear reset + self.MainDigitalB.set(value=0x00,index=0x000) # clear reset diff --git a/python/surf/devices/ti/_Lmx2615.py b/python/surf/devices/ti/_Lmx2615.py index 0d01156c58..992509f49b 100644 --- a/python/surf/devices/ti/_Lmx2615.py +++ b/python/surf/devices/ti/_Lmx2615.py @@ -18,34 +18,25 @@ def __init__(self, **kwargs): # Address = 0x00 (R0) # Write only because MUXOUT_LD_SEL's default is not readback SPI mode ##################################################################### + super().__init__(**kwargs) - self._useVars = rogue.Version.greaterThanEqual('5.4.0') - - if self._useVars: - size = 0 - else: - size = (1 <<12) - - super().__init__(size = size, **kwargs) - - if self._useVars: - self.add(pr.RemoteVariable( - name = "DataBlock", - description = "", - offset = 0, - bitSize = 32 * 1024, - bitOffset = 0, - numValues = 1024, - valueBits = 32, - valueStride = 32, - updateNotify = True, - bulkOpEn = False, # FALSE for large variables - overlapEn = True, - verify = False, # FALSE due to a mix of RO/WO/RW variables - hidden = True, - base = pr.UInt, - mode = "RW", - )) + self.add(pr.RemoteVariable( + name = "DataBlock", + description = "", + offset = 0, + bitSize = 32 * 1024, + bitOffset = 0, + numValues = 1024, + valueBits = 32, + valueStride = 32, + updateNotify = True, + bulkOpEn = False, # FALSE for large variables + overlapEn = True, + verify = False, # FALSE due to a mix of RO/WO/RW variables + hidden = True, + base = pr.UInt, + mode = "RW", + )) self.add(pr.RemoteVariable( name = 'VCO_PHASE_SYNC', @@ -764,13 +755,7 @@ def LoadCodeLoaderHexFile(arg): else: data = int("0x" + s[1][-4:], 0) print(f'writing {addr:#04x}: {data:#06x}') - if self._useVars: - self.DataBlock.set(value=data, index=addr, write=True) - else: - self._rawWrite( 4 * addr, data) + self.DataBlock.set(value=data, index=addr, write=True) self.MUXOUT_LD_SEL.set(0x0) - if not self._useVars: - self.readBlocks(recurse=True) - self.checkBlocks(recurse=True) From aa2f4b031e499733c506a669d82a5c0498c92a2e Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Thu, 6 Jul 2023 14:36:32 -0700 Subject: [PATCH 15/32] Formatting errors --- python/surf/devices/microchip/_Axi24LC64FT.py | 2 -- python/surf/devices/micron/_AxiMicronMt28ew.py | 1 - python/surf/devices/micron/_AxiMicronN25Q.py | 1 - python/surf/devices/micron/_AxiMicronP30.py | 1 - python/surf/devices/micron/_DdrSpd.py | 1 - python/surf/devices/silabs/_Si5324.py | 1 - python/surf/devices/silabs/_Si5345Lite.py | 1 - python/surf/devices/ti/_Adc32Rf45.py | 1 - python/surf/devices/ti/_Lmx2615.py | 2 -- 9 files changed, 11 deletions(-) diff --git a/python/surf/devices/microchip/_Axi24LC64FT.py b/python/surf/devices/microchip/_Axi24LC64FT.py index dab5e6993c..5d66a39306 100644 --- a/python/surf/devices/microchip/_Axi24LC64FT.py +++ b/python/surf/devices/microchip/_Axi24LC64FT.py @@ -38,5 +38,3 @@ def __init__(self, bitSize = 32 * nelms, # mode = "RO", )) - - diff --git a/python/surf/devices/micron/_AxiMicronMt28ew.py b/python/surf/devices/micron/_AxiMicronMt28ew.py index 99e7b1f8a4..8cf4ca2da8 100644 --- a/python/surf/devices/micron/_AxiMicronMt28ew.py +++ b/python/surf/devices/micron/_AxiMicronMt28ew.py @@ -19,7 +19,6 @@ import time import datetime import math -import rogue class AxiMicronMt28ew(pr.Device): def __init__(self, diff --git a/python/surf/devices/micron/_AxiMicronN25Q.py b/python/surf/devices/micron/_AxiMicronN25Q.py index 0bdb3db7c7..56483f3ec0 100644 --- a/python/surf/devices/micron/_AxiMicronN25Q.py +++ b/python/surf/devices/micron/_AxiMicronN25Q.py @@ -14,7 +14,6 @@ #----------------------------------------------------------------------------- import pyrogue as pr -import rogue import surf.misc import click import time diff --git a/python/surf/devices/micron/_AxiMicronP30.py b/python/surf/devices/micron/_AxiMicronP30.py index 089bc2a690..ff59d99ea7 100644 --- a/python/surf/devices/micron/_AxiMicronP30.py +++ b/python/surf/devices/micron/_AxiMicronP30.py @@ -19,7 +19,6 @@ import time import datetime import math -import rogue class AxiMicronP30(pr.Device): def __init__(self, diff --git a/python/surf/devices/micron/_DdrSpd.py b/python/surf/devices/micron/_DdrSpd.py index 889b685072..04307e23f8 100644 --- a/python/surf/devices/micron/_DdrSpd.py +++ b/python/surf/devices/micron/_DdrSpd.py @@ -35,4 +35,3 @@ def __init__( self, bitSize = 32 * nelms, # mode = "RO", )) - diff --git a/python/surf/devices/silabs/_Si5324.py b/python/surf/devices/silabs/_Si5324.py index 4e28209150..aa5aaabffc 100644 --- a/python/surf/devices/silabs/_Si5324.py +++ b/python/surf/devices/silabs/_Si5324.py @@ -9,7 +9,6 @@ #----------------------------------------------------------------------------- import pyrogue as pr -import rogue import click import fnmatch diff --git a/python/surf/devices/silabs/_Si5345Lite.py b/python/surf/devices/silabs/_Si5345Lite.py index 66573f4f69..86928a9c92 100644 --- a/python/surf/devices/silabs/_Si5345Lite.py +++ b/python/surf/devices/silabs/_Si5345Lite.py @@ -13,7 +13,6 @@ import csv import click import fnmatch -import rogue class Si5345Lite(pr.Device): def __init__(self, diff --git a/python/surf/devices/ti/_Adc32Rf45.py b/python/surf/devices/ti/_Adc32Rf45.py index ecb8dbdf6e..4776191058 100644 --- a/python/surf/devices/ti/_Adc32Rf45.py +++ b/python/surf/devices/ti/_Adc32Rf45.py @@ -14,7 +14,6 @@ import pyrogue as pr import time import surf.devices.ti -import rogue class Adc32Rf45(pr.Device): def __init__( self, verify=True, **kwargs): diff --git a/python/surf/devices/ti/_Lmx2615.py b/python/surf/devices/ti/_Lmx2615.py index 992509f49b..c1b38e74cf 100644 --- a/python/surf/devices/ti/_Lmx2615.py +++ b/python/surf/devices/ti/_Lmx2615.py @@ -9,7 +9,6 @@ #----------------------------------------------------------------------------- import pyrogue as pr -import rogue class Lmx2615(pr.Device): def __init__(self, **kwargs): @@ -758,4 +757,3 @@ def LoadCodeLoaderHexFile(arg): self.DataBlock.set(value=data, index=addr, write=True) self.MUXOUT_LD_SEL.set(0x0) - From b963a4a14d653169c316ad98b72527cf81b88c9c Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Thu, 6 Jul 2023 14:37:03 -0700 Subject: [PATCH 16/32] Formatting errors --- python/surf/devices/silabs/_Si5326.py | 1 - python/surf/devices/silabs/_Si5394Lite.py | 1 - 2 files changed, 2 deletions(-) diff --git a/python/surf/devices/silabs/_Si5326.py b/python/surf/devices/silabs/_Si5326.py index 288efdc247..3346368383 100644 --- a/python/surf/devices/silabs/_Si5326.py +++ b/python/surf/devices/silabs/_Si5326.py @@ -9,7 +9,6 @@ #----------------------------------------------------------------------------- import pyrogue as pr -import rogue import click import fnmatch diff --git a/python/surf/devices/silabs/_Si5394Lite.py b/python/surf/devices/silabs/_Si5394Lite.py index 6dd967d704..499ec1617c 100644 --- a/python/surf/devices/silabs/_Si5394Lite.py +++ b/python/surf/devices/silabs/_Si5394Lite.py @@ -13,7 +13,6 @@ import csv import click import fnmatch -import rogue import time class Si5394Lite(pr.Device): From 01e4e3dab9e9fee3f94a8e34bf46894107c676db Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 7 Jul 2023 08:10:51 -0700 Subject: [PATCH 17/32] allowing RF block in gen1 type --- python/surf/xilinx/_RfTile.py | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/python/surf/xilinx/_RfTile.py b/python/surf/xilinx/_RfTile.py index e8ba4f8e4d..fed32f9872 100644 --- a/python/surf/xilinx/_RfTile.py +++ b/python/surf/xilinx/_RfTile.py @@ -196,14 +196,13 @@ def __init__( hidden = True, )) - if gen3: - prefix = 'adc' if isAdc else 'dac' - - for i in range(4): - self.add(xil.RfBlock( - name = f'{prefix}Block[{i}]', - isAdc = isAdc, - RestartSM = self.RestartSM, - offset = 0x2000 + 0x400*i, - expand = False, - )) + prefix = 'adc' if isAdc else 'dac' + + for i in range(4): + self.add(xil.RfBlock( + name = f'{prefix}Block[{i}]', + isAdc = isAdc, + RestartSM = self.RestartSM, + offset = 0x2000 + 0x400*i, + expand = False, + )) From f25ad407c1749375bd83e5ccfc10a27381ed7649 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 7 Jul 2023 13:32:29 -0700 Subject: [PATCH 18/32] Decoder initial disparity now 00 to match encoder --- protocols/line-codes/rtl/Decoder12b14b.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/line-codes/rtl/Decoder12b14b.vhd b/protocols/line-codes/rtl/Decoder12b14b.vhd index 9a5c2dd6b9..7ff6322753 100644 --- a/protocols/line-codes/rtl/Decoder12b14b.vhd +++ b/protocols/line-codes/rtl/Decoder12b14b.vhd @@ -57,7 +57,7 @@ architecture rtl of Decoder12b14b is constant REG_INIT_C : RegType := ( validOut => '0', - dispOut => "01", + dispOut => "00", dataOut => (others => '0'), dataKOut => '0', codeError => '0', From 8bb13144ebe9bd5ba19eebf20240fa14db3b8108 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 7 Jul 2023 13:48:17 -0700 Subject: [PATCH 19/32] adding custom testPattern to test_LineCode12b14bTb.py --- tests/test_LineCode12b14bTb.py | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/tests/test_LineCode12b14bTb.py b/tests/test_LineCode12b14bTb.py index 59aa3d20b1..05bd7d03c0 100644 --- a/tests/test_LineCode12b14bTb.py +++ b/tests/test_LineCode12b14bTb.py @@ -127,6 +127,64 @@ def dut_tb(dut): # Check the results for errors check_result(dut, dataIn, dataKIn) + testPattern = [ + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x078,1], + [0x5F8,1], + [0xEAD,0], + [0x0BD,0], + [0xEAD,0], + [0x1BD,0], + [0xEAD,0], + [0x2BD,0], + [0xEAD,0], + [0x3BD,0], + [0xEAD,0], + [0x4BD,0], + [0xEAD,0], + [0x5BD,0], + [0xEAD,0], + [0x6BD,0], + [0xEAD,0], + [0x7BD,0], + [0xEAD,0], + [0x8BD,0], + [0xEAD,0], + [0x9BD,0], + [0xEAD,0], + [0xABD,0], + [0xEAD,0], + [0xBBD,0], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + [0x5F8,1], + ] + for dataIn,dataKIn in testPattern: + + # Load the values + yield load_value(dut, dataIn, dataKIn) + + # Check the results for errors + check_result(dut, dataIn, dataKIn) + dut._log.info("DUT: Passed") tests_dir = os.path.dirname(__file__) From 53cf2d8e659310de45c1d0262bf2b96da122a1ce Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 10:23:48 -0700 Subject: [PATCH 20/32] migrating from .VCD to .GHW because GHW supports record type dumps --- tests/test_AxiStreamFifoV2IpIntegrator.py | 6 ++++-- tests/test_AxiVersionIpIntegrator.py | 6 ++++-- tests/test_DspComparator.py | 5 +++++ tests/test_LineCode10b12bTb.py | 6 ++++-- tests/test_LineCode12b14bTb.py | 6 ++++-- tests/test_LineCode8b10bTb.py | 6 ++++-- 6 files changed, 25 insertions(+), 10 deletions(-) diff --git a/tests/test_AxiStreamFifoV2IpIntegrator.py b/tests/test_AxiStreamFifoV2IpIntegrator.py index e35d7ca460..e9afe7c8d2 100644 --- a/tests/test_AxiStreamFifoV2IpIntegrator.py +++ b/tests/test_AxiStreamFifoV2IpIntegrator.py @@ -195,6 +195,8 @@ def test_AxiStreamFifoV2IpIntegrator(parameters): # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], - # Dump waveform to file ($ gtkwave sim_build/AxiStreamFifoV2IpIntegrator/AxiStreamFifoV2IpIntegrator.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_AxiVersionIpIntegrator.py b/tests/test_AxiVersionIpIntegrator.py index 520ea76dc6..32fffb491a 100644 --- a/tests/test_AxiVersionIpIntegrator.py +++ b/tests/test_AxiVersionIpIntegrator.py @@ -130,6 +130,8 @@ def test_AxiVersionIpIntegrator(parameters): # -frelaxed-rules option to allow IP integrator attributes vhdl_compile_args = ['-fsynopsys','-frelaxed-rules'], - # Dump waveform to file ($ gtkwave sim_build/AxiVersionIpIntegrator/AxiVersionIpIntegrator.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_DspComparator.py b/tests/test_DspComparator.py index 85b4673633..b06634d10a 100644 --- a/tests/test_DspComparator.py +++ b/tests/test_DspComparator.py @@ -161,4 +161,9 @@ def test_DspComparator(parameters): # Select a simulator simulator="ghdl", + + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_LineCode10b12bTb.py b/tests/test_LineCode10b12bTb.py index a87dac1f2f..ed76db45ca 100644 --- a/tests/test_LineCode10b12bTb.py +++ b/tests/test_LineCode10b12bTb.py @@ -169,6 +169,8 @@ def test_LineCode10b12bTb(parameters): # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys', '-fexplicit'], - # Dump waveform to file ($ gtkwave sim_build/LineCode12b14bTb./LineCode12b14bTb.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_LineCode12b14bTb.py b/tests/test_LineCode12b14bTb.py index 05bd7d03c0..fdd4c0f817 100644 --- a/tests/test_LineCode12b14bTb.py +++ b/tests/test_LineCode12b14bTb.py @@ -233,6 +233,8 @@ def test_LineCode12b14bTb(parameters): # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys', '-fexplicit'], - # Dump waveform to file ($ gtkwave sim_build/LineCode12b14bTb./LineCode12b14bTb.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_LineCode8b10bTb.py b/tests/test_LineCode8b10bTb.py index 4da7ca93ba..8c6f065362 100644 --- a/tests/test_LineCode8b10bTb.py +++ b/tests/test_LineCode8b10bTb.py @@ -162,6 +162,8 @@ def test_LineCode8b10bTb(parameters): # Select a simulator simulator="ghdl", - # Dump waveform to file ($ gtkwave sim_build/LineCode8b10bTb.NUM_BYTES_G\=1/LineCode8b10bTb.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) From 010b9c44982fa0ab9e6ee2c4634d064ca3b579db Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 13:43:22 -0700 Subject: [PATCH 21/32] bug fixes for AxiStreamGearbox.vhd --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index 05e7411855..30a785eae6 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -72,7 +72,7 @@ architecture rtl of AxiStreamGearbox is constant MAX_C : positive := maximum(MST_BYTES_C, SLV_BYTES_C); constant MIN_C : positive := minimum(MST_BYTES_C, SLV_BYTES_C); - constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C; + constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C + 1; type RegType is record writeIndex : natural range 0 to SHIFT_WIDTH_C-1; @@ -265,7 +265,7 @@ begin end if; -- Increment writeIndex - v.writeIndex := v.writeIndex + SLV_BYTES_C; + v.writeIndex := v.writeIndex + getTKeep(resize(sAxisMaster.tKeep(1*SLV_BYTES_C-1 downto 0), AXI_STREAM_MAX_TKEEP_WIDTH_C), SLAVE_AXI_CONFIG_G); -- Assert tValid if (v.writeIndex >= MST_BYTES_C) or (sAxisMaster.tLast = '1') then From 4a90a1e7598f1fd3a5ea90f42cc30050272cd2e9 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 14:09:42 -0700 Subject: [PATCH 22/32] bug fixes for AxiStreamGearbox.vhd for when (SLV_BYTES_C>2*MST_BYTES_C) and terminating a frame --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index 30a785eae6..0901b7f163 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -72,7 +72,7 @@ architecture rtl of AxiStreamGearbox is constant MAX_C : positive := maximum(MST_BYTES_C, SLV_BYTES_C); constant MIN_C : positive := minimum(MST_BYTES_C, SLV_BYTES_C); - constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C + 1; + constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C; type RegType is record writeIndex : natural range 0 to SHIFT_WIDTH_C-1; @@ -212,8 +212,10 @@ begin -- Set the flags v.tValid := '1'; - v.tLast := r.tLastDly; - v.tLastDly := '0'; + if (v.writeIndex <= MST_BYTES_C) then + v.tLast := r.tLastDly; + v.tLastDly := '0'; + end if; end if; From 22f55b66bcceee8722fb07242bed8c100dd4f2ea Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 14:12:26 -0700 Subject: [PATCH 23/32] updating paramSweep to include non-word multiple to execise AxiStreamGearbox --- tests/test_AxiStreamFifoV2IpIntegrator.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tests/test_AxiStreamFifoV2IpIntegrator.py b/tests/test_AxiStreamFifoV2IpIntegrator.py index e9afe7c8d2..641d419970 100644 --- a/tests/test_AxiStreamFifoV2IpIntegrator.py +++ b/tests/test_AxiStreamFifoV2IpIntegrator.py @@ -87,6 +87,10 @@ async def m_cycle_reset(self): async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + # Debug messages in case it fails + dut._log.info( f'Found M_TDATA_NUM_BYTES={dut.M_TDATA_NUM_BYTES.value.integer}' ) + dut._log.info( f'Found S_TDATA_NUM_BYTES={dut.S_TDATA_NUM_BYTES.value.integer}' ) + tb = TB(dut) id_count = 2**len(tb.source.bus.tid) @@ -144,8 +148,8 @@ def incrementing_payload(length): ############################################################################## paramSweep = [] -for sTdataByte in ['2','6']: - for mTdataByte in ['2','6']: +for sTdataByte in ['2','5','6']: + for mTdataByte in ['2','5','6']: tmpDict = { "M_TDATA_NUM_BYTES": mTdataByte, "S_TDATA_NUM_BYTES": sTdataByte, From d255eb3525d681fa5370625c67761f29e442537e Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Tue, 11 Jul 2023 22:58:14 -0700 Subject: [PATCH 24/32] Fix ADC python code --- python/surf/devices/ti/_Adc32Rf45.py | 437 ++++++++------------ python/surf/devices/ti/_Adc32Rf45Channel.py | 57 ++- 2 files changed, 212 insertions(+), 282 deletions(-) diff --git a/python/surf/devices/ti/_Adc32Rf45.py b/python/surf/devices/ti/_Adc32Rf45.py index 4776191058..df58f21540 100644 --- a/python/surf/devices/ti/_Adc32Rf45.py +++ b/python/surf/devices/ti/_Adc32Rf45.py @@ -22,36 +22,28 @@ def __init__( self, verify=True, **kwargs): ################ # Base addresses ################ - generalAddr = (0x0 << 14) # 0000000 - offsetCorrector = (0x1 << 14) # With respect to CH # 0x04000 - # digitalGain = (0x2 << 14) # With respect to CH # 0x08000 - mainDigital = (0x3 << 14) # With respect to CH # 0x0C000 - jesdDigital = (0x4 << 14) # With respect to CH # 0x10000 - # decFilter = (0x5 << 14) # With respect to CH # 0x14000 - # pwrDet = (0x6 << 14) # With respect to CH # 0x18000 - masterPage = (0x7 << 14) # 0x1C000 - analogPage = (0x8 << 14) # 0x20000 - chA = (0x0 << 14) - chB = (0x8 << 14) - rawInterface = (0x1 << 18) # 0x40000 - - + generalAddr = (0x0 << 14) # 0000000 + masterPage = (0x7 << 14) # 0x1C000 + analogPage = (0x8 << 14) # 0x20000 + chA = (0x0 << 14) # 0x00000 + chB = (0x8 << 14) # 0x20000 + rawInterface = (0x1 << 18) # 0x40000 ##################### # Add Device Channels ##################### - self.add(surf.devices.ti.Adc32Rf45Channel(name='CH[0]',description='Channel A',offset=(0x0 << 14),expand=False,verify=verify)) - self.add(surf.devices.ti.Adc32Rf45Channel(name='CH[1]',description='Channel B',offset=(0x8 << 14),expand=False,verify=verify)) + self.add(surf.devices.ti.Adc32Rf45Channel(name='CH[0]',description='Channel A',offset=chA,expand=False,verify=verify)) + self.add(surf.devices.ti.Adc32Rf45Channel(name='CH[1]',description='Channel B',offset=chB,expand=False,verify=verify)) ################## # General Register ################## - self.add(pr.RemoteVariable(name='GeneralAddr0', - offset = generalAddr + (4*0x0000), # 0x00000 - 0x00FFF + self.add(pr.RemoteVariable(name='GeneralAddr', + offset = generalAddr + (4*0x0000), # 0x00000 - 0x001FF base = pr.UInt, - bitSize = 32*0x400, # 4KBytes + bitSize = 32*0x80, # 512Bytes bitOffset = 0, - numValues = 0x400, + numValues = 0x80, valueBits = 32, valueStride = 32, updateNotify = False, @@ -60,20 +52,6 @@ def __init__( self, verify=True, **kwargs): overlapEn = True, verify = False)) - self.add(pr.RemoteVariable(name='GeneralAddr4', - offset = generalAddr + (4*0x4000), # 0x08000 - 0x08FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - overlapEn = False, - verify = False)) - self.add(pr.RemoteCommand( name = "RESET", description = "Send 0x81 value to reset the device", @@ -96,138 +74,49 @@ def __init__( self, verify=True, **kwargs): base = pr.UInt, mode = "RW", hidden = True, + overlapEn = True, )) - ################## - # Offset Corrector - ################## - self.add(pr.RemoteVariable(name='OffsetCorrectorA', - offset = offsetCorrector + chA, # 0x04000 - 0x04FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - self.add(pr.RemoteVariable(name='OffsetCorrectorB', - offset = offsetCorrector + chB, # 0x24000 - 0x24FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - ################## - # Main Digital - ################## - self.add(pr.RemoteVariable(name='MainDigitalA', - offset = mainDigital + chA, # 0x0C000 - 0x0CFFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - self.add(pr.RemoteVariable(name='MainDigitalB', - offset = mainDigital + chB, # 0x2C000 - 0x2CFFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - ################## - # JSESD Digital - ################## - self.add(pr.RemoteVariable(name='JesdDigitalA', - offset = jesdDigital + chA, # 0x10000 - 0x10FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - - self.add(pr.RemoteVariable(name='JesdDigitalB', - offset = jesdDigital + chB, # 0x30000 - 0x30FFF - base = pr.UInt, - bitSize = 32*0x400, # 4KBytes - bitOffset = 0, - numValues = 0x400, - valueBits = 32, - valueStride = 32, - updateNotify = False, - bulkOpEn = False, - hidden = True, - verify = False)) - ################## # Raw Interface ################## self.add(pr.RemoteVariable(name='RawInterface0', - offset = rawInterface + (4*0x0000), # 0x40000 - 0x40FFF + offset = rawInterface + (4*0x0000), # 0x40000 - 0x401FF base = pr.UInt, - bitSize = 32*0x400, # 4KBytes + bitSize = 32*0x80, # 512 Bytes bitOffset = 0, - numValues = 0x400, + numValues = 0x80, valueBits = 32, valueStride = 32, updateNotify = False, bulkOpEn = False, hidden = True, - overlapEn = False, verify = False)) self.add(pr.RemoteVariable(name='RawInterface4', - offset = rawInterface + (4*0x4000), # 0x50000 - 0x50FFF + offset = rawInterface + (4*0x4000), # 0x50000 - 0x5003F base = pr.UInt, - bitSize = 32*0x400, # 4KBytes + bitSize = 32*0x10, # 64 Bytes bitOffset = 0, - numValues = 0x400, + numValues = 0x10, valueBits = 32, valueStride = 32, updateNotify = False, bulkOpEn = False, hidden = True, - overlapEn = False, verify = False)) self.add(pr.RemoteVariable(name='RawInterface6', - offset = rawInterface + (4*0x6000), # 0x58000 - 0x58FFF + offset = rawInterface + (4*0x6000), # 0x58000 - 0x583FF base = pr.UInt, - bitSize = 32*0x400, # 4KBytes + bitSize = 32*0x100, # 1024 Bytes bitOffset = 0, - numValues = 0x400, + numValues = 0x100, valueBits = 32, valueStride = 32, updateNotify = False, bulkOpEn = False, hidden = True, - overlapEn = False, verify = False)) ############# @@ -402,9 +291,9 @@ def __init__( self, verify=True, **kwargs): verify = verify, )) - # ########## - # # ADC PAGE - # ########## + # ########## + # # ADC PAGE + # ########## self.add(pr.RemoteVariable( name = "SLOW_SP_EN1", description = "0 = ADC sampling rates are faster than 2.5 GSPS, 1 = ADC sampling rates are slower than 2.5 GSPS", @@ -433,12 +322,12 @@ def __init__( self, verify=True, **kwargs): ############################## @self.command(description = "Device Initiation") def Init(): - self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select - self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier - self.GeneralAddr0.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero - self.GeneralAddr0.set(value=0x00,index=0x020) - self.JesdDigitalA.set(value=0x00,index=0x03E) - self.JesdDigitalB.set(value=0x00,index=0x03E) + self.GeneralAddr.set(value=0x04,index=0x012) # write 4 to address 12 page select + self.GeneralAddr.set(value=0x00,index=0x056) # sysref dis - check this was written earlier + self.GeneralAddr.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero + self.GeneralAddr.set(value=0x00,index=0x020) + self.CH[0].JesdDigital.set(value=0x00,index=0x03E) + self.CH[1].JesdDigital.set(value=0x00,index=0x03E) self.IL_Config_Nyq1_ChA() self.IL_Config_Nyq1_ChB() @@ -453,87 +342,87 @@ def Init(): time.sleep(0.250) - self.OffsetCorrectorA.set(value=0xA2,index=0x068) #... freeze offset estimation - self.OffsetCorrectorB.set(value=0xA2,index=0x068) #... freeze offset estimation + self.CH0[0].OffsetCorrector.set(value=0xA2,index=0x068) #... freeze offset estimation + self.CH0[1].OffsetCorrector.set(value=0xA2,index=0x068) #... freeze offset estimation - self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select - self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier - self.GeneralAddr0.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero - self.GeneralAddr0.set(value=0x00,index=0x020) + self.GeneralAddr.set(value=0x04,index=0x012) # write 4 to address 12 page select + self.GeneralAddr.set(value=0x00,index=0x056) # sysref dis - check this was written earlier + self.GeneralAddr.set(value=0x00,index=0x057) # sysref dis - whether it has to be zero + self.GeneralAddr.set(value=0x00,index=0x020) - self.GeneralAddr0.set(value=0x04,index=0x012) # write 4 to address 12 page select - self.JesdDigitalA.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF - self.JesdDigitalB.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF + self.GeneralAddr.set(value=0x04,index=0x012) # write 4 to address 12 page select + self.CH[0].JesdDigital.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF + self.CH[1].JesdDigital.set(value=0x40,index=0x03E) #... MASK CLKDIV SYSREF - self.JesdDigitalA.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF - self.JesdDigitalB.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF + self.CH[0].JesdDigital.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF + self.CH[1].JesdDigital.set(value=0x60,index=0x03E) #... MASK CLKDIV SYSREF + MASK NCO SYSREF - self.GeneralAddr0.set(value=0x10,index=0x020) # PDN_SYSREF = 0x1 + self.GeneralAddr.set(value=0x10,index=0x020) # PDN_SYSREF = 0x1 @self.command() def Powerup_AnalogConfig(): - self.GeneralAddr0.set(value=0x81,index=0x000) # Global software reset. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config - self.GeneralAddr0.set(value=0xFF,index=0x011) # Select ADC page. - self.GeneralAddr0.set(value=0xC0,index=0x022) # Analog trims start here. - self.GeneralAddr0.set(value=0x80,index=0x032) # ... - self.GeneralAddr0.set(value=0x08,index=0x033) # ... - self.GeneralAddr0.set(value=0x03,index=0x042) # ... - self.GeneralAddr0.set(value=0x03,index=0x043) # ... - self.GeneralAddr0.set(value=0x58,index=0x045) # ... - self.GeneralAddr0.set(value=0xC4,index=0x046) # ... - self.GeneralAddr0.set(value=0x01,index=0x047) # ... - self.GeneralAddr0.set(value=0x01,index=0x053) # ... - self.GeneralAddr0.set(value=0x08,index=0x054) # ... - self.GeneralAddr0.set(value=0x05,index=0x064) # ... - self.GeneralAddr0.set(value=0x84,index=0x072) # ... - self.GeneralAddr0.set(value=0x80,index=0x08C) # ... - self.GeneralAddr0.set(value=0x80,index=0x097) # ... - self.GeneralAddr0.set(value=0x38,index=0x0F0) # ... - self.GeneralAddr0.set(value=0xBF,index=0x0F1) # Analog trims ended here. - self.GeneralAddr0.set(value=0x00,index=0x011) # Disable ADC Page - self.GeneralAddr0.set(value=0x04,index=0x012) # Select Master Page - self.GeneralAddr0.set(value=0x01,index=0x025) # Global Analog Trims start here. - self.GeneralAddr0.set(value=0x40,index=0x026) #... - self.GeneralAddr0.set(value=0x80,index=0x027) #... - self.GeneralAddr0.set(value=0x40,index=0x029) #... - self.GeneralAddr0.set(value=0x80,index=0x02A) #... - self.GeneralAddr0.set(value=0x40,index=0x02C) #... - self.GeneralAddr0.set(value=0x80,index=0x02D) #... - self.GeneralAddr0.set(value=0x40,index=0x02F) #... - self.GeneralAddr0.set(value=0x01,index=0x034) #... - self.GeneralAddr0.set(value=0x01,index=0x03F) #... - self.GeneralAddr0.set(value=0x50,index=0x039) #... - self.GeneralAddr0.set(value=0x28,index=0x03B) #... - self.GeneralAddr0.set(value=0x80,index=0x040) #... - self.GeneralAddr0.set(value=0x40,index=0x042) #... - self.GeneralAddr0.set(value=0x80,index=0x043) #... - self.GeneralAddr0.set(value=0x40,index=0x045) #... - self.GeneralAddr0.set(value=0x80,index=0x046) #... - self.GeneralAddr0.set(value=0x40,index=0x048) #... - self.GeneralAddr0.set(value=0x80,index=0x049) #... - self.GeneralAddr0.set(value=0x40,index=0x04B) #... - self.GeneralAddr0.set(value=0x60,index=0x053) #... - self.GeneralAddr0.set(value=0x02,index=0x059) #... - self.GeneralAddr0.set(value=0x08,index=0x05B) #... - self.GeneralAddr0.set(value=0x07,index=0x05C) #... - self.GeneralAddr0.set(value=0x10,index=0x057) # Register control for SYSREF --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x00,index=0x057) # Give SYSREF control back to device pin --these lines are added in revision SBAA226C. - self.GeneralAddr0.set(value=0x00,index=0x056) # sysref dis - check this was written earlier - self.GeneralAddr0.set(value=0x00,index=0x020) # Pdn sysref = 0 - self.GeneralAddr0.set(value=0x00,index=0x012) # Master page disabled - self.GeneralAddr0.set(value=0xFF,index=0x011) # Select ADC Page - self.GeneralAddr0.set(value=0x07,index=0x083) # Additioanal Analog trims - self.GeneralAddr0.set(value=0x00,index=0x05C) #... - self.GeneralAddr0.set(value=0x01,index=0x05C) #... - self.GeneralAddr0.set(value=0x00,index=0x011) #Disable ADC Page. Power up Analog writes end here. Program appropriate -->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config - - self.GeneralAddr4.set(value=0x00,index=0x001) #DC corrector Bandwidth settings - self.GeneralAddr4.set(value=0x00,index=0x002) #... - self.GeneralAddr4.set(value=0x00,index=0x003) #... + self.GeneralAddr.set(value=0x81,index=0x000) # Global software reset. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config + self.GeneralAddr.set(value=0xFF,index=0x011) # Select ADC page. + self.GeneralAddr.set(value=0xC0,index=0x022) # Analog trims start here. + self.GeneralAddr.set(value=0x80,index=0x032) # ... + self.GeneralAddr.set(value=0x08,index=0x033) # ... + self.GeneralAddr.set(value=0x03,index=0x042) # ... + self.GeneralAddr.set(value=0x03,index=0x043) # ... + self.GeneralAddr.set(value=0x58,index=0x045) # ... + self.GeneralAddr.set(value=0xC4,index=0x046) # ... + self.GeneralAddr.set(value=0x01,index=0x047) # ... + self.GeneralAddr.set(value=0x01,index=0x053) # ... + self.GeneralAddr.set(value=0x08,index=0x054) # ... + self.GeneralAddr.set(value=0x05,index=0x064) # ... + self.GeneralAddr.set(value=0x84,index=0x072) # ... + self.GeneralAddr.set(value=0x80,index=0x08C) # ... + self.GeneralAddr.set(value=0x80,index=0x097) # ... + self.GeneralAddr.set(value=0x38,index=0x0F0) # ... + self.GeneralAddr.set(value=0xBF,index=0x0F1) # Analog trims ended here. + self.GeneralAddr.set(value=0x00,index=0x011) # Disable ADC Page + self.GeneralAddr.set(value=0x04,index=0x012) # Select Master Page + self.GeneralAddr.set(value=0x01,index=0x025) # Global Analog Trims start here. + self.GeneralAddr.set(value=0x40,index=0x026) #... + self.GeneralAddr.set(value=0x80,index=0x027) #... + self.GeneralAddr.set(value=0x40,index=0x029) #... + self.GeneralAddr.set(value=0x80,index=0x02A) #... + self.GeneralAddr.set(value=0x40,index=0x02C) #... + self.GeneralAddr.set(value=0x80,index=0x02D) #... + self.GeneralAddr.set(value=0x40,index=0x02F) #... + self.GeneralAddr.set(value=0x01,index=0x034) #... + self.GeneralAddr.set(value=0x01,index=0x03F) #... + self.GeneralAddr.set(value=0x50,index=0x039) #... + self.GeneralAddr.set(value=0x28,index=0x03B) #... + self.GeneralAddr.set(value=0x80,index=0x040) #... + self.GeneralAddr.set(value=0x40,index=0x042) #... + self.GeneralAddr.set(value=0x80,index=0x043) #... + self.GeneralAddr.set(value=0x40,index=0x045) #... + self.GeneralAddr.set(value=0x80,index=0x046) #... + self.GeneralAddr.set(value=0x40,index=0x048) #... + self.GeneralAddr.set(value=0x80,index=0x049) #... + self.GeneralAddr.set(value=0x40,index=0x04B) #... + self.GeneralAddr.set(value=0x60,index=0x053) #... + self.GeneralAddr.set(value=0x02,index=0x059) #... + self.GeneralAddr.set(value=0x08,index=0x05B) #... + self.GeneralAddr.set(value=0x07,index=0x05C) #... + self.GeneralAddr.set(value=0x10,index=0x057) # Register control for SYSREF --these lines are added in revision SBAA226C. + self.GeneralAddr.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. + self.GeneralAddr.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. + self.GeneralAddr.set(value=0x18,index=0x057) # Pulse SYSREF, pull high --these lines are added in revision SBAA226C. + self.GeneralAddr.set(value=0x10,index=0x057) # Pulse SYSREF, pull back low --these lines are added in revision SBAA226C. + self.GeneralAddr.set(value=0x00,index=0x057) # Give SYSREF control back to device pin --these lines are added in revision SBAA226C. + self.GeneralAddr.set(value=0x00,index=0x056) # sysref dis - check this was written earlier + self.GeneralAddr.set(value=0x00,index=0x020) # Pdn sysref = 0 + self.GeneralAddr.set(value=0x00,index=0x012) # Master page disabled + self.GeneralAddr.set(value=0xFF,index=0x011) # Select ADC Page + self.GeneralAddr.set(value=0x07,index=0x083) # Additioanal Analog trims + self.GeneralAddr.set(value=0x00,index=0x05C) #... + self.GeneralAddr.set(value=0x01,index=0x05C) #... + self.GeneralAddr.set(value=0x00,index=0x011) #Disable ADC Page. Power up Analog writes end here. Program appropriate -->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config + + self.RawInterface4.set(value=0x00,index=0x001) #DC corrector Bandwidth settings + self.RawInterface4.set(value=0x00,index=0x002) #... + self.RawInterface4.set(value=0x00,index=0x003) #... self.RawInterface4.set(value=0x61,index=0x004) #... self.RawInterface6.set(value=0x22,index=0x068) #... self.RawInterface4.set(value=0x01,index=0x003) #... @@ -541,55 +430,55 @@ def Powerup_AnalogConfig(): @self.command(description = "Set IL ChA") def IL_Config_Nyq1_ChA(): - self.MainDigitalA.set(value=0x01,index=0x044) # Program global settings for Interleaving Corrector - self.MainDigitalA.set(value=0x04,index=0x068) # - self.MainDigitalA.set(value=0xC0,index=0x0FF) #... - self.MainDigitalA.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A - self.MainDigitalA.set(value=0x03,index=0x0A9) #... - self.MainDigitalA.set(value=0x77,index=0x0AB) #... - self.MainDigitalA.set(value=0x01,index=0x0AC) #... - self.MainDigitalA.set(value=0x77,index=0x0AD) #... - self.MainDigitalA.set(value=0x01,index=0x0AE) #... - self.MainDigitalA.set(value=0x0F,index=0x096) #... - self.MainDigitalA.set(value=0x26,index=0x097) #... - self.MainDigitalA.set(value=0x0C,index=0x08F) #... - self.MainDigitalA.set(value=0x08,index=0x08C) #... - self.MainDigitalA.set(value=0x0F,index=0x080) #... - self.MainDigitalA.set(value=0xCB,index=0x081) #... - self.MainDigitalA.set(value=0x03,index=0x07D) #... - self.MainDigitalA.set(value=0x75,index=0x056) #... - self.MainDigitalA.set(value=0x75,index=0x057) #... - self.MainDigitalA.set(value=0x00,index=0x053) #... - self.MainDigitalA.set(value=0x03,index=0x04B) #... - self.MainDigitalA.set(value=0x80,index=0x049) #... - self.MainDigitalA.set(value=0x26,index=0x043) #... - self.MainDigitalA.set(value=0x01,index=0x05E) #... - self.MainDigitalA.set(value=0x38,index=0x042) #... - self.MainDigitalA.set(value=0x04,index=0x05A) #... - self.MainDigitalA.set(value=0x20,index=0x071) #... - self.MainDigitalA.set(value=0x00,index=0x062) #... - self.MainDigitalA.set(value=0x00,index=0x098) #... - self.MainDigitalA.set(value=0x08,index=0x099) #... - self.MainDigitalA.set(value=0x08,index=0x09C) #... - self.MainDigitalA.set(value=0x20,index=0x09D) #... - self.MainDigitalA.set(value=0x03,index=0x0BE) #... - self.MainDigitalA.set(value=0x00,index=0x069) #... - self.MainDigitalA.set(value=0x10,index=0x045) #... - self.MainDigitalA.set(value=0x64,index=0x08D) #... - self.MainDigitalA.set(value=0x20,index=0x08B) #... - self.MainDigitalA.set(value=0x00,index=0x000) # Dig Core reset - self.MainDigitalA.set(value=0x01,index=0x000) #... - self.MainDigitalA.set(value=0x00,index=0x000) #... + self.CH[0].MainDigital.set(value=0x01,index=0x044) # Program global settings for Interleaving Corrector + self.CH[0].MainDigital.set(value=0x04,index=0x068) # + self.CH[0].MainDigital.set(value=0xC0,index=0x0FF) #... + self.CH[0].MainDigital.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A + self.CH[0].MainDigital.set(value=0x03,index=0x0A9) #... + self.CH[0].MainDigital.set(value=0x77,index=0x0AB) #... + self.CH[0].MainDigital.set(value=0x01,index=0x0AC) #... + self.CH[0].MainDigital.set(value=0x77,index=0x0AD) #... + self.CH[0].MainDigital.set(value=0x01,index=0x0AE) #... + self.CH[0].MainDigital.set(value=0x0F,index=0x096) #... + self.CH[0].MainDigital.set(value=0x26,index=0x097) #... + self.CH[0].MainDigital.set(value=0x0C,index=0x08F) #... + self.CH[0].MainDigital.set(value=0x08,index=0x08C) #... + self.CH[0].MainDigital.set(value=0x0F,index=0x080) #... + self.CH[0].MainDigital.set(value=0xCB,index=0x081) #... + self.CH[0].MainDigital.set(value=0x03,index=0x07D) #... + self.CH[0].MainDigital.set(value=0x75,index=0x056) #... + self.CH[0].MainDigital.set(value=0x75,index=0x057) #... + self.CH[0].MainDigital.set(value=0x00,index=0x053) #... + self.CH[0].MainDigital.set(value=0x03,index=0x04B) #... + self.CH[0].MainDigital.set(value=0x80,index=0x049) #... + self.CH[0].MainDigital.set(value=0x26,index=0x043) #... + self.CH[0].MainDigital.set(value=0x01,index=0x05E) #... + self.CH[0].MainDigital.set(value=0x38,index=0x042) #... + self.CH[0].MainDigital.set(value=0x04,index=0x05A) #... + self.CH[0].MainDigital.set(value=0x20,index=0x071) #... + self.CH[0].MainDigital.set(value=0x00,index=0x062) #... + self.CH[0].MainDigital.set(value=0x00,index=0x098) #... + self.CH[0].MainDigital.set(value=0x08,index=0x099) #... + self.CH[0].MainDigital.set(value=0x08,index=0x09C) #... + self.CH[0].MainDigital.set(value=0x20,index=0x09D) #... + self.CH[0].MainDigital.set(value=0x03,index=0x0BE) #... + self.CH[0].MainDigital.set(value=0x00,index=0x069) #... + self.CH[0].MainDigital.set(value=0x10,index=0x045) #... + self.CH[0].MainDigital.set(value=0x64,index=0x08D) #... + self.CH[0].MainDigital.set(value=0x20,index=0x08B) #... + self.CH[0].MainDigital.set(value=0x00,index=0x000) # Dig Core reset + self.CH[0].MainDigital.set(value=0x01,index=0x000) #... + self.CH[0].MainDigital.set(value=0x00,index=0x000) #... @self.command() def IL_Config_Nyq1_ChB(): - self.MainDigitalB.set(value=0x80,index=0x049) # Special setting for chB - self.MainDigitalB.set(value=0x20,index=0x042) # Special setting for chB - self.MainDigitalB.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chB, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A - self.MainDigitalB.set(value=0x00,index=0x003) # Main digital page selected for chA - self.MainDigitalB.set(value=0x00,index=0x000) #... - self.MainDigitalB.set(value=0x01,index=0x000) #... - self.MainDigitalB.set(value=0x00,index=0x000) #... + self.CH[1].MainDigital.set(value=0x80,index=0x049) # Special setting for chB + self.CH[1].MainDigital.set(value=0x20,index=0x042) # Special setting for chB + self.CH[1].MainDigital.set(value=0x08,index=0x0A2) # Progam nyquist zone 1 for chB, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A + self.CH[1].MainDigital.set(value=0x00,index=0x003) # Main digital page selected for chA + self.CH[1].MainDigital.set(value=0x00,index=0x000) #... + self.CH[1].MainDigital.set(value=0x01,index=0x000) #... + self.CH[1].MainDigital.set(value=0x00,index=0x000) #... @self.command(description = "Set nonlinear trims") def SetNLTrim(): @@ -775,18 +664,18 @@ def JESD_DDC_config(): def DigRst(): # Wait for 50 ms for the device to estimate the interleaving errors time.sleep(0.250) # TODO: Optimize this timeout - self.JesdDigitalA.set(value=0x00,index=0x000) # clear reset - self.JesdDigitalB.set(value=0x00,index=0x000) # clear reset - self.JesdDigitalA.set(value=0x01,index=0x000) # CHA digital reset - self.JesdDigitalB.set(value=0x01,index=0x000) # CHB digital reset - self.JesdDigitalA.set(value=0x00,index=0x000) # clear reset - self.JesdDigitalB.set(value=0x00,index=0x000) # clear reset + self.CH[0].JesdDigital.set(value=0x00,index=0x000) # clear reset + self.CH[1].JesdDigital.set(value=0x00,index=0x000) # clear reset + self.CH[0].JesdDigital.set(value=0x01,index=0x000) # CHA digital reset + self.CH[1].JesdDigital.set(value=0x01,index=0x000) # CHB digital reset + self.CH[0].JesdDigital.set(value=0x00,index=0x000) # clear reset + self.CH[1].JesdDigital.set(value=0x00,index=0x000) # clear reset # Wait for 50 ms for the device to estimate the interleaving errors time.sleep(0.250) # TODO: Optimize this timeout - self.MainDigitalA.set(value=0x00,index=0x000) # clear reset - self.MainDigitalB.set(value=0x00,index=0x000) # clear reset - self.MainDigitalA.set(value=0x01,index=0x000) # CHA digital reset - self.MainDigitalB.set(value=0x01,index=0x000) # CHB digital reset - self.MainDigitalA.set(value=0x00,index=0x000) # clear reset - self.MainDigitalB.set(value=0x00,index=0x000) # clear reset + self.CH[0].MainDigital.set(value=0x00,index=0x000) # clear reset + self.CH[1].MainDigital.set(value=0x00,index=0x000) # clear reset + self.CH[0].MainDigital.set(value=0x01,index=0x000) # CHA digital reset + self.CH[1].MainDigital.set(value=0x01,index=0x000) # CHB digital reset + self.CH[0].MainDigital.set(value=0x00,index=0x000) # clear reset + self.CH[1].MainDigital.set(value=0x00,index=0x000) # clear reset diff --git a/python/surf/devices/ti/_Adc32Rf45Channel.py b/python/surf/devices/ti/_Adc32Rf45Channel.py index b0ac9e15e0..dd3ec1160b 100644 --- a/python/surf/devices/ti/_Adc32Rf45Channel.py +++ b/python/surf/devices/ti/_Adc32Rf45Channel.py @@ -15,23 +15,37 @@ import time class Adc32Rf45Channel(pr.Device): - def __init__( self, verify=True, **kwargs): + def __init__( self, verify=True, offset=0, **kwargs): - super().__init__(**kwargs) + super().__init__(offset=offset, **kwargs) ####################### # Paging base addresses ####################### - offsetCorrector = (0x1 << 14) - digitalGain = (0x2 << 14) - mainDigital = (0x3 << 14) - jesdDigital = (0x4 << 14) - decFilter = (0x5 << 14) - pwrDet = (0x6 << 14) + offsetCorrector = offset + (0x1 << 14) # 0x04000 + digitalGain = offset + (0x2 << 14) # 0x08000 + mainDigital = offset + (0x3 << 14) # 0x0C000 + jesdDigital = offset + (0x4 << 14) # 0x10000 + decFilter = offset + (0x5 << 14) # 0x14000 + pwrDet = offset + (0x6 << 14) # 0x18000 ################## # Offset Corr Page ################## + self.add(pr.RemoteVariable(name='OffsetCorrector', + offset = offsetCorrector, # 0x04000 - 0x041FF + base = pr.UInt, + bitSize = 32*0x80, # 512 Bytes + bitOffset = 0, + numValues = 0x80, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + overlapEn = True, + hidden = True, + verify = False)) + self.add(pr.RemoteVariable( name = "SEL_EXT_EST", description = "This bit selects the external estimate for the offset correction block", @@ -114,6 +128,19 @@ def __init__( self, verify=True, **kwargs): ################### # Main Digital Page ################### + self.add(pr.RemoteVariable(name='MainDigital', + offset = mainDigital, # 0x0C000 - 0x0C1FF + base = pr.UInt, + bitSize = 32*0x80, # 512 Bytes + bitOffset = 0, + numValues = 0x80, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + overlapEn = True, + hidden = True, + verify = False)) self.add(pr.RemoteVariable( name = "NQ_ZONE_EN", @@ -142,6 +169,20 @@ def __init__( self, verify=True, **kwargs): ################### # JESD DIGITAL PAGE ################### + self.add(pr.RemoteVariable(name='JesdDigital', + offset = jesdDigital, # 0x10000 - 0x101FF + base = pr.UInt, + bitSize = 32*0x80, # 512 Bytes + bitOffset = 0, + numValues = 0x80, + valueBits = 32, + valueStride = 32, + updateNotify = False, + bulkOpEn = False, + overlapEn = True, + hidden = True, + verify = False)) + self.add(pr.RemoteVariable( name = "CTRL_K", description = "0 = Default is five frames per multiframe, 1 = Frames per multiframe can be set in register 06h", From 9aaa8cb3d436a66baa5bebcc5d370b5bb8ee9ac0 Mon Sep 17 00:00:00 2001 From: Ryan Herbst Date: Tue, 11 Jul 2023 23:11:16 -0700 Subject: [PATCH 25/32] Fix indentation --- python/surf/devices/ti/_Adc32Rf45.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/python/surf/devices/ti/_Adc32Rf45.py b/python/surf/devices/ti/_Adc32Rf45.py index df58f21540..38971c5b5e 100644 --- a/python/surf/devices/ti/_Adc32Rf45.py +++ b/python/surf/devices/ti/_Adc32Rf45.py @@ -291,9 +291,9 @@ def __init__( self, verify=True, **kwargs): verify = verify, )) - # ########## - # # ADC PAGE - # ########## + # ########## + # # ADC PAGE + # ########## self.add(pr.RemoteVariable( name = "SLOW_SP_EN1", description = "0 = ADC sampling rates are faster than 2.5 GSPS, 1 = ADC sampling rates are slower than 2.5 GSPS", From 8a6243448dd58888f13ae1325835dbbde8eff30d Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 20 Jul 2023 13:15:42 -0700 Subject: [PATCH 26/32] adding test_AxiStreamDemuxMuxTb.py --- axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd | 175 +++++++++++++++++++++ tests/test_AxiStreamDemuxMuxTb.py | 180 ++++++++++++++++++++++ 2 files changed, 355 insertions(+) create mode 100644 axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd create mode 100644 tests/test_AxiStreamDemuxMuxTb.py diff --git a/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd new file mode 100644 index 0000000000..4300c9d7a3 --- /dev/null +++ b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd @@ -0,0 +1,175 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Integrator Wrapper for surf.AxiStreamFifoV2 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity AxiStreamDemuxMuxTb is + generic ( + -- AXI Stream Configuration + TUSER_WIDTH_G : positive range 1 to 8 := 1; + TID_WIDTH_G : positive range 1 to 8 := 1; + TDEST_WIDTH_G : positive range 1 to 8 := 1; + TDATA_NUM_BYTES_G : positive range 1 to 128 := 1; + MUX_STREAMS_G : positive := 2; + PIPE_STAGES_G : natural := 0; + ILEAVE_EN_G : boolean := false; + ILEAVE_ON_NOTVALID_G : boolean := false; + ILEAVE_REARB_G : natural := 0; + REARB_DELAY_G : boolean := true; + FORCED_REARB_HOLD_G : boolean := false); + port ( + -- Clock and Reset + AXIS_ACLK : in std_logic := '0'; + AXIS_ARESETN : in std_logic := '0'; + -- IP Integrator Slave AXI Stream Interface + S_AXIS_TVALID : in std_logic := '0'; + S_AXIS_TDATA : in std_logic_vector((8*TDATA_NUM_BYTES_G)-1 downto 0) := (others => '0'); + S_AXIS_TSTRB : in std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0) := (others => '0'); + S_AXIS_TKEEP : in std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0) := (others => '0'); + S_AXIS_TLAST : in std_logic := '0'; + S_AXIS_TDEST : in std_logic_vector(TDEST_WIDTH_G-1 downto 0) := (others => '0'); + S_AXIS_TID : in std_logic_vector(TID_WIDTH_G-1 downto 0) := (others => '0'); + S_AXIS_TUSER : in std_logic_vector(TUSER_WIDTH_G-1 downto 0) := (others => '0'); + S_AXIS_TREADY : out std_logic; + -- IP Integrator Master AXI Stream Interface + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector((8*TDATA_NUM_BYTES_G)-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0); + M_AXIS_TKEEP : out std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(TDEST_WIDTH_G-1 downto 0); + M_AXIS_TID : out std_logic_vector(TID_WIDTH_G-1 downto 0); + M_AXIS_TUSER : out std_logic_vector(TUSER_WIDTH_G-1 downto 0); + M_AXIS_TREADY : in std_logic); +end AxiStreamDemuxMuxTb; + +architecture mapping of AxiStreamDemuxMuxTb is + + signal axisClk : sl := '0'; + signal axisRst : sl := '0'; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + + signal axisMasters : AxiStreamMasterArray(MUX_STREAMS_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal axisSlaves : AxiStreamSlaveArray(MUX_STREAMS_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 1, + HAS_TREADY => 1, + TUSER_WIDTH => TUSER_WIDTH_G, + TID_WIDTH => TID_WIDTH_G, + TDEST_WIDTH => TDEST_WIDTH_G, + TDATA_NUM_BYTES => TDATA_NUM_BYTES_G) + port map ( + -- IP Integrator AXI Stream Interface + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TSTRB => S_AXIS_TSTRB, + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => S_AXIS_TDEST, + S_AXIS_TID => S_AXIS_TID, + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => axisClk, + axisRst => axisRst, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + U_DeMux : entity surf.AxiStreamDeMux + generic map ( + NUM_MASTERS_G => MUX_STREAMS_G, + PIPE_STAGES_G => PIPE_STAGES_G) + port map ( + -- Clock and reset + axisClk => axisClk, + axisRst => axisRst, + -- Slave + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + -- Masters + mAxisMasters => axisMasters, + mAxisSlaves => axisSlaves); + + U_Mux : entity surf.AxiStreamMux + generic map ( + NUM_SLAVES_G => MUX_STREAMS_G, + PIPE_STAGES_G => PIPE_STAGES_G, + ILEAVE_EN_G => ILEAVE_EN_G, + ILEAVE_ON_NOTVALID_G => ILEAVE_ON_NOTVALID_G, + ILEAVE_REARB_G => ILEAVE_REARB_G, + REARB_DELAY_G => REARB_DELAY_G, + FORCED_REARB_HOLD_G => FORCED_REARB_HOLD_G) + port map ( + -- Clock and reset + axisClk => axisClk, + axisRst => axisRst, + -- Slaves + sAxisMasters => axisMasters, + sAxisSlaves => axisSlaves, + -- Master + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 1, + HAS_TREADY => 1, + TUSER_WIDTH => TUSER_WIDTH_G, + TID_WIDTH => TID_WIDTH_G, + TDEST_WIDTH => TDEST_WIDTH_G, + TDATA_NUM_BYTES => TDATA_NUM_BYTES_G) + port map ( + -- IP Integrator AXI Stream Interface + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TSTRB => M_AXIS_TSTRB, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => M_AXIS_TDEST, + M_AXIS_TID => M_AXIS_TID, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => open, + axisRst => open, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + +end mapping; diff --git a/tests/test_AxiStreamDemuxMuxTb.py b/tests/test_AxiStreamDemuxMuxTb.py new file mode 100644 index 0000000000..4a31856021 --- /dev/null +++ b/tests/test_AxiStreamDemuxMuxTb.py @@ -0,0 +1,180 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import itertools +import logging +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink + +# test_AxiStreamDemuxMuxTb +from cocotb_test.simulator import run +import pytest +import glob +import os + +class TB: + def __init__(self, dut): + + # Pointer to DUT object + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Start AXIS_ACLK clock (200 MHz) in a separate thread + cocotb.start_soon(Clock(dut.AXIS_ACLK, 5.0, units='ns').start()) + + # Setup the AXI stream source + self.source = AxiStreamSource( + bus = AxiStreamBus.from_prefix(dut, "S_AXIS"), + clock = dut.AXIS_ACLK, + reset = dut.AXIS_ARESETN, + reset_active_level = False, + ) + + # Setup the AXI stream sink + self.sink = AxiStreamSink( + bus = AxiStreamBus.from_prefix(dut, "M_AXIS"), + clock = dut.AXIS_ACLK, + reset = dut.AXIS_ARESETN, + reset_active_level = False, + ) + + def set_idle_generator(self, generator=None): + if generator: + self.source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.sink.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.AXIS_ARESETN.setimmediatevalue(0) + await RisingEdge(self.dut.AXIS_ACLK) + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 0 + await RisingEdge(self.dut.AXIS_ACLK) + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 1 + await RisingEdge(self.dut.AXIS_ACLK) + await RisingEdge(self.dut.AXIS_ACLK) + +async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + id_count = 2**len(tb.source.bus.tid) + + cur_id = 1 + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for test_data in [payload_data(x) for x in payload_lengths()]: + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id + test_frame.tdest = cur_id + await tb.source.send(test_frame) + + test_frames.append(test_frame) + + cur_id = (cur_id + 1) % id_count + + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + +def size_list(): + return list(range(1, 32+1)) + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + +if cocotb.SIM_NAME: + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + +tests_dir = os.path.dirname(__file__) +tests_module = 'AxiStreamDemuxMuxTb' + +############################################################################## + +@pytest.mark.parametrize( + "parameters", [ + {'MUX_STREAMS_G': '2', 'PIPE_STAGES_G': '0'}, + {'MUX_STREAMS_G': '3', 'PIPE_STAGES_G': '1'}, + ]) +def test_AxiStreamDemuxMuxTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}.' + ",".join((f"{key}={value}" for key, value in parameters.items())), + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # -frelaxed-rules option to allow IP integrator attributes + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], + + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], + ) From 801ad8d3f77ea90c6a7e242ad1d0fecebfe642b1 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 20 Jul 2023 15:43:23 -0700 Subject: [PATCH 27/32] code clean up --- axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd | 2 +- tests/test_LineCode10b12bTb.py | 2 +- tests/test_LineCode12b14bTb.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd index 4300c9d7a3..330106d80e 100644 --- a/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd +++ b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: IP Integrator Wrapper for surf.AxiStreamFifoV2 +-- Description: surf.AxiStreamDemux/surf.AxiStreamMux cocoTB testbed ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/tests/test_LineCode10b12bTb.py b/tests/test_LineCode10b12bTb.py index ed76db45ca..099cb906e3 100644 --- a/tests/test_LineCode10b12bTb.py +++ b/tests/test_LineCode10b12bTb.py @@ -157,7 +157,7 @@ def test_LineCode10b12bTb(parameters): parameters = parameters, # The directory used to compile the tests. (default: sim_build) - sim_build = f'{tests_dir}/sim_build/{tests_module}.', + sim_build = f'{tests_dir}/sim_build/{tests_module}', # A dictionary of extra environment variables set in simulator process. extra_env=parameters, diff --git a/tests/test_LineCode12b14bTb.py b/tests/test_LineCode12b14bTb.py index fdd4c0f817..f429e68937 100644 --- a/tests/test_LineCode12b14bTb.py +++ b/tests/test_LineCode12b14bTb.py @@ -221,7 +221,7 @@ def test_LineCode12b14bTb(parameters): parameters = parameters, # The directory used to compile the tests. (default: sim_build) - sim_build = f'{tests_dir}/sim_build/{tests_module}.', + sim_build = f'{tests_dir}/sim_build/{tests_module}', # A dictionary of extra environment variables set in simulator process. extra_env=parameters, From e82ca430b90175c619ae5a03b6be679a1ead59fc Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 21 Jul 2023 13:07:34 -0700 Subject: [PATCH 28/32] Add initialization values for tx registers --- protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd | 85 +------------------ protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd | 64 +++++++------- protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd | 22 ++--- protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd | 22 ++--- 4 files changed, 56 insertions(+), 137 deletions(-) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index baf6c5cf88..3602ecd79c 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -5,87 +5,6 @@ ------------------------------------------------------------------------------- -- Description: -- AXI-Lite block to manage the PGP interface. --- --- Address map (offset from base): --- 0x00 = Read/Write --- Bits 0 = Count Reset --- 0x04 = Read/Write --- Bits 0 = Reset Rx --- 0x08 = Read/Write --- Bits 0 = Flush --- 0x0C = Read/Write --- Bits 1:0 = Loop Back --- 0x10 = Read/Write --- Bits 7:0 = Sideband data to transmit --- Bits 8 = Sideband data enable --- 0x14 = Read/Write --- Bits 0 = Auto Status Send Enable (PPI) --- 0x18 = Read/Write --- Bits 0 = Disable Flow Control --- 0x20 = Read Only --- Bits 0 = Rx Phy Ready --- Bits 1 = Tx Phy Ready --- Bits 2 = Local Link Ready --- Bits 3 = Remote Link Ready --- Bits 4 = Transmit Ready --- Bits 9:8 = Receive Link Polarity --- Bits 15:12 = Remote Pause Status --- Bits 19:16 = Local Pause Status --- Bits 23:20 = Remote Overflow Status --- Bits 27:24 = Local Overflow Status --- 0x24 = Read Only --- Bits 7:0 = Remote Link Data --- 0x28 = Read Only --- Bits ?:0 = Cell Error Count --- 0x2C = Read Only --- Bits ?:0 = Link Down Count --- 0x30 = Read Only --- Bits ?:0 = Link Error Count --- 0x34 = Read Only --- Bits ?:0 = Remote Overflow VC 0 Count --- 0x38 = Read Only --- Bits ?:0 = Remote Overflow VC 1 Count --- 0x3C = Read Only --- Bits ?:0 = Remote Overflow VC 2 Count --- 0x40 = Read Only --- Bits ?:0 = Remote Overflow VC 3 Count --- 0x44 = Read Only --- Bits ?:0 = Receive Frame Error Count --- 0x48 = Read Only --- Bits ?:0 = Receive Frame Count --- 0x4C = Read Only --- Bits ?:0 = Local Overflow VC 0 Count --- 0x50 = Read Only --- Bits ?:0 = Local Overflow VC 1 Count --- 0x54 = Read Only --- Bits ?:0 = Local Overflow VC 2 Count --- 0x58 = Read Only --- Bits ?:0 = Local Overflow VC 3 Count --- 0x5C = Read Only --- Bits ?:0 = Transmit Frame Error Count --- 0x60 = Read Only --- Bits ?:0 = Transmit Frame Count --- 0x64 = Read Only --- Bits 31:0 = Receive Clock Frequency --- 0x68 = Read Only --- Bits 31:0 = Transmit Clock Frequency --- 0x70 = Read Only --- Bits 7:0 = Last OpCode Transmitted --- 0x74 = Read Only --- Bits 7:0 = Last OpCode Received --- 0x78 = Read Only --- Bits ?:0 = OpCode Transmit count --- 0x7C = Read Only --- Bits ?:0 = OpCode Received count --- --- Status vector: --- Bits 31:24 = Rx Link Down Count --- Bits 23:16 = Rx Frame Error Count --- Bits 15:8 = Rx Cell Error Count --- Bits 7:6 = Zeros --- Bits 5 = Remote Link Ready --- Bits 4 = Local Link Ready --- Bits 3:0 = Remote Overflow Status ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -400,7 +319,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 100.0, + REFRESH_RATE_G => 1000.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32) @@ -515,7 +434,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 100.0, + REFRESH_RATE_G => 1000.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd index 1ff581ef07..bd5316cd87 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd @@ -41,16 +41,16 @@ entity Pgp2bTxCell is pgpTxLinkReady : in sl; -- Local side has link -- Phy Transmit Interface - cellTxSOC : out sl; -- Cell data start of cell - cellTxSOF : out sl; -- Cell data start of frame - cellTxEOC : out sl; -- Cell data end of cell - cellTxEOF : out sl; -- Cell data end of frame - cellTxEOFE : out sl; -- Cell data end of frame error - cellTxData : out slv(TX_LANE_CNT_G*16-1 downto 0); -- Cell data data + cellTxSOC : out sl := '0'; -- Cell data start of cell + cellTxSOF : out sl := '0'; -- Cell data start of frame + cellTxEOC : out sl := '0'; -- Cell data end of cell + cellTxEOF : out sl := '0'; -- Cell data end of frame + cellTxEOFE : out sl := '0'; -- Cell data end of frame error + cellTxData : out slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); -- Cell data data -- Transmit Scheduler Interface - schTxSOF : out sl; -- Cell contained SOF - schTxEOF : out sl; -- Cell contained EOF + schTxSOF : out sl := '0'; -- Cell contained SOF + schTxEOF : out sl := '0'; -- Cell contained EOF schTxIdle : in sl; -- Force IDLE transmit schTxReq : in sl; -- Cell transmit request schTxAck : out sl; -- Cell transmit acknowledge @@ -121,12 +121,12 @@ architecture Pgp2bTxCell of Pgp2bTxCell is signal muxFrameTxEOFE : sl; signal muxFrameTxData : slv(TX_LANE_CNT_G*16-1 downto 0); signal muxRemAlmostFull : sl; - signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0); + signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0) := (others => '0'); signal cellCntRst : sl; signal nxtFrameTxReady : sl; signal nxtType : slv(2 downto 0); signal nxtTypeLast : slv(2 downto 0); - signal curTypeLast : slv(2 downto 0); + signal curTypeLast : slv(2 downto 0) := (others => '0'); signal nxtTxSOF : sl; signal nxtTxEOF : sl; signal nxtTxAck : sl; @@ -136,27 +136,27 @@ architecture Pgp2bTxCell of Pgp2bTxCell is signal crcWordA : slv(TX_LANE_CNT_G*16-1 downto 0); signal crcWordB : slv(TX_LANE_CNT_G*16-1 downto 0); signal serialCntEn : sl; - signal vc0Serial : slv(5 downto 0); - signal vc1Serial : slv(5 downto 0); - signal vc2Serial : slv(5 downto 0); - signal vc3Serial : slv(5 downto 0); + signal vc0Serial : slv(5 downto 0) := (others => '0'); + signal vc1Serial : slv(5 downto 0) := (others => '0'); + signal vc2Serial : slv(5 downto 0) := (others => '0'); + signal vc3Serial : slv(5 downto 0) := (others => '0'); signal muxSerial : slv(5 downto 0); - signal dly0Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly0Type : slv(2 downto 0); - signal dly1Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly1Type : slv(2 downto 0); - signal dly2Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly2Type : slv(2 downto 0); - signal dly3Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly3Type : slv(2 downto 0); - signal dly4Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly4Type : slv(2 downto 0); - signal int0FrameTxReady : sl; - signal int1FrameTxReady : sl; - signal int2FrameTxReady : sl; - signal int3FrameTxReady : sl; - signal intTimeout : sl; - signal intOverflow : slv(3 downto 0); + signal dly0Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly0Type : slv(2 downto 0) := (others => '0'); + signal dly1Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly1Type : slv(2 downto 0) := (others => '0'); + signal dly2Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly2Type : slv(2 downto 0) := (others => '0'); + signal dly3Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly3Type : slv(2 downto 0) := (others => '0'); + signal dly4Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly4Type : slv(2 downto 0) := (others => '0'); + signal int0FrameTxReady : sl := '0'; + signal int1FrameTxReady : sl := '0'; + signal int2FrameTxReady : sl := '0'; + signal int3FrameTxReady : sl := '0'; + signal intTimeout : sl := '0'; + signal intOverflow : slv(3 downto 0) := (others => '0'); -- Transmit Data Marker constant TX_DATA_C : slv(2 downto 0) := "000"; @@ -169,8 +169,6 @@ architecture Pgp2bTxCell of Pgp2bTxCell is constant TX_CRCB_C : slv(2 downto 0) := "111"; -- Transmit states - signal curState : slv(2 downto 0); - signal nxtState : slv(2 downto 0); constant ST_IDLE_C : slv(2 downto 0) := "001"; constant ST_EMPTY_C : slv(2 downto 0) := "010"; constant ST_SOC_C : slv(2 downto 0) := "011"; @@ -178,6 +176,8 @@ architecture Pgp2bTxCell of Pgp2bTxCell is constant ST_CRCA_C : slv(2 downto 0) := "101"; constant ST_CRCB_C : slv(2 downto 0) := "110"; constant ST_EOC_C : slv(2 downto 0) := "111"; + signal curState : slv(2 downto 0) := ST_IDLE_C; + signal nxtState : slv(2 downto 0); begin diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd index 55c99c2930..7b2269bc55 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd @@ -68,19 +68,19 @@ end Pgp2bTxPhy; architecture Pgp2bTxPhy of Pgp2bTxPhy is -- Local Signals - signal algnCnt : slv(6 downto 0); + signal algnCnt : slv(6 downto 0) := (others => '0'); signal algnCntRst : sl; - signal intTxLinkReady : sl; + signal intTxLinkReady : sl := '0'; signal nxtTxLinkReady : sl; signal nxtTxData : slv(TX_LANE_CNT_G*16-1 downto 0); signal nxtTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal dlyTxData : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dlyTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal dlySelect : sl; - signal intTxData : slv(TX_LANE_CNT_G*16-1 downto 0); - signal intTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal intTxOpCode : slv(7 downto 0); - signal intTxOpCodeEn : sl; + signal dlyTxData : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dlyTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0) := (others => '0'); + signal dlySelect : sl := '0'; + signal intTxData : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal intTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0) := (others => '0'); + signal intTxOpCode : slv(7 downto 0) := (others => '0'); + signal intTxOpCodeEn : sl := '0'; signal skpAData : slv(TX_LANE_CNT_G*16-1 downto 0); signal skpADataK : slv(TX_LANE_CNT_G*2-1 downto 0); signal skpBData : slv(TX_LANE_CNT_G*16-1 downto 0); @@ -95,7 +95,7 @@ architecture Pgp2bTxPhy of Pgp2bTxPhy is signal ltsBDataK : slv(TX_LANE_CNT_G*2-1 downto 0); signal cellData : slv(TX_LANE_CNT_G*16-1 downto 0); signal cellDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal dlyTxEOC : sl; + signal dlyTxEOC : sl := '0'; -- Physical Link State constant ST_LOCK_C : slv(3 downto 0) := "0000"; @@ -107,7 +107,7 @@ architecture Pgp2bTxPhy of Pgp2bTxPhy is constant ST_ALN_B_C : slv(3 downto 0) := "0110"; constant ST_CELL_C : slv(3 downto 0) := "0111"; constant ST_EMPTY_C : slv(3 downto 0) := "1000"; - signal curState : slv(3 downto 0); + signal curState : slv(3 downto 0) := ST_LOCK_C; signal nxtState : slv(3 downto 0); begin diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd index 149f406368..2ec0b9534e 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd @@ -73,22 +73,22 @@ architecture Pgp2bTxSched of Pgp2bTxSched is -- Local Signals signal currValid : sl; - signal currVc : slv(1 downto 0); + signal currVc : slv(1 downto 0) := (others => '0'); signal nextVc : slv(1 downto 0); signal arbVc : slv(1 downto 0); signal arbValid : sl; - signal vcInFrame : slv(3 downto 0); - signal intTxReq : sl; - signal intTxIdle : sl; + signal vcInFrame : slv(3 downto 0) := (others => '0'); + signal intTxReq : sl := '0'; + signal intTxIdle : sl := '0'; signal nxtTxReq : sl; signal nxtTxIdle : sl; signal nxtTxTimeout : sl; - signal intTxTimeout : sl; - signal vcTimerA : slv(23 downto 0); - signal vcTimerB : slv(23 downto 0); - signal vcTimerC : slv(23 downto 0); - signal vcTimerD : slv(23 downto 0); - signal vcTimeout : slv(3 downto 0); + signal intTxTimeout : sl := '0'; + signal vcTimerA : slv(23 downto 0) := (others => '0'); + signal vcTimerB : slv(23 downto 0) := (others => '0'); + signal vcTimerC : slv(23 downto 0) := (others => '0'); + signal vcTimerD : slv(23 downto 0) := (others => '0'); + signal vcTimeout : slv(3 downto 0) := (others => '0'); signal gateTxValid : slv(3 downto 0); -- Schedular state @@ -98,7 +98,7 @@ architecture Pgp2bTxSched of Pgp2bTxSched is constant ST_GAP_A_C : slv(2 downto 0) := "100"; constant ST_GAP_B_C : slv(2 downto 0) := "101"; constant ST_GAP_C_C : slv(2 downto 0) := "110"; - signal curState : slv(2 downto 0); + signal curState : slv(2 downto 0) := ST_ARB_C; signal nxtState : slv(2 downto 0); begin From 1d900d3b0df5439460e266e678f95a8af14b9e75 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 21 Jul 2023 16:30:25 -0700 Subject: [PATCH 29/32] bug fix for out-of-bound SLV when (DATA_WIDTH_G <= 32) --- axi/axi-lite/rtl/AxiDualPortRam.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/axi/axi-lite/rtl/AxiDualPortRam.vhd b/axi/axi-lite/rtl/AxiDualPortRam.vhd index 6e50266ca0..60047b36d8 100644 --- a/axi/axi-lite/rtl/AxiDualPortRam.vhd +++ b/axi/axi-lite/rtl/AxiDualPortRam.vhd @@ -361,11 +361,11 @@ begin if (AXI_WR_EN_G) then v.axiAddr := axiWriteMaster.awaddr(AXI_RAM_ADDR_HIGH_C downto AXI_RAM_ADDR_LOW_C); if (DATA_WIDTH_G <= 32) then - decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_RAM_ADDR_LOW_C-1 downto 0)); + v.axiWrStrobe := axiWriteMaster.wstrb; else decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_DEC_ADDR_RANGE_C)); + v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) := axiWriteMaster.wstrb; end if; - v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) := axiWriteMaster.wstrb; end if; axiSlaveWriteResponse(v.axiWriteSlave, ite(AXI_WR_EN_G, AXI_RESP_OK_C, AXI_RESP_SLVERR_C)); -- Check for read transaction From 22b7416590042c07694c50c929a51e0fec908b06 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 21 Jul 2023 16:30:54 -0700 Subject: [PATCH 30/32] adding test_AxiLiteCrossbarTb.py --- axi/axi-lite/tb/AxiLiteCrossbarTb.vhd | 189 ++++++++++++++++++ tests/test_AxiLiteCrossbarTb.py | 266 ++++++++++++++++++++++++++ 2 files changed, 455 insertions(+) create mode 100644 axi/axi-lite/tb/AxiLiteCrossbarTb.vhd create mode 100644 tests/test_AxiLiteCrossbarTb.py diff --git a/axi/axi-lite/tb/AxiLiteCrossbarTb.vhd b/axi/axi-lite/tb/AxiLiteCrossbarTb.vhd new file mode 100644 index 0000000000..f897644063 --- /dev/null +++ b/axi/axi-lite/tb/AxiLiteCrossbarTb.vhd @@ -0,0 +1,189 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: surf.AxiLiteCrossbar cocoTB testbed +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity AxiLiteCrossbarTb is + port ( + -- AXI-Lite Interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(31 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(31 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic); +end AxiLiteCrossbarTb; + +architecture mapping of AxiLiteCrossbarTb is + + constant NUM_AXIL_MASTERS_C : positive := 2; + + constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := genAxiLiteConfig(NUM_AXIL_MASTERS_C, x"0000_0000", 22, 20); + + constant NUM_CASCADE_MASTERS_C : positive := 2; + + constant CASCADE_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_CASCADE_MASTERS_C-1 downto 0) := ( + 0 => ( + baseAddr => x"0010_2000", + addrBits => 12, + connectivity => X"0001"), + 1 => ( + baseAddr => x"0016_0000", + addrBits => 17, + connectivity => X"0001")); + + signal axilClk : sl; + signal axilRst : sl; + + signal axilReadMaster : AxiLiteReadMasterType; + signal axilReadSlave : AxiLiteReadSlaveType; + signal axilWriteMaster : AxiLiteWriteMasterType; + signal axilWriteSlave : AxiLiteWriteSlaveType; + + signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); + signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + + signal cascadeReadMasters : AxiLiteReadMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0); + signal cascadeReadSlaves : AxiLiteReadSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + signal cascadeWriteMasters : AxiLiteWriteMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0); + signal cascadeWriteSlaves : AxiLiteWriteSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + +begin + + U_ShimLayer : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + EN_ERROR_RESP => true, + FREQ_HZ => 125000000, + ADDR_WIDTH => 32) + port map ( + -- IP Integrator AXI-Lite Interface + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + -- SURF AXI-Lite Interface + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + U_AXIL_XBAR : entity surf.AxiLiteCrossbar + generic map ( + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => NUM_AXIL_MASTERS_C, + MASTERS_CONFIG_G => AXIL_XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + U_MEM : entity surf.AxiDualPortRam + generic map ( + ADDR_WIDTH_G => 10, + DATA_WIDTH_G => 32) + port map ( + -- Axi Port + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => axilReadMasters(0), + axiReadSlave => axilReadSlaves(0), + axiWriteMaster => axilWriteMasters(0), + axiWriteSlave => axilWriteSlaves(0)); + + U_CASCADE_XBAR : entity surf.AxiLiteCrossbar + generic map ( + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => NUM_CASCADE_MASTERS_C, + MASTERS_CONFIG_G => CASCADE_XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMasters(1), + sAxiWriteSlaves(0) => axilWriteSlaves(1), + sAxiReadMasters(0) => axilReadMasters(1), + sAxiReadSlaves(0) => axilReadSlaves(1), + mAxiWriteMasters => cascadeWriteMasters, + mAxiWriteSlaves => cascadeWriteSlaves, + mAxiReadMasters => cascadeReadMasters, + mAxiReadSlaves => cascadeReadSlaves); + + GEN_VEC : + for i in NUM_CASCADE_MASTERS_C-1 downto 0 generate + + U_MEM : entity surf.AxiDualPortRam + generic map ( + ADDR_WIDTH_G => 10, + DATA_WIDTH_G => 32) + port map ( + -- Axi Port + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => cascadeReadMasters(i), + axiReadSlave => cascadeReadSlaves(i), + axiWriteMaster => cascadeWriteMasters(i), + axiWriteSlave => cascadeWriteSlaves(i)); + + end generate GEN_VEC; + +end mapping; diff --git a/tests/test_AxiLiteCrossbarTb.py b/tests/test_AxiLiteCrossbarTb.py new file mode 100644 index 0000000000..779508723d --- /dev/null +++ b/tests/test_AxiLiteCrossbarTb.py @@ -0,0 +1,266 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import itertools +import logging +import os +import random + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiLiteBus, AxiLiteMaster + +# test_AxiLiteCrossbarTb +from cocotb_test.simulator import run +import pytest +import glob +import os + +class TB: + def __init__(self, dut): + + # Pointer to DUT object + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Start clock (125 MHz) in a separate thread + cocotb.start_soon(Clock(dut.S_AXI_ACLK, 8.0, units='ns').start()) + + # Create the AXI-Lite Master + self.axil_master = AxiLiteMaster( + bus = AxiLiteBus.from_prefix(dut, 'S_AXI'), + clock = dut.S_AXI_ACLK, + reset = dut.S_AXI_ARESETN, + reset_active_level=False) + + def set_idle_generator(self, generator=None): + if generator: + self.axil_master.write_if.aw_channel.set_pause_generator(generator()) + self.axil_master.write_if.w_channel.set_pause_generator(generator()) + self.axil_master.read_if.ar_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.axil_master.write_if.b_channel.set_pause_generator(generator()) + self.axil_master.read_if.r_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.S_AXI_ARESETN.setimmediatevalue(0) + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + self.dut.S_AXI_ARESETN.value = 0 + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + self.dut.S_AXI_ARESETN.value = 1 + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + +async def run_test_bytes(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for memDev in [0x0000_0000,0x0010_2000,0x0016_0000]: + for offset in range(byte_lanes): + addr = offset+memDev + tb.log.info( f'length={length},addr={hex(addr)}' ) + test_data = bytearray([x % 256 for x in range(length)]) + await tb.axil_master.write(addr, test_data) + data = await tb.axil_master.read(addr, length) + + await RisingEdge(dut.S_AXI_ACLK) + await RisingEdge(dut.S_AXI_ACLK) + + +async def run_test_words(dut): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + for length in list(range(1, 4)): + for memDev in [0x0000_0000,0x0010_2000,0x0016_0000]: + for offset in list(range(byte_lanes)): + addr = offset + tb.log.info( f'length={length},addr={hex(addr)}' ) + + test_data = bytearray([x % 256 for x in range(length)]) + event = tb.axil_master.init_write(addr, test_data) + await event.wait() + event = tb.axil_master.init_read(addr, length) + await event.wait() + assert event.data.data == test_data + + test_data = bytearray([x % 256 for x in range(length)]) + await tb.axil_master.write(addr, test_data) + assert (await tb.axil_master.read(addr, length)).data == test_data + + test_data = [x * 0x1001 for x in range(length)] + await tb.axil_master.write_words(addr, test_data) + assert await tb.axil_master.read_words(addr, length) == test_data + + test_data = [x * 0x10200201 for x in range(length)] + await tb.axil_master.write_dwords(addr, test_data) + assert await tb.axil_master.read_dwords(addr, length) == test_data + + test_data = [x * 0x1020304004030201 for x in range(length)] + await tb.axil_master.write_qwords(addr, test_data) + assert await tb.axil_master.read_qwords(addr, length) == test_data + + test_data = 0x01*length + await tb.axil_master.write_byte(addr, test_data) + assert await tb.axil_master.read_byte(addr) == test_data + + test_data = 0x1001*length + await tb.axil_master.write_word(addr, test_data) + assert await tb.axil_master.read_word(addr) == test_data + + test_data = 0x10200201*length + await tb.axil_master.write_dword(addr, test_data) + assert await tb.axil_master.read_dword(addr) == test_data + + test_data = 0x1020304004030201*length + await tb.axil_master.write_qword(addr, test_data) + assert await tb.axil_master.read_qword(addr) == test_data + + await RisingEdge(dut.S_AXI_ACLK) + await RisingEdge(dut.S_AXI_ACLK) + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in [0x0000_0000,0x0010_2000,0x0016_0000]: + workers.append(cocotb.start_soon(worker(tb.axil_master, k, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.S_AXI_ACLK) + await RisingEdge(dut.S_AXI_ACLK) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if cocotb.SIM_NAME: + + ################# + # run_test_bytes + ################# + factory = TestFactory(run_test_bytes) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + ################# + # run_test_words + ################# + factory = TestFactory(run_test_words) + factory.generate_tests() + + ################# + # run_stress_test + ################# + factory = TestFactory(run_stress_test) + factory.generate_tests() + +tests_dir = os.path.dirname(__file__) +tests_module = 'AxiLiteCrossbarTb' + +############################################################################## + +@pytest.mark.parametrize( + "parameters", [ + None + ]) +def test_AxiLiteCrossbarTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}', + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # -frelaxed-rules option to allow IP integrator attributes + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], + + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], + ) From 89f050b7fe3bd328eff93f88caae1b190a36ad2e Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 21 Jul 2023 16:37:34 -0700 Subject: [PATCH 31/32] linter fix --- tests/test_AxiLiteCrossbarTb.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tests/test_AxiLiteCrossbarTb.py b/tests/test_AxiLiteCrossbarTb.py index 779508723d..03d9a5e950 100644 --- a/tests/test_AxiLiteCrossbarTb.py +++ b/tests/test_AxiLiteCrossbarTb.py @@ -8,12 +8,6 @@ ## the terms contained in the LICENSE.txt file. ############################################################################## -# dut_tb -import itertools -import logging -import os -import random - import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer @@ -26,6 +20,9 @@ import pytest import glob import os +import itertools +import logging +import random class TB: def __init__(self, dut): @@ -87,6 +84,7 @@ async def run_test_bytes(dut, data_in=None, idle_inserter=None, backpressure_ins test_data = bytearray([x % 256 for x in range(length)]) await tb.axil_master.write(addr, test_data) data = await tb.axil_master.read(addr, length) + assert data.data == test_data await RisingEdge(dut.S_AXI_ACLK) await RisingEdge(dut.S_AXI_ACLK) From b4a2ffbccc223a3bb3ea3fd043219a14fda84dd5 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 21 Jul 2023 16:58:10 -0700 Subject: [PATCH 32/32] Revert to previous refresh rate --- protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index 3602ecd79c..42602b5c9e 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -319,7 +319,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 1000.0, + REFRESH_RATE_G => 100.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32) @@ -434,7 +434,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 1000.0, + REFRESH_RATE_G => 100.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32)