2019-10-20_05-11-16_Library.scr

# Created by Ultra Librarian Gold 8.3.134 Copyright © 1999-2018
# Frank Frank, Accelerated Designs

Grid mil;
Set Wire_Bend 2;


Edit 'LPG3.pac';
Change Drill 30;
Pad '1' 42 R0 (-100 0);
Change Drill 30;
Pad '2' Long 0 42 R90 (-50 0);
Change Drill 30;
Pad '3' Long 0 42 R90 (0 0);
Layer 39;
Wire 6 (-141 44) (-141 -52);
Wire 6 (-141 -52) (41 -52);
Wire 6 (41 -52) (41 44);
Wire 6 (41 44) (-141 44);
Layer 39;
Change Spacing 50;
Change Pour solid;
Polygon 6  (-140.7086 43.5) (-140.7086 -52.4213) (40.7086 -52.4213) (40.7086 43.5) (-140.7086 43.5);
Layer 21;
Wire 6 (-136 -47) (36 -47);
Wire 6 (36 -47) (36 26);
Wire 6 (-136 26) (-136 -47);
Wire 20 (-146 0) -180 (-176 0);
Wire 20 (-176 0) -180 (-146 0);
Layer 51;
Wire 6 (-131 -42) (31 -42);
Wire 6 (31 -42) (31 21);
Wire 6 (31 21) (-131 21);
Wire 6 (-131 21) (-131 -42);
Wire 20 (-85 -75) -180 (-115 -75);
Wire 20 (-115 -75) -180 (-85 -75);
Layer 23;
Wire 6 (-110 0) (-90 0);
Wire 6 (-100 -10) (-100 10);
Layer 22;
Wire 20 (-146 0) -180 (-176 0);
Wire 20 (-176 0) -180 (-146 0);
Layer 25;
Change Size 50;
Change Ratio 6;
Text '>Name' SR0 (-179 -25);
Layer 27;

Edit 'DRV5053VAQLPGM.sym';
Layer 94;
Pin 'VCC' Pwr None Middle R0 Both 0 (100 0)
Pin 'GND' Pwr None Middle R180 Both 0 (1500 -100)
Pin 'OUT' Out None Middle R180 Both 0 (1500 0)
Wire 6 (300 200) (300 -300);
Wire 6 (300 -300) (1300 -300);
Wire 6 (1300 -300) (1300 200);
Wire 6 (1300 200) (300 200);
Layer 97;
Layer 95;
Change Size 82;
Change Ratio 6;
Text '>Name' SR0 (614 359);
Layer 96;
Change Size 82;
Change Ratio 6;
Text '>Value' SR0 (589 259);

Edit 'DRV5053VAQLPGM.dev';
Prefix 'U';
Description '';
Value Off;
Add DRV5053VAQLPGM 'A' Next  0 (0 0);
Package 'LPG3';
Technology '';
Attribute Vendor 'Texas Instruments';
Attribute Manufacturer_Part_Number 'DRV5053VAQLPGM';
Connect 'A.VCC' '1';
Connect 'A.GND' '2';
Connect 'A.OUT' '3';