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Merge branch 'master' into cleanup/safe-row-major-matrix-variant
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mcalancea committed Dec 10, 2024
2 parents e13ef15 + 33901fd commit f179d5d
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Showing 6 changed files with 56 additions and 42 deletions.
6 changes: 4 additions & 2 deletions .github/workflows/integration.yml
Original file line number Diff line number Diff line change
Expand Up @@ -56,10 +56,12 @@ jobs:
- name: Run example
env:
RAYON_NUM_THREADS: 2
run: cargo run --release --package ceno_zkvm --example riscv_opcodes --target ${{ matrix.target }} -- --start 10 --end 11
RUSTFLAGS: "-C opt-level=3"
run: cargo run --package ceno_zkvm --example riscv_opcodes --target ${{ matrix.target }} -- --start 10 --end 11

- name: Run fibonacci
env:
RAYON_NUM_THREADS: 8
RUST_LOG: debug
run: cargo run --release --package ceno_zkvm --bin e2e --target ${{ matrix.target }} -- --platform=sp1 ceno_zkvm/examples/fibonacci.elf
RUSTFLAGS: "-C opt-level=3"
run: cargo run --package ceno_zkvm --bin e2e --target ${{ matrix.target }} -- --platform=sp1 ceno_zkvm/examples/fibonacci.elf
3 changes: 3 additions & 0 deletions Cargo.toml
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Expand Up @@ -52,5 +52,8 @@ tracing = { version = "0.1", features = [
tracing-forest = { version = "0.1.6" }
tracing-subscriber = { version = "0.3", features = ["env-filter"] }

[profile.dev]
lto = "thin"

[profile.release]
lto = "thin"
1 change: 0 additions & 1 deletion ceno_zkvm/src/gadgets/is_zero.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

use ff_ext::ExtensionField;
use goldilocks::SmallField;

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1 change: 0 additions & 1 deletion ceno_zkvm/src/instructions/riscv/config.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

use crate::{expression::WitIn, set_val, utils::i64_to_base, witness::LkMultiplicity};
use goldilocks::SmallField;
use itertools::Itertools;
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79 changes: 42 additions & 37 deletions ceno_zkvm/src/instructions/riscv/slti.rs
Original file line number Diff line number Diff line change
Expand Up @@ -149,29 +149,31 @@ mod test {

#[test]
fn test_sltiu_true() {
verify::<SltiuOp>("lt = true, 0 < 1", 0, 1, 1);
verify::<SltiuOp>("lt = true, 1 < 2", 1, 2, 1);
verify::<SltiuOp>("lt = true, 10 < 20", 10, 20, 1);
verify::<SltiuOp>("lt = true, 0 < imm upper boundary", 0, 2047, 1);
let verify = |name, a, imm| verify::<SltiuOp>(name, a, imm, true);
verify("lt = true, 0 < 1", 0, 1);
verify("lt = true, 1 < 2", 1, 2);
verify("lt = true, 10 < 20", 10, 20);
verify("lt = true, 0 < imm upper boundary", 0, 2047);
// negative imm is treated as positive
verify::<SltiuOp>("lt = true, 0 < u32::MAX-1", 0, -1, 1);
verify::<SltiuOp>("lt = true, 1 < u32::MAX-1", 1, -1, 1);
verify::<SltiuOp>("lt = true, 0 < imm lower bondary", 0, -2048, 1);
verify("lt = true, 0 < u32::MAX-1", 0, -1);
verify("lt = true, 1 < u32::MAX-1", 1, -1);
verify("lt = true, 0 < imm lower bondary", 0, -2048);
}

#[test]
fn test_sltiu_false() {
verify::<SltiuOp>("lt = false, 1 < 0", 1, 0, 0);
verify::<SltiuOp>("lt = false, 2 < 1", 2, 1, 0);
verify::<SltiuOp>("lt = false, 100 < 50", 100, 50, 0);
verify::<SltiuOp>("lt = false, 500 < 100", 500, 100, 0);
verify::<SltiuOp>("lt = false, 100000 < 2047", 100000, 2047, 0);
verify::<SltiuOp>("lt = false, 100000 < 0", 100000, 0, 0);
verify::<SltiuOp>("lt = false, 0 == 0", 0, 0, 0);
verify::<SltiuOp>("lt = false, 1 == 1", 1, 1, 0);
verify::<SltiuOp>("lt = false, imm upper bondary", u32::MAX, 2047, 0);
let verify = |name, a, imm| verify::<SltiuOp>(name, a, imm, false);
verify("lt = false, 1 < 0", 1, 0);
verify("lt = false, 2 < 1", 2, 1);
verify("lt = false, 100 < 50", 100, 50);
verify("lt = false, 500 < 100", 500, 100);
verify("lt = false, 100000 < 2047", 100000, 2047);
verify("lt = false, 100000 < 0", 100000, 0);
verify("lt = false, 0 == 0", 0, 0);
verify("lt = false, 1 == 1", 1, 1);
verify("lt = false, imm upper bondary", u32::MAX, 2047);
// negative imm is treated as positive
verify::<SltiuOp>("lt = false, imm lower bondary", u32::MAX, -2048, 0);
verify("lt = false, imm lower bondary", u32::MAX, -2048);
}

#[test]
Expand All @@ -180,34 +182,36 @@ mod test {
let a: u32 = rng.gen::<u32>();
let b: i32 = rng.gen_range(-2048..2048);
println!("random: {} <? {}", a, b); // For debugging, do not delete.
verify::<SltiuOp>("random unsigned comparison", a, b, (a < (b as u32)) as u32);
verify::<SltiuOp>("random unsigned comparison", a, b, a < (b as u32));
}

#[test]
fn test_slti_true() {
verify::<SltiOp>("lt = true, 0 < 1", 0, 1, 1);
verify::<SltiOp>("lt = true, 1 < 2", 1, 2, 1);
verify::<SltiOp>("lt = true, -1 < 0", -1i32 as u32, 0, 1);
verify::<SltiOp>("lt = true, -1 < 1", -1i32 as u32, 1, 1);
verify::<SltiOp>("lt = true, -2 < -1", -2i32 as u32, -1, 1);
let verify = |name, a: i32, imm| verify::<SltiOp>(name, a as u32, imm, true);
verify("lt = true, 0 < 1", 0, 1);
verify("lt = true, 1 < 2", 1, 2);
verify("lt = true, -1 < 0", -1, 0);
verify("lt = true, -1 < 1", -1, 1);
verify("lt = true, -2 < -1", -2, -1);
// -2048 <= imm <= 2047
verify::<SltiOp>("lt = true, imm upper bondary", i32::MIN as u32, 2047, 1);
verify::<SltiOp>("lt = true, imm lower bondary", i32::MIN as u32, -2048, 1);
verify("lt = true, imm upper bondary", i32::MIN, 2047);
verify("lt = true, imm lower bondary", i32::MIN, -2048);
}

#[test]
fn test_slti_false() {
verify::<SltiOp>("lt = false, 1 < 0", 1, 0, 0);
verify::<SltiOp>("lt = false, 2 < 1", 2, 1, 0);
verify::<SltiOp>("lt = false, 0 < -1", 0, -1, 0);
verify::<SltiOp>("lt = false, 1 < -1", 1, -1, 0);
verify::<SltiOp>("lt = false, -1 < -2", -1i32 as u32, -2, 0);
verify::<SltiOp>("lt = false, 0 == 0", 0, 0, 0);
verify::<SltiOp>("lt = false, 1 == 1", 1, 1, 0);
verify::<SltiOp>("lt = false, -1 == -1", -1i32 as u32, -1, 0);
let verify = |name, a: i32, imm| verify::<SltiOp>(name, a as u32, imm, false);
verify("lt = false, 1 < 0", 1, 0);
verify("lt = false, 2 < 1", 2, 1);
verify("lt = false, 0 < -1", 0, -1);
verify("lt = false, 1 < -1", 1, -1);
verify("lt = false, -1 < -2", -1, -2);
verify("lt = false, 0 == 0", 0, 0);
verify("lt = false, 1 == 1", 1, 1);
verify("lt = false, -1 == -1", -1, -1);
// -2048 <= imm <= 2047
verify::<SltiOp>("lt = false, imm upper bondary", i32::MAX as u32, 2047, 0);
verify::<SltiOp>("lt = false, imm lower bondary", i32::MAX as u32, -2048, 0);
verify("lt = false, imm upper bondary", i32::MAX, 2047);
verify("lt = false, imm lower bondary", i32::MAX, -2048);
}

#[test]
Expand All @@ -216,10 +220,11 @@ mod test {
let a: i32 = rng.gen();
let b: i32 = rng.gen_range(-2048..2048);
println!("random: {} <? {}", a, b); // For debugging, do not delete.
verify::<SltiOp>("random 1", a as u32, b, (a < b) as u32);
verify::<SltiOp>("random 1", a as u32, b, a < b);
}

fn verify<I: RIVInstruction>(name: &'static str, rs1_read: u32, imm: i32, expected_rd: u32) {
fn verify<I: RIVInstruction>(name: &'static str, rs1_read: u32, imm: i32, expected_rd: bool) {
let expected_rd = expected_rd as u32;
let mut cs = ConstraintSystem::<GoldilocksExt2>::new(|| "riscv");
let mut cb = CircuitBuilder::new(&mut cs);

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8 changes: 7 additions & 1 deletion transcript/src/basic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,13 @@ impl<E: ExtensionField> Transcript<E> for BasicTranscript<E> {
}

fn read_challenge(&mut self) -> Challenge<E> {
let r = E::from_bases(self.permutation.squeeze());
// notice `from_bases` and `from_limbs` has the same behavior but
// `from_bases` has a sanity check for length of input slices
// while `from_limbs` use the first two fields silently
// we select `from_base` here to make it being more clear that
// we only use the first 2 fields here to construct the
// extension field (i.e. the challenge)
let r = E::from_bases(&self.permutation.squeeze()[..2]);

Challenge { elements: r }
}
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