Merge branch 'master' into matthias/remove-target-stuff

.github/workflows/lints.yml

@@ -56,7 +56,7 @@ jobs:
         run: |
           cargo make --version || cargo install cargo-make
       - name: Check code format
-        run: cargo make fmt-all-check
+        run: cargo fmt --all --check
 
       - name: Run clippy
         env:

Makefile.toml

@@ -3,10 +3,6 @@ CARGO_MAKE_EXTEND_WORKSPACE_MAKEFILE = true
 CORE = { script = ["nproc"] }
 RAYON_NUM_THREADS = "${CORE}"
 
-[tasks.build]
-# Override the default `--all-features`, that's broken, because some of our features are mutually exclusive.
-args = ["build"]
-
 [tasks.tests]
 args = [
   "test",
@@ -23,26 +19,11 @@ args = [
 command = "cargo"
 workspace = false
 
-[tasks.fmt-all-check]
-args = ["fmt", "--all", "--", "--check"]
-command = "cargo"
-workspace = false
-
-[tasks.fmt-all]
-args = ["fmt", "--all"]
-command = "cargo"
-workspace = false
-
 [tasks.clippy-all]
 args = ["clippy", "--all-features", "--all-targets", "--", "-D", "warnings"]
 command = "cargo"
 workspace = false
 
-[tasks.fmt]
-args = ["fmt", "-p", "ceno_zkvm", "--", "--check"]
-command = "cargo"
-workspace = false
-
 [tasks.riscv_stats]
 args = ["run", "--bin", "riscv_stats"]
 command = "cargo"

ceno_zkvm/Cargo.toml

@@ -52,12 +52,9 @@ pprof2.workspace = true
 glob = "0.3"
 
 [features]
-default = ["riv32", "forbid_overflow"]
+default = ["forbid_overflow"]
 flamegraph = ["pprof2/flamegraph", "pprof2/criterion"]
 forbid_overflow = []
-non_pow2_rayon_thread = []
-riv32 = []
-riv64 = []
 
 [[bench]]
 harness = false

ceno_zkvm/src/chip_handler.rs

@@ -3,7 +3,7 @@ use ff_ext::ExtensionField;
 use crate::{
     error::ZKVMError,
     expression::{Expression, ToExpr},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::riscv::constants::UINT_LIMBS,
 };
 
@@ -34,7 +34,7 @@ pub trait RegisterChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce(
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 
     #[allow(clippy::too_many_arguments)]
     fn register_write(
@@ -45,7 +45,7 @@ pub trait RegisterChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce(
         ts: Expression<E>,
         prev_values: RegisterExpr<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 }
 
 /// The common representation of a memory address.
@@ -62,7 +62,7 @@ pub trait MemoryChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce()
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 
     #[allow(clippy::too_many_arguments)]
     fn memory_write(
@@ -73,5 +73,5 @@ pub trait MemoryChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce()
         ts: Expression<E>,
         prev_values: MemoryExpr<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 }

ceno_zkvm/src/chip_handler/memory.rs

@@ -3,7 +3,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::Expression,
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::riscv::constants::UINT_LIMBS,
     structs::RAMType,
 };
@@ -19,7 +19,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
             let read_record = [
@@ -39,7 +39,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
             cb.write_record(|| "write_record", RAMType::Memory, write_record)?;
 
             // assert prev_ts < current_ts
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,
@@ -61,7 +61,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
         ts: Expression<E>,
         prev_values: MemoryExpr<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
             let read_record = [
@@ -80,7 +80,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
             cb.read_record(|| "read_record", RAMType::Memory, read_record)?;
             cb.write_record(|| "write_record", RAMType::Memory, write_record)?;
 
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,

ceno_zkvm/src/chip_handler/register.rs

@@ -4,7 +4,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{Expression, ToExpr},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::riscv::constants::UINT_LIMBS,
     structs::RAMType,
 };
@@ -21,7 +21,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
             let read_record = [
@@ -43,7 +43,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
             cb.write_record(|| "write_record", RAMType::Register, write_record)?;
 
             // assert prev_ts < current_ts
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,
@@ -65,7 +65,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
         ts: Expression<E>,
         prev_values: RegisterExpr<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         assert!(register_id.expr().degree() <= 1);
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
@@ -87,7 +87,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
             cb.read_record(|| "read_record", RAMType::Register, read_record)?;
             cb.write_record(|| "write_record", RAMType::Register, write_record)?;
 
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,

ceno_zkvm/src/gadgets/div.rs

@@ -10,13 +10,13 @@ use crate::{
     witness::LkMultiplicity,
 };
 
-use super::AssertLTConfig;
+use super::AssertLtConfig;
 
 /// divide gadget
 #[derive(Debug, Clone)]
 pub struct DivConfig<E: ExtensionField> {
     pub dividend: UInt<E>,
-    pub r_lt: AssertLTConfig,
+    pub r_lt: AssertLtConfig,
     pub intermediate_mul: UInt<E>,
 }
 
@@ -35,7 +35,7 @@ impl<E: ExtensionField> DivConfig<E> {
             let (dividend, intermediate_mul) =
                 divisor.mul_add(|| "divisor * outcome + r", cb, quotient, remainder, true)?;
 
-            let r_lt = AssertLTConfig::construct_circuit(
+            let r_lt = AssertLtConfig::construct_circuit(
                 cb,
                 || "remainder < divisor",
                 remainder.value(),

ceno_zkvm/src/gadgets/is_lt.rs

@@ -19,9 +19,9 @@ use crate::{
 use super::SignedExtendConfig;
 
 #[derive(Debug, Clone)]
-pub struct AssertLTConfig(InnerLtConfig);
+pub struct AssertLtConfig(InnerLtConfig);
 
-impl AssertLTConfig {
+impl AssertLtConfig {
     pub fn construct_circuit<
         E: ExtensionField,
         NR: Into<String> + Display + Clone,

ceno_zkvm/src/gadgets/mod.rs

@@ -5,7 +5,7 @@ mod signed_ext;
 
 pub use div::DivConfig;
 pub use is_lt::{
-    AssertLTConfig, AssertSignedLtConfig, InnerLtConfig, IsLtConfig, SignedLtConfig, cal_lt_diff,
+    AssertLtConfig, AssertSignedLtConfig, InnerLtConfig, IsLtConfig, SignedLtConfig, cal_lt_diff,
 };
 pub use is_zero::{IsEqualConfig, IsZeroConfig};
 pub use signed_ext::SignedExtendConfig;

ceno_zkvm/src/instructions/riscv.rs

@@ -11,7 +11,7 @@ pub mod arith_imm;
 pub mod branch;
 pub mod config;
 pub mod constants;
-pub mod divu;
+pub mod div;
 pub mod dummy;
 pub mod ecall;
 pub mod jump;

ceno_zkvm/src/instructions/riscv/constants.rs

@@ -14,10 +14,8 @@ pub const PUBLIC_IO_IDX: usize = 6;
 pub const LIMB_BITS: usize = 16;
 pub const LIMB_MASK: u32 = 0xFFFF;
 
-#[cfg(feature = "riv32")]
 pub const BIT_WIDTH: usize = 32usize;
-#[cfg(feature = "riv64")]
-pub const BIT_WIDTH: usize = 64usize;
+
 pub type UInt<E> = UIntLimbs<BIT_WIDTH, LIMB_BITS, E>;
 pub type UIntMul<E> = UIntLimbs<{ 2 * BIT_WIDTH }, LIMB_BITS, E>;
 /// use UInt<x> for x bits limb size

ceno_zkvm/src/instructions/riscv/divu.rs → ceno_zkvm/src/instructions/riscv/div.rs

@@ -181,7 +181,7 @@ mod test {
             circuit_builder::{CircuitBuilder, ConstraintSystem},
             instructions::{
                 Instruction,
-                riscv::{constants::UInt, divu::DivUInstruction},
+                riscv::{constants::UInt, div::DivUInstruction},
             },
             scheme::mock_prover::{MOCK_PC_START, MockProver},
         };

ceno_zkvm/src/instructions/riscv/ecall/halt.rs

@@ -3,7 +3,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{ToExpr, WitIn},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::{
         Instruction,
         riscv::{
@@ -21,7 +21,7 @@ use std::{marker::PhantomData, mem::MaybeUninit};
 pub struct HaltConfig {
     ecall_cfg: EcallInstructionConfig,
     prev_x10_ts: WitIn,
-    lt_x10_cfg: AssertLTConfig,
+    lt_x10_cfg: AssertLtConfig,
 }
 
 pub struct HaltInstruction<E>(PhantomData<E>);

ceno_zkvm/src/instructions/riscv/ecall_insn.rs

@@ -5,7 +5,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{Expression, ToExpr, WitIn},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     set_val,
     tables::InsnRecord,
     witness::LkMultiplicity,
@@ -18,7 +18,7 @@ pub struct EcallInstructionConfig {
     pub pc: WitIn,
     pub ts: WitIn,
     prev_x5_ts: WitIn,
-    lt_x5_cfg: AssertLTConfig,
+    lt_x5_cfg: AssertLtConfig,
 }
 
 impl EcallInstructionConfig {

ceno_zkvm/src/instructions/riscv/insn_base.rs

@@ -12,7 +12,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{Expression, ToExpr, WitIn},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     set_val,
     uint::Value,
     witness::LkMultiplicity,
@@ -77,7 +77,7 @@ impl<E: ExtensionField> StateInOut<E> {
 pub struct ReadRS1<E: ExtensionField> {
     pub id: WitIn,
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
     _field_type: PhantomData<E>,
 }
 
@@ -131,7 +131,7 @@ impl<E: ExtensionField> ReadRS1<E> {
 pub struct ReadRS2<E: ExtensionField> {
     pub id: WitIn,
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
     _field_type: PhantomData<E>,
 }
 
@@ -186,7 +186,7 @@ pub struct WriteRD<E: ExtensionField> {
     pub id: WitIn,
     pub prev_ts: WitIn,
     pub prev_value: UInt<E>,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
 }
 
 impl<E: ExtensionField> WriteRD<E> {
@@ -246,7 +246,7 @@ impl<E: ExtensionField> WriteRD<E> {
 #[derive(Debug)]
 pub struct ReadMEM<E: ExtensionField> {
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
     _field_type: PhantomData<E>,
 }
 
@@ -301,7 +301,7 @@ impl<E: ExtensionField> ReadMEM<E> {
 #[derive(Debug)]
 pub struct WriteMEM {
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
 }
 
 impl WriteMEM {

ceno_zkvm/src/instructions/riscv/mul.rs

@@ -432,9 +432,7 @@ impl<E: ExtensionField> Signed<E> {
             lkm,
             *val.as_u16_limbs().last().unwrap() as u64,
         )?;
-        let signed_val = val.as_u32() as i32;
-
-        Ok(signed_val)
+        Ok(i32::from(val))
     }
 
     pub fn expr(&self) -> Expression<E> {

ceno_zkvm/src/instructions/riscv/rv32im.rs

@@ -7,7 +7,7 @@ use crate::{
             branch::{
                 BeqInstruction, BgeInstruction, BgeuInstruction, BltInstruction, BneInstruction,
             },
-            divu::DivUInstruction,
+            div::DivUInstruction,
             logic::{AndInstruction, OrInstruction, XorInstruction},
             logic_imm::{AndiInstruction, OriInstruction, XoriInstruction},
             mul::MulhuInstruction,
@@ -27,7 +27,7 @@ use ceno_emul::{
     InsnKind::{self, *},
     Platform, StepRecord,
 };
-use divu::{DivDummy, RemDummy, RemuDummy};
+use div::{DivDummy, RemDummy, RemuDummy};
 use ecall::EcallDummy;
 use ff_ext::ExtensionField;
 use itertools::Itertools;