Merge remote-tracking branch 'origin/master' into basefold-improve-open

.github/workflows/lints.yml

@@ -33,6 +33,13 @@ jobs:
     timeout-minutes: 30
     runs-on: ubuntu-latest
 
+    strategy:
+      matrix:
+        target: [x86_64-unknown-linux-gnu, riscv32im-unknown-none-elf]
+        # Exclude the riscv32im-unknown-none-elf target
+        exclude:
+          - target: riscv32im-unknown-none-elf
+
     steps:
       - uses: actions/checkout@v2
       - uses: actions-rs/toolchain@v1
@@ -52,7 +59,7 @@ jobs:
 
       - name: Install cargo make
         run: |
-          cargo install --force cargo-make
+          cargo install cargo-make || echo "cargo-make already installed"
       - name: Check code format
         uses: actions-rs/cargo@v1
         with:
@@ -61,6 +68,8 @@ jobs:
 
       - name: Run clippy
         uses: actions-rs/cargo@v1
+        env:
+          TARGET: ${{ matrix.target }}
         with:
           command: make
           args: clippy-check-selected-packages

.github/workflows/tests.yml

@@ -31,6 +31,14 @@ jobs:
     name: Run Tests
     timeout-minutes: 30
     runs-on: ubuntu-latest
+
+    strategy:
+      matrix:
+        target: [x86_64-unknown-linux-gnu, riscv32im-unknown-none-elf]
+        # Exclude the riscv32im-unknown-none-elf target
+        exclude:
+          - target: riscv32im-unknown-none-elf
+
     steps:
       - uses: actions/checkout@v2
       - name: Cargo cache
@@ -46,9 +54,11 @@ jobs:
 
       - name: Install cargo make
         run: |
-          cargo install --force cargo-make
+          cargo install cargo-make || echo "cargo-make already installed"
       - name: run test
         uses: actions-rs/cargo@v1
+        env:
+          TARGET: ${{ matrix.target }}
         with:
           command: make
           args: tests

Cargo.toml

@@ -1,6 +1,7 @@
 [workspace]
 members = [
     "ceno_emul",
+    "ceno_rt",
     "gkr",
     "gkr-graph",
     "mpcs",

Makefile.toml

@@ -5,7 +5,7 @@ RAYON_NUM_THREADS = "${CORE}"
 
 [tasks.tests]
 command = "cargo"
-args = ["test", "--lib", "--release", "--workspace", "--exclude", "singer-pro"]
+args = ["test", "--lib", "--release", "--target", "${TARGET}", "--workspace", "--exclude", "singer-pro", "--exclude", "ceno_rt"]
 
 [tasks.fmt-check]
 command = "cargo"
@@ -25,4 +25,4 @@ args = ["fmt", "-p", "ceno_zkvm", "--", "--check"]
 
 [tasks.clippy-check-selected-packages]
 command = "cargo"
-args = ["clippy", "-p", "ceno_zkvm", "--", "-D", "warnings"]
+args = ["clippy", "-p", "ceno_zkvm", "--target", "${TARGET}", "--", "-D", "warnings"]

ceno_emul/Cargo.toml

@@ -9,3 +9,4 @@ anyhow = { version = "1.0", default-features = false }
 tracing = { version = "0.1", default-features = false, features = [
     "attributes",
 ] }
+elf = { version = "0.7.4" }

ceno_emul/src/elf.rs

@@ -0,0 +1,112 @@
+// Based on: https://github.com/risc0/risc0/blob/6b6daeafa1545984aa28581fca56d9ef13dcbae6/risc0/binfmt/src/elf.rs
+//
+// Copyright 2024 RISC Zero, Inc.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+extern crate alloc;
+
+use alloc::collections::BTreeMap;
+
+use crate::addr::WORD_SIZE;
+use anyhow::{anyhow, bail, Context, Result};
+use elf::{endian::LittleEndian, file::Class, ElfBytes};
+
+/// A RISC Zero program
+pub struct Program {
+    /// The entrypoint of the program
+    pub entry: u32,
+
+    /// The initial memory image
+    pub image: BTreeMap<u32, u32>,
+}
+
+impl Program {
+    /// Initialize a RISC Zero Program from an appropriate ELF file
+    pub fn load_elf(input: &[u8], max_mem: u32) -> Result<Program> {
+        let mut image: BTreeMap<u32, u32> = BTreeMap::new();
+        let elf = ElfBytes::<LittleEndian>::minimal_parse(input)
+            .map_err(|err| anyhow!("Elf parse error: {err}"))?;
+        if elf.ehdr.class != Class::ELF32 {
+            bail!("Not a 32-bit ELF");
+        }
+        if elf.ehdr.e_machine != elf::abi::EM_RISCV {
+            bail!("Invalid machine type, must be RISC-V");
+        }
+        if elf.ehdr.e_type != elf::abi::ET_EXEC {
+            bail!("Invalid ELF type, must be executable");
+        }
+        let entry: u32 = elf
+            .ehdr
+            .e_entry
+            .try_into()
+            .map_err(|err| anyhow!("e_entry was larger than 32 bits. {err}"))?;
+        if entry >= max_mem || entry % WORD_SIZE as u32 != 0 {
+            bail!("Invalid entrypoint");
+        }
+        let segments = elf.segments().ok_or(anyhow!("Missing segment table"))?;
+        if segments.len() > 256 {
+            bail!("Too many program headers");
+        }
+        for segment in segments.iter().filter(|x| x.p_type == elf::abi::PT_LOAD) {
+            let file_size: u32 = segment
+                .p_filesz
+                .try_into()
+                .map_err(|err| anyhow!("filesize was larger than 32 bits. {err}"))?;
+            if file_size >= max_mem {
+                bail!("Invalid segment file_size");
+            }
+            let mem_size: u32 = segment
+                .p_memsz
+                .try_into()
+                .map_err(|err| anyhow!("mem_size was larger than 32 bits {err}"))?;
+            if mem_size >= max_mem {
+                bail!("Invalid segment mem_size");
+            }
+            let vaddr: u32 = segment
+                .p_vaddr
+                .try_into()
+                .map_err(|err| anyhow!("vaddr is larger than 32 bits. {err}"))?;
+            if vaddr % WORD_SIZE as u32 != 0 {
+                bail!("vaddr {vaddr:08x} is unaligned");
+            }
+            let offset: u32 = segment
+                .p_offset
+                .try_into()
+                .map_err(|err| anyhow!("offset is larger than 32 bits. {err}"))?;
+            for i in (0..mem_size).step_by(WORD_SIZE) {
+                let addr = vaddr.checked_add(i).context("Invalid segment vaddr")?;
+                if addr >= max_mem {
+                    bail!(
+                        "Address [0x{addr:08x}] exceeds maximum address for guest programs [0x{max_mem:08x}]"
+                    );
+                }
+                if i >= file_size {
+                    // Past the file size, all zeros.
+                    image.insert(addr, 0);
+                } else {
+                    let mut word = 0;
+                    // Don't read past the end of the file.
+                    let len = core::cmp::min(file_size - i, WORD_SIZE as u32);
+                    for j in 0..len {
+                        let offset = (offset + i + j) as usize;
+                        let byte = input.get(offset).context("Invalid segment offset")?;
+                        word |= (*byte as u32) << (j * 8);
+                    }
+                    image.insert(addr, word);
+                }
+            }
+        }
+        Ok(Program { entry, image })
+    }
+}

ceno_emul/src/lib.rs

@@ -12,3 +12,6 @@ pub use vm_state::VMState;
 
 mod rv32im;
 pub use rv32im::{DecodedInstruction, EmuContext, InsnCategory, InsnKind};
+
+mod elf;
+pub use elf::Program;

ceno_emul/src/rv32im.rs

@@ -97,7 +97,7 @@ pub enum TrapCause {
     LoadAccessFault(ByteAddr),
     StoreAddressMisaligned(ByteAddr),
     StoreAccessFault,
-    EnvironmentCallFromUserMode,
+    EcallError,
 }
 
 #[derive(Clone, Debug, Default)]

ceno_emul/src/tracer.rs

@@ -19,16 +19,16 @@ use crate::{
 /// - Any pair of `rs1 / rs2 / rd` **may be the same**. Then, one op will point to the other op in the same instruction but a different subcycle. The circuits may follow the operations **without special handling** of repeated registers.
 #[derive(Clone, Debug, Default)]
 pub struct StepRecord {
-    cycle: Cycle,
-    pc: Change<ByteAddr>,
-    insn_code: Word,
+    pub cycle: Cycle,
+    pub pc: Change<ByteAddr>,
+    pub insn_code: Word,
 
-    rs1: Option<ReadOp>,
-    rs2: Option<ReadOp>,
+    pub rs1: Option<ReadOp>,
+    pub rs2: Option<ReadOp>,
 
-    rd: Option<WriteOp>,
+    pub rd: Option<WriteOp>,
 
-    memory_op: Option<WriteOp>,
+    pub memory_op: Option<WriteOp>,
 }
 
 #[derive(Clone, Debug, PartialEq, Eq, Hash)]
@@ -77,6 +77,10 @@ impl StepRecord {
     pub fn memory_op(&self) -> Option<WriteOp> {
         self.memory_op.clone()
     }
+
+    pub fn is_busy_loop(&self) -> bool {
+        self.pc.before == self.pc.after
+    }
 }
 
 #[derive(Debug)]