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Fix a couple of missed changes in rv32im.rs needed for new opcodes
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Bryan Gillespie committed Dec 10, 2024
1 parent 36c2af4 commit 3e7931b
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions ceno_zkvm/src/instructions/riscv/rv32im.rs
Original file line number Diff line number Diff line change
Expand Up @@ -384,9 +384,9 @@ impl<E: ExtensionField> Rv32imConfig<E> {
assign_opcode!(MULHSU, MulhsuInstruction<E>, mulhsu_config);
assign_opcode!(MULHU, MulhuInstruction<E>, mulhu_config);
assign_opcode!(DIVU, DivuInstruction<E>, divu_config);
assign_opcode!(REMU, RemuInstruction<E>, divu_config);
assign_opcode!(DIV, DivInstruction<E>, divu_config);
assign_opcode!(REM, RemInstruction<E>, divu_config);
assign_opcode!(REMU, RemuInstruction<E>, remu_config);
assign_opcode!(DIV, DivInstruction<E>, div_config);
assign_opcode!(REM, RemInstruction<E>, rem_config);
// alu with imm
assign_opcode!(ADDI, AddiInstruction<E>, addi_config);
assign_opcode!(ANDI, AndiInstruction<E>, andi_config);
Expand Down Expand Up @@ -425,7 +425,7 @@ impl<E: ExtensionField> Rv32imConfig<E> {
assert_eq!(
all_records.keys().cloned().collect::<BTreeSet<_>>(),
// these are opcodes that haven't been implemented
[INVALID, DIV, REM, REMU, EANY]
[INVALID, EANY]
.into_iter()
.map(|insn_kind| insn_kind as usize)
.collect::<BTreeSet<_>>(),
Expand Down

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