Merge branch 'master' into matthias/simplify-allocator

.github/workflows/lints.yml

@@ -63,7 +63,7 @@ jobs:
         run: |
           cargo make --version || cargo install cargo-make
       - name: Check code format
-        run: cargo make fmt-all-check
+        run: cargo fmt --all --check
 
       - name: Run clippy
         env:

Makefile.toml

@@ -33,26 +33,11 @@ args = [
 command = "cargo"
 workspace = false
 
-[tasks.fmt-all-check]
-args = ["fmt", "--all", "--", "--check"]
-command = "cargo"
-workspace = false
-
-[tasks.fmt-all]
-args = ["fmt", "--all"]
-command = "cargo"
-workspace = false
-
 [tasks.clippy-all]
 args = ["clippy", "--all-features", "--all-targets", "--", "-D", "warnings"]
 command = "cargo"
 workspace = false
 
-[tasks.fmt]
-args = ["fmt", "-p", "ceno_zkvm", "--", "--check"]
-command = "cargo"
-workspace = false
-
 [tasks.riscv_stats]
 args = ["run", "--bin", "riscv_stats"]
 command = "cargo"

ceno_zkvm/src/instructions/riscv.rs

@@ -11,7 +11,7 @@ pub mod arith_imm;
 pub mod branch;
 pub mod config;
 pub mod constants;
-pub mod divu;
+pub mod div;
 pub mod dummy;
 pub mod ecall;
 pub mod jump;

ceno_zkvm/src/instructions/riscv/divu.rs → ceno_zkvm/src/instructions/riscv/div.rs

@@ -181,7 +181,7 @@ mod test {
             circuit_builder::{CircuitBuilder, ConstraintSystem},
             instructions::{
                 Instruction,
-                riscv::{constants::UInt, divu::DivUInstruction},
+                riscv::{constants::UInt, div::DivUInstruction},
             },
             scheme::mock_prover::{MOCK_PC_START, MockProver},
         };

ceno_zkvm/src/instructions/riscv/mul.rs

@@ -432,9 +432,7 @@ impl<E: ExtensionField> Signed<E> {
             lkm,
             *val.as_u16_limbs().last().unwrap() as u64,
         )?;
-        let signed_val = val.as_u32() as i32;
-
-        Ok(signed_val)
+        Ok(i32::from(val))
     }
 
     pub fn expr(&self) -> Expression<E> {

ceno_zkvm/src/instructions/riscv/rv32im.rs

@@ -7,7 +7,7 @@ use crate::{
             branch::{
                 BeqInstruction, BgeInstruction, BgeuInstruction, BltInstruction, BneInstruction,
             },
-            divu::DivUInstruction,
+            div::DivUInstruction,
             logic::{AndInstruction, OrInstruction, XorInstruction},
             logic_imm::{AndiInstruction, OriInstruction, XoriInstruction},
             mul::MulhuInstruction,
@@ -27,7 +27,7 @@ use ceno_emul::{
     InsnKind::{self, *},
     Platform, StepRecord,
 };
-use divu::{DivDummy, RemDummy, RemuDummy};
+use div::{DivDummy, RemDummy, RemuDummy};
 use ecall::EcallDummy;
 use ff_ext::ExtensionField;
 use itertools::Itertools;

ceno_zkvm/src/uint.rs

@@ -606,6 +606,30 @@ pub struct Value<'a, T: Into<u64> + From<u32> + Copy + Default> {
     pub limbs: Cow<'a, [u16]>,
 }
 
+impl<'a, T: Into<u64> + From<u32> + Copy + Default> From<&'a Value<'a, T>> for &'a [u16] {
+    fn from(v: &'a Value<'a, T>) -> Self {
+        v.as_u16_limbs()
+    }
+}
+
+impl<'a, T: Into<u64> + From<u32> + Copy + Default> From<&Value<'a, T>> for u64 {
+    fn from(v: &Value<'a, T>) -> Self {
+        v.as_u64()
+    }
+}
+
+impl<'a, T: Into<u64> + From<u32> + Copy + Default> From<&Value<'a, T>> for u32 {
+    fn from(v: &Value<'a, T>) -> Self {
+        v.as_u32()
+    }
+}
+
+impl<'a, T: Into<u64> + From<u32> + Copy + Default> From<&Value<'a, T>> for i32 {
+    fn from(v: &Value<'a, T>) -> Self {
+        v.as_i32()
+    }
+}
+
 // TODO generalize to support non 16 bit limbs
 // TODO optimize api with fixed size array
 impl<'a, T: Into<u64> + From<u32> + Copy + Default> Value<'a, T> {
@@ -616,10 +640,7 @@ impl<'a, T: Into<u64> + From<u32> + Copy + Default> Value<'a, T> {
     const LIMBS: usize = (Self::M + 15) / 16;
 
     pub fn new(val: T, lkm: &mut LkMultiplicity) -> Self {
-        let uint = Value::<T> {
-            val,
-            limbs: Cow::Owned(Self::split_to_u16(val)),
-        };
+        let uint = Self::new_unchecked(val);
         Self::assert_u16(&uint.limbs, lkm);
         uint
     }
@@ -684,6 +705,11 @@ impl<'a, T: Into<u64> + From<u32> + Copy + Default> Value<'a, T> {
         self.as_u64() as u32
     }
 
+    /// Convert the limbs to an i32 value
+    pub fn as_i32(&self) -> i32 {
+        self.as_u32() as i32
+    }
+
     pub fn u16_fields<F: SmallField>(&self) -> Vec<F> {
         self.limbs.iter().map(|v| F::from(*v as u64)).collect_vec()
     }