Rename AssertLTConfig to AssertLtConfig (#731)

Implementing a TODO from #596

ceno_zkvm/src/chip_handler.rs

@@ -3,7 +3,7 @@ use ff_ext::ExtensionField;
 use crate::{
     error::ZKVMError,
     expression::{Expression, ToExpr},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::riscv::constants::UINT_LIMBS,
 };
 
@@ -34,7 +34,7 @@ pub trait RegisterChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce(
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 
     #[allow(clippy::too_many_arguments)]
     fn register_write(
@@ -45,7 +45,7 @@ pub trait RegisterChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce(
         ts: Expression<E>,
         prev_values: RegisterExpr<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 }
 
 /// The common representation of a memory address.
@@ -62,7 +62,7 @@ pub trait MemoryChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce()
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 
     #[allow(clippy::too_many_arguments)]
     fn memory_write(
@@ -73,5 +73,5 @@ pub trait MemoryChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce()
         ts: Expression<E>,
         prev_values: MemoryExpr<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
 }

ceno_zkvm/src/chip_handler/memory.rs

@@ -3,7 +3,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::Expression,
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::riscv::constants::UINT_LIMBS,
     structs::RAMType,
 };
@@ -19,7 +19,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
             let read_record = [
@@ -39,7 +39,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
             cb.write_record(|| "write_record", RAMType::Memory, write_record)?;
 
             // assert prev_ts < current_ts
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,
@@ -61,7 +61,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
         ts: Expression<E>,
         prev_values: MemoryExpr<E>,
         value: MemoryExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
             let read_record = [
@@ -80,7 +80,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
             cb.read_record(|| "read_record", RAMType::Memory, read_record)?;
             cb.write_record(|| "write_record", RAMType::Memory, write_record)?;
 
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,

ceno_zkvm/src/chip_handler/register.rs

@@ -4,7 +4,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{Expression, ToExpr},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::riscv::constants::UINT_LIMBS,
     structs::RAMType,
 };
@@ -21,7 +21,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
         prev_ts: Expression<E>,
         ts: Expression<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
             let read_record = [
@@ -43,7 +43,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
             cb.write_record(|| "write_record", RAMType::Register, write_record)?;
 
             // assert prev_ts < current_ts
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,
@@ -65,7 +65,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
         ts: Expression<E>,
         prev_values: RegisterExpr<E>,
         value: RegisterExpr<E>,
-    ) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
+    ) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
         assert!(register_id.expr().degree() <= 1);
         self.namespace(name_fn, |cb| {
             // READ (a, v, t)
@@ -87,7 +87,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
             cb.read_record(|| "read_record", RAMType::Register, read_record)?;
             cb.write_record(|| "write_record", RAMType::Register, write_record)?;
 
-            let lt_cfg = AssertLTConfig::construct_circuit(
+            let lt_cfg = AssertLtConfig::construct_circuit(
                 cb,
                 || "prev_ts < ts",
                 prev_ts,

ceno_zkvm/src/gadgets/div.rs

@@ -10,13 +10,13 @@ use crate::{
     witness::LkMultiplicity,
 };
 
-use super::AssertLTConfig;
+use super::AssertLtConfig;
 
 /// divide gadget
 #[derive(Debug, Clone)]
 pub struct DivConfig<E: ExtensionField> {
     pub dividend: UInt<E>,
-    pub r_lt: AssertLTConfig,
+    pub r_lt: AssertLtConfig,
     pub intermediate_mul: UInt<E>,
 }
 
@@ -35,7 +35,7 @@ impl<E: ExtensionField> DivConfig<E> {
             let (dividend, intermediate_mul) =
                 divisor.mul_add(|| "divisor * outcome + r", cb, quotient, remainder, true)?;
 
-            let r_lt = AssertLTConfig::construct_circuit(
+            let r_lt = AssertLtConfig::construct_circuit(
                 cb,
                 || "remainder < divisor",
                 remainder.value(),

ceno_zkvm/src/gadgets/is_lt.rs

@@ -19,9 +19,9 @@ use crate::{
 use super::SignedExtendConfig;
 
 #[derive(Debug, Clone)]
-pub struct AssertLTConfig(InnerLtConfig);
+pub struct AssertLtConfig(InnerLtConfig);
 
-impl AssertLTConfig {
+impl AssertLtConfig {
     pub fn construct_circuit<
         E: ExtensionField,
         NR: Into<String> + Display + Clone,

ceno_zkvm/src/gadgets/mod.rs

@@ -5,7 +5,7 @@ mod signed_ext;
 
 pub use div::DivConfig;
 pub use is_lt::{
-    AssertLTConfig, AssertSignedLtConfig, InnerLtConfig, IsLtConfig, SignedLtConfig, cal_lt_diff,
+    AssertLtConfig, AssertSignedLtConfig, InnerLtConfig, IsLtConfig, SignedLtConfig, cal_lt_diff,
 };
 pub use is_zero::{IsEqualConfig, IsZeroConfig};
 pub use signed_ext::SignedExtendConfig;

ceno_zkvm/src/instructions/riscv/ecall/halt.rs

@@ -3,7 +3,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{ToExpr, WitIn},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     instructions::{
         Instruction,
         riscv::{
@@ -21,7 +21,7 @@ use std::{marker::PhantomData, mem::MaybeUninit};
 pub struct HaltConfig {
     ecall_cfg: EcallInstructionConfig,
     prev_x10_ts: WitIn,
-    lt_x10_cfg: AssertLTConfig,
+    lt_x10_cfg: AssertLtConfig,
 }
 
 pub struct HaltInstruction<E>(PhantomData<E>);

ceno_zkvm/src/instructions/riscv/ecall_insn.rs

@@ -5,7 +5,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{Expression, ToExpr, WitIn},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     set_val,
     tables::InsnRecord,
     witness::LkMultiplicity,
@@ -18,7 +18,7 @@ pub struct EcallInstructionConfig {
     pub pc: WitIn,
     pub ts: WitIn,
     prev_x5_ts: WitIn,
-    lt_x5_cfg: AssertLTConfig,
+    lt_x5_cfg: AssertLtConfig,
 }
 
 impl EcallInstructionConfig {

ceno_zkvm/src/instructions/riscv/insn_base.rs

@@ -12,7 +12,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{Expression, ToExpr, WitIn},
-    gadgets::AssertLTConfig,
+    gadgets::AssertLtConfig,
     set_val,
     uint::Value,
     witness::LkMultiplicity,
@@ -77,7 +77,7 @@ impl<E: ExtensionField> StateInOut<E> {
 pub struct ReadRS1<E: ExtensionField> {
     pub id: WitIn,
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
     _field_type: PhantomData<E>,
 }
 
@@ -131,7 +131,7 @@ impl<E: ExtensionField> ReadRS1<E> {
 pub struct ReadRS2<E: ExtensionField> {
     pub id: WitIn,
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
     _field_type: PhantomData<E>,
 }
 
@@ -186,7 +186,7 @@ pub struct WriteRD<E: ExtensionField> {
     pub id: WitIn,
     pub prev_ts: WitIn,
     pub prev_value: UInt<E>,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
 }
 
 impl<E: ExtensionField> WriteRD<E> {
@@ -246,7 +246,7 @@ impl<E: ExtensionField> WriteRD<E> {
 #[derive(Debug)]
 pub struct ReadMEM<E: ExtensionField> {
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
     _field_type: PhantomData<E>,
 }
 
@@ -301,7 +301,7 @@ impl<E: ExtensionField> ReadMEM<E> {
 #[derive(Debug)]
 pub struct WriteMEM {
     pub prev_ts: WitIn,
-    pub lt_cfg: AssertLTConfig,
+    pub lt_cfg: AssertLtConfig,
 }
 
 impl WriteMEM {

ceno_zkvm/src/instructions/riscv/shift.rs

@@ -7,7 +7,7 @@ use crate::{
     Value,
     error::ZKVMError,
     expression::{Expression, ToExpr, WitIn},
-    gadgets::{AssertLTConfig, SignedExtendConfig},
+    gadgets::{AssertLtConfig, SignedExtendConfig},
     instructions::Instruction,
     set_val,
 };
@@ -26,7 +26,7 @@ pub struct ShiftConfig<E: ExtensionField> {
     pow2_rs2_low5: WitIn,
 
     outflow: WitIn,
-    assert_lt_config: AssertLTConfig,
+    assert_lt_config: AssertLtConfig,
 
     // SRA
     signed_extend_config: Option<SignedExtendConfig<E>>,
@@ -90,7 +90,7 @@ impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for ShiftLogicalInstru
         let rs2_high = UInt::new(|| "rs2_high", circuit_builder)?;
 
         let outflow = circuit_builder.create_witin(|| "outflow");
-        let assert_lt_config = AssertLTConfig::construct_circuit(
+        let assert_lt_config = AssertLtConfig::construct_circuit(
             circuit_builder,
             || "outflow < pow2_rs2_low5",
             outflow.expr(),

ceno_zkvm/src/instructions/riscv/shift_imm.rs

@@ -4,7 +4,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::ZKVMError,
     expression::{Expression, ToExpr, WitIn},
-    gadgets::{AssertLTConfig, SignedExtendConfig},
+    gadgets::{AssertLtConfig, SignedExtendConfig},
     instructions::{
         Instruction,
         riscv::{constants::UInt, i_insn::IInstructionConfig},
@@ -24,7 +24,7 @@ pub struct ShiftImmConfig<E: ExtensionField> {
     rs1_read: UInt<E>,
     rd_written: UInt<E>,
     outflow: WitIn,
-    assert_lt_config: AssertLTConfig,
+    assert_lt_config: AssertLtConfig,
 
     // SRAI
     is_lt_config: Option<SignedExtendConfig<E>>,
@@ -83,7 +83,7 @@ impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for ShiftImmInstructio
         let rd_written = UInt::new(|| "rd_written", circuit_builder)?;
 
         let outflow = circuit_builder.create_witin(|| "outflow");
-        let assert_lt_config = AssertLTConfig::construct_circuit(
+        let assert_lt_config = AssertLtConfig::construct_circuit(
             circuit_builder,
             || "outflow < imm",
             outflow.expr(),

ceno_zkvm/src/scheme/mock_prover.rs

@@ -1213,7 +1213,7 @@ mod tests {
         ROMType::U5,
         error::ZKVMError,
         expression::{ToExpr, WitIn},
-        gadgets::{AssertLTConfig, IsLtConfig},
+        gadgets::{AssertLtConfig, IsLtConfig},
         set_val,
         witness::{LkMultiplicity, RowMajorMatrix},
     };
@@ -1357,7 +1357,7 @@ mod tests {
     struct AssertLtCircuit {
         pub a: WitIn,
         pub b: WitIn,
-        pub lt_wtns: AssertLTConfig,
+        pub lt_wtns: AssertLtConfig,
     }
 
     struct AssertLtCircuitInput {
@@ -1369,7 +1369,7 @@ mod tests {
         fn construct_circuit(cb: &mut CircuitBuilder<GoldilocksExt2>) -> Result<Self, ZKVMError> {
             let a = cb.create_witin(|| "a");
             let b = cb.create_witin(|| "b");
-            let lt_wtns = AssertLTConfig::construct_circuit(cb, || "lt", a.expr(), b.expr(), 1)?;
+            let lt_wtns = AssertLtConfig::construct_circuit(cb, || "lt", a.expr(), b.expr(), 1)?;
             Ok(Self { a, b, lt_wtns })
         }
 

ceno_zkvm/src/uint.rs

@@ -8,7 +8,7 @@ use crate::{
     circuit_builder::CircuitBuilder,
     error::{UtilError, ZKVMError},
     expression::{Expression, ToExpr, WitIn},
-    gadgets::{AssertLTConfig, SignedExtendConfig},
+    gadgets::{AssertLtConfig, SignedExtendConfig},
     instructions::riscv::constants::UInt,
     utils::add_one_to_big_num,
     witness::LkMultiplicity,
@@ -83,7 +83,7 @@ pub struct UIntLimbs<const M: usize, const C: usize, E: ExtensionField> {
     // We don't need `overflow` witness since the last element of `carries` represents it.
     pub carries: Option<Vec<WitIn>>,
     // for carry range check using lt tricks
-    pub carries_auxiliary_lt_config: Option<Vec<AssertLTConfig>>,
+    pub carries_auxiliary_lt_config: Option<Vec<AssertLtConfig>>,
 }
 
 impl<const M: usize, const C: usize, E: ExtensionField> UIntLimbs<M, C, E> {
@@ -131,7 +131,7 @@ impl<const M: usize, const C: usize, E: ExtensionField> UIntLimbs<M, C, E> {
     pub fn from_witins_unchecked(
         limbs: Vec<WitIn>,
         carries: Option<Vec<WitIn>>,
-        carries_auxiliary_lt_config: Option<Vec<AssertLTConfig>>,
+        carries_auxiliary_lt_config: Option<Vec<AssertLtConfig>>,
     ) -> Self {
         assert!(limbs.len() == Self::NUM_LIMBS);
         if let Some(carries) = &carries {