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What do we do if we still want partial bulk connection #18
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chisel-book/src/main/scala/components.scala Line 192 in 1ed8428
Prompted errors: [info] [0.000] Elaborating design... [error] chisel3.internal.ChiselException: Connection between left (AnonymousBundle(IO io in Fetch)) and source (AnonymousBundle(IO io in Decode)) failed @.regB: Left Record missing field (regB). [error] ... [error] at ammonite.$sess.cmd27$Helper$Processor.<init>(cmd27.sc:44) [error] at ammonite.$sess.cmd28$Helper.$anonfun$res28$1(cmd28.sc:1) [error] ... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace) scala.MatchError: ChiselExecutionFailure(Failed to elaborate Chisel circuit) (of class chisel3.ChiselExecutionFailure) ammonite.$file.dummy.source.load$minusivy_2$Helper.getVerilog(Main.sc:24) ammonite.$sess.cmd28$Helper.<init>(cmd28.sc:1) ammonite.$sess.cmd28$.<init>(cmd28.sc:7) ammonite.$sess.cmd28$.<clinit>(cmd28.sc:-1)
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Would you mind taking a look at this? Really appreciate it. @schoeberl |
Link:chisel3-vs-chisel2 I'm sorry that I have not understanded how to use <> in Chisel3.In my opinion, you should avoid to use <> in Chisel3. |
For 4.3 Bulk Connections, the
If a name is missing, it is not connected.
seems to be deactivated already. What do we do if we still want to use<>
for partial bulk connection? i.e., for the samefetch
decode
execute
as before?The text was updated successfully, but these errors were encountered: