diff --git a/rp2040-hal/src/adc.rs b/rp2040-hal/src/adc.rs index c3c566488..846677db7 100644 --- a/rp2040-hal/src/adc.rs +++ b/rp2040-hal/src/adc.rs @@ -532,7 +532,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { self } - /// Enable the FIFO interrupt ([`ADC_IRQ_FIFO`](pac::Interrupt::ADC_IRQ_FIFO)) + /// Enable the FIFO interrupt ([`ADC_IRQ_FIFO`](crate::pac::Interrupt::ADC_IRQ_FIFO)) /// /// It will be triggered whenever there are at least `threshold` samples waiting in the FIFO. pub fn enable_interrupt(self, threshold: u8) -> Self { @@ -606,7 +606,7 @@ impl<'a, Word> AdcFifoBuilder<'a, Word> { } } - /// Alias for [`start_paused`]. + /// Alias for [`AdcFifoBuilder::start_paused`]. #[deprecated(note = "Use `start_paused()` instead.", since = "0.10.0")] pub fn prepare(self) -> AdcFifo<'a, Word> { self.start_paused() @@ -796,14 +796,14 @@ impl<'a, Word> AdcFifo<'a, Word> { /// Trigger a single conversion /// - /// Ignored unless in [`AdcFifoBuilder::manual_trigger`] mode. + /// Ignored when in [`Adc::free_running`] mode. pub fn trigger(&mut self) { self.adc.device.cs().modify(|_, w| w.start_once().set_bit()); } /// Check if ADC is ready for the next conversion trigger /// - /// Only useful in [`AdcFifoBuilder::manual_trigger`] mode. + /// Not useful when in [`Adc::free_running`] mode. pub fn is_ready(&self) -> bool { self.adc.device.cs().read().ready().bit_is_set() } diff --git a/rp2040-hal/src/dma/single_channel.rs b/rp2040-hal/src/dma/single_channel.rs index 1b016eb71..bfe444be7 100644 --- a/rp2040-hal/src/dma/single_channel.rs +++ b/rp2040-hal/src/dma/single_channel.rs @@ -106,18 +106,6 @@ pub trait SingleChannel: Sealed { } } -/// Trait which implements low-level functionality for transfers requiring two DMA channels. -/// -/// Anything that requires more than a single buffer exactly once requires two channels to be -/// combined. -pub trait ChannelPair: SingleChannel + Sealed { - /// Returns the registers associated with the second DMA channel associated with this channel - /// pair. - fn ch2(&self) -> &crate::pac::dma::CH; - /// Returns the index of the second DMA channel. - fn id2(&self) -> u8; -} - impl SingleChannel for Channel { fn ch(&self) -> &crate::pac::dma::CH { self.regs() diff --git a/rp2040-hal/src/float/mod.rs b/rp2040-hal/src/float/mod.rs index 963b781f6..ad5df5fad 100644 --- a/rp2040-hal/src/float/mod.rs +++ b/rp2040-hal/src/float/mod.rs @@ -92,6 +92,7 @@ pub trait Float: } /// Returns true if `self` is infinity + #[allow(unused)] fn is_infinity(self) -> bool { (self.repr() & (Self::EXPONENT_MASK | Self::SIGNIFICAND_MASK)) == Self::EXPONENT_MASK } diff --git a/rp2040-hal/src/gpio/func.rs b/rp2040-hal/src/gpio/func.rs index 353180df2..f988bbb85 100644 --- a/rp2040-hal/src/gpio/func.rs +++ b/rp2040-hal/src/gpio/func.rs @@ -11,7 +11,6 @@ pub(crate) mod func_sealed { fn from(f: DynFunction) -> Self; fn as_dyn(&self) -> DynFunction; } - pub trait TypeLevelFunction {} } /// Type-level `enum` for pin function. @@ -83,7 +82,6 @@ macro_rules! pin_func { /// Type-level `variant` for pin [`Function`]. pub struct [](pub(super) ()); impl Function for [] {} - impl func_sealed::TypeLevelFunction for [] {} impl func_sealed::Function for [] { #[inline] fn from(_f: DynFunction) -> Self { @@ -110,7 +108,6 @@ pin_func!(Xip, Spi, Uart, I2c as I2C, Pwm, Pio0, Pio1, Clock, Usb, Null); /// Type-level `variant` for pin [`Function`]. pub struct FunctionSio(PhantomData); impl Function for FunctionSio {} -impl func_sealed::TypeLevelFunction for FunctionSio {} impl func_sealed::Function for FunctionSio { fn from(_f: DynFunction) -> Self { FunctionSio(PhantomData) diff --git a/rp2040-hal/src/pwm/mod.rs b/rp2040-hal/src/pwm/mod.rs index 22fc36a35..b4c811a53 100644 --- a/rp2040-hal/src/pwm/mod.rs +++ b/rp2040-hal/src/pwm/mod.rs @@ -100,7 +100,7 @@ use reg::RegisterInterface; /// Used to pin traits to a specific channel (A or B) pub trait ChannelId: Sealed { - /// Corresponding [`DynChannelId`](dyn_slice::DynChannelId) + /// Corresponding [`DynChannelId`] const DYN: DynChannelId; } @@ -140,7 +140,7 @@ pub trait ValidSliceInputMode: Sealed + ValidSliceMode {} /// Mode for slice pub trait SliceMode: Sealed + Sized { - /// Corresponding [`DynSliceMode`](dyn_slice::DynSliceMode) + /// Corresponding [`DynSliceMode`] const DYN: DynSliceMode; } @@ -175,7 +175,7 @@ impl ValidSliceInputMode for CountFallingEdge {} /// Type-level `enum` for slice IDs pub trait SliceId: Sealed { - /// Corresponding [`DynSliceId`](dyn_slice::DynSliceId) + /// Corresponding [`DynSliceId`] const DYN: DynSliceId; /// [`SliceMode`] at reset type Reset; diff --git a/rp2040-hal/src/timer.rs b/rp2040-hal/src/timer.rs index 4810a78c6..2a3272a91 100644 --- a/rp2040-hal/src/timer.rs +++ b/rp2040-hal/src/timer.rs @@ -188,7 +188,7 @@ impl embedded_hal::delay::DelayNs for Timer { } } -/// Implementation of the [`embedded_hal_0_2::timer`] traits using [`rp2040_hal::timer`] counter. +/// Implementation of the [`embedded_hal_0_2::timer`] traits using [`rp2040_hal::timer`](crate::timer) counter. /// /// There is no Embedded HAL 1.0 equivalent at this time. /// diff --git a/rp2040-hal/src/watchdog.rs b/rp2040-hal/src/watchdog.rs index 31e35d550..97e30fa1e 100644 --- a/rp2040-hal/src/watchdog.rs +++ b/rp2040-hal/src/watchdog.rs @@ -175,7 +175,7 @@ impl Watchdog { } /// Start the watchdog. This enables a timer which will reboot the - /// rp2040 if [`feed()`] doesnot get called for the configured period. + /// rp2040 if [`Watchdog::feed()`] does not get called for the configured period. pub fn start>(&mut self, period: T) { const MAX_PERIOD: u32 = 0xFFFFFF;