diff --git a/on-target-tests/tests/i2c_loopback.rs b/on-target-tests/tests/i2c_loopback.rs index bad66a8ea..a907843c7 100644 --- a/on-target-tests/tests/i2c_loopback.rs +++ b/on-target-tests/tests/i2c_loopback.rs @@ -59,13 +59,13 @@ mod tests { #[test] fn write_iter_read(state: &mut State) { i2c_tests::blocking::write_iter_read(state, ADDR_7BIT, 1..=1); - i2c_tests::blocking::write_iter_read(state, ADDR_10BIT, 2..=2); + i2c_tests::blocking::write_iter_read(state, ADDR_10BIT, 1..=1); } #[test] fn write_read(state: &mut State) { i2c_tests::blocking::write_read(state, ADDR_7BIT, 1..=1); - i2c_tests::blocking::write_read(state, ADDR_10BIT, 2..=2); + i2c_tests::blocking::write_read(state, ADDR_10BIT, 1..=1); } #[test] @@ -89,25 +89,26 @@ mod tests { #[test] fn transactions_read_write(state: &mut State) { i2c_tests::blocking::transactions_read_write(state, ADDR_7BIT, 1..=1); + // An initial read in 10 bit mode contains an implicit restart condition i2c_tests::blocking::transactions_read_write(state, ADDR_10BIT, 2..=2); } #[test] fn transactions_write_read(state: &mut State) { i2c_tests::blocking::transactions_write_read(state, ADDR_7BIT, 1..=1); - i2c_tests::blocking::transactions_write_read(state, ADDR_10BIT, 2..=2); + i2c_tests::blocking::transactions_write_read(state, ADDR_10BIT, 1..=1); } #[test] fn transaction(state: &mut State) { - i2c_tests::blocking::transaction(state, ADDR_7BIT, 7..=9); - i2c_tests::blocking::transaction(state, ADDR_10BIT, 7..=9); + i2c_tests::blocking::transaction(state, ADDR_7BIT, 5..=5); + i2c_tests::blocking::transaction(state, ADDR_10BIT, 5..=5); } #[test] fn transactions_iter(state: &mut State) { i2c_tests::blocking::transactions_iter(state, ADDR_7BIT, 1..=1); - i2c_tests::blocking::transactions_iter(state, ADDR_10BIT, 2..=2); + i2c_tests::blocking::transactions_iter(state, ADDR_10BIT, 1..=1); } #[test] diff --git a/on-target-tests/tests/i2c_loopback_async.rs b/on-target-tests/tests/i2c_loopback_async.rs index b8d4543e0..e604cf3bf 100644 --- a/on-target-tests/tests/i2c_loopback_async.rs +++ b/on-target-tests/tests/i2c_loopback_async.rs @@ -60,8 +60,8 @@ mod tests { #[test] fn transactions_iter(state: &mut State) { - run_test(non_blocking::transaction(state, ADDR_7BIT, 7..=9)); - run_test(non_blocking::transaction(state, ADDR_10BIT, 7..=14)); + run_test(non_blocking::transaction(state, ADDR_7BIT, 5..=5)); + run_test(non_blocking::transaction(state, ADDR_10BIT, 5..=5)); } #[test] diff --git a/on-target-tests/tests/i2c_tests/blocking.rs b/on-target-tests/tests/i2c_tests/blocking.rs index 13d731c0c..58eda5219 100644 --- a/on-target-tests/tests/i2c_tests/blocking.rs +++ b/on-target-tests/tests/i2c_tests/blocking.rs @@ -330,7 +330,7 @@ pub fn transactions_read_write( restart_count: RangeInclusive, ) { use embedded_hal::i2c::{I2c, Operation}; - let controller = reset(state, addr, true); + let controller = reset(state, addr, false); let samples_seq: FIFOBuffer = Generator::seq().take(25).collect(); let samples_fib: FIFOBuffer = Generator::fib().take(25).collect(); @@ -381,9 +381,9 @@ pub fn transaction( // does not "waste" bytes that would be discarded otherwise. // // One down side of this is that the Target implementation is unable to detect restarts - // between consicutive write operations + // between consecutive write operations use embedded_hal::i2c::{I2c, Operation}; - let controller = reset(state, addr, true); + let controller = reset(state, addr, false); let mut v = ([0u8; 14], [0u8; 25], [0u8; 25], [0u8; 14], [0u8; 14]); let samples: FIFOBuffer = Generator::seq().take(25).collect(); @@ -391,15 +391,15 @@ pub fn transaction( .transaction( addr, &mut [ - Operation::Write(&samples), // goes to v2 + Operation::Write(&samples), Operation::Read(&mut v.0), Operation::Read(&mut v.1), Operation::Read(&mut v.2), - Operation::Write(&samples), // goes to v3 + Operation::Write(&samples), Operation::Read(&mut v.3), - Operation::Write(&samples), // goes to v4 - Operation::Write(&samples), // remains in buffer - Operation::Write(&samples), // remains in buffer + Operation::Write(&samples), + Operation::Write(&samples), + Operation::Write(&samples), Operation::Read(&mut v.4), ], ) @@ -423,7 +423,12 @@ pub fn transaction( assert_vec_eq!(e); // assert reads - let g: FIFOBuffer = Generator::seq().take(92).collect(); + let g: FIFOBuffer = itertools::chain!( + Generator::seq().take(14 + 25 + 25), + Generator::fib().take(14), + Generator::seq().take(14), + ) + .collect(); let h: FIFOBuffer = itertools::chain!( v.0.into_iter(), v.1.into_iter(), diff --git a/on-target-tests/tests/i2c_tests/mod.rs b/on-target-tests/tests/i2c_tests/mod.rs index d186e3a69..40f1973b6 100644 --- a/on-target-tests/tests/i2c_tests/mod.rs +++ b/on-target-tests/tests/i2c_tests/mod.rs @@ -100,7 +100,10 @@ fn target_handler( } = payload; match evt { Event::Start => *first = true, - Event::Restart => *restart_cnt += 1, + Event::Restart => { + *first = true; + *restart_cnt += 1; + } Event::TransferRead => { let n = throttle.then_some(1).unwrap_or(target.tx_fifo_available()); let v: FIFOBuffer = gen.take(n.into()).collect(); diff --git a/on-target-tests/tests/i2c_tests/non_blocking.rs b/on-target-tests/tests/i2c_tests/non_blocking.rs index 43923fd36..033cfabc5 100644 --- a/on-target-tests/tests/i2c_tests/non_blocking.rs +++ b/on-target-tests/tests/i2c_tests/non_blocking.rs @@ -342,11 +342,9 @@ pub async fn transaction( assert_eq!(e, state.payload.borrow().vec); // assert reads let g: FIFOBuffer = itertools::chain!( - Generator::fib().take(25), - Generator::fib().skip(32).take(25), - Generator::fib().skip(64).take(25), - Generator::fib().skip(96).take(14), - Generator::fib().skip(112).take(14), + Generator::fib().take(25 * 3), + Generator::seq().take(14), + Generator::fib().take(14), ) .collect(); let h: FIFOBuffer = itertools::chain!(