MNXTI CSR clarifications?

[mark-honman]

Section 3.8.7 "Next Interrupt Handler Address and Interrupt-Enable CSR"

It seems like the use of CSRRS was added after the text was written, leading to some inconsistencies.

• text refers to "mstatus CSR is used for the RMW portion of the operation" but the CSRRS example only affects the bottom 5 bits of mstatus.
• text refers to "must have a level greater than the saved interrupt level mcause.mpil" but the CSRRS example does not check this value, and instead uses rs1[23:16]. Maybe this is intentional but there is no explanation...
• It seems weird that CSRRS is permitted but not CSRRC.
• Similarly weird, the CSRRSI immediate cannot include non-zero immediate values for bits 0, 2, and 4 but no such restriction applies to CSRRS or CSRRCI.

Perhaps it would be helpful to be more explicit, say "mie and sie bits of the mstatus CSR are used for the RMW portion of the operation; no other bits may be set in the CSRRS/I or CSRRC/I operand"

It may be useful to describe in the conditions for a "suitable" pending interrupt, that those tests are independent of global interrupt enable (which appears to be the case, by inference from the example interrupt handler code in the SW section).

[hirooih]

• text refers to "must have a level greater than the saved interrupt level mcause.mpil" but the CSRRS example does not check this value, and instead uses rs1[23:16]. Maybe this is intentional but there is no explanation...

I also would like to know the use-case of csrrs rd, xnxti, rs1 (rs1 != x0). All of sample codes in Appendix use only csrrsi/csrrci xnxti.

The use-case for csrrs rd, xnxti, x0 is described:

This can be used to determine if an interrupt could be taken without actually updating mil and exccode.

But in this case mcause.mpil should be used instead of x0[23:16]. Pseudo-code for this is very simple and easy to implement by reusing logic for csrrsi/csrrci xnxti.

 if (clic.priv==M && clic.level > mcause.mpil && clic.level > mintthresh.th) {
   rd = VTBASE + XLEN/8 * clic.id; // Return pointer to trap handler entry.
 } else {
   rd = 0;
 }

The current specification of csrrs rd, xnxti, rs1 (rs1 may be x0) has no known use-case and is not easy to implement.