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debug: Fix nonexistent trigger registers trap handle in entry.S #549

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merged 1 commit into from
May 9, 2024

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@leesum1 leesum1 commented Apr 17, 2024

In Sv39Test, SV48Test, and SV57Test, if the processor does not implement the trigger module, accessing the trigger csr registers will result in a trap, causing the mpp field in mstatus to be modified to machine mode. Additionally, in the original code, mstatus is not restored after trap, resulting in the effective privilege mode being machine mode in subsequent translate tests, which prevents address translation and leads to test failures.

This PR ensures that processors without implementing the trigger module can pass the tests successfully.

@aap-sc aap-sc requested review from en-sc and aap-sc April 21, 2024 13:30
@aap-sc aap-sc merged commit 29e6bc8 into riscv-software-src:master May 9, 2024
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2 participants