From c797379936ea3b71832df9ecbc8563d40d7573f7 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Sat, 3 Aug 2024 17:59:43 +0530 Subject: [PATCH] Improve the requirement for callers with paging enabled The current requirement of ensuring semihosting instruction sequence is aligned within a single page is not suitable for RISC-V platforms where TLB is not implemented. To address this, add more stricter requirement where caller must ensure semihosting instruction sequence and data passed via memory are both paged in. Suggested-by: Ved Shanbhogue Signed-off-by: Anup Patel --- src/binary-interface.adoc | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/binary-interface.adoc b/src/binary-interface.adoc index 086c3f7..37a3b89 100644 --- a/src/binary-interface.adoc +++ b/src/binary-interface.adoc @@ -22,19 +22,18 @@ srai x0, x0, 7 # 0x40705013 Exit NOP ---- These three instructions must be 32-bit wide instructions. This same sequence -is used on all RISC-V architectures. If paging is in use in the current mode, -this sequence must not cross a page boundary as the semihosting system must -be able to check for the semihosting sequence without needing data from -potentially missing pages. The <> shows how this can be done by -placing the sequence in a separate assembly function and aligning that to -prevent that from spanning a page boundary. +is used on all RISC-V architectures. If address translation and protection is +enabled for the semihosting caller then the semihosting instruction sequence +and data passed via memory must be paged in else the behavior of the semihosting +call is UNSPECIFIED. The <> shows an example assembly function to invoke +a semihosting service which can be used by callers with no address translation and +protection. .RISC-V Semihosting Assembly Reference Function [#function] ---- .option norvc .text - .balign 16 .global sys_semihost .type sys_semihost @function sys_semihost: