INIT.MAC

	subttl	File: INIT.MAC

; *** INIT.MAC  This file contains the initialization part of CBIOS.
;
; This code is run at address D700 (but will run as well at address 380)
; which is where the loader puts it.
;
; The comments have been expanded and translated to English 910512
;

	DI			; Time to do some non-interrupted device programming
;
;MOVE THE CODE PART OF BIOS
;
	LD	HL,LOADADDR	;  The code is read at $0000 (or $0100 when
	LD	DE,CODEDESTINAT	;  from a .COM file, and is moved to the $D700
	LD	BC,CODELENGTH	;  address here.  Please note that this will
	LDIR			;  be patched by PUTBIOS.PAS
;
;MOVE THE CONVERSION PART OF THE BIOS
;
	LD	HL,CONVLOADADDR	;   Move the maps to their final place.
	LD	DE,KEYOUTTABLE	;
	LD	BC,CONVLENGTH	; 
	LDIR			; 
	LD	SP,DEFDMAAREA	;   We need some stack.
	LD	HL,INTERRUPTPAGE;   (* Defined in C.MAC at the interrupt system *)
	LD	A, H		;
	LD	I,A		;   Tell the CPU what to do about it, in
	IM	2		;   daisychain mode.  Interrupts are not
				;   enabled before *all* devices have been
				;   initialized.
	ld	hl, cl$yy
	ld	(clockaddr), hl	; <- Pointer to date/time record.
	page
;
; Setup Z80PIO (Keyboard= 12h, Parallel= 13h).    Zilog doc page 191.
;
; 910131 - Keyboard is configured as input, and parallel (unused) as output.
;
; PIO consists of two I/O ports (A & B), which both can be put to work
; in 4 modes.
;
; Output(0), Input(1), Both ways(2) and Bitcontrol(3)
;
; Output and Input are straightforward.  Both ways uses both ports named by
; A.  Port B must be inactivated (put in mode 3 and DI).  See Zilog page 192.
;
; Bit control works for both ports.  Here each bit is defined seperately as
; I or O.  An interrupt is generated, if either one or all of the specified
; bits are changed (one= A0, all= A1). 
;
; mmxx1111= Mode control word. mm=(mode 0,1,2, (0-2 further) 3 (1-3 further)
;
; vvvvvvv0= Interrupt vector
;
; iiiiiiii= I/O register control word (0=output, 1=input). Follows immediately
;	    after MCW in mode 3.
;
; IAHM0111= Interrupt control word    (I1=Interrupt enabled, A1=And function,
;		H1=Active High, M1=Mask control word follows)
;
; mmmmmmmm= Mask Control Word - If def as input and m=0 an interrupt will 
;				occur when bit goes high
; ixxx0011= Interrupt disable.  i1=enable, i0=Disable.
;

kbintvect	equ	20h	; Keyboard interrupt vector
parintvect	equ	22h	; Parallel -//-
pioAcontrl	equ	12h	; Control- and dataports for each Pio channel
pioAdata	equ	10h	; 
pioBcontrl	equ	13h	;
pioBdata	equ	11h	;

				; BEGIN (* PIO INT *)
	LD	A,kbintvect	;   PIO[A].IntVect:= KbIntVect;
	OUT	(pioAcontrl),A	; 
	LD	A,parintvect	;   PIO[B].IntVect:= ParIntVect;
	OUT	(pioBcontrl),A	; 
	LD	A,01001111b	;   PIO[A].Mode:= Output;
	OUT	(pioAcontrl),A	; 
	LD	A,00001111b	;   PIO[B].Mode:= Input;
	OUT	(pioBcontrl),A	; 
	LD	A,10000011b	;   PiO[A].InterruptOk:= TRUE;
	OUT	(pioAcontrl),A	;   
	OUT	(pioBcontrl),A	;   PIO[B].InterruptOk:= TRUE;
	page			; END; (* PIO INIT *)
;
; Setup Z80CTC (0ch= SIO terminal, 0dh= SIO printer, 0eh= Disp int, 0fh= Floppy)
; Zilog documentation page 205.  RC documentation 2.3.5
;
; The Z80 Counter/Timer circuit has 4 independent counters/timers which can
; be used for various thingies.
;
; Programming is done with 2 bytes pr channel.  A third is neccesary when 
; interrupts are active.  When the channel is started, the countdown goes
; until zero.  When zero is reached the timeconstant is reloaded and count-
; down resumed.

; Channel Control Word :
;  7: Interrupt enable
;  6: 0= Timer / 1= Counter
;  5: 0= Prescalerx16 / 1=Prescalerx256
;  4: 0= Downward edge / 1= Upward edge
;  3: 0= Automatic trigger / 1=Start at extern CLK/TRG pulse
;  2: 0= No timeconstant (used by update)/ 1= Timeconstant follows
;  1: 1= Software reset
;  0: 0= Interrupt vektor, 1= Control word
;
; Time Constant:  
;  0..255. Tidsinterval= Clock periode x Prescale x Time Constant.
;
; Interrupt Vector Word:
;  VVVVVxx0 : Vektor.  xx is automatically set to 0-3
;
; RC notes:
;   Channels 0 and 1 are used to generate the clock to channel A/B in SIO.
;   The clock is further divided up in the SIO to get the baud rates.
;   Supplies 0.614 MHz.
;   Channels 2 and 3 are initiated in counter mode with interrupt enabled
;   and with a time constant of 1.  This means that for every clock input
;   an interrupt is sent to the CPU.  Channel 2 for display, 3 for floppy.
;
ctc0port	equ	0ch
ctc1port	equ	0dh
ctc2port	equ	0eh
ctc3port	equ	0fh

	LD	A,0		; BEGIN 
	OUT	(ctc0port),A	;   CTC.InterruptVektor:= 0;
	LD	A,(CTC0C)	; 
	OUT	(ctc0port),A	;   Setup each port as defined in the
	LD	A,(CTC0T)	;   long term configuration block
	OUT	(ctc0port),A	; 
	LD	A,(CTC1C)	; 
	OUT	(ctc1port),A	; 0) $47 $10
	LD	A,(CTC1T)	; 
	OUT	(ctc1port),A	; 1) $47 $08
	LD	A,(CTC2C)	; 
	OUT	(ctc2port),A	; 2) $D7 $01	(* Disp int *)
	LD	A,(CTC2T)	; 
	OUT	(ctc2port),A	; 3) $D7 $01
	LD	A,(CTC3C)	; 
	OUT	(ctc3port),A	; 
	LD	A,(CTC3T)	; 
	OUT	(ctc3port),A	; END;
;
; Warning: Unknown unit initialization.  My guess is a high-resolution
; graphics screen.
;
	LD	A,8		; 
	OUT	(44H),A		; 
	LD	A,(LD544)	; 
	OUT	(44H),A		; 
	LD	A,(LD545)	; 
	OUT	(44H),A		; 
	LD	A,(LD546)	; 
	OUT	(45H),A		; 
	LD	A,(LD546)	; 
	OUT	(46H),A		; 
	LD	A,(LD546)	; 
	OUT	(47H),A		; 
;
;
; SIO - Documentation is present in SERIAL.MAC
;
;***T$Ctrl	equ	10
;***T$Data	equ	8
;***L$Ctrl	equ	11
;***L$Data	equ	9

;INIT SIO (TERMINAL)
;
	LD	HL,TERMINIT	;  Set up the serial ports
	LD	B,9		; 
	LD	C,T$Ctrl	; 
	OTIR			; 
;
;INIT SIO (PRINTER)		;  ######### Note: External when splitting into modules
;
	LD	HL,PRINTINIT	; 
	LD	B,0BH		; 
	LD	C,L$Ctrl	; 
	OTIR			; 
				;
	IN	A,(T$Ctrl)	;  .. Save the result for later.
	LD	(T$RR0),A	; 
	LD	A,1		; TermRR0:= Sio[0].RR0;
	OUT	(T$Ctrl),A	; TermRR1:= Sio[0].RR1;
	IN	A,(T$Ctrl)	; 
	LD	(T$RR1),A	; 
	IN	A,(L$Ctrl)	; 
	LD	(L$RR0),A	;  PrinterRR0:= Sio[1].RR0;
	LD	A,1		;  PrinterRR1:= Sio[1].RR1;
	OUT	(L$Ctrl),A	; 
	IN	A,(L$Ctrl)	; 
	LD	(L$RR1),A	; 
	page

; DMA controller (Am9517A multimode DMA controller)
;
; This curcuit contains 4 independent channels, with 64k address and
; word count possibillity.  It contains these registers (W= 16bit, 8= 8bit, 4= 4bit)

; Name:					Number of regs:
; Base address registers (W)		4
; Base Word Count registers (W)		4
; Current Address Registers (W)		4
; Current Word Count registers (W)	4
; Temporary Address register (W)	1
; Temporary Word COunt register (W)	1
; Status register (8)			1
; Command register (8)			1
; Temporary Register (8)		1
; Mode registers (8)			4
; Mask register (4)			1
; Request register (4)			1
;
; PORT allocation
;
; Nr	Read			Write
; F0	0) Current address	0) Base and Current address
; F1	0) Current Word count	0) Base Word Count
; F2	1) Current address	1) Base and Current address
; F3	1) Current Word count	1) Base Word Count
; F4	2) Current address	2) Base and Current address
; F5	2) Current Word count	2) Base Word Count
; F6	3) Current address	3) Base and Current address
; F7	3) Current Word count	3) Base Word Count
; F8	Status register		Command register
; F9	-			Request register
; FA	-			Single mask register
; FB	- 			Mode register
; FC	-			Clear Flip/Flop (hi/low switch)
; FD	Temporary register	Master Clear
; FE	-			-
; FF	-			All mask register bits
;
; Command register:
;   7: 0= DACK sense active low,  1= DACK sense active high
;   6: 0= DREQ sense active high, 1= DREQ sense active low
;   5: 0= Late write selection,   1= Extended write selection (X if bit 3=1)
;   4: 0= Fixed priority, 	  1= Rotating priority
;   3: 0= Normal timing, 	  1= Compressed timing (don't care if bit 0=1)
;   2: 0= Controller enable, 	  1= Controller disable
;   1: Channel 0 address hold 0=disable/1=enable (don't care if bit 0=0)
;   0: Memory-Memory 0=Disable/   1= Enable
;
; Mode register:
;   76: Select mode           (00= Demand, 01= Single, 10= Block, 11= Cascade)
;   5:  0= Address increment, 1= Address decrement
;   4:  0= No autoinitialize, 1= Do autoinitialize
;   32: Transfer              (00= Verify, 01= Write, 10= Read, 11= Illegal, xx if 76:=11)
;   10: Channel  	      (00= 0, 01=1, 10=2, 11=3)
;
; Request register:
;   76543:  Don't care
;    2: 0= Reset request bit, 1= Set request bit
;   10: Channel               (00=0, 01=1, 10=2, 11=3)
;
; Mask register 
;   76543: Don't care
;    2: 0= Clear mask bit, 1= Set mask bit
;   10: Channel 	      (00=0, 01=1, 10=2, 11=3)
;
; All bits mask register      Status register                             
;  7654: Don't care              7: Channel 3 request                     
;    3: Channel 3 bit            6: Channel 2 request                     
;    2: Channel 2 bit            5: Channel 1 request                     
;    1: Channel 1 bit            4: Channel 0 request                     
;    0: Channel 0 bit            3: Channel 3 has reached terminal count  
;                                2: Channel 2 has reached terminal count  
;                                1: Channel 1 has reached terminal count  
;                                0: Channel 0 has reached terminal count  
;
; Clear First/Last flip-flop.    Resets the flip/flop to point at the low-
; byte of the word.  When writing this byte (which goes in the low-end) the
; flip/flop flips to let the next byte go in the high-end.
;
; Master Clear.  Functions as a hardware reset, works on all channels.
;
;
; Channel allocation:
; 0: Harddisk I/O routines.		--- RC says "External debugger"
; 1: Floppy I/O
; 2: CRT controller feeder
; 3: -//-. Reset by CRT interrupt. (Very weird)

dmacmd		equ	0f8h	; Write Command register
dmarequest	equ	0f9h	; Write Request register
dmasinglebit	equ	0fah	; Write Single mask register bit
dmamode		equ	0fbh	; Write Mode register
dmaclrff	equ	0fch	; Clear flip/flop
dmareset	equ	0fdh	; Master reset
dmaallbit	equ	0ffh	; Write all mask register bits

dmastatus	equ	0f8h	; Read status register
dmatmp		equ	0fdh	; Read temporary register

; Rotatin priority, 0-3: Write/ Single/ Auto-increment
	LD	A,00100000b	; BEGIN
	OUT	(dmacmd),A	;   WITH DMA DO BEGIN
	LD	A,(DMA0INIT)	;     No memory-memory, Controller enabled,
	OUT	(dmamode),A	;     Normal timing, Fixed priority, 
	LD	A,(DMA2INIT)	;     DREQ sense high, DACK sense low.
	OUT	(dmamode),A	; 
	LD	A,(DMA3INIT)	;   
	OUT	(dmamode),A	; END; END;
	page
				;
				; Do we need to set up a 5" machine??
	IN	A,(14H)		; 
	AND	80H		; Nope, when 8" skip this
	Jr	Z,FDCBUSY	; Yes, alas.  Lets go ahead
				;
	LD	HL,IFLOPCONF	; *** Change DD8" to DD5" for 5"machines.
	LD	A,(HL)		; 
	CP	8		; 
	jr	NZ,DISKTYPEOK	; 
	LD	(HL),10H	; 
DISKTYPEOK:			; 
	INC	HL		; 
	LD	A,(HL)		; 
	CP	8		; 
	jr	NZ,INITFDC	; 
	LD	(HL),10H	; 
	page			;

; Floppy Disk Controller. uPD765
;
; Reading from FDCctrl gives the Main Status Register with these
; meanings: (Bitpositions= 76543210, where 7= 80h and 0= 1h)
;
; Main Status Register (Always available from controlport)
; ====================
;
;   0=01: 			      1= Drive 0 Seeks
;   1=02: 			      1= Drive 1 Seeks
;   2=04: 			      1= Drive 2 Seeks
;   3=08: 			      1= Drive 3 Seeks
;   4=10: 0= FDC is idle              1= FDC is executing a command.  Do not disturb
;   5=20: 0= DMA mode,                1= Non-DMA mode
;   6=40: 0= Data from CPU to FDC,    1= Data from FDC to CPU
;   7=80: 0= Not ready to send/rec    1= Ready to rec/send data
;
; Also the FDC returns its results in its status registers. (4 of these).
; If (SIS) is noted, you will need to use the Sense Interrupt Status command
; to get this information

;
; ST0:  ( Status register 0)
; ==========================
;
; 7,6=C0 : 00= Command terminated correctly
;          01= Command terminated incorrectly
;          10= Unknown command
;          11= Change of ready state for a drive (Could be diskette in/out)
; 5=20   :  1= Seek/Recalibrate command done (SIS)
; 4=10   :  1= Drive has not reached track 0 during recalibrate (SIS)
; 3=08   :  1= Drive not ready.
; 2=04   :  ?= Head address.  (Upper/lower surface of diskette)
; 1,0=03 : 00= Drive 0, 01=Drive 1, 10= Drive 2, 11= Drive 3
;
;
; ST1:  ( Status register 1)
; ==========================
;
; 7=80   :  1= End of track.  Controller read too much without being interupted
; 6=40   :     Unused.
; 5=20   :  1= CRC error (Yecch).  Check ST2.5 to see where the error is.
; 4=10   :  1= Overrun.  The CPU ain't fast enough to remove data from FDC.
; 3=08   :     Unused.
; 2=04   :  1= No data.  Three possibillities for this:
;		1) Cannot find the given sector eventhough the address mark
;		   was found (READ, WRITE, SCAN)
;		2) Error by READ ID
;		3) Cannot find startsector (READ TRACK)
; 1=02   :  Diskette is writeprotected
; 0=01   :  Error in addressmark.  Check ST2.0 to see where the error is.
;
;
; ST2:  ( Status register 2)
; ==========================
;
; 7=80   :  Unused.
; 6=40   :  Tried to read DELETED data in non-deleted read, or vice versa.
;	    The DELETED DATA facillity is not used by CP/M
; 5=20   :  CRC-error in datafield.  ST1.5 is also set.
; 4=10   :  Wrong track.  Only if the wanted sector cannot be found, and all
;	    the sectors on the current track have tracknumber different from
;	    the specified, which is _not_ $FF. 
; 3=08   :  SCAN command has found "Equal" data on disk.
; 2=04   :  SCAN did not succed on this track.
; 1=02   :  Same as ST2.4, but where tracknumber is $FF
; 0=01   :  No addressmark in datafield.  ST1.0 is also set.
;
;
; ST3:  ( Status register 3)
; ==========================
;
; 7=80   :  Unused.
; 6=40   :  Write protect status
; 5=20   :  Ready status
; 4=10   :  Track 0 status
; 3=08   :  Unused
; 2=04   :  Head select status
; 0,1=03 :  Drive selected: 00=0, 01=1, 10=2, 11=3.
;
;
; Kommandobyte nr 1
; =================
; 
; 7=80   : MT.  "Multi-track".  When set, both surfaces can be read.
; 6=40   : MFM. "Modified frequency modulation". 1=MFM, 0=FM.  MFM is the best
;	   but requieres better hardware, especially the read head.  See
;	   external documentation.
; 5=20   : SK. "Skip" (???)
; 4-0=1F : The actual command
;  00010 = Read a track       (A)
; (00011 = Specify)
;  00100 = Sense drive status (B)
;  00101 = Write data         (A)
;  00110 = Read data          (A)
;  00111 = Recalibrate        (C)
;  01000 = Sense interrupt    (D)
;  01001 = Write deleted data (A)
;  01010 = Read ID            (E)
;  01100 = Read deleted data  (A)
;  01101 = Format a track     (F)
;  01111 = Seek               (G)
;  10001 = Scan equal         (H)
;  11001 = Scan low or equal  (H)
;  11101 = Scan high or equal (H)
;
; 		Data in				Data out
;(A)	Track, Head, Sector, Bytes/	ST0, ST1, ST2, Track, Head, Sector,
;	Sector,  EOT sector, Gap,	Bytes/Sector
;	Data length
;(B)	-nil-				ST3
;(C)	-nil-				-nil-
;(D)	-nil-	(note: only 1 byte)	ST0, Track
;(E)	-nil-				som (A)
;(F)	Bytes/Sector, Sectors/Track,	som (A)
;	Gap, Data pattern		
;(G)	Track				-nil-
;(H)	Track, Head, Sector, Bytes/	som (A)
;	sector, EOT sector, Gap,
;	Sector step size

FDCctrl	equ	5		; Control port
FDCdata	equ	4		; Data port
				; Please note that this is as given in the
				; Rc700 Comal80 handbook.  It may *really* be in
				; the reverse order.  I am not sure.


				; FDC commands
				;
FDCrecal	equ	7	; Recalibrate FDC
FDCsds		equ	4	; Sense drive status
FDCsis		equ	8	; Sense interrupt status
FDCseekcmd	equ	15	; Seek track

INITFDC:			; PROCEDURE InitFDC;
	LD	A,0FH		; BEGIN
	LD	(LD526),A	;   LD526:= $15;
FDCBUSY:			; 
	IN	A,(FDCdata)	;   REPEAT
	AND	00011111b	;     Check FDC status;
	jr	NZ,FDCBUSY	;   UNTIL CommandDone && NoSeekingDrives;
	LD	HL,FCBINITDATA	; 
	LD	B,(HL)		;   FOR B:= 1 TO FcbInitData[0] DO
INITFCBNEXT:			;   BEGIN
	INC	HL		;     REPEAT
INITFCB1:			;       Check FDC status;
	IN	A,(FDCdata)	;     UNTIL Ready to receive Command;
	AND	0C0H		;     FDC.Command:= FcbInitData[ B ];
	CP	80H		;   END;
	jr	NZ,INITFCB1	; 
	LD	A,(HL)		; 
	OUT	(FDCctrl),A	; 
	DEC	B		; 
	jr	NZ,INITFCBNEXT	; END;
;
;CLEAR SCREEN
;
	LD	HL,SCREENBASE	; Fill(Screen, Size(Screen), ' ');
	LD	DE,ScrPos2	; 
	LD	BC,SCREENsize	; 910307 -- Erases also the 26th line
	LD	(HL),' '	; 
	LDIR			; 
	ld	(hl), 0ffh	; Last visible screenbyte. Stops DMAfeed to CRT.
	call	n$statl		; Display default statusline.
;
;CLEAR CHARACTER ATTIBUTES
;
	if	fb$ena
	 LD	HL,FB$BASE	; Fill(ForeBack, Size(ForeBack), 0);
	 LD	DE,FB$POS1	; 
	 LD	BC,0FAH		; 
	 LD	(HL),0		; 
	 LDIR			; 
	endif
;
;CLEAR VARIABLES ABOVE SCREENMEM 
;Made unnecessary 910302, as these have been moved.  It is, however, 
;necessary to clear the clock.

	ld	hl,0
	ld	(clocklow), hl
	ld	(clockhigh), hl

;	LD	HL,XCOOR	; Fill($FFD1..$FFFF, 0);
;	LD	DE,ScrLineBase	; 
;	LD	(HL),0		; 
;	LD	BC,0ffffh-Xcoor	; 
;	LDIR			; 

	page			;
; CRT controller  Intel 8275
;
; This controller is *very* primitive.  It is crippeled by having its video-
; attributes physically present on the screen, which makes it very unfit
; for terminal emulation.
;
; The controller has eight commands (+ is write parameter, - is read returned)
;
; 00000000 +4 Reset		- Sets up a lot of things.  See documentation
; 001sssbb    Start display	- (sss*8)-1 clocks/dma req, 2^bb dma cycles/burst
; 01000000    Stop display	- Turns off display.
; 01100000 -2 Read lightpen	- Unprecise. 
; 10000000 +2 Load Cursor	- Gotoxy(parm1, Parm2)
; 10100000    Enable interrupt
; 11000000    Disable interrupt
; 11100000    Preset counters   - Reset display timers
;

CRTctrl	equ	1		; CRT command port
CRTdata	equ	0		; CRT data port

CRTgoto		equ	80h	; CRT gotoxy command
CRTreset	equ	0	; CRT reset  command

	LD	A,CRTreset	; BEGIN
	OUT	(CRTctrl),A	; 
	LD	A,(CRT0)	; 
	OUT	(CRTdata),A	;   Setup CRT
	LD	A,(CRT1)	; 
	ifdef	crt26		;
	 sub	 03fh		;   VerticalRetraceCount=-1; LinesOnScren=+1;
	endif			;
	OUT	(CRTdata),A	; 
	LD	A,(CRT2)	; 
;	ifdef	crt26		;
;	 add	 a, 030h	;   UnderLinePlacement=+3; 
;	endif			;   
	OUT	(CRTdata),A	; 
	LD	A,(CRT3)	; 
	OUT	(CRTdata),A	; 
				;
	LD	A,CRTgoto	;   GotoXY(0,0); 
	OUT	(CRTctrl),A	; 
	LD	A,0		; 
	OUT	(CRTdata),A	; 
	OUT	(CRTdata),A	; 
				;   Preset counters for display
	LD	A,11100000b	; 
	OUT	(CRTctrl),A	; 
	LD	A,00100011b	;   Start Display. 0 clocks between dma req,
LD84C:				;   2 dma cycles pr burst
	OUT	(CRTctrl),A	; 
;
;
;ZERO ALL BUFFER AREA (DMA FOR A: .. FB$)
;
	LD	DE,BUFFERSTART	; Fill(BufferStart..ForeBackBase-1,0);
	LD	HL,FB$BASE	; 
	AND	A		; 
	SBC	HL,DE		; 
	LD	C,L		; 
	LD	B,H		; 
	LD	HL,BufferStart+1; 
	EX	DE,HL		; 
	LD	(HL),0		; 
	LDIR			; 
;
;EXTRACT SIO-BITLENGTHS
;
	LD	A,(TERMBYTE)	; 
	AND	60H		; 
	LD	(TERMBITS),A	; 
	LD	A,(PRINTBYTE)	; 
	AND	60H		; 
	LD	(PRINTBITS),A	; 
				; 
	LD	A,(CXB4Y)	; 
	LD	(XB4Y),A	; 
	LD	HL,(CMOTOROFFTIM)
	LD	(MOTOROFFTIME),HL
	LD	A,True		; 
	LD	(FDCRESOK),A	; 
	CALL	MOVECONF	; 
	EI			; --- OK.  System activated.
	LD	A,1		; 
	LD	(FLOPPYBOOT),A	; When all other fails, start from floppy
	if 	UseHD
TRYLOADHD:			; 
	 LD	B,1		; BUT if a harddisk is present, (which answers)
	 LD	A,' '		; then use it instead
	 CALL	OUT66		; 
	 LD	BC,0F000h	; 
LD895:				; 
	 LD	A,(HDREADY)	; 
	 OR	A		; Below is a few weird things, which is some
				; silly things in the original code.
ld89a	 equ	$+1		; (done 910112/Th )

	 JR	NZ,HDLOAD	;
	 DEC	BC		; 
	 LD	A,B		; 
	 OR	C		; 
	 JR	NZ,LD895	; 
	 JP	NOHARDDISK	; 
HDLOAD:				; PROCEDURE HdLoad;
	 LD	A,(ERFLAG)	; BEGIN
	 OR	A		;   ErFlagWas:= ErFlag;
	 LD	A,0		;   ErFlag:= FALSE;
	 LD	(ERFLAG),A	;   HdReady:= FALSE; (* Ack int *)
	 LD	(HDREADY),A	; 
	 PUSH	AF		;   IF WaitStr[1]<>@0 THEN
	 LD	HL,WAITMSG	;     WriteLn('Waiting'); (* WaitStr *)
	 CALL	PRINTSTR	; 
				;   (* DON'T PRINT MESSAGE ANYMORE *)
	 XOR	A		;   WaitStr[1]:= @0;
	 LD	(WAITMSG),A	; 
	 POP	AF		; 
	 jr	NZ,TRYLOADHD	; IF ErFlagWAS= TRUE THEN GOTO TryLoadHd;
	 XOR	A		; (* Try again*)
				;
				;**  LOAD CONFIGURATION FROM HARDDISK TO $80;
				;
	 LD	(HDREADY),A	;   HdReady:= FALSE;
	 LD	(FLOPPYBOOT),A	;   FloppyBoot:= FALSE;
	 LD	BC,2		; 
	 CALL	SELDSK		;   IF DiskRead(
	 LD	BC,0		;        Drive=C,
	 CALL	SETTRK		;        Track=0,
	 LD	BC,7CH		;        Sector=1,
	 CALL	SETSEC		;        DMA=DefDmaArea)<>OK
	 LD	BC,DEFDMAAREA	;   THEN 
	 CALL	SETDMA		;   BEGIN
	 CALL	DSKREAD		;     WriteLn('Cannot Load configuration');
	 OR	A		; 
	 JR	Z,MOVENEWCONF	; 
	 LD	HL,CANNOTMSG	; 
	 CALL	PRINTSTR	;     Cancel ClearScreen in SignonMSg;
	 LD	A,0DH		;  
	 LD	(SIGNONMSG),A	;     Goto NoHardDisk;
	 JR	NOHARDDISK	;   END; (* Cannot load config from hd *)
				;
				;*** MOVE NEWLY READ CONFIGURATION RECORD TO
				;    CORRECT PLACE
MOVENEWCONF:			; 
	 LD	DE,IHDCONF	; 
	 LD	HL,DEFDMAAREA	; 
	 LD	BC,13H		; =19
	 LDIR			; 
	 LD	HL,IHDCONF	; 
	 LD	A,(HL)		; 
	 CP	' '		; IF $20 or $28 => Ld923 (* OK drev *)
	 JR	Z,LD923		; 
	 CP	'('		; else set it to the same type as A:
	 JR	Z,LD923		; and setup some parameters.
	 LD	A,(DR0)		; 
	 ADD	A,18H		; 
	 LD	(HL),A		; 
	 INC	HL		; 
	 LD	(HL),True	; 
	 LD	HL,LD540	; 
	 LD	(HL),2		; 
	 INC	HL		; 
	 LD	(HL),1		; 
	 JR	LD923		; HardDisk routines ^^
	endif	; UseHD		; --------------------------------
NOHARDDISK:			; 
	LD	A,True		; Common startup.
	LD	(IHDCONF),A	; 
	XOR	A		; 
	LD	(BOOTDRIVE),A	; 
LD923:				; 
	CALL	MOVECONF	; 
	LD	HL,C$DPB	; 
	LD	(CURFCB),HL	; 
	LD	HL,DR2		; 
	PUSH	HL		; 
SETUPHD:			; 
	POP	HL		; 
	PUSH	HL		; 
	CALL	GETDPBADDR	; 
	POP	HL		; 
	INC	HL		; 
	PUSH	HL		; 
	LD	A,(HL)		; 
	CP	True		; 
	JR	NZ,SETUPHD	; 
	POP	HL		; 
	LD	BC,1BH		; 
	LD	HL,DRVHDCONF	; 
	LD	DE,LEA98	; 
LD947:				; 
	LD	A,(HL)		; 
	PUSH	HL		; 
	AND	0F8H		; 
	LD	HL,29H		; 
	CP	'0'		; 
	CALL	Z,SAVEHLBC2DE	; 
	LD	HL,52H		; 
	CP	'8'		; 
	CALL	Z,SAVEHLBC2DE	; 
	LD	HL,0A5H		; 
	CP	'@'		; 
	CALL	Z,SAVEHLBC2DE	; 
	POP	HL		; 
	LD	A,(HL)		; 
	INC	HL		; 
	CP	0FFH		; 
	JR	NZ,LD947	; 
	JP	JPCOLDBOOT	; 
				;
				; 
CURFCB:				; ### This is not entirely sure <-
	DW	0		; 

	page
;
;
MOVECONF:			; 
	LD	C,0		; 
	LD	HL,IFLOPCONF	; 
	LD	DE,DR0		; 
NEXTCONF:			; 
	LD	A,(HL)		; 
	CP	0FFH		; 
	jr	Z,DONECONF	; 
	LD	(DE),A		; 
	INC	C		; 
	INC	DE		; 
	INC	HL		; 
	jr	NEXTCONF	; 
DONECONF:			; 
	LD	A,C		; 
	DEC	A		; 
	LD	(DRNO),A	; 
	LD	A,2		; 
	LD	(MAXFLOPPY),A	; 
	LD	HL,LD541	; 
	LD	DE,LF336	; 
	LD	BC,3		; 
	LDIR			; 
	RET			; 
;
;
GETDPBADDR:			; 
	LD	DE,DPBSIZE	; 
	LD	B,8		; 
	LD	A,(HL)		; 
	AND	0F8H		; 
	LD	HL,DPBLK0	; 
	OR	A		; 
	JR	Z,DPBOK		; 
SKIPDPBS:			; 
	ADD	HL,DE		; 
	SUB	B		; 
	JR	NZ,SKIPDPBS	; 
DPBOK:				; 
	LD	DE,(CURFCB)	; 
	EX	DE,HL		; 
	LD	(HL),E		; 
	INC	HL		; 
	LD	(HL),D		; 
	LD	DE,DPBSIZE	; 
	ADD	HL,DE		; 
	LD	(CURFCB),HL	; 
	RET			; 
;
;
; BC,(DE):= HL+BC ;  (HL:= HL+OLDBC+2) ??

SAVEHLBC2DE:			; 
	ADD	HL,BC		; 
	EX	DE,HL		; 
	LD	(HL),E		; 
	INC	HL		; 
	LD	(HL),D		; 
	INC	HL		; 
	EX	DE,HL		; 
	LD	B,H		; 
	LD	C,L		; 
	RET			; 

	if	usephase
	if	$ ge biosbase
	>> INIT part overlaps residential bios <<
	endif
	endif

	page