MAX2769 SPI interface not connected to GPIO with access to SPI module on STM32f4xx

[kwilsonpdx]

This is a duplicate of avionics-cad repo. Issue 2.
(Perhaps it should only have been entered here.)

I have added mod wire proposals to the schematic for the v2 board.

[andrewgreenberg]

We very carefully thought about this. As far as I remember:

1. We absolutely need a SPI bus for the serial data output stream.

2. I believe there are no other SPI busses available on that chip. Also, I'm not sure the "two wire interface" as they call it is SPI, it's more like I2C, but in any case, it's a write once kind of thing, and very slow, so we thought we'd bit bang it.

I'll go take a look at your proposals.

[andrewgreenberg]

AARRRGHHH K is annoyingly correct. SPI2 is available and we should thus use it. How did we miss this? I approve of the mod wires for SPI2_MOSI and SPI2_SCLK.

K, I think there's no reason to use SPI2_NSS because that's really just a GPIO pin, and we can continue to just use PE12. I don't believe the NSS does anything when the SPI peripheral is in master mode. Can you please confirm this?

[JustRob83]

I recommend not bothering with the NSS pin. On RTx, I happen to be using the pin designated NSS (external ADCs on SPI1), but I'm neither configuring it in its SPI Alternate Function, nor am I calling the SPISelect() or SPIUnselect() functions, but rather just setting/clearing this pin.Rob

On Fri, Jun 13, 2014 at 9:38 AM, Andrew Greenberg
[email protected] wrote:

AARRRGHHH K is annoyingly correct. SPI2 is available and we should thus use it. How did we miss this? I approve of the mod wires for SPI2_MOSI and SPI2_SCLK.

K, I think there's no reason to use SPI2_NSS because that's really just a GPIO pin, and we can continue to just use PE12. I don't believe the NSS does anything when the SPI peripheral is in master mode. Can you please confirm this?

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#4 (comment)

[ThirteenFish]

The SPI peripheral has some trivial master mode NSS management (see ref. man. p860), but ChibiOS opts not to use this feature and instead manage NSS through it's GPIO driver. The implementation of SPISelect is literally palClearPad(). Furthermore the SPIConfig struct lets you set any pin to be managed by the SPISelect function.

I too think it's fine to leave it alone.

[kwilsonpdx]

I have removed the modwire proposal from the v2 schematic for SPI2_NSS. We can use the chip select connection (PE12) in GPIO mode.