This document is a collection of links to documentation on various vendors' micro-architecture.
BPi-F3 Datasheet: Spacemit-K1 Datasheet:
To purchase: AliExpress, Amazon
"SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP". AnandTech. https://www.anandtech.com/show/15036/sifive-announces-first-riscv-ooo-cpu-core-the-u8series-processor-ip/2
"Incredibly Scalable High-Performance RISC-V Core IP". https://www.sifive.com/blog/incredibly-scalable-high-performance-risc-v-core-ip -- Minimal information, but the point about being able to issue int ops to fp-pipe is interesting and not covered in the anandtech writeup.
WikiChip. https://en.wikichip.org/wiki/sifive -- Some information on the various N-series cores, unclear sourcing and quality.
"SiFive U74 Core Complex Manual". https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf
"Avispado: A RISC-V core supporting the RISC-V vector instruction set by Roger Espasa", https://www.youtube.com/watch?v=NQuE2j0B_aA
"Building AI Silicon: Ascalon RiscV Processor". https://www.youtube.com/watch?v=KOHQQyAKY14&t=494s
"A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI". https://fuse.wikichip.org/news/4911/a-look-at-the-et-soc-1-esperantos-massively-multi-core-risc-v-approach-to-ai/
"ESPERANTO MAXES OUT RISC-V". Linley Group, Microprocessor Report. December 10, 2018. https://www.esperanto.ai/wp-content/uploads/2018/12/Esperanto-Maxes-Out-RISC-V.pdf
"T-head RVB-ICE Development Board,Dual-core XuanTie C910 RISC-V 64GC ,1.2GHz, Support Android/Debian System" https://www.aliexpress.com/item/3256803209663707.html?gatewayAdapt=4itemAdapt. Sales page, but scroll down to description section for a reasonable detailed description.
"T-Head ISA extension specification" https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf. Defines the custom extensions shipped by T-Head.
"VTx-family custom instructions: Custom ISA extensions for Ventana Micro Systems RISC-V cores" https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
Reddit post: https://www.reddit.com/r/RISCV/comments/uf0kc5/riscv_optimization_guides_resource_request/i6qp5p7/. Has some good commentary; was also source of two of the better links above.