From 7b37ee0ee331b536579497fc585b4b6c1a989ed4 Mon Sep 17 00:00:00 2001
From: Kirill Mikhailov <konnor1980@yandex.ru>
Date: Wed, 18 Dec 2024 10:24:46 +0100
Subject: [PATCH] dumb

dumb2
---
 esp-hal/src/i2c/master/mod.rs | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/esp-hal/src/i2c/master/mod.rs b/esp-hal/src/i2c/master/mod.rs
index c0eaa8d9b3..da3a2136fb 100644
--- a/esp-hal/src/i2c/master/mod.rs
+++ b/esp-hal/src/i2c/master/mod.rs
@@ -895,7 +895,7 @@ fn configure_clock(
             w.scl_wait_high_period().bits(
                 scl_wait_high_period
                     .try_into()
-                    .map_err(|_| Error::InvalidFrequency)?,
+                    .map_err(|_| ConfigError::InvalidFrequency)?,
             );
             w.scl_high_period().bits(scl_high_period as u16)
         });
@@ -931,7 +931,7 @@ fn configure_clock(
                 if let Some(timeout_value) = timeout {
                     register_block.to().write(|w| w.time_out().bits(timeout_value));
                 } else {
-                    return Err(Error::InvalidTimeout);
+                    return Err(ConfigError::InvalidTimeout);
                 }
             } else {
                 register_block
@@ -1147,6 +1147,8 @@ impl Driver<'_> {
             scl_stop_hold_time,
             timeout,
         )?;
+
+        Ok(())
     }
 
     #[cfg(esp32s2)]
@@ -1202,6 +1204,8 @@ impl Driver<'_> {
             scl_stop_hold_time,
             timeout.map(|to_bus| (to_bus * 2 * half_cycle).min(0xFF_FFFF)),
         )?;
+
+        Ok(())
     }
 
     #[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
@@ -1277,6 +1281,8 @@ impl Driver<'_> {
                 raw.min(0x1F)
             }),
         )?;
+
+        Ok(())
     }
 
     #[cfg(any(esp32, esp32s2))]