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Possible hazard in combinational logic of control unit #25

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rjlv2 opened this issue May 21, 2019 · 1 comment
Open

Possible hazard in combinational logic of control unit #25

rjlv2 opened this issue May 21, 2019 · 1 comment
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rjlv2 commented May 21, 2019 •
edited by harrysarson
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Specifically ALUSrc control signal. Somehow it accepts (~6).(~4) + (~6).(~5).(4) but not (~6).(~4) + (~6).~(5), though they are the same in boolean logic.
@rjlv2 rjlv2 self-assigned this May 21, 2019
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rjlv2 commented May 21, 2019

This issue seems to be only limited to the branch of Sail used in uncertainty propagation. Works ok on the normal RV32I processor.

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