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asm_avr.inc
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asm_avr.inc
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#define DEC_20 19
#define DEC_24 23
#define DEC_28 27
#define DEC_32 31
#define DEC(N) uECC_CONCAT(DEC_, N)
#define REPEAT_1(stuff) stuff
#define REPEAT_2(stuff) REPEAT_1(stuff) stuff
#define REPEAT_3(stuff) REPEAT_2(stuff) stuff
#define REPEAT_4(stuff) REPEAT_3(stuff) stuff
#define REPEAT_5(stuff) REPEAT_4(stuff) stuff
#define REPEAT_6(stuff) REPEAT_5(stuff) stuff
#define REPEAT_7(stuff) REPEAT_6(stuff) stuff
#define REPEAT_8(stuff) REPEAT_7(stuff) stuff
#define REPEAT_9(stuff) REPEAT_8(stuff) stuff
#define REPEAT_10(stuff) REPEAT_9(stuff) stuff
#define REPEAT_11(stuff) REPEAT_10(stuff) stuff
#define REPEAT_12(stuff) REPEAT_11(stuff) stuff
#define REPEAT_13(stuff) REPEAT_12(stuff) stuff
#define REPEAT_14(stuff) REPEAT_13(stuff) stuff
#define REPEAT_15(stuff) REPEAT_14(stuff) stuff
#define REPEAT_16(stuff) REPEAT_15(stuff) stuff
#define REPEAT_17(stuff) REPEAT_16(stuff) stuff
#define REPEAT_18(stuff) REPEAT_17(stuff) stuff
#define REPEAT_19(stuff) REPEAT_18(stuff) stuff
#define REPEAT_20(stuff) REPEAT_19(stuff) stuff
#define REPEAT_21(stuff) REPEAT_20(stuff) stuff
#define REPEAT_22(stuff) REPEAT_21(stuff) stuff
#define REPEAT_23(stuff) REPEAT_22(stuff) stuff
#define REPEAT_24(stuff) REPEAT_23(stuff) stuff
#define REPEAT_25(stuff) REPEAT_24(stuff) stuff
#define REPEAT_26(stuff) REPEAT_25(stuff) stuff
#define REPEAT_27(stuff) REPEAT_26(stuff) stuff
#define REPEAT_28(stuff) REPEAT_27(stuff) stuff
#define REPEAT_29(stuff) REPEAT_28(stuff) stuff
#define REPEAT_30(stuff) REPEAT_29(stuff) stuff
#define REPEAT_31(stuff) REPEAT_30(stuff) stuff
#define REPEAT_32(stuff) REPEAT_31(stuff) stuff
#define REPEAT(N, stuff) uECC_CONCAT(REPEAT_, N)(stuff)
#define STR2(thing) #thing
#define STR(thing) STR2(thing)
#if (uECC_ASM == uECC_asm_fast)
static void vli_clear(uint8_t *vli) {
__asm__ volatile (
REPEAT(uECC_BYTES,
"st %a[ptr]+, r1 \n\t")
: [ptr] "+e" (vli)
:
: "r0", "cc", "memory"
);
}
#define asm_clear 1
static void vli_set(uint8_t *dest, const uint8_t *src) {
__asm__ volatile (
REPEAT(uECC_BYTES,
"ld r0, %a[sptr]+ \n\t"
"st %a[dptr]+, r0 \n\t")
: [dptr] "+e" (dest), [sptr] "+e" (src)
:
: "r0", "cc", "memory"
);
}
#define asm_set 1
static void vli_rshift1(uint8_t *vli) {
__asm__ volatile (
"adiw r30, " STR(uECC_BYTES) " \n\t"
"ld r0, -z \n\t" /* Load byte. */
"lsr r0 \n\t" /* Shift. */
"st z, r0 \n\t" /* Store the first result byte. */
/* Now we just do the remaining bytes with the carry bit (using ROR) */
REPEAT(DEC(uECC_BYTES),
"ld r0, -z \n\t"
"ror r0 \n\t"
"st z, r0 \n\t")
: "+z" (vli)
:
: "r0", "cc", "memory"
);
}
#define asm_rshift1 1
/* Computes result = left + right, returning carry. Can modify in place. */
static uint8_t vli_add(uint8_t *result, const uint8_t *left, const uint8_t *right) {
uint8_t carry = 0;
uint8_t left_byte;
uint8_t right_byte;
__asm__ volatile (
"ld %[left], x+ \n\t" /* Load left byte. */
"ld %[right], y+ \n\t" /* Load right byte. */
"add %[left], %[right] \n\t" /* Add the first byte. */
"st z+, %[left] \n\t" /* Store the first result byte. */
/* Now we just do the remaining bytes with the carry bit (using ADC) */
REPEAT(DEC(uECC_BYTES),
"ld %[left], x+ \n\t"
"ld %[right], y+ \n\t"
"adc %[left], %[right] \n\t"
"st z+, %[left] \n\t")
"adc %[carry], %[carry] \n\t" /* Store carry bit. */
"sbiw r28, " STR(uECC_BYTES) " \n\t" /* Restore Y */
: "+z" (result), "+x" (left),
[carry] "+r" (carry), [left] "=&r" (left_byte), [right] "=&r" (right_byte)
: "y" (right)
: "cc", "memory"
);
return carry;
}
#define asm_add 1
/* Computes result = left - right, returning borrow. Can modify in place. */
static uint8_t vli_sub(uint8_t *result, const uint8_t *left, const uint8_t *right) {
uint8_t borrow = 0;
uint8_t left_byte;
uint8_t right_byte;
__asm__ volatile (
"ld %[left], x+ \n\t" /* Load left byte. */
"ld %[right], y+ \n\t" /* Load right byte. */
"sub %[left], %[right] \n\t" /* Subtract the first byte. */
"st z+, %[left] \n\t" /* Store the first result byte. */
/* Now we just do the remaining bytes with the carry bit (using SBC) */
REPEAT(DEC(uECC_BYTES),
"ld %[left], x+ \n\t"
"ld %[right], y+ \n\t"
"sbc %[left], %[right] \n\t"
"st z+, %[left] \n\t")
"adc %[borrow], %[borrow] \n\t" /* Store carry bit in borrow. */
"sbiw r28, " STR(uECC_BYTES) " \n\t" /* Restore Y */
: "+z" (result), "+x" (left),
[borrow] "+r" (borrow), [left] "=&r" (left_byte), [right] "=&r" (right_byte)
: "y" (right)
: "cc", "memory"
);
return borrow;
}
#define asm_sub 1
#if (uECC_BYTES == 20)
__attribute((noinline))
static void vli_mult(uint8_t *result, const uint8_t *left, const uint8_t *right) {
__asm__ volatile (
"adiw r30, 10 \n\t"
"adiw r28, 10 \n\t"
"ld r2, x+ \n\t"
"ld r3, x+ \n\t"
"ld r4, x+ \n\t"
"ld r5, x+ \n\t"
"ld r6, x+ \n\t"
"ld r7, x+ \n\t"
"ld r8, x+ \n\t"
"ld r9, x+ \n\t"
"ld r10, x+ \n\t"
"ld r11, x+ \n\t"
"ld r12, y+ \n\t"
"ld r13, y+ \n\t"
"ld r14, y+ \n\t"
"ld r15, y+ \n\t"
"ld r16, y+ \n\t"
"ld r17, y+ \n\t"
"ld r18, y+ \n\t"
"ld r19, y+ \n\t"
"ld r20, y+ \n\t"
"ld r21, y+ \n\t"
"ldi r25, 0 \n\t"
"ldi r23, 0 \n\t"
"mul r2, r12 \n\t"
"st z+, r0 \n\t"
"mov r22, r1 \n\t"
"ldi r24, 0 \n\t"
"mul r2, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"mul r3, r12 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r2, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r3, r13 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r4, r12 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r2, r15 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r3, r14 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r4, r13 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r5, r12 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ldi r24, 0 \n\t"
"mul r2, r16 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r3, r15 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r4, r14 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r5, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r6, r12 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r2, r17 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r3, r16 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r4, r15 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r5, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r6, r13 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r7, r12 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r2, r18 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r3, r17 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r4, r16 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r5, r15 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r6, r14 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r7, r13 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r8, r12 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ldi r24, 0 \n\t"
"mul r2, r19 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r3, r18 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r4, r17 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r5, r16 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r6, r15 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r7, r14 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r8, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r9, r12 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r2, r20 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r3, r19 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r4, r18 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r5, r17 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r6, r16 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r7, r15 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r8, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r9, r13 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r10, r12 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r2, r21 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r3, r20 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r4, r19 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r5, r18 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r6, r17 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r7, r16 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r8, r15 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r9, r14 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r10, r13 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r11, r12 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ldi r24, 0 \n\t"
"mul r3, r21 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r4, r20 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r5, r19 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r6, r18 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r7, r17 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r8, r16 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r9, r15 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r10, r14 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r11, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r4, r21 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r5, r20 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r6, r19 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r7, r18 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r8, r17 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r9, r16 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r10, r15 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r11, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r5, r21 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r6, r20 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r7, r19 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r8, r18 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r9, r17 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r10, r16 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r11, r15 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ldi r24, 0 \n\t"
"mul r6, r21 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r7, r20 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r8, r19 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r9, r18 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r10, r17 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r11, r16 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r7, r21 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r8, r20 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r9, r19 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r10, r18 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r11, r17 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r8, r21 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r9, r20 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r10, r19 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r11, r18 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ldi r24, 0 \n\t"
"mul r9, r21 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r10, r20 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r11, r19 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r10, r21 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r11, r20 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"mul r11, r21 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"st z+, r24 \n\t"
"st z+, r22 \n\t"
"sbiw r30, 30 \n\t"
"sbiw r28, 20 \n\t"
"ld r12, y+ \n\t"
"ld r13, y+ \n\t"
"ld r14, y+ \n\t"
"ld r15, y+ \n\t"
"ld r16, y+ \n\t"
"ld r17, y+ \n\t"
"ld r18, y+ \n\t"
"ld r19, y+ \n\t"
"ld r20, y+ \n\t"
"ld r21, y+ \n\t"
"ldi r23, 0 \n\t"
"mul r2, r12 \n\t"
"st z+, r0 \n\t"
"mov r22, r1 \n\t"
"ldi r24, 0 \n\t"
"mul r2, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"mul r3, r12 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r2, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r3, r13 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r4, r12 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r2, r15 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r3, r14 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r4, r13 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r5, r12 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ldi r24, 0 \n\t"
"mul r2, r16 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r3, r15 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r4, r14 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r5, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r6, r12 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r2, r17 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r3, r16 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r4, r15 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r5, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r6, r13 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r7, r12 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r2, r18 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r3, r17 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r4, r16 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r5, r15 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r6, r14 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r7, r13 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r8, r12 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ldi r24, 0 \n\t"
"mul r2, r19 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r3, r18 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r4, r17 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r5, r16 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r6, r15 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r7, r14 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r8, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r9, r12 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ldi r22, 0 \n\t"
"mul r2, r20 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r3, r19 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r4, r18 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r5, r17 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r6, r16 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r7, r15 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r8, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r9, r13 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r10, r12 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ldi r23, 0 \n\t"
"mul r2, r21 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r3, r20 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r4, r19 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r5, r18 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r6, r17 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r7, r16 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r8, r15 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r9, r14 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r10, r13 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r11, r12 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"st z+, r24 \n\t"
"ld r2, x+ \n\t"
"ldi r24, 0 \n\t"
"mul r3, r21 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r4, r20 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r5, r19 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r6, r18 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r7, r17 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r8, r16 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r9, r15 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r10, r14 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r11, r13 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"mul r2, r12 \n\t"
"add r22, r0 \n\t"
"adc r23, r1 \n\t"
"adc r24, r25 \n\t"
"ld r0, z \n\t"
"add r22, r0 \n\t"
"adc r23, r25 \n\t"
"adc r24, r25 \n\t"
"st z+, r22 \n\t"
"ld r3, x+ \n\t"
"ldi r22, 0 \n\t"
"mul r4, r21 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r5, r20 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r6, r19 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r7, r18 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r8, r17 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r9, r16 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r10, r15 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r11, r14 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r2, r13 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"mul r3, r12 \n\t"
"add r23, r0 \n\t"
"adc r24, r1 \n\t"
"adc r22, r25 \n\t"
"ld r0, z \n\t"
"add r23, r0 \n\t"
"adc r24, r25 \n\t"
"adc r22, r25 \n\t"
"st z+, r23 \n\t"
"ld r4, x+ \n\t"
"ldi r23, 0 \n\t"
"mul r5, r21 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r6, r20 \n\t"
"add r24, r0 \n\t"
"adc r22, r1 \n\t"
"adc r23, r25 \n\t"
"mul r7, r19 \n\t"
"add r24, r0 \n\t"