From 6e844ff6bef12379d2278fd188401807f85fbf8f Mon Sep 17 00:00:00 2001 From: rojer Date: Sat, 15 Aug 2015 11:55:31 +0100 Subject: [PATCH 01/10] Compile newlib with -DMALLOC_PROVIDED ESP provides its own malloc, so whenever newlib tries to use its own implementation, bad things happen. This way, *alloc symbols remain external in libc.a and can be redirected to the ESP versions. Right now this is left to the user. --- 9000-malloc-provided.patch | 10 ++++++++++ Makefile | 1 + 2 files changed, 11 insertions(+) create mode 100644 9000-malloc-provided.patch diff --git a/9000-malloc-provided.patch b/9000-malloc-provided.patch new file mode 100644 index 000000000..35e6b4933 --- /dev/null +++ b/9000-malloc-provided.patch @@ -0,0 +1,10 @@ +--- a/newlib/configure.host 2015-08-14 16:31:23.033541019 +0000 ++++ b/newlib/configure.host 2015-08-14 16:31:28.757594282 +0000 +@@ -286,6 +286,7 @@ + libm_machine_dir=xtensa + machine_dir=xtensa + newlib_cflags="${newlib_cflags} -mlongcalls" ++ newlib_cflags="${newlib_cflags} -DMALLOC_PROVIDED" + newlib_cflags="${newlib_cflags} -DREENTRANT_SYSCALLS_PROVIDED" + ;; + z8k) diff --git a/Makefile b/Makefile index d3ccaa756..ccfd46329 100644 --- a/Makefile +++ b/Makefile @@ -271,6 +271,7 @@ _toolchain: crosstool-NG: crosstool-NG/ct-ng crosstool-NG/ct-ng: crosstool-NG/bootstrap + cp 9000-malloc-provided.patch crosstool-NG/local-patches/newlib/2.0.0 make -C crosstool-NG -f ../Makefile _ct-ng _ct-ng: From 211928c9e5ea516f305268c3749158332d66f153 Mon Sep 17 00:00:00 2001 From: Alexander Alashkin Date: Thu, 5 Nov 2015 21:48:40 +0200 Subject: [PATCH 02/10] Update esptools --- esptool | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool b/esptool index 80a34f5e5..765cf23f8 160000 --- a/esptool +++ b/esptool @@ -1 +1 @@ -Subproject commit 80a34f5e5d40049f19dd2a84b6c1e529e83edc77 +Subproject commit 765cf23f878a522db6bc34854d4a14bbae470ff6 From 2c5a7fb8460215b5a26efe2acb10480f1b4c7803 Mon Sep 17 00:00:00 2001 From: rojer Date: Mon, 9 Nov 2015 20:03:17 +0000 Subject: [PATCH 03/10] SDK 1.4.1 (pre_5) --- Makefile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index dc281eedc..e408e34b6 100644 --- a/Makefile +++ b/Makefile @@ -1,12 +1,14 @@ TOP = $(PWD) TOOLCHAIN = $(TOP)/xtensa-lx106-elf -VENDOR_SDK = 1.4.0 +VENDOR_SDK = 1.4.1 UNZIP = unzip -q -o VENDOR_SDK_ZIP = $(VENDOR_SDK_ZIP_$(VENDOR_SDK)) VENDOR_SDK_DIR = $(VENDOR_SDK_DIR_$(VENDOR_SDK)) +VENDOR_SDK_ZIP_1.4.1 = esp_iot_sdk_v1.4.1_pre5_15_10_27.zip +VENDOR_SDK_DIR_1.4.1 = esp_iot_sdk_v1.4.1_pre5 VENDOR_SDK_ZIP_1.4.0 = esp_iot_sdk_v1.4.0_15_09_18.zip VENDOR_SDK_DIR_1.4.0 = esp_iot_sdk_v1.4.0 VENDOR_SDK_ZIP_1.3.0 = esp_iot_sdk_v1.3.0_15_08_08.zip @@ -73,6 +75,10 @@ libcirom: $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/lib/libcirom.a sdk_patch: .sdk_patch_$(VENDOR_SDK) +.sdk_patch_1.4.1: + patch -N -d $(VENDOR_SDK_DIR_1.4.1) -p1 < c_types-c99.patch + @touch $@ + .sdk_patch_1.4.0: patch -N -d $(VENDOR_SDK_DIR_1.4.0) -p1 < c_types-c99.patch @touch $@ @@ -204,6 +210,9 @@ $(VENDOR_SDK_DIR)/.dir: $(VENDOR_SDK_ZIP) -mv License $(VENDOR_SDK_DIR) touch $@ +esp_iot_sdk_v1.4.1_pre5_15_10_27.zip: + wget --content-disposition "http://bbs.espressif.com/download/file.php?id=917" + esp_iot_sdk_v1.4.0_15_09_18.zip: wget --content-disposition "http://bbs.espressif.com/download/file.php?id=838" From 36a161a0010dac289d080074c9bd6499520f0ef9 Mon Sep 17 00:00:00 2001 From: rojer Date: Thu, 12 Nov 2015 14:12:32 +0000 Subject: [PATCH 04/10] Compile newlib with -ffunction_sections and -Os Move other lib patching to the Makefile --- 9000-malloc-provided.patch | 10 ------- 9000-newlib-flags.patch | 12 +++++++++ 9001-newlib-strcmp-literals.patch | 22 +++++++++++++++ Makefile | 45 ++++++++++++++++++++----------- 4 files changed, 64 insertions(+), 25 deletions(-) delete mode 100644 9000-malloc-provided.patch create mode 100644 9000-newlib-flags.patch create mode 100644 9001-newlib-strcmp-literals.patch diff --git a/9000-malloc-provided.patch b/9000-malloc-provided.patch deleted file mode 100644 index 35e6b4933..000000000 --- a/9000-malloc-provided.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/newlib/configure.host 2015-08-14 16:31:23.033541019 +0000 -+++ b/newlib/configure.host 2015-08-14 16:31:28.757594282 +0000 -@@ -286,6 +286,7 @@ - libm_machine_dir=xtensa - machine_dir=xtensa - newlib_cflags="${newlib_cflags} -mlongcalls" -+ newlib_cflags="${newlib_cflags} -DMALLOC_PROVIDED" - newlib_cflags="${newlib_cflags} -DREENTRANT_SYSCALLS_PROVIDED" - ;; - z8k) diff --git a/9000-newlib-flags.patch b/9000-newlib-flags.patch new file mode 100644 index 000000000..4120423d9 --- /dev/null +++ b/9000-newlib-flags.patch @@ -0,0 +1,12 @@ +--- a/newlib/configure.host 2015-11-12 14:04:48.064467034 +0000 ++++ b/newlib/configure.host 2015-11-12 14:07:45.645532708 +0000 +@@ -285,7 +285,8 @@ + xtensa) + libm_machine_dir=xtensa + machine_dir=xtensa +- newlib_cflags="${newlib_cflags} -mlongcalls" ++ newlib_cflags="${newlib_cflags} -mlongcalls -ffunction-sections -mtext-section-literals -Os" ++ newlib_cflags="${newlib_cflags} -DMALLOC_PROVIDED" + newlib_cflags="${newlib_cflags} -DREENTRANT_SYSCALLS_PROVIDED" + ;; + z8k) diff --git a/9001-newlib-strcmp-literals.patch b/9001-newlib-strcmp-literals.patch new file mode 100644 index 000000000..2a2299cf4 --- /dev/null +++ b/9001-newlib-strcmp-literals.patch @@ -0,0 +1,22 @@ +--- a/newlib/libc/machine/xtensa/strcmp.S 2015-11-12 16:23:00.623220071 +0000 ++++ b/newlib/libc/machine/xtensa/strcmp.S 2015-11-12 18:00:14.995375550 +0000 +@@ -26,6 +26,8 @@ + #define MASK4 0x40404040 + + ++ .align 4 ++ .literal_position + #if XCHAL_HAVE_L32R + .literal .Lmask0, MASK0 + .literal .Lmask1, MASK1 +@@ -33,10 +35,6 @@ + .literal .Lmask3, MASK3 + .literal .Lmask4, MASK4 + #endif /* XCHAL_HAVE_L32R */ +- +- .text +- .align 4 +- .literal_position + .global strcmp + .type strcmp, @function + strcmp: diff --git a/Makefile b/Makefile index e408e34b6..f6d50392e 100644 --- a/Makefile +++ b/Makefile @@ -44,9 +44,12 @@ VENDOR_SDK_ZIP_0.9.2 = esp_iot_sdk_v0.9.2_14_10_24.zip VENDOR_SDK_DIR_0.9.2 = esp_iot_sdk_v0.9.2 STANDALONE = y -.PHONY: crosstool-NG toolchain libhal libcirom sdk +.PHONY: crosstool-NG toolchain libhal sdk -all: esptool libcirom standalone sdk sdk_patch $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/usr/lib/libhal.a $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc +LIBHAL := $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/usr/lib/libhal.a +LIBGCC := $(TOOLCHAIN)/lib/gcc/xtensa-lx106-elf/4.8.2/libgcc.a + +all: esptool standalone sdk .sdk_patch $(LIBHAL) $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc @echo @echo "Xtensa toolchain is built, to use it:" @echo @@ -66,14 +69,14 @@ endif esptool: toolchain cp esptool/esptool.py $(TOOLCHAIN)/bin/ -$(TOOLCHAIN)/xtensa-lx106-elf/sysroot/lib/libcirom.a: $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/lib/libc.a $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc - @echo "Creating irom version of libc..." - $(TOOLCHAIN)/bin/xtensa-lx106-elf-objcopy --rename-section .text=.irom0.text \ - --rename-section .literal=.irom0.literal $(<) $(@); - -libcirom: $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/lib/libcirom.a - -sdk_patch: .sdk_patch_$(VENDOR_SDK) +.sdk_patch: .sdk_patch_$(VENDOR_SDK) $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc + for l in sdk/lib/lib*.a; do \ + $(TOOLCHAIN)/bin/xtensa-lx106-elf-objcopy \ + --rename-section .text=.fast.text \ + --rename-section .irom0.text=.text \ + $$l; \ + done + @touch $@ .sdk_patch_1.4.1: patch -N -d $(VENDOR_SDK_DIR_1.4.1) -p1 < c_types-c99.patch @@ -166,7 +169,7 @@ empty_user_rf_pre_init.o: empty_user_rf_pre_init.c $(TOOLCHAIN)/bin/xtensa-lx106 cp FRM_ERR_PATCH/*.a $(VENDOR_SDK_DIR)/lib/ @touch $@ -standalone: sdk sdk_patch toolchain +standalone: sdk .sdk_patch toolchain ifeq ($(STANDALONE),y) @echo "Installing vendor SDK headers into toolchain sysroot" @cp -Rf sdk/include/* $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/usr/include/ @@ -261,11 +264,17 @@ esp_iot_sdk_v0.9.3_14_11_21.zip: esp_iot_sdk_v0.9.2_14_10_24.zip: wget --content-disposition "http://bbs.espressif.com/download/file.php?id=9" -libhal: $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/usr/lib/libhal.a +libhal: $(LIBHAL) .patch_libhal -$(TOOLCHAIN)/xtensa-lx106-elf/sysroot/usr/lib/libhal.a: $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc +$(LIBHAL): $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc make -C lx106-hal -f ../Makefile _libhal +.patch_libhal: $(LIBHAL) + $(TOOLCHAIN)/bin/xtensa-lx106-elf-objcopy \ + --rename-section .text=.fast.text \ + $(LIBHAL) + @touch $@ + _libhal: autoreconf -i PATH=$(TOOLCHAIN)/bin:$(PATH) ./configure --host=xtensa-lx106-elf --prefix=$(TOOLCHAIN)/xtensa-lx106-elf/sysroot/usr @@ -273,11 +282,17 @@ _libhal: PATH=$(TOOLCHAIN)/bin:$(PATH) make install -toolchain: $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc +toolchain: $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc .patch_libgcc $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc: crosstool-NG/ct-ng make -C crosstool-NG -f ../Makefile _toolchain +.patch_libgcc: $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc + $(TOOLCHAIN)/bin/xtensa-lx106-elf-objcopy \ + --rename-section .text=.fast.text \ + $(LIBGCC) + @touch $@ + _toolchain: ./ct-ng xtensa-lx106-elf sed -r -i.org s%CT_PREFIX_DIR=.*%CT_PREFIX_DIR="$(TOOLCHAIN)"% .config @@ -289,7 +304,7 @@ _toolchain: crosstool-NG: crosstool-NG/ct-ng crosstool-NG/ct-ng: crosstool-NG/bootstrap - cp 9000-malloc-provided.patch crosstool-NG/local-patches/newlib/2.0.0 + cp *-newlib-*.patch crosstool-NG/local-patches/newlib/2.0.0 make -C crosstool-NG -f ../Makefile _ct-ng _ct-ng: From 2c41b375c6d0fac636de1adc322a99ed466ea20e Mon Sep 17 00:00:00 2001 From: rojer Date: Mon, 30 Nov 2015 10:25:23 +0000 Subject: [PATCH 05/10] SDK 1.5.0 and GDB 7.5.1 patches from Sysprogs --- 0000-gdb-7.5.1-sysprogs.patch | 30286 ++++++++++++++++++++++++++++++++ Makefile | 13 +- 2 files changed, 30298 insertions(+), 1 deletion(-) create mode 100644 0000-gdb-7.5.1-sysprogs.patch diff --git a/0000-gdb-7.5.1-sysprogs.patch b/0000-gdb-7.5.1-sysprogs.patch new file mode 100644 index 000000000..e25660914 --- /dev/null +++ b/0000-gdb-7.5.1-sysprogs.patch @@ -0,0 +1,30286 @@ +diff -urN gdb-7.5.1-orig/bfd/xtensa-modules.c gdb-7.5.1/bfd/xtensa-modules.c +--- gdb-7.5.1-orig/bfd/xtensa-modules.c 2010-05-28 11:10:45.000000000 -0700 ++++ gdb-7.5.1/bfd/xtensa-modules.c 2015-08-23 19:30:39.181635000 -0700 +@@ -1,22 +1,25 @@ + /* Xtensa configuration-specific ISA information. +- Copyright 2003, 2004, 2005 Free Software Foundation, Inc. + +- This file is part of BFD, the Binary File Descriptor library. ++ Copyright (c) 2003-2010 Tensilica Inc. + +- This program is free software; you can redistribute it and/or +- modify it under the terms of the GNU General Public License as +- published by the Free Software Foundation; either version 2 of the +- License, or (at your option) any later version. +- +- This program is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program; if not, write to the Free Software +- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +- 02110-1301, USA. */ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + #include "ansidecl.h" + #include +@@ -26,17 +29,6 @@ + /* Sysregs. */ + + static xtensa_sysreg_internal sysregs[] = { +- { "LBEG", 0, 0 }, +- { "LEND", 1, 0 }, +- { "LCOUNT", 2, 0 }, +- { "BR", 4, 0 }, +- { "ACCLO", 16, 0 }, +- { "ACCHI", 17, 0 }, +- { "M0", 32, 0 }, +- { "M1", 33, 0 }, +- { "M2", 34, 0 }, +- { "M3", 35, 0 }, +- { "PTEVADDR", 83, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, +@@ -47,254 +39,112 @@ + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, +- { "CCOMPARE1", 241, 0 }, +- { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, +- { "EPC4", 180, 0 }, +- { "EPC5", 181, 0 }, +- { "EPC6", 182, 0 }, +- { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, +- { "EXCSAVE4", 212, 0 }, +- { "EXCSAVE5", 213, 0 }, +- { "EXCSAVE6", 214, 0 }, +- { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, +- { "EPS4", 196, 0 }, +- { "EPS5", 197, 0 }, +- { "EPS6", 198, 0 }, +- { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, +- { "WINDOWBASE", 72, 0 }, +- { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, +- { "MISC0", 244, 0 }, +- { "MISC1", 245, 0 }, +- { "MISC2", 246, 0 }, +- { "MISC3", 247, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, +- { "DBREAKA1", 145, 0 }, +- { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, +- { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, +- { "DEBUGCAUSE", 233, 0 }, +- { "RASID", 90, 0 }, +- { "ITLBCFG", 91, 0 }, +- { "DTLBCFG", 92, 0 }, +- { "CPENABLE", 224, 0 }, +- { "SCOMPARE1", 12, 0 }, +- { "THREADPTR", 231, 1 }, +- { "FCR", 232, 1 }, +- { "FSR", 233, 1 } ++ { "DEBUGCAUSE", 233, 0 } + }; + +-#define NUM_SYSREGS 74 +-#define MAX_SPECIAL_REG 247 +-#define MAX_USER_REG 233 ++#define NUM_SYSREGS 32 ++#define MAX_SPECIAL_REG 240 ++#define MAX_USER_REG 0 + + + /* Processor states. */ + + static xtensa_state_internal states[] = { +- { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, +- { "INTERRUPT", 32, 0 }, ++ { "INTERRUPT", 15, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, +- { "VECBASE", 22, 0 }, ++ { "VECBASE", 25, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, +- { "EPC4", 32, 0 }, +- { "EPC5", 32, 0 }, +- { "EPC6", 32, 0 }, +- { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, +- { "EXCSAVE4", 32, 0 }, +- { "EXCSAVE5", 32, 0 }, +- { "EXCSAVE6", 32, 0 }, +- { "EXCSAVE7", 32, 0 }, +- { "EPS2", 15, 0 }, +- { "EPS3", 15, 0 }, +- { "EPS4", 15, 0 }, +- { "EPS5", 15, 0 }, +- { "EPS6", 15, 0 }, +- { "EPS7", 15, 0 }, ++ { "EPS2", 6, 0 }, ++ { "EPS3", 6, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, +- { "PSWOE", 1, 0 }, +- { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, +- { "WindowBase", 4, 0 }, +- { "WindowStart", 16, 0 }, +- { "PSCALLINC", 2, 0 }, +- { "PSOWB", 4, 0 }, +- { "LBEG", 32, 0 }, +- { "LEND", 32, 0 }, + { "SAR", 6, 0 }, +- { "THREADPTR", 32, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, +- { "MISC0", 32, 0 }, +- { "MISC1", 32, 0 }, +- { "MISC2", 32, 0 }, +- { "MISC3", 32, 0 }, +- { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, +- { "INTENABLE", 32, 0 }, ++ { "INTENABLE", 15, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, +- { "DBREAKA1", 32, 0 }, +- { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, +- { "IBREAKA1", 32, 0 }, +- { "IBREAKENABLE", 2, 0 }, ++ { "IBREAKENABLE", 1, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, +- { "CCOMPARE0", 32, 0 }, +- { "CCOMPARE1", 32, 0 }, +- { "CCOMPARE2", 32, 0 }, +- { "ASID3", 8, 0 }, +- { "ASID2", 8, 0 }, +- { "ASID1", 8, 0 }, +- { "INSTPGSZID4", 2, 0 }, +- { "DATAPGSZID4", 2, 0 }, +- { "PTBASE", 10, 0 }, +- { "CPENABLE", 1, 0 }, +- { "SCOMPARE1", 32, 0 }, +- { "RoundMode", 2, 0 }, +- { "InvalidEnable", 1, 0 }, +- { "DivZeroEnable", 1, 0 }, +- { "OverflowEnable", 1, 0 }, +- { "UnderflowEnable", 1, 0 }, +- { "InexactEnable", 1, 0 }, +- { "InvalidFlag", 1, 0 }, +- { "DivZeroFlag", 1, 0 }, +- { "OverflowFlag", 1, 0 }, +- { "UnderflowFlag", 1, 0 }, +- { "InexactFlag", 1, 0 }, +- { "FPreserved20", 20, 0 }, +- { "FPreserved20a", 20, 0 }, +- { "FPreserved5", 5, 0 }, +- { "FPreserved7", 7, 0 } +-}; +- +-#define NUM_STATES 89 +- +-/* Macros for xtensa_state numbers (for use in iclasses because the +- state numbers are not available when the iclass table is generated). */ +- +-#define STATE_LCOUNT 0 +-#define STATE_PC 1 +-#define STATE_ICOUNT 2 +-#define STATE_DDR 3 +-#define STATE_INTERRUPT 4 +-#define STATE_CCOUNT 5 +-#define STATE_XTSYNC 6 +-#define STATE_VECBASE 7 +-#define STATE_EPC1 8 +-#define STATE_EPC2 9 +-#define STATE_EPC3 10 +-#define STATE_EPC4 11 +-#define STATE_EPC5 12 +-#define STATE_EPC6 13 +-#define STATE_EPC7 14 +-#define STATE_EXCSAVE1 15 +-#define STATE_EXCSAVE2 16 +-#define STATE_EXCSAVE3 17 +-#define STATE_EXCSAVE4 18 +-#define STATE_EXCSAVE5 19 +-#define STATE_EXCSAVE6 20 +-#define STATE_EXCSAVE7 21 +-#define STATE_EPS2 22 +-#define STATE_EPS3 23 +-#define STATE_EPS4 24 +-#define STATE_EPS5 25 +-#define STATE_EPS6 26 +-#define STATE_EPS7 27 +-#define STATE_EXCCAUSE 28 +-#define STATE_PSINTLEVEL 29 +-#define STATE_PSUM 30 +-#define STATE_PSWOE 31 +-#define STATE_PSRING 32 +-#define STATE_PSEXCM 33 +-#define STATE_DEPC 34 +-#define STATE_EXCVADDR 35 +-#define STATE_WindowBase 36 +-#define STATE_WindowStart 37 +-#define STATE_PSCALLINC 38 +-#define STATE_PSOWB 39 +-#define STATE_LBEG 40 +-#define STATE_LEND 41 +-#define STATE_SAR 42 +-#define STATE_THREADPTR 43 +-#define STATE_LITBADDR 44 +-#define STATE_LITBEN 45 +-#define STATE_MISC0 46 +-#define STATE_MISC1 47 +-#define STATE_MISC2 48 +-#define STATE_MISC3 49 +-#define STATE_ACC 50 +-#define STATE_InOCDMode 51 +-#define STATE_INTENABLE 52 +-#define STATE_DBREAKA0 53 +-#define STATE_DBREAKC0 54 +-#define STATE_DBREAKA1 55 +-#define STATE_DBREAKC1 56 +-#define STATE_IBREAKA0 57 +-#define STATE_IBREAKA1 58 +-#define STATE_IBREAKENABLE 59 +-#define STATE_ICOUNTLEVEL 60 +-#define STATE_DEBUGCAUSE 61 +-#define STATE_DBNUM 62 +-#define STATE_CCOMPARE0 63 +-#define STATE_CCOMPARE1 64 +-#define STATE_CCOMPARE2 65 +-#define STATE_ASID3 66 +-#define STATE_ASID2 67 +-#define STATE_ASID1 68 +-#define STATE_INSTPGSZID4 69 +-#define STATE_DATAPGSZID4 70 +-#define STATE_PTBASE 71 +-#define STATE_CPENABLE 72 +-#define STATE_SCOMPARE1 73 +-#define STATE_RoundMode 74 +-#define STATE_InvalidEnable 75 +-#define STATE_DivZeroEnable 76 +-#define STATE_OverflowEnable 77 +-#define STATE_UnderflowEnable 78 +-#define STATE_InexactEnable 79 +-#define STATE_InvalidFlag 80 +-#define STATE_DivZeroFlag 81 +-#define STATE_OverflowFlag 82 +-#define STATE_UnderflowFlag 83 +-#define STATE_InexactFlag 84 +-#define STATE_FPreserved20 85 +-#define STATE_FPreserved20a 86 +-#define STATE_FPreserved5 87 +-#define STATE_FPreserved7 88 ++ { "CCOMPARE0", 32, 0 } ++}; ++ ++#define NUM_STATES 34 ++ ++enum xtensa_state_id { ++ STATE_PC, ++ STATE_ICOUNT, ++ STATE_DDR, ++ STATE_INTERRUPT, ++ STATE_CCOUNT, ++ STATE_XTSYNC, ++ STATE_VECBASE, ++ STATE_EPC1, ++ STATE_EPC2, ++ STATE_EPC3, ++ STATE_EXCSAVE1, ++ STATE_EXCSAVE2, ++ STATE_EXCSAVE3, ++ STATE_EPS2, ++ STATE_EPS3, ++ STATE_EXCCAUSE, ++ STATE_PSINTLEVEL, ++ STATE_PSUM, ++ STATE_PSEXCM, ++ STATE_DEPC, ++ STATE_EXCVADDR, ++ STATE_SAR, ++ STATE_LITBADDR, ++ STATE_LITBEN, ++ STATE_InOCDMode, ++ STATE_INTENABLE, ++ STATE_DBREAKA0, ++ STATE_DBREAKC0, ++ STATE_IBREAKA0, ++ STATE_IBREAKENABLE, ++ STATE_ICOUNTLEVEL, ++ STATE_DEBUGCAUSE, ++ STATE_DBNUM, ++ STATE_CCOMPARE0 ++}; + + + /* Field definitions. */ +@@ -316,71 +166,71 @@ + } + + static unsigned +-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) ++Field_s_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + } + + static unsigned +-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) ++Field_r_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_op2_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; + } + + static void +-Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); + } + + static unsigned +-Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_op1_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; + } + + static void +-Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + } + + static unsigned +-Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) ++Field_op0_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +@@ -388,7 +238,7 @@ + } + + static void +-Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) ++Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +@@ -396,172 +246,166 @@ + } + + static unsigned +-Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) ++Field_m_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; + } + + static void +-Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) ++Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + } + + static unsigned +-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) ++Field_n_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; + } + + static void +-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + } + + static unsigned +-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) ++Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; + } + + static void +-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + } + + static unsigned +-Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) ++Field_sr_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) ++Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 24) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) ++Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); ++ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; + } + + static void +-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 20) >> 20; +- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + } + + static unsigned +-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) ++Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); ++ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; + } + + static void +-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 24) >> 24; +- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + } + + static unsigned +-Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); ++ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; + } + + static void +-Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 24) >> 24; +- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + } + + static unsigned +-Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; + } + + static void +-Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + } + + static unsigned +-Field_s_Slot_inst_get (const xtensa_insnbuf insn) ++Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; + } + + static void +-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + } + + static unsigned +-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) ++Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +@@ -581,7 +425,7 @@ + } + + static unsigned +-Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); +@@ -589,7 +433,7 @@ + } + + static void +-Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +@@ -597,105 +441,105 @@ + } + + static unsigned +-Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; + } + + static void +-Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + } + + static unsigned +-Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) ++Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; + } + + static void +-Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) ++Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + } + + static unsigned +-Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) ++Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; + } + + static void +-Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) ++Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 20) >> 20; ++ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); + } + + static unsigned +-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) ++Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; + } + + static void +-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +- tie_t = (val << 20) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + } + + static unsigned +-Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); +- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 24) >> 24; +- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +- tie_t = (val << 20) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + } + + static unsigned +-Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; + } + + static void +-Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 20) >> 20; +- insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); ++ tie_t = (val << 24) >> 24; ++ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); ++ tie_t = (val << 20) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + } + + static unsigned +@@ -715,247 +559,258 @@ + } + + static unsigned +-Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_offset_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); ++ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; + } + + static void +-Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 16) >> 16; +- insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); ++ tie_t = (val << 14) >> 14; ++ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); + } + + static unsigned +-Field_m_Slot_inst_get (const xtensa_insnbuf insn) ++Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); ++ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; + } + + static void +-Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc) | (tie_t << 2); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + } + + static unsigned +-Field_n_Slot_inst_get (const xtensa_insnbuf insn) ++Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; + } + + static void +-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + } + + static unsigned +-Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_sae_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); ++ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x3) | (tie_t << 0); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + } + + static unsigned +-Field_offset_Slot_inst_get (const xtensa_insnbuf insn) ++Field_sal_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); ++ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; + } + + static void +-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 14) >> 14; +- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + } + + static unsigned +-Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); ++ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 14) >> 14; +- insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); + } + + static unsigned +-Field_op0_Slot_inst_get (const xtensa_insnbuf insn) ++Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; + } + + static void +-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + } + + static unsigned +-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) ++Field_sas_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +-} +- +-static unsigned +-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} +- +-static void +-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 27) >> 31; ++ insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + } + + static unsigned +-Field_op1_Slot_inst_get (const xtensa_insnbuf insn) ++Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 24) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; + } + + static void +-Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_op2_Slot_inst_get (const xtensa_insnbuf insn) ++Field_st_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; + } + + static void +-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 24) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + } + + static unsigned +-Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; + } + + static void +-Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 24) >> 28; ++ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + } + + static unsigned +-Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; + } + + static void +-Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + } + + static unsigned +-Field_r_Slot_inst_get (const xtensa_insnbuf insn) ++Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +@@ -963,7 +818,7 @@ + } + + static void +-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +@@ -971,7 +826,7 @@ + } + + static unsigned +-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) ++Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +@@ -979,7 +834,7 @@ + } + + static void +-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +@@ -987,7 +842,7 @@ + } + + static unsigned +-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) ++Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +@@ -995,7 +850,7 @@ + } + + static void +-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +@@ -1003,19832 +858,6491 @@ + } + + static unsigned +-Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; + } + + static void +-Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + } + + static unsigned +-Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) ++Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) ++Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) ++Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; + } + + static void +-Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) ++Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + } + + static unsigned +-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) ++Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; + } + + static void +-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); ++ tie_t = (val << 30) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + } + + static unsigned +-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) ++Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); ++ tie_t = (val << 28) >> 28; ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + } + + static unsigned +-Field_sae_Slot_inst_get (const xtensa_insnbuf insn) ++Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; + } + + static void +-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + } + + static unsigned +-Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; + } + + static void +-Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); ++ tie_t = (val << 29) >> 29; ++ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + } + + static unsigned +-Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); ++ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; + } + + static void +-Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 27) >> 27; +- insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); ++ tie_t = (val << 31) >> 31; ++ insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + } + + static unsigned +-Field_sal_Slot_inst_get (const xtensa_insnbuf insn) ++Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ tie_t = (val << 26) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + } + + static unsigned +-Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ tie_t = (val << 26) >> 30; ++ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + } + + static unsigned +-Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); ++ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ tie_t = (val << 25) >> 29; ++ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + } + + static unsigned +-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) ++Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); ++ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); ++ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; + } + + static void +-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; + tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); ++ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ tie_t = (val << 25) >> 29; ++ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + } + + static unsigned +-Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); ++ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; + } + + static void +-Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); ++ tie_t = (val << 17) >> 17; ++ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); + } + + static unsigned +-Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) ++Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) + { + unsigned tie_t = 0; +- tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); ++ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; + } + + static void +-Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) ++Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) + { + uint32 tie_t; +- tie_t = (val << 27) >> 27; +- insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +-} +- +-static unsigned +-Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); +- return tie_t; ++ tie_t = (val << 14) >> 14; ++ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); + } + + static void +-Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) ++Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, ++ uint32 val ATTRIBUTE_UNUSED) + { +- uint32 tie_t; +- tie_t = (val << 27) >> 27; +- insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); ++ /* Do nothing. */ + } + + static unsigned +-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) ++Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); +- return tie_t; ++ return 0; + } + +-static void +-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +-} ++enum xtensa_field_id { ++ FIELD_t, ++ FIELD_bbi4, ++ FIELD_bbi, ++ FIELD_imm12, ++ FIELD_imm8, ++ FIELD_s, ++ FIELD_imm12b, ++ FIELD_imm16, ++ FIELD_m, ++ FIELD_n, ++ FIELD_offset, ++ FIELD_op0, ++ FIELD_op1, ++ FIELD_op2, ++ FIELD_r, ++ FIELD_sa4, ++ FIELD_sae4, ++ FIELD_sae, ++ FIELD_sal, ++ FIELD_sargt, ++ FIELD_sas4, ++ FIELD_sas, ++ FIELD_sr, ++ FIELD_st, ++ FIELD_thi3, ++ FIELD_imm4, ++ FIELD_i, ++ FIELD_imm6lo, ++ FIELD_imm6hi, ++ FIELD_imm7lo, ++ FIELD_imm7hi, ++ FIELD_z, ++ FIELD_imm6, ++ FIELD_imm7, ++ FIELD_xt_wbr15_imm, ++ FIELD_xt_wbr18_imm, ++ FIELD__ar0 ++}; + +-static unsigned +-Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- return tie_t; +-} ++ ++/* Functional units. */ + +-static void +-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static xtensa_funcUnit_internal funcUnits[] = { ++ ++}; ++ ++ ++/* Register files. */ ++ ++enum xtensa_regfile_id { ++ REGFILE_AR ++}; ++ ++static xtensa_regfile_internal regfiles[] = { ++ { "AR", "a", REGFILE_AR, 32, 16 } ++}; ++ ++ ++/* Interfaces. */ ++ ++static xtensa_interface_internal interfaces[] = { ++ ++}; ++ ++ ++/* Constant tables. */ ++ ++/* constant table ai4c */ ++static const unsigned CONST_TBL_ai4c_0[] = { ++ 0xffffffff, ++ 0x1, ++ 0x2, ++ 0x3, ++ 0x4, ++ 0x5, ++ 0x6, ++ 0x7, ++ 0x8, ++ 0x9, ++ 0xa, ++ 0xb, ++ 0xc, ++ 0xd, ++ 0xe, ++ 0xf, ++ 0 ++}; ++ ++/* constant table b4c */ ++static const unsigned CONST_TBL_b4c_0[] = { ++ 0xffffffff, ++ 0x1, ++ 0x2, ++ 0x3, ++ 0x4, ++ 0x5, ++ 0x6, ++ 0x7, ++ 0x8, ++ 0xa, ++ 0xc, ++ 0x10, ++ 0x20, ++ 0x40, ++ 0x80, ++ 0x100, ++ 0 ++}; ++ ++/* constant table b4cu */ ++static const unsigned CONST_TBL_b4cu_0[] = { ++ 0x8000, ++ 0x10000, ++ 0x2, ++ 0x3, ++ 0x4, ++ 0x5, ++ 0x6, ++ 0x7, ++ 0x8, ++ 0xa, ++ 0xc, ++ 0x10, ++ 0x20, ++ 0x40, ++ 0x80, ++ 0x100, ++ 0 ++}; ++ ++ ++/* Instruction operands. */ ++ ++static int ++Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); ++ return 0; + } + +-static unsigned +-Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++static int ++Operand_art_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); +- return tie_t; ++ int error; ++ error = (*valp & ~0xf) != 0; ++ return error; + } + +-static void +-Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x1) | (tie_t << 0); ++ return 0; + } + +-static unsigned +-Field_sr_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_ars_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- return tie_t; ++ int error; ++ error = (*valp & ~0xf) != 0; ++ return error; + } + +-static void +-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ return 0; + } + +-static unsigned +-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_arr_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- return tie_t; ++ int error; ++ error = (*valp & ~0xf) != 0; ++ return error; + } + +-static void +-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ return 0; + } + +-static unsigned +-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_ar0_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- return tie_t; ++ int error; ++ error = (*valp & ~0xf) != 0; ++ return error; + } + +-static void +-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_soffsetx4_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned soffsetx4_0, offset_0; ++ offset_0 = *valp & 0x3ffff; ++ soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); ++ *valp = soffsetx4_0; ++ return 0; + } + +-static unsigned +-Field_st_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_soffsetx4_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); +- return tie_t; ++ unsigned offset_0, soffsetx4_0; ++ soffsetx4_0 = *valp; ++ offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; ++ *valp = offset_0; ++ return 0; + } + +-static void +-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_soffsetx4_ator (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ *valp -= (pc & ~0x3); ++ return 0; + } + +-static unsigned +-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); +- return tie_t; ++ *valp += (pc & ~0x3); ++ return 0; + } + +-static void +-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_lsi4x4_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ unsigned lsi4x4_0, r_0; ++ r_0 = *valp & 0xf; ++ lsi4x4_0 = r_0 << 2; ++ *valp = lsi4x4_0; ++ return 0; + } + +-static unsigned +-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_lsi4x4_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); +- return tie_t; ++ unsigned r_0, lsi4x4_0; ++ lsi4x4_0 = *valp; ++ r_0 = ((lsi4x4_0 >> 2) & 0xf); ++ *valp = r_0; ++ return 0; + } + +-static void +-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_simm7_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); ++ unsigned simm7_0, imm7_0; ++ imm7_0 = *valp & 0x7f; ++ simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; ++ *valp = simm7_0; ++ return 0; + } + +-static unsigned +-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_simm7_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); +- return tie_t; ++ unsigned imm7_0, simm7_0; ++ simm7_0 = *valp; ++ imm7_0 = (simm7_0 & 0x7f); ++ *valp = imm7_0; ++ return 0; + } + +-static void +-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm6_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); ++ unsigned uimm6_0, imm6_0; ++ imm6_0 = *valp & 0x3f; ++ uimm6_0 = 0x4 + (((0) << 6) | imm6_0); ++ *valp = uimm6_0; ++ return 0; + } + +-static unsigned +-Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm6_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); +- return tie_t; ++ unsigned imm6_0, uimm6_0; ++ uimm6_0 = *valp; ++ imm6_0 = (uimm6_0 - 0x4) & 0x3f; ++ *valp = imm6_0; ++ return 0; + } + +-static void +-Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm6_ator (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe) | (tie_t << 1); ++ *valp -= pc; ++ return 0; + } + +-static unsigned +-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm6_rtoa (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ *valp += pc; ++ return 0; + } + +-static void +-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_ai4const_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned ai4const_0, t_0; ++ t_0 = *valp & 0xf; ++ ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; ++ *valp = ai4const_0; ++ return 0; + } + +-static unsigned +-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_ai4const_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ unsigned t_0, ai4const_0; ++ ai4const_0 = *valp; ++ switch (ai4const_0) ++ { ++ case 0xffffffff: t_0 = 0; break; ++ case 0x1: t_0 = 0x1; break; ++ case 0x2: t_0 = 0x2; break; ++ case 0x3: t_0 = 0x3; break; ++ case 0x4: t_0 = 0x4; break; ++ case 0x5: t_0 = 0x5; break; ++ case 0x6: t_0 = 0x6; break; ++ case 0x7: t_0 = 0x7; break; ++ case 0x8: t_0 = 0x8; break; ++ case 0x9: t_0 = 0x9; break; ++ case 0xa: t_0 = 0xa; break; ++ case 0xb: t_0 = 0xb; break; ++ case 0xc: t_0 = 0xc; break; ++ case 0xd: t_0 = 0xd; break; ++ case 0xe: t_0 = 0xe; break; ++ default: t_0 = 0xf; break; ++ } ++ *valp = t_0; ++ return 0; + } + +-static void +-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_b4const_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned b4const_0, r_0; ++ r_0 = *valp & 0xf; ++ b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; ++ *valp = b4const_0; ++ return 0; + } + +-static unsigned +-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_b4const_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ unsigned r_0, b4const_0; ++ b4const_0 = *valp; ++ switch (b4const_0) ++ { ++ case 0xffffffff: r_0 = 0; break; ++ case 0x1: r_0 = 0x1; break; ++ case 0x2: r_0 = 0x2; break; ++ case 0x3: r_0 = 0x3; break; ++ case 0x4: r_0 = 0x4; break; ++ case 0x5: r_0 = 0x5; break; ++ case 0x6: r_0 = 0x6; break; ++ case 0x7: r_0 = 0x7; break; ++ case 0x8: r_0 = 0x8; break; ++ case 0xa: r_0 = 0x9; break; ++ case 0xc: r_0 = 0xa; break; ++ case 0x10: r_0 = 0xb; break; ++ case 0x20: r_0 = 0xc; break; ++ case 0x40: r_0 = 0xd; break; ++ case 0x80: r_0 = 0xe; break; ++ default: r_0 = 0xf; break; ++ } ++ *valp = r_0; ++ return 0; + } + +-static void +-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_b4constu_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned b4constu_0, r_0; ++ r_0 = *valp & 0xf; ++ b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; ++ *valp = b4constu_0; ++ return 0; + } + +-static unsigned +-Field_mn_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_b4constu_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); +- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); +- return tie_t; ++ unsigned r_0, b4constu_0; ++ b4constu_0 = *valp; ++ switch (b4constu_0) ++ { ++ case 0x8000: r_0 = 0; break; ++ case 0x10000: r_0 = 0x1; break; ++ case 0x2: r_0 = 0x2; break; ++ case 0x3: r_0 = 0x3; break; ++ case 0x4: r_0 = 0x4; break; ++ case 0x5: r_0 = 0x5; break; ++ case 0x6: r_0 = 0x6; break; ++ case 0x7: r_0 = 0x7; break; ++ case 0x8: r_0 = 0x8; break; ++ case 0xa: r_0 = 0x9; break; ++ case 0xc: r_0 = 0xa; break; ++ case 0x10: r_0 = 0xb; break; ++ case 0x20: r_0 = 0xc; break; ++ case 0x40: r_0 = 0xd; break; ++ case 0x80: r_0 = 0xe; break; ++ default: r_0 = 0xf; break; ++ } ++ *valp = r_0; ++ return 0; + } + +-static void +-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm8_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +- tie_t = (val << 28) >> 30; +- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); ++ unsigned uimm8_0, imm8_0; ++ imm8_0 = *valp & 0xff; ++ uimm8_0 = imm8_0; ++ *valp = uimm8_0; ++ return 0; + } + +-static unsigned +-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm8_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; ++ unsigned imm8_0, uimm8_0; ++ uimm8_0 = *valp; ++ imm8_0 = (uimm8_0 & 0xff); ++ *valp = imm8_0; ++ return 0; + } + +-static void +-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm8x2_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); ++ unsigned uimm8x2_0, imm8_0; ++ imm8_0 = *valp & 0xff; ++ uimm8x2_0 = imm8_0 << 1; ++ *valp = uimm8x2_0; ++ return 0; + } + +-static unsigned +-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm8x2_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; ++ unsigned imm8_0, uimm8x2_0; ++ uimm8x2_0 = *valp; ++ imm8_0 = ((uimm8x2_0 >> 1) & 0xff); ++ *valp = imm8_0; ++ return 0; + } + +-static void +-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm8x4_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); ++ unsigned uimm8x4_0, imm8_0; ++ imm8_0 = *valp & 0xff; ++ uimm8x4_0 = imm8_0 << 2; ++ *valp = uimm8x4_0; ++ return 0; + } + +-static unsigned +-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm8x4_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ unsigned imm8_0, uimm8x4_0; ++ uimm8x4_0 = *valp; ++ imm8_0 = ((uimm8x4_0 >> 2) & 0xff); ++ *valp = imm8_0; ++ return 0; + } + +-static void +-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm4x16_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned uimm4x16_0, op2_0; ++ op2_0 = *valp & 0xf; ++ uimm4x16_0 = op2_0 << 4; ++ *valp = uimm4x16_0; ++ return 0; + } + +-static unsigned +-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm4x16_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ unsigned op2_0, uimm4x16_0; ++ uimm4x16_0 = *valp; ++ op2_0 = ((uimm4x16_0 >> 4) & 0xf); ++ *valp = op2_0; ++ return 0; + } + +-static void +-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_simm8_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned simm8_0, imm8_0; ++ imm8_0 = *valp & 0xff; ++ simm8_0 = ((int) imm8_0 << 24) >> 24; ++ *valp = simm8_0; ++ return 0; + } + +-static unsigned +-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_simm8_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); +- return tie_t; ++ unsigned imm8_0, simm8_0; ++ simm8_0 = *valp; ++ imm8_0 = (simm8_0 & 0xff); ++ *valp = imm8_0; ++ return 0; + } + +-static void +-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_simm8x256_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++ unsigned simm8x256_0, imm8_0; ++ imm8_0 = *valp & 0xff; ++ simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; ++ *valp = simm8x256_0; ++ return 0; + } + +-static unsigned +-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_simm8x256_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); +- return tie_t; ++ unsigned imm8_0, simm8x256_0; ++ simm8x256_0 = *valp; ++ imm8_0 = ((simm8x256_0 >> 8) & 0xff); ++ *valp = imm8_0; ++ return 0; + } + +-static void +-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_simm12b_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++ unsigned simm12b_0, imm12b_0; ++ imm12b_0 = *valp & 0xfff; ++ simm12b_0 = ((int) imm12b_0 << 20) >> 20; ++ *valp = simm12b_0; ++ return 0; + } + +-static unsigned +-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_simm12b_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ unsigned imm12b_0, simm12b_0; ++ simm12b_0 = *valp; ++ imm12b_0 = (simm12b_0 & 0xfff); ++ *valp = imm12b_0; ++ return 0; + } + +-static void +-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_msalp32_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned msalp32_0, sal_0; ++ sal_0 = *valp & 0x1f; ++ msalp32_0 = 0x20 - sal_0; ++ *valp = msalp32_0; ++ return 0; + } + +-static unsigned +-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_msalp32_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ unsigned sal_0, msalp32_0; ++ msalp32_0 = *valp; ++ sal_0 = (0x20 - msalp32_0) & 0x1f; ++ *valp = sal_0; ++ return 0; + } + +-static void +-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_op2p1_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); ++ unsigned op2p1_0, op2_0; ++ op2_0 = *valp & 0xf; ++ op2p1_0 = op2_0 + 0x1; ++ *valp = op2p1_0; ++ return 0; + } + +-static unsigned +-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_op2p1_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); +- return tie_t; ++ unsigned op2_0, op2p1_0; ++ op2p1_0 = *valp; ++ op2_0 = (op2p1_0 - 0x1) & 0xf; ++ *valp = op2_0; ++ return 0; + } + +-static void +-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_label8_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); ++ unsigned label8_0, imm8_0; ++ imm8_0 = *valp & 0xff; ++ label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); ++ *valp = label8_0; ++ return 0; + } + +-static unsigned +-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_label8_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); +- return tie_t; ++ unsigned imm8_0, label8_0; ++ label8_0 = *valp; ++ imm8_0 = (label8_0 - 0x4) & 0xff; ++ *valp = imm8_0; ++ return 0; + } + +-static void +-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_label8_ator (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); ++ *valp -= pc; ++ return 0; + } + +-static unsigned +-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_label8_rtoa (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); +- return tie_t; ++ *valp += pc; ++ return 0; + } + +-static void +-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_label12_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); ++ unsigned label12_0, imm12_0; ++ imm12_0 = *valp & 0xfff; ++ label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); ++ *valp = label12_0; ++ return 0; + } + +-static unsigned +-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_label12_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); +- return tie_t; ++ unsigned imm12_0, label12_0; ++ label12_0 = *valp; ++ imm12_0 = (label12_0 - 0x4) & 0xfff; ++ *valp = imm12_0; ++ return 0; + } + +-static void +-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_label12_ator (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); ++ *valp -= pc; ++ return 0; + } + +-static unsigned +-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_label12_rtoa (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ *valp += pc; ++ return 0; + } + +-static void +-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_soffset_decode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +- tie_t = (val << 26) >> 30; +- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++ unsigned soffset_0, offset_0; ++ offset_0 = *valp & 0x3ffff; ++ soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); ++ *valp = soffset_0; ++ return 0; + } + +-static unsigned +-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) ++static int ++Operand_soffset_encode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; ++ unsigned offset_0, soffset_0; ++ soffset_0 = *valp; ++ offset_0 = (soffset_0 - 0x4) & 0x3ffff; ++ *valp = offset_0; ++ return 0; + } + +-static void +-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +- tie_t = (val << 26) >> 30; +- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +-} +- +-static unsigned +-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; +-} +- +-static void +-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +- tie_t = (val << 25) >> 29; +- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +-} +- +-static unsigned +-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; +-} +- +-static void +-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +- tie_t = (val << 25) >> 29; +- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +-} +- +-static unsigned +-Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); +- return tie_t; +-} +- +-static void +-Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 25) >> 25; +- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +-} +- +-static unsigned +-Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); +- return tie_t; +-} +- +-static void +-Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +-} +- +-static unsigned +-Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); +- return tie_t; +-} +- +-static void +-Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +-} +- +-static unsigned +-Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_soffset_ator (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); +- return tie_t; ++ *valp -= pc; ++ return 0; + } + +-static void +-Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_soffset_rtoa (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); ++ *valp += pc; ++ return 0; + } + +-static unsigned +-Field_t3_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm16x4_decode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; ++ unsigned uimm16x4_0, imm16_0; ++ imm16_0 = *valp & 0xffff; ++ uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; ++ *valp = uimm16x4_0; ++ return 0; + } + +-static void +-Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm16x4_encode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); ++ unsigned imm16_0, uimm16x4_0; ++ uimm16x4_0 = *valp; ++ imm16_0 = (uimm16x4_0 >> 2) & 0xffff; ++ *valp = imm16_0; ++ return 0; + } + +-static unsigned +-Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_uimm16x4_ator (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); +- return tie_t; ++ *valp -= ((pc + 3) & ~0x3); ++ return 0; + } + +-static void +-Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); ++ *valp += ((pc + 3) & ~0x3); ++ return 0; + } + +-static unsigned +-Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_immt_decode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); +- return tie_t; ++ unsigned immt_0, t_0; ++ t_0 = *valp & 0xf; ++ immt_0 = t_0; ++ *valp = immt_0; ++ return 0; + } + +-static void +-Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_immt_encode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); ++ unsigned t_0, immt_0; ++ immt_0 = *valp; ++ t_0 = immt_0 & 0xf; ++ *valp = t_0; ++ return 0; + } + +-static unsigned +-Field_w_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_imms_decode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); +- return tie_t; ++ unsigned imms_0, s_0; ++ s_0 = *valp & 0xf; ++ imms_0 = s_0; ++ *valp = imms_0; ++ return 0; + } + +-static void +-Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_imms_encode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); ++ unsigned s_0, imms_0; ++ imms_0 = *valp; ++ s_0 = imms_0 & 0xf; ++ *valp = s_0; ++ return 0; + } + +-static unsigned +-Field_y_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_xt_wbr15_label_decode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); +- return tie_t; ++ unsigned xt_wbr15_label_0, xt_wbr15_imm_0; ++ xt_wbr15_imm_0 = *valp & 0x7fff; ++ xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); ++ *valp = xt_wbr15_label_0; ++ return 0; + } + +-static void +-Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_xt_wbr15_label_encode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); ++ unsigned xt_wbr15_imm_0, xt_wbr15_label_0; ++ xt_wbr15_label_0 = *valp; ++ xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; ++ *valp = xt_wbr15_imm_0; ++ return 0; + } + +-static unsigned +-Field_x_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); +- return tie_t; ++ *valp -= pc; ++ return 0; + } + +-static void +-Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); ++ *valp += pc; ++ return 0; + } + +-static unsigned +-Field_t2_Slot_inst_get (const xtensa_insnbuf insn) ++static int ++Operand_xt_wbr18_label_decode (uint32 *valp) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); +- return tie_t; ++ unsigned xt_wbr18_label_0, xt_wbr18_imm_0; ++ xt_wbr18_imm_0 = *valp & 0x3ffff; ++ xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); ++ *valp = xt_wbr18_label_0; ++ return 0; + } + +-static void +-Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_xt_wbr18_label_encode (uint32 *valp) + { +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); ++ unsigned xt_wbr18_imm_0, xt_wbr18_label_0; ++ xt_wbr18_label_0 = *valp; ++ xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; ++ *valp = xt_wbr18_imm_0; ++ return 0; + } + +-static unsigned +-Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) ++static int ++Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) + { +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); +- return tie_t; ++ *valp -= pc; ++ return 0; + } + +-static void +-Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) ++static int ++Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) + { +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); ++ *valp += pc; ++ return 0; + } + +-static unsigned +-Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); +- return tie_t; +-} ++static xtensa_operand_internal operands[] = { ++ { "art", FIELD_t, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER, ++ Operand_art_encode, Operand_art_decode, ++ 0, 0 }, ++ { "ars", FIELD_s, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER, ++ Operand_ars_encode, Operand_ars_decode, ++ 0, 0 }, ++ { "*ars_invisible", FIELD_s, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, ++ Operand_ars_encode, Operand_ars_decode, ++ 0, 0 }, ++ { "arr", FIELD_r, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER, ++ Operand_arr_encode, Operand_arr_decode, ++ 0, 0 }, ++ { "ar0", FIELD__ar0, REGFILE_AR, 1, ++ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, ++ Operand_ar0_encode, Operand_ar0_decode, ++ 0, 0 }, ++ { "soffsetx4", FIELD_offset, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_soffsetx4_encode, Operand_soffsetx4_decode, ++ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, ++ { "lsi4x4", FIELD_r, -1, 0, ++ 0, ++ Operand_lsi4x4_encode, Operand_lsi4x4_decode, ++ 0, 0 }, ++ { "simm7", FIELD_imm7, -1, 0, ++ 0, ++ Operand_simm7_encode, Operand_simm7_decode, ++ 0, 0 }, ++ { "uimm6", FIELD_imm6, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_uimm6_encode, Operand_uimm6_decode, ++ Operand_uimm6_ator, Operand_uimm6_rtoa }, ++ { "ai4const", FIELD_t, -1, 0, ++ 0, ++ Operand_ai4const_encode, Operand_ai4const_decode, ++ 0, 0 }, ++ { "b4const", FIELD_r, -1, 0, ++ 0, ++ Operand_b4const_encode, Operand_b4const_decode, ++ 0, 0 }, ++ { "b4constu", FIELD_r, -1, 0, ++ 0, ++ Operand_b4constu_encode, Operand_b4constu_decode, ++ 0, 0 }, ++ { "uimm8", FIELD_imm8, -1, 0, ++ 0, ++ Operand_uimm8_encode, Operand_uimm8_decode, ++ 0, 0 }, ++ { "uimm8x2", FIELD_imm8, -1, 0, ++ 0, ++ Operand_uimm8x2_encode, Operand_uimm8x2_decode, ++ 0, 0 }, ++ { "uimm8x4", FIELD_imm8, -1, 0, ++ 0, ++ Operand_uimm8x4_encode, Operand_uimm8x4_decode, ++ 0, 0 }, ++ { "uimm4x16", FIELD_op2, -1, 0, ++ 0, ++ Operand_uimm4x16_encode, Operand_uimm4x16_decode, ++ 0, 0 }, ++ { "simm8", FIELD_imm8, -1, 0, ++ 0, ++ Operand_simm8_encode, Operand_simm8_decode, ++ 0, 0 }, ++ { "simm8x256", FIELD_imm8, -1, 0, ++ 0, ++ Operand_simm8x256_encode, Operand_simm8x256_decode, ++ 0, 0 }, ++ { "simm12b", FIELD_imm12b, -1, 0, ++ 0, ++ Operand_simm12b_encode, Operand_simm12b_decode, ++ 0, 0 }, ++ { "msalp32", FIELD_sal, -1, 0, ++ 0, ++ Operand_msalp32_encode, Operand_msalp32_decode, ++ 0, 0 }, ++ { "op2p1", FIELD_op2, -1, 0, ++ 0, ++ Operand_op2p1_encode, Operand_op2p1_decode, ++ 0, 0 }, ++ { "label8", FIELD_imm8, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_label8_encode, Operand_label8_decode, ++ Operand_label8_ator, Operand_label8_rtoa }, ++ { "label12", FIELD_imm12, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_label12_encode, Operand_label12_decode, ++ Operand_label12_ator, Operand_label12_rtoa }, ++ { "soffset", FIELD_offset, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_soffset_encode, Operand_soffset_decode, ++ Operand_soffset_ator, Operand_soffset_rtoa }, ++ { "uimm16x4", FIELD_imm16, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_uimm16x4_encode, Operand_uimm16x4_decode, ++ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, ++ { "immt", FIELD_t, -1, 0, ++ 0, ++ Operand_immt_encode, Operand_immt_decode, ++ 0, 0 }, ++ { "imms", FIELD_s, -1, 0, ++ 0, ++ Operand_imms_encode, Operand_imms_decode, ++ 0, 0 }, ++ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, ++ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, ++ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, ++ XTENSA_OPERAND_IS_PCRELATIVE, ++ Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, ++ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, ++ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, ++ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, ++ { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, ++ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, ++ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, ++ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, ++ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, ++ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, ++ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, ++ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, ++ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, ++ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, ++ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, ++ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, ++ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, ++ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, ++ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, ++ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 } ++}; ++ ++enum xtensa_operand_id { ++ OPERAND_art, ++ OPERAND_ars, ++ OPERAND__ars_invisible, ++ OPERAND_arr, ++ OPERAND_ar0, ++ OPERAND_soffsetx4, ++ OPERAND_lsi4x4, ++ OPERAND_simm7, ++ OPERAND_uimm6, ++ OPERAND_ai4const, ++ OPERAND_b4const, ++ OPERAND_b4constu, ++ OPERAND_uimm8, ++ OPERAND_uimm8x2, ++ OPERAND_uimm8x4, ++ OPERAND_uimm4x16, ++ OPERAND_simm8, ++ OPERAND_simm8x256, ++ OPERAND_simm12b, ++ OPERAND_msalp32, ++ OPERAND_op2p1, ++ OPERAND_label8, ++ OPERAND_label12, ++ OPERAND_soffset, ++ OPERAND_uimm16x4, ++ OPERAND_immt, ++ OPERAND_imms, ++ OPERAND_xt_wbr15_label, ++ OPERAND_xt_wbr18_label, ++ OPERAND_t, ++ OPERAND_bbi4, ++ OPERAND_bbi, ++ OPERAND_imm12, ++ OPERAND_imm8, ++ OPERAND_s, ++ OPERAND_imm12b, ++ OPERAND_imm16, ++ OPERAND_m, ++ OPERAND_n, ++ OPERAND_offset, ++ OPERAND_op0, ++ OPERAND_op1, ++ OPERAND_op2, ++ OPERAND_r, ++ OPERAND_sa4, ++ OPERAND_sae4, ++ OPERAND_sae, ++ OPERAND_sal, ++ OPERAND_sargt, ++ OPERAND_sas4, ++ OPERAND_sas, ++ OPERAND_sr, ++ OPERAND_st, ++ OPERAND_thi3, ++ OPERAND_imm4, ++ OPERAND_i, ++ OPERAND_imm6lo, ++ OPERAND_imm6hi, ++ OPERAND_imm7lo, ++ OPERAND_imm7hi, ++ OPERAND_z, ++ OPERAND_imm6, ++ OPERAND_imm7, ++ OPERAND_xt_wbr15_imm, ++ OPERAND_xt_wbr18_imm ++}; + +-static void +-Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +-} ++ ++/* Iclass table. */ + +-static unsigned +-Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { ++ { { STATE_PSEXCM }, 'o' }, ++ { { STATE_EPC1 }, 'i' } ++}; + +-static void +-Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { ++ { { STATE_DEPC }, 'i' } ++}; + +-static unsigned +-Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +-} ++static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_ai4const }, 'i' } ++}; + +-static unsigned +-Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm6 }, 'i' } ++}; + +-static void +-Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +-} ++static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_lsi4x4 }, 'i' } ++}; + +-static unsigned +-Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; + +-static void +-Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +-} ++static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { ++ { { OPERAND_ars }, 'o' }, ++ { { OPERAND_simm7 }, 'i' } ++}; + +-static unsigned +-Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { ++ { { OPERAND__ars_invisible }, 'i' } ++}; + +-static void +-Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +-} ++static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_lsi4x4 }, 'i' } ++}; + +-static unsigned +-Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_simm8 }, 'i' } ++}; + +-static void +-Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +-} ++static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_simm8x256 }, 'i' } ++}; + +-static unsigned +-Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +-} ++static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_b4const }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; + +-static void +-Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +-} ++static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_bbi }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; + +-static unsigned +-Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_b4constu }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; + +-static void +-Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +-} ++static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_label8 }, 'i' } ++}; + +-static unsigned +-Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_label12 }, 'i' } ++}; + +-static void +-Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +-} ++static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { ++ { { OPERAND_soffsetx4 }, 'i' }, ++ { { OPERAND_ar0 }, 'o' } ++}; + +-static unsigned +-Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_ar0 }, 'o' } ++}; + +-static void +-Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +-} ++static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_sae }, 'i' }, ++ { { OPERAND_op2p1 }, 'i' } ++}; + +-static unsigned +-Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { ++ { { OPERAND_soffset }, 'i' } ++}; + +-static void +-Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +-} ++static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { ++ { { OPERAND_ars }, 'i' } ++}; + +-static unsigned +-Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x2 }, 'i' } ++}; + +-static void +-Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +-} ++static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x2 }, 'i' } ++}; + +-static unsigned +-Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x4 }, 'i' } ++}; + +-static void +-Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +-} ++static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_uimm16x4 }, 'i' } ++}; + +-static unsigned +-Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { ++ { { STATE_LITBADDR }, 'i' }, ++ { { STATE_LITBEN }, 'i' } ++}; + +-static void +-Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +-} ++static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8 }, 'i' } ++}; + +-static unsigned +-Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_simm12b }, 'i' } ++}; + +-static void +-Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +-} ++static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { ++ { { OPERAND_arr }, 'm' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +-} ++static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { ++ { { OPERAND__ars_invisible }, 'i' } ++}; + +-static unsigned +-Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x2 }, 'i' } ++}; + +-static void +-Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +-} ++static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8x4 }, 'i' } ++}; + +-static unsigned +-Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_uimm8 }, 'i' } ++}; + +-static void +-Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +-} ++static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { ++ { { OPERAND_ars }, 'i' } ++}; + +-static unsigned +-Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { ++ { { STATE_SAR }, 'o' } ++}; + +-static void +-Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +-} ++static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { ++ { { OPERAND_sas }, 'i' } ++}; + +-static unsigned +-Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { ++ { { STATE_SAR }, 'o' } ++}; + +-static void +-Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +-} ++static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; + +-static unsigned +-Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; + +-static void +-Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +-} ++static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; + +-static void +-Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +-} ++static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; + +-static void +-Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +-} ++static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_msalp32 }, 'i' } ++}; + +-static unsigned +-Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_sargt }, 'i' } ++}; + +-static void +-Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 17) >> 17; +- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +-} ++static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_s }, 'i' } ++}; + +-static unsigned +-Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { ++ { { STATE_XTSYNC }, 'i' } ++}; + +-static void +-Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 14) >> 14; +- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_s }, 'i' } ++}; + +-static unsigned +-Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { ++ { { STATE_PSUM }, 'i' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'm' } ++}; + +-static void +-Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 14) >> 14; +- insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); +- return tie_t; +-} +- +-static void +-Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { ++ { { STATE_SAR }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { ++ { { STATE_SAR }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { ++ { { STATE_SAR }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { ++ { { STATE_LITBADDR }, 'i' }, ++ { { STATE_LITBEN }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { ++ { { STATE_LITBADDR }, 'o' }, ++ { { STATE_LITBEN }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +- tie_t = (val << 24) >> 28; +- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { ++ { { STATE_LITBADDR }, 'm' }, ++ { { STATE_LITBEN }, 'm' } ++}; + +-static unsigned +-Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { ++ { { STATE_PSUM }, 'i' }, ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { ++ { { STATE_PSUM }, 'o' }, ++ { { STATE_PSEXCM }, 'o' }, ++ { { STATE_PSINTLEVEL }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { ++ { { STATE_PSUM }, 'm' }, ++ { { STATE_PSEXCM }, 'm' }, ++ { { STATE_PSINTLEVEL }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 27) >> 27; +- insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { ++ { { STATE_EPC1 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 26) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { ++ { { STATE_EPC1 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +- tie_t = (val << 23) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { ++ { { STATE_EPC1 }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +- tie_t = (val << 23) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { ++ { { STATE_EXCSAVE1 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +- tie_t = (val << 24) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { ++ { { STATE_EXCSAVE1 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +- tie_t = (val << 25) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { ++ { { STATE_EXCSAVE1 }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +- tie_t = (val << 24) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { ++ { { STATE_EPC2 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +- tie_t = (val << 24) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); +- tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { ++ { { STATE_EPC2 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +- tie_t = (val << 25) >> 26; +- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { ++ { { STATE_EPC2 }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { ++ { { STATE_EXCSAVE2 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { ++ { { STATE_EXCSAVE2 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { ++ { { STATE_EXCSAVE2 }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); +- tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { ++ { { STATE_EPC3 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 26) >> 26; +- insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +- tie_t = (val << 21) >> 27; +- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { ++ { { STATE_EPC3 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); +- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { ++ { { STATE_EPC3 }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +- tie_t = (val << 29) >> 30; +- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { ++ { { STATE_EXCSAVE3 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 27) >> 27; +- insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +- tie_t = (val << 26) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { ++ { { STATE_EXCSAVE3 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { ++ { { STATE_EXCSAVE3 }, 'm' } ++}; + +-static void +-Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { ++ { { STATE_EPS2 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { ++ { { STATE_EPS2 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +- tie_t = (val << 30) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { ++ { { STATE_EPS2 }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +- tie_t = (val << 30) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +- tie_t = (val << 29) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); +- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { ++ { { STATE_EPS3 }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +- tie_t = (val << 30) >> 31; +- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +- tie_t = (val << 29) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { ++ { { STATE_EPS3 }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +- tie_t = (val << 28) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { ++ { { STATE_EPS3 }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +- tie_t = (val << 28) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { ++ { { STATE_EXCVADDR }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +- tie_t = (val << 29) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); +- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { ++ { { STATE_EXCVADDR }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +- tie_t = (val << 30) >> 31; +- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { ++ { { STATE_EXCVADDR }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { ++ { { STATE_DEPC }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); +- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { ++ { { STATE_DEPC }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 26) >> 30; +- insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +- tie_t = (val << 22) >> 28; +- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); +- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { ++ { { STATE_DEPC }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +- tie_t = (val << 30) >> 31; +- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); +- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { ++ { { STATE_EXCCAUSE }, 'i' }, ++ { { STATE_XTSYNC }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 30) >> 30; +- insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +- tie_t = (val << 29) >> 31; +- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { ++ { { STATE_EXCCAUSE }, 'o' } ++}; + +-static void +-Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 27) >> 27; +- insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { ++ { { STATE_EXCCAUSE }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 24) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 29) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { ++ { { STATE_VECBASE }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 24) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { ++ { { STATE_VECBASE }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 24) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { ++ { { STATE_VECBASE }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_mul16_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +- tie_t = (val << 27) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 24) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_mul32_args[] = { ++ { { OPERAND_arr }, 'o' }, ++ { { OPERAND_ars }, 'i' }, ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { ++ { { OPERAND_s }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { ++ { { STATE_PSUM }, 'o' }, ++ { { STATE_PSEXCM }, 'o' }, ++ { { STATE_PSINTLEVEL }, 'o' }, ++ { { STATE_EPC1 }, 'i' }, ++ { { STATE_EPC2 }, 'i' }, ++ { { STATE_EPC3 }, 'i' }, ++ { { STATE_EPS2 }, 'i' }, ++ { { STATE_EPS3 }, 'i' }, ++ { { STATE_InOCDMode }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { ++ { { OPERAND_s }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { ++ { { STATE_PSINTLEVEL }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { ++ { { STATE_INTERRUPT }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { ++ { { STATE_INTENABLE }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { ++ { { STATE_INTENABLE }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { ++ { { STATE_INTENABLE }, 'm' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { ++ { { OPERAND_imms }, 'i' }, ++ { { OPERAND_immt }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { ++ { { OPERAND_imms }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { ++ { { STATE_PSEXCM }, 'i' }, ++ { { STATE_PSINTLEVEL }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { ++ { { STATE_DBREAKA0 }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { ++ { { STATE_DBREAKA0 }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { ++ { { STATE_DBREAKA0 }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { ++ { { STATE_DBREAKC0 }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { ++ { { STATE_DBREAKC0 }, 'o' }, ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { ++ { { STATE_DBREAKC0 }, 'm' }, ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { ++ { { STATE_IBREAKA0 }, 'i' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static void +-Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 31) >> 31; +- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +- tie_t = (val << 28) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { ++ { { STATE_IBREAKA0 }, 'o' } ++}; + +-static unsigned +-Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); +- tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static void +-Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 5) >> 5; +- insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0); +- tie_t = (val << 2) >> 29; +- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { ++ { { STATE_IBREAKA0 }, 'm' } ++}; + +-static unsigned +-Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) +-{ +- unsigned tie_t = 0; +- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); +- return tie_t; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static void +-Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) +-{ +- uint32 tie_t; +- tie_t = (val << 28) >> 28; +- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { ++ { { STATE_IBREAKENABLE }, 'i' } ++}; + +-static void +-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, +- uint32 val ATTRIBUTE_UNUSED) +-{ +- /* Do nothing. */ +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { ++ { { STATE_IBREAKENABLE }, 'o' } ++}; + +-static unsigned +-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 4; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 8; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { ++ { { STATE_IBREAKENABLE }, 'm' } ++}; + +-static unsigned +-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 12; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { ++ { { STATE_DEBUGCAUSE }, 'i' }, ++ { { STATE_DBNUM }, 'i' } ++}; + +-static unsigned +-Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 1; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static unsigned +-Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 2; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { ++ { { STATE_DEBUGCAUSE }, 'o' }, ++ { { STATE_DBNUM }, 'o' } ++}; + +-static unsigned +-Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 3; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static unsigned +-Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { ++ { { STATE_DEBUGCAUSE }, 'm' }, ++ { { STATE_DBNUM }, 'm' } ++}; + +-static unsigned +-Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static unsigned +-Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { ++ { { STATE_ICOUNT }, 'i' } ++}; + +-static unsigned +-Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +- +-/* Functional units. */ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_ICOUNT }, 'o' } ++}; + +-static xtensa_funcUnit_internal funcUnits[] = { ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_ICOUNT }, 'm' } + }; + +- +-/* Register files. */ ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static xtensa_regfile_internal regfiles[] = { +- { "AR", "a", 0, 32, 64 }, +- { "MR", "m", 1, 32, 4 }, +- { "BR", "b", 2, 1, 16 }, +- { "FR", "f", 3, 32, 16 }, +- { "BR2", "b", 2, 2, 8 }, +- { "BR4", "b", 2, 4, 4 }, +- { "BR8", "b", 2, 8, 2 }, +- { "BR16", "b", 2, 16, 1 } ++static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { ++ { { STATE_ICOUNTLEVEL }, 'i' } + }; + +- +-/* Interfaces. */ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static xtensa_interface_internal interfaces[] = { ++static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { ++ { { STATE_ICOUNTLEVEL }, 'o' } ++}; + ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { ++ { { OPERAND_art }, 'm' } + }; + +- +-/* Constant tables. */ ++static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { ++ { { STATE_ICOUNTLEVEL }, 'm' } ++}; + +-/* constant table ai4c */ +-static const unsigned CONST_TBL_ai4c_0[] = { +- 0xffffffff, +- 0x1, +- 0x2, +- 0x3, +- 0x4, +- 0x5, +- 0x6, +- 0x7, +- 0x8, +- 0x9, +- 0xa, +- 0xb, +- 0xc, +- 0xd, +- 0xe, +- 0xf, +- 0 ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { ++ { { OPERAND_art }, 'o' } + }; + +-/* constant table b4c */ +-static const unsigned CONST_TBL_b4c_0[] = { +- 0xffffffff, +- 0x1, +- 0x2, +- 0x3, +- 0x4, +- 0x5, +- 0x6, +- 0x7, +- 0x8, +- 0xa, +- 0xc, +- 0x10, +- 0x20, +- 0x40, +- 0x80, +- 0x100, +- 0 ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { ++ { { STATE_DDR }, 'i' } + }; + +-/* constant table b4cu */ +-static const unsigned CONST_TBL_b4cu_0[] = { +- 0x8000, +- 0x10000, +- 0x2, +- 0x3, +- 0x4, +- 0x5, +- 0x6, +- 0x7, +- 0x8, +- 0xa, +- 0xc, +- 0x10, +- 0x20, +- 0x40, +- 0x80, +- 0x100, +- 0 ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { ++ { { OPERAND_art }, 'i' } + }; + +- +-/* Instruction operands. */ ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_DDR }, 'o' } ++}; + +-static int +-Operand_soffsetx4_decode (uint32 *valp) +-{ +- unsigned soffsetx4_0, offset_0; +- offset_0 = *valp & 0x3ffff; +- soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); +- *valp = soffsetx4_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static int +-Operand_soffsetx4_encode (uint32 *valp) +-{ +- unsigned offset_0, soffsetx4_0; +- soffsetx4_0 = *valp; +- offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; +- *valp = offset_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_DDR }, 'm' } ++}; + +-static int +-Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +-{ +- *valp -= (pc & ~0x3); +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { ++ { { OPERAND_imms }, 'i' } ++}; + +-static int +-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +-{ +- *valp += (pc & ~0x3); +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { ++ { { STATE_InOCDMode }, 'm' }, ++ { { STATE_EPC2 }, 'i' }, ++ { { STATE_PSUM }, 'o' }, ++ { { STATE_PSEXCM }, 'o' }, ++ { { STATE_PSINTLEVEL }, 'o' }, ++ { { STATE_EPS2 }, 'i' } ++}; + +-static int +-Operand_uimm12x8_decode (uint32 *valp) +-{ +- unsigned uimm12x8_0, imm12_0; +- imm12_0 = *valp & 0xfff; +- uimm12x8_0 = imm12_0 << 3; +- *valp = uimm12x8_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { ++ { { STATE_InOCDMode }, 'm' } ++}; + +-static int +-Operand_uimm12x8_encode (uint32 *valp) +-{ +- unsigned imm12_0, uimm12x8_0; +- uimm12x8_0 = *valp; +- imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); +- *valp = imm12_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static int +-Operand_simm4_decode (uint32 *valp) +-{ +- unsigned simm4_0, mn_0; +- mn_0 = *valp & 0xf; +- simm4_0 = ((int) mn_0 << 28) >> 28; +- *valp = simm4_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static int +-Operand_simm4_encode (uint32 *valp) +-{ +- unsigned mn_0, simm4_0; +- simm4_0 = *valp; +- mn_0 = (simm4_0 & 0xf); +- *valp = mn_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static int +-Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { ++ { { STATE_CCOUNT }, 'i' } ++}; + +-static int +-Operand_arr_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0xf) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static int +-Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_CCOUNT }, 'o' } ++}; + +-static int +-Operand_ars_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0xf) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static int +-Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' }, ++ { { STATE_CCOUNT }, 'm' } ++}; + +-static int +-Operand_art_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0xf) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { ++ { { OPERAND_art }, 'o' } ++}; + +-static int +-Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { ++ { { STATE_CCOMPARE0 }, 'i' } ++}; + +-static int +-Operand_ar0_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0x3f) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { ++ { { OPERAND_art }, 'i' } ++}; + +-static int +-Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { ++ { { STATE_CCOMPARE0 }, 'o' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; + +-static int +-Operand_ar4_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0x3f) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { ++ { { OPERAND_art }, 'm' } ++}; + +-static int +-Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { ++ { { STATE_CCOMPARE0 }, 'm' }, ++ { { STATE_INTERRUPT }, 'm' } ++}; + +-static int +-Operand_ar8_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0x3f) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { ++ { { OPERAND_ars }, 'i' } ++}; + +-static int +-Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static int +-Operand_ar12_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0x3f) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; + +-static int +-Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' } ++}; + +-static int +-Operand_ars_entry_encode (uint32 *valp) +-{ +- int error; +- error = (*valp & ~0x3f) != 0; +- return error; +-} ++static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { ++ { { STATE_XTSYNC }, 'o' } ++}; + +-static int +-Operand_immrx4_decode (uint32 *valp) +-{ +- unsigned immrx4_0, r_0; +- r_0 = *valp & 0xf; +- immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; +- *valp = immrx4_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { ++ { { OPERAND_ars }, 'i' } ++}; + +-static int +-Operand_immrx4_encode (uint32 *valp) +-{ +- unsigned r_0, immrx4_0; +- immrx4_0 = *valp; +- r_0 = ((immrx4_0 >> 2) & 0xf); +- *valp = r_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; + +-static int +-Operand_lsi4x4_decode (uint32 *valp) +-{ +- unsigned lsi4x4_0, r_0; +- r_0 = *valp & 0xf; +- lsi4x4_0 = r_0 << 2; +- *valp = lsi4x4_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { ++ { { OPERAND_art }, 'i' }, ++ { { OPERAND_ars }, 'i' } ++}; + +-static int +-Operand_lsi4x4_encode (uint32 *valp) +-{ +- unsigned r_0, lsi4x4_0; +- lsi4x4_0 = *valp; +- r_0 = ((lsi4x4_0 >> 2) & 0xf); +- *valp = r_0; +- return 0; +-} ++static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { ++ { { OPERAND_art }, 'o' }, ++ { { OPERAND_ars }, 'i' } ++}; + +-static int +-Operand_simm7_decode (uint32 *valp) +-{ +- unsigned simm7_0, imm7_0; +- imm7_0 = *valp & 0x7f; +- simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; +- *valp = simm7_0; +- return 0; +-} ++static xtensa_iclass_internal iclasses[] = { ++ { 0, 0 /* xt_iclass_excw */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_rfe */, ++ 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_rfde */, ++ 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_syscall */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_simcall */, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_add_n_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addi_n_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_bz6_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_ill_n */, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_loadi4_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_mov_n_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_movi_n_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_nopn */, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_retn_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_storei4_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addi_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addmi_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_addsub_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bit_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bsi8_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bsi8b_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bsi8u_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_bst8_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_bsz12_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_call0_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_callx0_args, ++ 0, 0, 0, 0 }, ++ { 4, Iclass_xt_iclass_exti_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_ill */, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_jump_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_jumpx_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l16ui_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l16si_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_l32i_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_l32r_args, ++ 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_l8i_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_movi_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_movz_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_neg_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_nop */, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_return_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s16i_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s32i_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_s8i_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_sar_args, ++ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_sari_args, ++ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_shifts_args, ++ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_shiftst_args, ++ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_shiftt_args, ++ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_iclass_slli_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_srai_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_iclass_srli_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_memw */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_extw */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_isync */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_sync */, ++ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_rsil_args, ++ 3, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_sar_args, ++ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_sar_args, ++ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_sar_args, ++ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_litbase_args, ++ 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_litbase_args, ++ 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_litbase_args, ++ 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_176_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_176_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_208_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ps_args, ++ 3, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ps_args, ++ 3, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ps_args, ++ 3, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc1_args, ++ 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc1_args, ++ 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc1_args, ++ 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave1_args, ++ 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave1_args, ++ 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave1_args, ++ 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc2_args, ++ 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc2_args, ++ 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc2_args, ++ 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave2_args, ++ 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave2_args, ++ 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave2_args, ++ 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_epc3_args, ++ 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_epc3_args, ++ 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_epc3_args, ++ 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excsave3_args, ++ 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excsave3_args, ++ 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excsave3_args, ++ 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps2_args, ++ 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps2_args, ++ 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps2_args, ++ 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_eps3_args, ++ 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_eps3_args, ++ 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_eps3_args, ++ 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_excvaddr_args, ++ 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_excvaddr_args, ++ 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_excvaddr_args, ++ 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_depc_args, ++ 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_depc_args, ++ 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_depc_args, ++ 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_exccause_args, ++ 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_exccause_args, ++ 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_exccause_args, ++ 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_prid_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_vecbase_args, ++ 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_vecbase_args, ++ 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_vecbase_args, ++ 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, ++ { 3, Iclass_xt_mul16_args, ++ 0, 0, 0, 0 }, ++ { 3, Iclass_xt_mul32_args, ++ 0, 0, 0, 0 }, ++ { 1, Iclass_xt_iclass_rfi_args, ++ 9, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wait_args, ++ 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_interrupt_args, ++ 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_intset_args, ++ 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_intclear_args, ++ 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_intenable_args, ++ 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_intenable_args, ++ 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_intenable_args, ++ 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_break_args, ++ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_break_n_args, ++ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_dbreaka0_args, ++ 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_dbreaka0_args, ++ 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_dbreaka0_args, ++ 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_dbreakc0_args, ++ 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_dbreakc0_args, ++ 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_dbreakc0_args, ++ 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ibreaka0_args, ++ 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ibreaka0_args, ++ 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ibreaka0_args, ++ 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ibreakenable_args, ++ 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ibreakenable_args, ++ 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ibreakenable_args, ++ 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_debugcause_args, ++ 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_debugcause_args, ++ 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_debugcause_args, ++ 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_icount_args, ++ 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_icount_args, ++ 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_icount_args, ++ 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_icountlevel_args, ++ 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_icountlevel_args, ++ 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_icountlevel_args, ++ 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ddr_args, ++ 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ddr_args, ++ 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ddr_args, ++ 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rfdo_args, ++ 6, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, ++ { 0, 0 /* xt_iclass_rfdd */, ++ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_mmid_args, ++ 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ccount_args, ++ 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ccount_args, ++ 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ccount_args, ++ 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_rsr_ccompare0_args, ++ 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_wsr_ccompare0_args, ++ 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_xsr_ccompare0_args, ++ 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_idtlb_args, ++ 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, ++ { 2, Iclass_xt_iclass_rdtlb_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_wdtlb_args, ++ 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, ++ { 1, Iclass_xt_iclass_iitlb_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_ritlb_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_witlb_args, ++ 0, 0, 0, 0 }, ++ { 2, Iclass_xt_iclass_nsa_args, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_rer */, ++ 0, 0, 0, 0 }, ++ { 0, 0 /* xt_iclass_wer */, ++ 0, 0, 0, 0 } ++}; + +-static int +-Operand_simm7_encode (uint32 *valp) +-{ +- unsigned imm7_0, simm7_0; +- simm7_0 = *valp; +- imm7_0 = (simm7_0 & 0x7f); +- *valp = imm7_0; +- return 0; +-} ++enum xtensa_iclass_id { ++ ICLASS_xt_iclass_excw, ++ ICLASS_xt_iclass_rfe, ++ ICLASS_xt_iclass_rfde, ++ ICLASS_xt_iclass_syscall, ++ ICLASS_xt_iclass_simcall, ++ ICLASS_xt_iclass_add_n, ++ ICLASS_xt_iclass_addi_n, ++ ICLASS_xt_iclass_bz6, ++ ICLASS_xt_iclass_ill_n, ++ ICLASS_xt_iclass_loadi4, ++ ICLASS_xt_iclass_mov_n, ++ ICLASS_xt_iclass_movi_n, ++ ICLASS_xt_iclass_nopn, ++ ICLASS_xt_iclass_retn, ++ ICLASS_xt_iclass_storei4, ++ ICLASS_xt_iclass_addi, ++ ICLASS_xt_iclass_addmi, ++ ICLASS_xt_iclass_addsub, ++ ICLASS_xt_iclass_bit, ++ ICLASS_xt_iclass_bsi8, ++ ICLASS_xt_iclass_bsi8b, ++ ICLASS_xt_iclass_bsi8u, ++ ICLASS_xt_iclass_bst8, ++ ICLASS_xt_iclass_bsz12, ++ ICLASS_xt_iclass_call0, ++ ICLASS_xt_iclass_callx0, ++ ICLASS_xt_iclass_exti, ++ ICLASS_xt_iclass_ill, ++ ICLASS_xt_iclass_jump, ++ ICLASS_xt_iclass_jumpx, ++ ICLASS_xt_iclass_l16ui, ++ ICLASS_xt_iclass_l16si, ++ ICLASS_xt_iclass_l32i, ++ ICLASS_xt_iclass_l32r, ++ ICLASS_xt_iclass_l8i, ++ ICLASS_xt_iclass_movi, ++ ICLASS_xt_iclass_movz, ++ ICLASS_xt_iclass_neg, ++ ICLASS_xt_iclass_nop, ++ ICLASS_xt_iclass_return, ++ ICLASS_xt_iclass_s16i, ++ ICLASS_xt_iclass_s32i, ++ ICLASS_xt_iclass_s8i, ++ ICLASS_xt_iclass_sar, ++ ICLASS_xt_iclass_sari, ++ ICLASS_xt_iclass_shifts, ++ ICLASS_xt_iclass_shiftst, ++ ICLASS_xt_iclass_shiftt, ++ ICLASS_xt_iclass_slli, ++ ICLASS_xt_iclass_srai, ++ ICLASS_xt_iclass_srli, ++ ICLASS_xt_iclass_memw, ++ ICLASS_xt_iclass_extw, ++ ICLASS_xt_iclass_isync, ++ ICLASS_xt_iclass_sync, ++ ICLASS_xt_iclass_rsil, ++ ICLASS_xt_iclass_rsr_sar, ++ ICLASS_xt_iclass_wsr_sar, ++ ICLASS_xt_iclass_xsr_sar, ++ ICLASS_xt_iclass_rsr_litbase, ++ ICLASS_xt_iclass_wsr_litbase, ++ ICLASS_xt_iclass_xsr_litbase, ++ ICLASS_xt_iclass_rsr_176, ++ ICLASS_xt_iclass_wsr_176, ++ ICLASS_xt_iclass_rsr_208, ++ ICLASS_xt_iclass_rsr_ps, ++ ICLASS_xt_iclass_wsr_ps, ++ ICLASS_xt_iclass_xsr_ps, ++ ICLASS_xt_iclass_rsr_epc1, ++ ICLASS_xt_iclass_wsr_epc1, ++ ICLASS_xt_iclass_xsr_epc1, ++ ICLASS_xt_iclass_rsr_excsave1, ++ ICLASS_xt_iclass_wsr_excsave1, ++ ICLASS_xt_iclass_xsr_excsave1, ++ ICLASS_xt_iclass_rsr_epc2, ++ ICLASS_xt_iclass_wsr_epc2, ++ ICLASS_xt_iclass_xsr_epc2, ++ ICLASS_xt_iclass_rsr_excsave2, ++ ICLASS_xt_iclass_wsr_excsave2, ++ ICLASS_xt_iclass_xsr_excsave2, ++ ICLASS_xt_iclass_rsr_epc3, ++ ICLASS_xt_iclass_wsr_epc3, ++ ICLASS_xt_iclass_xsr_epc3, ++ ICLASS_xt_iclass_rsr_excsave3, ++ ICLASS_xt_iclass_wsr_excsave3, ++ ICLASS_xt_iclass_xsr_excsave3, ++ ICLASS_xt_iclass_rsr_eps2, ++ ICLASS_xt_iclass_wsr_eps2, ++ ICLASS_xt_iclass_xsr_eps2, ++ ICLASS_xt_iclass_rsr_eps3, ++ ICLASS_xt_iclass_wsr_eps3, ++ ICLASS_xt_iclass_xsr_eps3, ++ ICLASS_xt_iclass_rsr_excvaddr, ++ ICLASS_xt_iclass_wsr_excvaddr, ++ ICLASS_xt_iclass_xsr_excvaddr, ++ ICLASS_xt_iclass_rsr_depc, ++ ICLASS_xt_iclass_wsr_depc, ++ ICLASS_xt_iclass_xsr_depc, ++ ICLASS_xt_iclass_rsr_exccause, ++ ICLASS_xt_iclass_wsr_exccause, ++ ICLASS_xt_iclass_xsr_exccause, ++ ICLASS_xt_iclass_rsr_prid, ++ ICLASS_xt_iclass_rsr_vecbase, ++ ICLASS_xt_iclass_wsr_vecbase, ++ ICLASS_xt_iclass_xsr_vecbase, ++ ICLASS_xt_mul16, ++ ICLASS_xt_mul32, ++ ICLASS_xt_iclass_rfi, ++ ICLASS_xt_iclass_wait, ++ ICLASS_xt_iclass_rsr_interrupt, ++ ICLASS_xt_iclass_wsr_intset, ++ ICLASS_xt_iclass_wsr_intclear, ++ ICLASS_xt_iclass_rsr_intenable, ++ ICLASS_xt_iclass_wsr_intenable, ++ ICLASS_xt_iclass_xsr_intenable, ++ ICLASS_xt_iclass_break, ++ ICLASS_xt_iclass_break_n, ++ ICLASS_xt_iclass_rsr_dbreaka0, ++ ICLASS_xt_iclass_wsr_dbreaka0, ++ ICLASS_xt_iclass_xsr_dbreaka0, ++ ICLASS_xt_iclass_rsr_dbreakc0, ++ ICLASS_xt_iclass_wsr_dbreakc0, ++ ICLASS_xt_iclass_xsr_dbreakc0, ++ ICLASS_xt_iclass_rsr_ibreaka0, ++ ICLASS_xt_iclass_wsr_ibreaka0, ++ ICLASS_xt_iclass_xsr_ibreaka0, ++ ICLASS_xt_iclass_rsr_ibreakenable, ++ ICLASS_xt_iclass_wsr_ibreakenable, ++ ICLASS_xt_iclass_xsr_ibreakenable, ++ ICLASS_xt_iclass_rsr_debugcause, ++ ICLASS_xt_iclass_wsr_debugcause, ++ ICLASS_xt_iclass_xsr_debugcause, ++ ICLASS_xt_iclass_rsr_icount, ++ ICLASS_xt_iclass_wsr_icount, ++ ICLASS_xt_iclass_xsr_icount, ++ ICLASS_xt_iclass_rsr_icountlevel, ++ ICLASS_xt_iclass_wsr_icountlevel, ++ ICLASS_xt_iclass_xsr_icountlevel, ++ ICLASS_xt_iclass_rsr_ddr, ++ ICLASS_xt_iclass_wsr_ddr, ++ ICLASS_xt_iclass_xsr_ddr, ++ ICLASS_xt_iclass_rfdo, ++ ICLASS_xt_iclass_rfdd, ++ ICLASS_xt_iclass_wsr_mmid, ++ ICLASS_xt_iclass_rsr_ccount, ++ ICLASS_xt_iclass_wsr_ccount, ++ ICLASS_xt_iclass_xsr_ccount, ++ ICLASS_xt_iclass_rsr_ccompare0, ++ ICLASS_xt_iclass_wsr_ccompare0, ++ ICLASS_xt_iclass_xsr_ccompare0, ++ ICLASS_xt_iclass_idtlb, ++ ICLASS_xt_iclass_rdtlb, ++ ICLASS_xt_iclass_wdtlb, ++ ICLASS_xt_iclass_iitlb, ++ ICLASS_xt_iclass_ritlb, ++ ICLASS_xt_iclass_witlb, ++ ICLASS_xt_iclass_nsa, ++ ICLASS_xt_iclass_rer, ++ ICLASS_xt_iclass_wer ++}; + +-static int +-Operand_uimm6_decode (uint32 *valp) ++ ++/* Opcode encodings. */ ++ ++static void ++Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned uimm6_0, imm6_0; +- imm6_0 = *valp & 0x3f; +- uimm6_0 = 0x4 + (((0) << 6) | imm6_0); +- *valp = uimm6_0; +- return 0; ++ slotbuf[0] = 0x2080; + } + +-static int +-Operand_uimm6_encode (uint32 *valp) ++static void ++Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm6_0, uimm6_0; +- uimm6_0 = *valp; +- imm6_0 = (uimm6_0 - 0x4) & 0x3f; +- *valp = imm6_0; +- return 0; ++ slotbuf[0] = 0x3000; + } + +-static int +-Operand_uimm6_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= pc; +- return 0; ++ slotbuf[0] = 0x3200; + } + +-static int +-Operand_uimm6_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += pc; +- return 0; ++ slotbuf[0] = 0x5000; + } + +-static int +-Operand_ai4const_decode (uint32 *valp) ++static void ++Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned ai4const_0, t_0; +- t_0 = *valp & 0xf; +- ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; +- *valp = ai4const_0; +- return 0; ++ slotbuf[0] = 0x5100; + } + +-static int +-Operand_ai4const_encode (uint32 *valp) ++static void ++Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) + { +- unsigned t_0, ai4const_0; +- ai4const_0 = *valp; +- switch (ai4const_0) +- { +- case 0xffffffff: t_0 = 0; break; +- case 0x1: t_0 = 0x1; break; +- case 0x2: t_0 = 0x2; break; +- case 0x3: t_0 = 0x3; break; +- case 0x4: t_0 = 0x4; break; +- case 0x5: t_0 = 0x5; break; +- case 0x6: t_0 = 0x6; break; +- case 0x7: t_0 = 0x7; break; +- case 0x8: t_0 = 0x8; break; +- case 0x9: t_0 = 0x9; break; +- case 0xa: t_0 = 0xa; break; +- case 0xb: t_0 = 0xb; break; +- case 0xc: t_0 = 0xc; break; +- case 0xd: t_0 = 0xd; break; +- case 0xe: t_0 = 0xe; break; +- default: t_0 = 0xf; break; +- } +- *valp = t_0; +- return 0; ++ slotbuf[0] = 0xa; + } + +-static int +-Operand_b4const_decode (uint32 *valp) ++static void ++Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) + { +- unsigned b4const_0, r_0; +- r_0 = *valp & 0xf; +- b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; +- *valp = b4const_0; +- return 0; ++ slotbuf[0] = 0xb; + } + +-static int +-Operand_b4const_encode (uint32 *valp) ++static void ++Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) + { +- unsigned r_0, b4const_0; +- b4const_0 = *valp; +- switch (b4const_0) +- { +- case 0xffffffff: r_0 = 0; break; +- case 0x1: r_0 = 0x1; break; +- case 0x2: r_0 = 0x2; break; +- case 0x3: r_0 = 0x3; break; +- case 0x4: r_0 = 0x4; break; +- case 0x5: r_0 = 0x5; break; +- case 0x6: r_0 = 0x6; break; +- case 0x7: r_0 = 0x7; break; +- case 0x8: r_0 = 0x8; break; +- case 0xa: r_0 = 0x9; break; +- case 0xc: r_0 = 0xa; break; +- case 0x10: r_0 = 0xb; break; +- case 0x20: r_0 = 0xc; break; +- case 0x40: r_0 = 0xd; break; +- case 0x80: r_0 = 0xe; break; +- default: r_0 = 0xf; break; +- } +- *valp = r_0; +- return 0; ++ slotbuf[0] = 0x8c; + } + +-static int +-Operand_b4constu_decode (uint32 *valp) ++static void ++Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) + { +- unsigned b4constu_0, r_0; +- r_0 = *valp & 0xf; +- b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; +- *valp = b4constu_0; +- return 0; ++ slotbuf[0] = 0xcc; + } + +-static int +-Operand_b4constu_encode (uint32 *valp) ++static void ++Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) + { +- unsigned r_0, b4constu_0; +- b4constu_0 = *valp; +- switch (b4constu_0) +- { +- case 0x8000: r_0 = 0; break; +- case 0x10000: r_0 = 0x1; break; +- case 0x2: r_0 = 0x2; break; +- case 0x3: r_0 = 0x3; break; +- case 0x4: r_0 = 0x4; break; +- case 0x5: r_0 = 0x5; break; +- case 0x6: r_0 = 0x6; break; +- case 0x7: r_0 = 0x7; break; +- case 0x8: r_0 = 0x8; break; +- case 0xa: r_0 = 0x9; break; +- case 0xc: r_0 = 0xa; break; +- case 0x10: r_0 = 0xb; break; +- case 0x20: r_0 = 0xc; break; +- case 0x40: r_0 = 0xd; break; +- case 0x80: r_0 = 0xe; break; +- default: r_0 = 0xf; break; +- } +- *valp = r_0; +- return 0; ++ slotbuf[0] = 0xf06d; + } + +-static int +-Operand_uimm8_decode (uint32 *valp) ++static void ++Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) + { +- unsigned uimm8_0, imm8_0; +- imm8_0 = *valp & 0xff; +- uimm8_0 = imm8_0; +- *valp = uimm8_0; +- return 0; ++ slotbuf[0] = 0x8; + } + +-static int +-Operand_uimm8_encode (uint32 *valp) ++static void ++Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, uimm8_0; +- uimm8_0 = *valp; +- imm8_0 = (uimm8_0 & 0xff); +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0xd; + } + +-static int +-Operand_uimm8x2_decode (uint32 *valp) ++static void ++Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) + { +- unsigned uimm8x2_0, imm8_0; +- imm8_0 = *valp & 0xff; +- uimm8x2_0 = imm8_0 << 1; +- *valp = uimm8x2_0; +- return 0; ++ slotbuf[0] = 0xc; + } + +-static int +-Operand_uimm8x2_encode (uint32 *valp) ++static void ++Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, uimm8x2_0; +- uimm8x2_0 = *valp; +- imm8_0 = ((uimm8x2_0 >> 1) & 0xff); +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0xf03d; + } + +-static int +-Operand_uimm8x4_decode (uint32 *valp) ++static void ++Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) + { +- unsigned uimm8x4_0, imm8_0; +- imm8_0 = *valp & 0xff; +- uimm8x4_0 = imm8_0 << 2; +- *valp = uimm8x4_0; +- return 0; ++ slotbuf[0] = 0xf00d; + } + +-static int +-Operand_uimm8x4_encode (uint32 *valp) ++static void ++Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, uimm8x4_0; +- uimm8x4_0 = *valp; +- imm8_0 = ((uimm8x4_0 >> 2) & 0xff); +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0x9; + } + +-static int +-Operand_uimm4x16_decode (uint32 *valp) ++static void ++Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned uimm4x16_0, op2_0; +- op2_0 = *valp & 0xf; +- uimm4x16_0 = op2_0 << 4; +- *valp = uimm4x16_0; +- return 0; ++ slotbuf[0] = 0xc002; + } + +-static int +-Operand_uimm4x16_encode (uint32 *valp) ++static void ++Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned op2_0, uimm4x16_0; +- uimm4x16_0 = *valp; +- op2_0 = ((uimm4x16_0 >> 4) & 0xf); +- *valp = op2_0; +- return 0; ++ slotbuf[0] = 0xd002; + } + +-static int +-Operand_simm8_decode (uint32 *valp) ++static void ++Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned simm8_0, imm8_0; +- imm8_0 = *valp & 0xff; +- simm8_0 = ((int) imm8_0 << 24) >> 24; +- *valp = simm8_0; +- return 0; ++ slotbuf[0] = 0x800000; + } + +-static int +-Operand_simm8_encode (uint32 *valp) ++static void ++Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, simm8_0; +- simm8_0 = *valp; +- imm8_0 = (simm8_0 & 0xff); +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0xc00000; + } + +-static int +-Operand_simm8x256_decode (uint32 *valp) ++static void ++Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned simm8x256_0, imm8_0; +- imm8_0 = *valp & 0xff; +- simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; +- *valp = simm8x256_0; +- return 0; ++ slotbuf[0] = 0x900000; + } + +-static int +-Operand_simm8x256_encode (uint32 *valp) ++static void ++Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, simm8x256_0; +- simm8x256_0 = *valp; +- imm8_0 = ((simm8x256_0 >> 8) & 0xff); +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0xa00000; + } + +-static int +-Operand_simm12b_decode (uint32 *valp) ++static void ++Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned simm12b_0, imm12b_0; +- imm12b_0 = *valp & 0xfff; +- simm12b_0 = ((int) imm12b_0 << 20) >> 20; +- *valp = simm12b_0; +- return 0; ++ slotbuf[0] = 0xb00000; + } + +-static int +-Operand_simm12b_encode (uint32 *valp) ++static void ++Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm12b_0, simm12b_0; +- simm12b_0 = *valp; +- imm12b_0 = (simm12b_0 & 0xfff); +- *valp = imm12b_0; +- return 0; ++ slotbuf[0] = 0xd00000; + } + +-static int +-Operand_msalp32_decode (uint32 *valp) ++static void ++Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned msalp32_0, sal_0; +- sal_0 = *valp & 0x1f; +- msalp32_0 = 0x20 - sal_0; +- *valp = msalp32_0; +- return 0; ++ slotbuf[0] = 0xe00000; + } + +-static int +-Operand_msalp32_encode (uint32 *valp) ++static void ++Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned sal_0, msalp32_0; +- msalp32_0 = *valp; +- sal_0 = (0x20 - msalp32_0) & 0x1f; +- *valp = sal_0; +- return 0; ++ slotbuf[0] = 0xf00000; + } + +-static int +-Operand_op2p1_decode (uint32 *valp) ++static void ++Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned op2p1_0, op2_0; +- op2_0 = *valp & 0xf; +- op2p1_0 = op2_0 + 0x1; +- *valp = op2p1_0; +- return 0; ++ slotbuf[0] = 0x100000; + } + +-static int +-Operand_op2p1_encode (uint32 *valp) ++static void ++Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned op2_0, op2p1_0; +- op2p1_0 = *valp; +- op2_0 = (op2p1_0 - 0x1) & 0xf; +- *valp = op2_0; +- return 0; ++ slotbuf[0] = 0x200000; + } + +-static int +-Operand_label8_decode (uint32 *valp) ++static void ++Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned label8_0, imm8_0; +- imm8_0 = *valp & 0xff; +- label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); +- *valp = label8_0; +- return 0; ++ slotbuf[0] = 0x300000; + } + +-static int +-Operand_label8_encode (uint32 *valp) ++static void ++Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, label8_0; +- label8_0 = *valp; +- imm8_0 = (label8_0 - 0x4) & 0xff; +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0x26; + } + +-static int +-Operand_label8_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= pc; +- return 0; ++ slotbuf[0] = 0x66; + } + +-static int +-Operand_label8_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += pc; +- return 0; ++ slotbuf[0] = 0xe6; + } + +-static int +-Operand_ulabel8_decode (uint32 *valp) ++static void ++Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned ulabel8_0, imm8_0; +- imm8_0 = *valp & 0xff; +- ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); +- *valp = ulabel8_0; +- return 0; ++ slotbuf[0] = 0xa6; + } + +-static int +-Operand_ulabel8_encode (uint32 *valp) ++static void ++Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, ulabel8_0; +- ulabel8_0 = *valp; +- imm8_0 = (ulabel8_0 - 0x4) & 0xff; +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0x6007; + } + +-static int +-Operand_ulabel8_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= pc; +- return 0; ++ slotbuf[0] = 0xe007; + } + +-static int +-Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += pc; +- return 0; ++ slotbuf[0] = 0xf6; + } + +-static int +-Operand_label12_decode (uint32 *valp) ++static void ++Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned label12_0, imm12_0; +- imm12_0 = *valp & 0xfff; +- label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); +- *valp = label12_0; +- return 0; ++ slotbuf[0] = 0xb6; + } + +-static int +-Operand_label12_encode (uint32 *valp) ++static void ++Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm12_0, label12_0; +- label12_0 = *valp; +- imm12_0 = (label12_0 - 0x4) & 0xfff; +- *valp = imm12_0; +- return 0; ++ slotbuf[0] = 0x1007; + } + +-static int +-Operand_label12_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= pc; +- return 0; ++ slotbuf[0] = 0x9007; + } + +-static int +-Operand_label12_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += pc; +- return 0; ++ slotbuf[0] = 0xa007; + } + +-static int +-Operand_soffset_decode (uint32 *valp) ++static void ++Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned soffset_0, offset_0; +- offset_0 = *valp & 0x3ffff; +- soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); +- *valp = soffset_0; +- return 0; ++ slotbuf[0] = 0x2007; + } + +-static int +-Operand_soffset_encode (uint32 *valp) ++static void ++Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned offset_0, soffset_0; +- soffset_0 = *valp; +- offset_0 = (soffset_0 - 0x4) & 0x3ffff; +- *valp = offset_0; +- return 0; ++ slotbuf[0] = 0xb007; + } + +-static int +-Operand_soffset_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= pc; +- return 0; ++ slotbuf[0] = 0x3007; + } + +-static int +-Operand_soffset_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += pc; +- return 0; ++ slotbuf[0] = 0x8007; + } + +-static int +-Operand_uimm16x4_decode (uint32 *valp) ++static void ++Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned uimm16x4_0, imm16_0; +- imm16_0 = *valp & 0xffff; +- uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; +- *valp = uimm16x4_0; +- return 0; ++ slotbuf[0] = 0x7; + } + +-static int +-Operand_uimm16x4_encode (uint32 *valp) ++static void ++Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm16_0, uimm16x4_0; +- uimm16x4_0 = *valp; +- imm16_0 = (uimm16x4_0 >> 2) & 0xffff; +- *valp = imm16_0; +- return 0; ++ slotbuf[0] = 0x4007; + } + +-static int +-Operand_uimm16x4_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= ((pc + 3) & ~0x3); +- return 0; ++ slotbuf[0] = 0xc007; + } + +-static int +-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += ((pc + 3) & ~0x3); +- return 0; ++ slotbuf[0] = 0x5007; + } + +-static int +-Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0xd007; + } + +-static int +-Operand_mx_encode (uint32 *valp) ++static void ++Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0x3) != 0; +- return error; ++ slotbuf[0] = 0x16; + } + +-static int +-Operand_my_decode (uint32 *valp) ++static void ++Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += 2; +- return 0; ++ slotbuf[0] = 0x56; + } + +-static int +-Operand_my_encode (uint32 *valp) ++static void ++Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); +- *valp = *valp & 1; +- return error; ++ slotbuf[0] = 0xd6; + } + +-static int +-Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x96; + } + +-static int +-Operand_mw_encode (uint32 *valp) ++static void ++Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0x3) != 0; +- return error; ++ slotbuf[0] = 0x5; + } + +-static int +-Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) +-{ +- return 0; +-} +- +-static int +-Operand_mr0_encode (uint32 *valp) ++static void ++Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0x3) != 0; +- return error; ++ slotbuf[0] = 0xc0; + } + +-static int +-Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x40000; + } + +-static int +-Operand_mr1_encode (uint32 *valp) ++static void ++Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0x3) != 0; +- return error; ++ slotbuf[0] = 0; + } + +-static int +-Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x6; + } + +-static int +-Operand_mr2_encode (uint32 *valp) ++static void ++Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0x3) != 0; +- return error; ++ slotbuf[0] = 0xa0; + } + +-static int +-Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x1002; + } + +-static int +-Operand_mr3_encode (uint32 *valp) ++static void ++Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0x3) != 0; +- return error; ++ slotbuf[0] = 0x9002; + } + +-static int +-Operand_immt_decode (uint32 *valp) ++static void ++Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned immt_0, t_0; +- t_0 = *valp & 0xf; +- immt_0 = t_0; +- *valp = immt_0; +- return 0; ++ slotbuf[0] = 0x2002; + } + +-static int +-Operand_immt_encode (uint32 *valp) ++static void ++Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned t_0, immt_0; +- immt_0 = *valp; +- t_0 = immt_0 & 0xf; +- *valp = t_0; +- return 0; ++ slotbuf[0] = 0x1; + } + +-static int +-Operand_imms_decode (uint32 *valp) ++static void ++Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imms_0, s_0; +- s_0 = *valp & 0xf; +- imms_0 = s_0; +- *valp = imms_0; +- return 0; ++ slotbuf[0] = 0x2; + } + +-static int +-Operand_imms_encode (uint32 *valp) ++static void ++Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned s_0, imms_0; +- imms_0 = *valp; +- s_0 = imms_0 & 0xf; +- *valp = s_0; +- return 0; ++ slotbuf[0] = 0xa002; + } + +-static int +-Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x830000; + } + +-static int +-Operand_bt_encode (uint32 *valp) ++static void ++Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0xf) != 0; +- return error; ++ slotbuf[0] = 0x930000; + } + +-static int +-Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0xa30000; + } + +-static int +-Operand_bs_encode (uint32 *valp) ++static void ++Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0xf) != 0; +- return error; ++ slotbuf[0] = 0xb30000; + } + +-static int +-Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x600000; + } + +-static int +-Operand_br_encode (uint32 *valp) ++static void ++Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0xf) != 0; +- return error; ++ slotbuf[0] = 0x600100; + } + +-static int +-Operand_bt2_decode (uint32 *valp) ++static void ++Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 1; +- return 0; ++ slotbuf[0] = 0x20f0; + } + +-static int +-Operand_bt2_encode (uint32 *valp) ++static void ++Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x7 << 1)) != 0; +- *valp = *valp >> 1; +- return error; ++ slotbuf[0] = 0x80; + } + +-static int +-Operand_bs2_decode (uint32 *valp) ++static void ++Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 1; +- return 0; ++ slotbuf[0] = 0x5002; + } + +-static int +-Operand_bs2_encode (uint32 *valp) ++static void ++Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x7 << 1)) != 0; +- *valp = *valp >> 1; +- return error; ++ slotbuf[0] = 0x6002; + } + +-static int +-Operand_br2_decode (uint32 *valp) ++static void ++Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 1; +- return 0; ++ slotbuf[0] = 0x4002; + } + +-static int +-Operand_br2_encode (uint32 *valp) ++static void ++Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x7 << 1)) != 0; +- *valp = *valp >> 1; +- return error; ++ slotbuf[0] = 0x400000; + } + +-static int +-Operand_bt4_decode (uint32 *valp) ++static void ++Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 2; +- return 0; ++ slotbuf[0] = 0x401000; + } + +-static int +-Operand_bt4_encode (uint32 *valp) ++static void ++Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x3 << 2)) != 0; +- *valp = *valp >> 2; +- return error; ++ slotbuf[0] = 0x402000; + } + +-static int +-Operand_bs4_decode (uint32 *valp) ++static void ++Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 2; +- return 0; ++ slotbuf[0] = 0x403000; + } + +-static int +-Operand_bs4_encode (uint32 *valp) ++static void ++Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x3 << 2)) != 0; +- *valp = *valp >> 2; +- return error; ++ slotbuf[0] = 0x404000; + } + +-static int +-Operand_br4_decode (uint32 *valp) ++static void ++Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 2; +- return 0; ++ slotbuf[0] = 0xa10000; + } + +-static int +-Operand_br4_encode (uint32 *valp) ++static void ++Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x3 << 2)) != 0; +- *valp = *valp >> 2; +- return error; ++ slotbuf[0] = 0x810000; + } + +-static int +-Operand_bt8_decode (uint32 *valp) ++static void ++Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 3; +- return 0; ++ slotbuf[0] = 0x910000; + } + +-static int +-Operand_bt8_encode (uint32 *valp) ++static void ++Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x1 << 3)) != 0; +- *valp = *valp >> 3; +- return error; ++ slotbuf[0] = 0xb10000; + } + +-static int +-Operand_bs8_decode (uint32 *valp) ++static void ++Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 3; +- return 0; ++ slotbuf[0] = 0x10000; + } + +-static int +-Operand_bs8_encode (uint32 *valp) ++static void ++Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x1 << 3)) != 0; +- *valp = *valp >> 3; +- return error; ++ slotbuf[0] = 0x210000; + } + +-static int +-Operand_br8_decode (uint32 *valp) ++static void ++Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 3; +- return 0; ++ slotbuf[0] = 0x410000; + } + +-static int +-Operand_br8_encode (uint32 *valp) ++static void ++Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0x1 << 3)) != 0; +- *valp = *valp >> 3; +- return error; ++ slotbuf[0] = 0x20c0; + } + +-static int +-Operand_bt16_decode (uint32 *valp) ++static void ++Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 4; +- return 0; ++ slotbuf[0] = 0x20d0; + } + +-static int +-Operand_bt16_encode (uint32 *valp) ++static void ++Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0 << 4)) != 0; +- *valp = *valp >> 4; +- return error; ++ slotbuf[0] = 0x2000; + } + +-static int +-Operand_bs16_decode (uint32 *valp) ++static void ++Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 4; +- return 0; ++ slotbuf[0] = 0x2010; + } + +-static int +-Operand_bs16_encode (uint32 *valp) ++static void ++Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0 << 4)) != 0; +- *valp = *valp >> 4; +- return error; ++ slotbuf[0] = 0x2020; + } + +-static int +-Operand_br16_decode (uint32 *valp) ++static void ++Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 4; +- return 0; ++ slotbuf[0] = 0x2030; + } + +-static int +-Operand_br16_encode (uint32 *valp) ++static void ++Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0 << 4)) != 0; +- *valp = *valp >> 4; +- return error; ++ slotbuf[0] = 0x6000; + } + +-static int +-Operand_brall_decode (uint32 *valp) ++static void ++Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp = *valp << 4; +- return 0; ++ slotbuf[0] = 0x30300; + } + +-static int +-Operand_brall_encode (uint32 *valp) ++static void ++Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~(0 << 4)) != 0; +- *valp = *valp >> 4; +- return error; ++ slotbuf[0] = 0x130300; + } + +-static int +-Operand_tp7_decode (uint32 *valp) ++static void ++Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned tp7_0, t_0; +- t_0 = *valp & 0xf; +- tp7_0 = t_0 + 0x7; +- *valp = tp7_0; +- return 0; ++ slotbuf[0] = 0x610300; + } + +-static int +-Operand_tp7_encode (uint32 *valp) ++static void ++Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned t_0, tp7_0; +- tp7_0 = *valp; +- t_0 = (tp7_0 - 0x7) & 0xf; +- *valp = t_0; +- return 0; ++ slotbuf[0] = 0x30500; + } + +-static int +-Operand_xt_wbr15_label_decode (uint32 *valp) ++static void ++Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned xt_wbr15_label_0, xt_wbr15_imm_0; +- xt_wbr15_imm_0 = *valp & 0x7fff; +- xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); +- *valp = xt_wbr15_label_0; +- return 0; ++ slotbuf[0] = 0x130500; + } + +-static int +-Operand_xt_wbr15_label_encode (uint32 *valp) ++static void ++Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned xt_wbr15_imm_0, xt_wbr15_label_0; +- xt_wbr15_label_0 = *valp; +- xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; +- *valp = xt_wbr15_imm_0; +- return 0; ++ slotbuf[0] = 0x610500; + } + +-static int +-Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= pc; +- return 0; ++ slotbuf[0] = 0x3b000; + } + +-static int +-Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += pc; +- return 0; ++ slotbuf[0] = 0x13b000; + } + +-static int +-Operand_xt_wbr18_label_decode (uint32 *valp) ++static void ++Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned xt_wbr18_label_0, xt_wbr18_imm_0; +- xt_wbr18_imm_0 = *valp & 0x3ffff; +- xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); +- *valp = xt_wbr18_label_0; +- return 0; ++ slotbuf[0] = 0x3d000; + } + +-static int +-Operand_xt_wbr18_label_encode (uint32 *valp) ++static void ++Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned xt_wbr18_imm_0, xt_wbr18_label_0; +- xt_wbr18_label_0 = *valp; +- xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; +- *valp = xt_wbr18_imm_0; +- return 0; ++ slotbuf[0] = 0x3e600; + } + +-static int +-Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) ++static void ++Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp -= pc; +- return 0; ++ slotbuf[0] = 0x13e600; + } + +-static int +-Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) ++static void ++Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- *valp += pc; +- return 0; ++ slotbuf[0] = 0x61e600; + } + +-static int +-Operand_cimm8x4_decode (uint32 *valp) ++static void ++Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned cimm8x4_0, imm8_0; +- imm8_0 = *valp & 0xff; +- cimm8x4_0 = (imm8_0 << 2) | 0; +- *valp = cimm8x4_0; +- return 0; ++ slotbuf[0] = 0x3b100; + } + +-static int +-Operand_cimm8x4_encode (uint32 *valp) ++static void ++Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- unsigned imm8_0, cimm8x4_0; +- cimm8x4_0 = *valp; +- imm8_0 = (cimm8x4_0 >> 2) & 0xff; +- *valp = imm8_0; +- return 0; ++ slotbuf[0] = 0x13b100; + } + +-static int +-Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x61b100; + } + +-static int +-Operand_frr_encode (uint32 *valp) ++static void ++Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0xf) != 0; +- return error; ++ slotbuf[0] = 0x3d100; + } + +-static int +-Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x13d100; + } + +-static int +-Operand_frs_encode (uint32 *valp) ++static void ++Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0xf) != 0; +- return error; ++ slotbuf[0] = 0x61d100; + } + +-static int +-Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED) ++static void ++Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- return 0; ++ slotbuf[0] = 0x3b200; + } + +-static int +-Operand_frt_encode (uint32 *valp) ++static void ++Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) + { +- int error; +- error = (*valp & ~0xf) != 0; +- return error; ++ slotbuf[0] = 0x13b200; + } + +-static xtensa_operand_internal operands[] = { +- { "soffsetx4", 10, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_soffsetx4_encode, Operand_soffsetx4_decode, +- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, +- { "uimm12x8", 3, -1, 0, +- 0, +- Operand_uimm12x8_encode, Operand_uimm12x8_decode, +- 0, 0 }, +- { "simm4", 26, -1, 0, +- 0, +- Operand_simm4_encode, Operand_simm4_decode, +- 0, 0 }, +- { "arr", 14, 0, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_arr_encode, Operand_arr_decode, +- 0, 0 }, +- { "ars", 5, 0, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_ars_encode, Operand_ars_decode, +- 0, 0 }, +- { "*ars_invisible", 5, 0, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_ars_encode, Operand_ars_decode, +- 0, 0 }, +- { "art", 0, 0, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_art_encode, Operand_art_decode, +- 0, 0 }, +- { "ar0", 123, 0, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_ar0_encode, Operand_ar0_decode, +- 0, 0 }, +- { "ar4", 124, 0, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_ar4_encode, Operand_ar4_decode, +- 0, 0 }, +- { "ar8", 125, 0, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_ar8_encode, Operand_ar8_decode, +- 0, 0 }, +- { "ar12", 126, 0, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_ar12_encode, Operand_ar12_decode, +- 0, 0 }, +- { "ars_entry", 5, 0, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_ars_entry_encode, Operand_ars_entry_decode, +- 0, 0 }, +- { "immrx4", 14, -1, 0, +- 0, +- Operand_immrx4_encode, Operand_immrx4_decode, +- 0, 0 }, +- { "lsi4x4", 14, -1, 0, +- 0, +- Operand_lsi4x4_encode, Operand_lsi4x4_decode, +- 0, 0 }, +- { "simm7", 34, -1, 0, +- 0, +- Operand_simm7_encode, Operand_simm7_decode, +- 0, 0 }, +- { "uimm6", 33, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_uimm6_encode, Operand_uimm6_decode, +- Operand_uimm6_ator, Operand_uimm6_rtoa }, +- { "ai4const", 0, -1, 0, +- 0, +- Operand_ai4const_encode, Operand_ai4const_decode, +- 0, 0 }, +- { "b4const", 14, -1, 0, +- 0, +- Operand_b4const_encode, Operand_b4const_decode, +- 0, 0 }, +- { "b4constu", 14, -1, 0, +- 0, +- Operand_b4constu_encode, Operand_b4constu_decode, +- 0, 0 }, +- { "uimm8", 4, -1, 0, +- 0, +- Operand_uimm8_encode, Operand_uimm8_decode, +- 0, 0 }, +- { "uimm8x2", 4, -1, 0, +- 0, +- Operand_uimm8x2_encode, Operand_uimm8x2_decode, +- 0, 0 }, +- { "uimm8x4", 4, -1, 0, +- 0, +- Operand_uimm8x4_encode, Operand_uimm8x4_decode, +- 0, 0 }, +- { "uimm4x16", 13, -1, 0, +- 0, +- Operand_uimm4x16_encode, Operand_uimm4x16_decode, +- 0, 0 }, +- { "simm8", 4, -1, 0, +- 0, +- Operand_simm8_encode, Operand_simm8_decode, +- 0, 0 }, +- { "simm8x256", 4, -1, 0, +- 0, +- Operand_simm8x256_encode, Operand_simm8x256_decode, +- 0, 0 }, +- { "simm12b", 6, -1, 0, +- 0, +- Operand_simm12b_encode, Operand_simm12b_decode, +- 0, 0 }, +- { "msalp32", 18, -1, 0, +- 0, +- Operand_msalp32_encode, Operand_msalp32_decode, +- 0, 0 }, +- { "op2p1", 13, -1, 0, +- 0, +- Operand_op2p1_encode, Operand_op2p1_decode, +- 0, 0 }, +- { "label8", 4, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_label8_encode, Operand_label8_decode, +- Operand_label8_ator, Operand_label8_rtoa }, +- { "ulabel8", 4, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_ulabel8_encode, Operand_ulabel8_decode, +- Operand_ulabel8_ator, Operand_ulabel8_rtoa }, +- { "label12", 3, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_label12_encode, Operand_label12_decode, +- Operand_label12_ator, Operand_label12_rtoa }, +- { "soffset", 10, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_soffset_encode, Operand_soffset_decode, +- Operand_soffset_ator, Operand_soffset_rtoa }, +- { "uimm16x4", 7, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_uimm16x4_encode, Operand_uimm16x4_decode, +- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, +- { "mx", 43, 1, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, +- Operand_mx_encode, Operand_mx_decode, +- 0, 0 }, +- { "my", 42, 1, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, +- Operand_my_encode, Operand_my_decode, +- 0, 0 }, +- { "mw", 41, 1, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_mw_encode, Operand_mw_decode, +- 0, 0 }, +- { "mr0", 127, 1, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_mr0_encode, Operand_mr0_decode, +- 0, 0 }, +- { "mr1", 128, 1, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_mr1_encode, Operand_mr1_decode, +- 0, 0 }, +- { "mr2", 129, 1, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_mr2_encode, Operand_mr2_decode, +- 0, 0 }, +- { "mr3", 130, 1, 1, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_mr3_encode, Operand_mr3_decode, +- 0, 0 }, +- { "immt", 0, -1, 0, +- 0, +- Operand_immt_encode, Operand_immt_decode, +- 0, 0 }, +- { "imms", 5, -1, 0, +- 0, +- Operand_imms_encode, Operand_imms_decode, +- 0, 0 }, +- { "bt", 0, 2, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bt_encode, Operand_bt_decode, +- 0, 0 }, +- { "bs", 5, 2, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bs_encode, Operand_bs_decode, +- 0, 0 }, +- { "br", 14, 2, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_br_encode, Operand_br_decode, +- 0, 0 }, +- { "bt2", 44, 2, 2, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bt2_encode, Operand_bt2_decode, +- 0, 0 }, +- { "bs2", 45, 2, 2, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bs2_encode, Operand_bs2_decode, +- 0, 0 }, +- { "br2", 46, 2, 2, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_br2_encode, Operand_br2_decode, +- 0, 0 }, +- { "bt4", 47, 2, 4, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bt4_encode, Operand_bt4_decode, +- 0, 0 }, +- { "bs4", 48, 2, 4, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bs4_encode, Operand_bs4_decode, +- 0, 0 }, +- { "br4", 49, 2, 4, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_br4_encode, Operand_br4_decode, +- 0, 0 }, +- { "bt8", 50, 2, 8, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bt8_encode, Operand_bt8_decode, +- 0, 0 }, +- { "bs8", 51, 2, 8, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bs8_encode, Operand_bs8_decode, +- 0, 0 }, +- { "br8", 52, 2, 8, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_br8_encode, Operand_br8_decode, +- 0, 0 }, +- { "bt16", 131, 2, 16, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bt16_encode, Operand_bt16_decode, +- 0, 0 }, +- { "bs16", 132, 2, 16, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_bs16_encode, Operand_bs16_decode, +- 0, 0 }, +- { "br16", 133, 2, 16, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_br16_encode, Operand_br16_decode, +- 0, 0 }, +- { "brall", 134, 2, 16, +- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, +- Operand_brall_encode, Operand_brall_decode, +- 0, 0 }, +- { "tp7", 0, -1, 0, +- 0, +- Operand_tp7_encode, Operand_tp7_decode, +- 0, 0 }, +- { "xt_wbr15_label", 53, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, +- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, +- { "xt_wbr18_label", 54, -1, 0, +- XTENSA_OPERAND_IS_PCRELATIVE, +- Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, +- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, +- { "cimm8x4", 4, -1, 0, +- 0, +- Operand_cimm8x4_encode, Operand_cimm8x4_decode, +- 0, 0 }, +- { "frr", 14, 3, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_frr_encode, Operand_frr_decode, +- 0, 0 }, +- { "frs", 5, 3, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_frs_encode, Operand_frs_decode, +- 0, 0 }, +- { "frt", 0, 3, 1, +- XTENSA_OPERAND_IS_REGISTER, +- Operand_frt_encode, Operand_frt_decode, +- 0, 0 }, +- { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, +- { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, +- { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, +- { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, +- { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, +- { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, +- { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, +- { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, +- { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, +- { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, +- { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, +- { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, +- { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, +- { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, +- { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, +- { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, +- { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, +- { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, +- { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, +- { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, +- { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, +- { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, +- { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, +- { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, +- { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, +- { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, +- { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, +- { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, +- { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, +- { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, +- { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, +- { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, +- { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, +- { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, +- { "t2", 44, -1, 0, 0, 0, 0, 0, 0 }, +- { "s2", 45, -1, 0, 0, 0, 0, 0, 0 }, +- { "r2", 46, -1, 0, 0, 0, 0, 0, 0 }, +- { "t4", 47, -1, 0, 0, 0, 0, 0, 0 }, +- { "s4", 48, -1, 0, 0, 0, 0, 0, 0 }, +- { "r4", 49, -1, 0, 0, 0, 0, 0, 0 }, +- { "t8", 50, -1, 0, 0, 0, 0, 0, 0 }, +- { "s8", 51, -1, 0, 0, 0, 0, 0, 0 }, +- { "r8", 52, -1, 0, 0, 0, 0, 0, 0 }, +- { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 }, +- { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 }, +- { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 }, +- { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 }, +- { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 }, +- { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 }, +- { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 }, +- { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 } +-}; +- +- +-/* Iclass table. */ ++static void ++Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { +- { { STATE_PSRING }, 'i' }, +- { { STATE_PSEXCM }, 'm' }, +- { { STATE_EPC1 }, 'i' } +-}; ++static void ++Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DEPC }, 'i' } +-}; ++static void ++Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { +- { { 0 /* soffsetx4 */ }, 'i' }, +- { { 10 /* ar12 */ }, 'o' } +-}; ++static void ++Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { +- { { STATE_PSCALLINC }, 'o' } +-}; ++static void ++Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3b300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { +- { { 0 /* soffsetx4 */ }, 'i' }, +- { { 9 /* ar8 */ }, 'o' } +-}; ++static void ++Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13b300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { +- { { STATE_PSCALLINC }, 'o' } +-}; ++static void ++Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61b300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { +- { { 0 /* soffsetx4 */ }, 'i' }, +- { { 8 /* ar4 */ }, 'o' } +-}; ++static void ++Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3d300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { +- { { STATE_PSCALLINC }, 'o' } +-}; ++static void ++Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13d300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 10 /* ar12 */ }, 'o' } +-}; ++static void ++Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61d300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { +- { { STATE_PSCALLINC }, 'o' } +-}; ++static void ++Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 9 /* ar8 */ }, 'o' } +-}; ++static void ++Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { +- { { STATE_PSCALLINC }, 'o' } +-}; ++static void ++Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 8 /* ar4 */ }, 'o' } +-}; ++static void ++Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { +- { { STATE_PSCALLINC }, 'o' } +-}; ++static void ++Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { +- { { 11 /* ars_entry */ }, 's' }, +- { { 4 /* ars */ }, 'i' }, +- { { 1 /* uimm12x8 */ }, 'i' } +-}; ++static void ++Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { +- { { STATE_PSCALLINC }, 'i' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSWOE }, 'i' }, +- { { STATE_WindowBase }, 'm' }, +- { { STATE_WindowStart }, 'm' } +-}; ++static void ++Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ee00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; ++static void ++Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ee00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { +- { { STATE_WindowBase }, 'i' }, +- { { STATE_WindowStart }, 'i' } +-}; ++static void ++Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ee00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { +- { { 2 /* simm4 */ }, 'i' } +-}; ++static void ++Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3c000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowBase }, 'm' } +-}; ++static void ++Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13c000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { +- { { 5 /* *ars_invisible */ }, 'i' } +-}; ++static void ++Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61c000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { +- { { STATE_WindowBase }, 'm' }, +- { { STATE_WindowStart }, 'm' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSWOE }, 'i' } +-}; ++static void ++Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e800; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { +- { { STATE_EPC1 }, 'i' }, +- { { STATE_PSEXCM }, 'm' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowBase }, 'm' }, +- { { STATE_WindowStart }, 'm' }, +- { { STATE_PSOWB }, 'i' } +-}; ++static void ++Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e800; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 12 /* immrx4 */ }, 'i' } +-}; ++static void ++Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e800; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; ++static void ++Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3eb00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 12 /* immrx4 */ }, 'i' } +-}; ++static void ++Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e700; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; ++static void ++Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e700; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { +- { { 6 /* art */ }, 'o' } +-}; ++static void ++Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e700; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowBase }, 'i' } +-}; ++static void ++Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xc10000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { +- { { 6 /* art */ }, 'i' } +-}; ++static void ++Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xd10000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowBase }, 'o' } +-}; ++static void ++Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x820000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { +- { { 6 /* art */ }, 'm' } +-}; ++static void ++Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3010; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowBase }, 'm' } +-}; ++static void ++Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x7000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowStart }, 'i' } +-}; ++static void ++Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { +- { { 6 /* art */ }, 'i' } +-}; ++static void ++Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e200; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowStart }, 'o' } +-}; ++static void ++Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e300; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { +- { { 6 /* art */ }, 'm' } +-}; ++static void ++Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e400; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_WindowStart }, 'm' } +-}; ++static void ++Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e400; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; ++static void ++Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e400; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 16 /* ai4const */ }, 'i' } +-}; ++static void ++Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x4000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 15 /* uimm6 */ }, 'i' } +-}; ++static void ++Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf02d; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 13 /* lsi4x4 */ }, 'i' } +-}; ++static void ++Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x39000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; ++static void ++Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x139000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { +- { { 4 /* ars */ }, 'o' }, +- { { 14 /* simm7 */ }, 'i' } +-}; ++static void ++Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x619000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { +- { { 5 /* *ars_invisible */ }, 'i' } +-}; ++static void ++Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3a000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 13 /* lsi4x4 */ }, 'i' } +-}; ++static void ++Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13a000; ++} + +-static xtensa_arg_internal Iclass_rur_threadptr_args[] = { +- { { 3 /* arr */ }, 'o' } +-}; ++static void ++Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61a000; ++} + +-static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { +- { { STATE_THREADPTR }, 'i' } +-}; ++static void ++Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x38000; ++} + +-static xtensa_arg_internal Iclass_wur_threadptr_args[] = { +- { { 6 /* art */ }, 'i' } +-}; ++static void ++Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x138000; ++} + +-static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { +- { { STATE_THREADPTR }, 'o' } +-}; ++static void ++Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x618000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 23 /* simm8 */ }, 'i' } +-}; ++static void ++Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 24 /* simm8x256 */ }, 'i' } +-}; ++static void ++Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x136000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; ++static void ++Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x616000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; ++static void ++Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3e900; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 17 /* b4const */ }, 'i' }, +- { { 28 /* label8 */ }, 'i' } +-}; ++static void ++Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13e900; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 67 /* bbi */ }, 'i' }, +- { { 28 /* label8 */ }, 'i' } +-}; ++static void ++Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61e900; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 18 /* b4constu */ }, 'i' }, +- { { 28 /* label8 */ }, 'i' } +-}; ++static void ++Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ec00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' }, +- { { 28 /* label8 */ }, 'i' } +-}; ++static void ++Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ec00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 30 /* label12 */ }, 'i' } +-}; ++static void ++Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ec00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { +- { { 0 /* soffsetx4 */ }, 'i' }, +- { { 7 /* ar0 */ }, 'o' } +-}; ++static void ++Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ed00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 7 /* ar0 */ }, 'o' } +-}; ++static void ++Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ed00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 6 /* art */ }, 'i' }, +- { { 82 /* sae */ }, 'i' }, +- { { 27 /* op2p1 */ }, 'i' } +-}; ++static void ++Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ed00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { +- { { 31 /* soffset */ }, 'i' } +-}; ++static void ++Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x36800; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { +- { { 4 /* ars */ }, 'i' } +-}; ++static void ++Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x136800; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 20 /* uimm8x2 */ }, 'i' } +-}; ++static void ++Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x616800; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 20 /* uimm8x2 */ }, 'i' } +-}; ++static void ++Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf1e000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; ++static void ++Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0xf1e010; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 32 /* uimm16x4 */ }, 'i' } +-}; ++static void ++Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x135900; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { +- { { STATE_LITBADDR }, 'i' }, +- { { STATE_LITBEN }, 'i' } +-}; ++static void ++Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3ea00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 19 /* uimm8 */ }, 'i' } +-}; ++static void ++Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13ea00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 29 /* ulabel8 */ }, 'i' } +-}; ++static void ++Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61ea00; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { +- { { STATE_LBEG }, 'o' }, +- { { STATE_LEND }, 'o' }, +- { { STATE_LCOUNT }, 'o' } +-}; ++static void ++Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x3f000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 29 /* ulabel8 */ }, 'i' } +-}; ++static void ++Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x13f000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { +- { { STATE_LBEG }, 'o' }, +- { { STATE_LEND }, 'o' }, +- { { STATE_LCOUNT }, 'o' } +-}; ++static void ++Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x61f000; ++} + +-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 25 /* simm12b */ }, 'i' } ++static void ++Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50c000; ++} ++ ++static void ++Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50d000; ++} ++ ++static void ++Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50b000; ++} ++ ++static void ++Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50f000; ++} ++ ++static void ++Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x50e000; ++} ++ ++static void ++Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x504000; ++} ++ ++static void ++Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x505000; ++} ++ ++static void ++Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x503000; ++} ++ ++static void ++Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x507000; ++} ++ ++static void ++Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x506000; ++} ++ ++static void ++Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x40e000; ++} ++ ++static void ++Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x40f000; ++} ++ ++static void ++Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x406000; ++} ++ ++static void ++Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = 0x407000; ++} ++ ++xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { ++ Opcode_excw_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { +- { { 3 /* arr */ }, 'm' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { ++ Opcode_rfe_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { ++ Opcode_rfde_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { +- { { 5 /* *ars_invisible */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { ++ Opcode_syscall_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 20 /* uimm8x2 */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { ++ Opcode_simcall_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { ++ 0, Opcode_add_n_Slot_inst16a_encode, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 19 /* uimm8 */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { ++ 0, Opcode_addi_n_Slot_inst16a_encode, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { +- { { 4 /* ars */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { ++ 0, 0, Opcode_beqz_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { +- { { STATE_SAR }, 'o' } ++xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { ++ 0, 0, Opcode_bnez_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { +- { { 86 /* sas */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { ++ 0, 0, Opcode_ill_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { +- { { STATE_SAR }, 'o' } ++xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { ++ 0, Opcode_l32i_n_Slot_inst16a_encode, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { ++ 0, 0, Opcode_mov_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { +- { { STATE_SAR }, 'i' } ++xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { ++ 0, 0, Opcode_movi_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { ++ 0, 0, Opcode_nop_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { +- { { STATE_SAR }, 'i' } ++xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { ++ 0, 0, Opcode_ret_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { ++ 0, Opcode_s32i_n_Slot_inst16a_encode, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { +- { { STATE_SAR }, 'i' } ++xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { ++ Opcode_addi_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 26 /* msalp32 */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { ++ Opcode_addmi_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 6 /* art */ }, 'i' }, +- { { 84 /* sargt */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { ++ Opcode_add_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 6 /* art */ }, 'i' }, +- { { 70 /* s */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { ++ Opcode_sub_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { +- { { STATE_XTSYNC }, 'i' } ++xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { ++ Opcode_addx2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 70 /* s */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { ++ Opcode_addx4_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { +- { { STATE_PSWOE }, 'i' }, +- { { STATE_PSCALLINC }, 'i' }, +- { { STATE_PSOWB }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_PSUM }, 'i' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSINTLEVEL }, 'm' } ++xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { ++ Opcode_addx8_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { ++ Opcode_subx2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { +- { { STATE_LEND }, 'i' } ++xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { ++ Opcode_subx4_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { ++ Opcode_subx8_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { +- { { STATE_LEND }, 'o' } ++xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { ++ Opcode_and_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { ++ Opcode_or_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { +- { { STATE_LEND }, 'm' } ++xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { ++ Opcode_xor_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { ++ Opcode_beqi_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { +- { { STATE_LCOUNT }, 'i' } ++xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { ++ Opcode_bnei_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { ++ Opcode_bgei_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_LCOUNT }, 'o' } ++xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { ++ Opcode_blti_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { ++ Opcode_bbci_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_LCOUNT }, 'm' } ++xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { ++ Opcode_bbsi_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { ++ Opcode_bgeui_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { +- { { STATE_LBEG }, 'i' } ++xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { ++ Opcode_bltui_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { ++ Opcode_beq_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { +- { { STATE_LBEG }, 'o' } ++xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { ++ Opcode_bne_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { ++ Opcode_bge_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { +- { { STATE_LBEG }, 'm' } ++xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { ++ Opcode_blt_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { ++ Opcode_bgeu_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { +- { { STATE_SAR }, 'i' } ++xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { ++ Opcode_bltu_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { ++ Opcode_bany_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { +- { { STATE_SAR }, 'o' }, +- { { STATE_XTSYNC }, 'o' } ++xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { ++ Opcode_bnone_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { ++ Opcode_ball_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { +- { { STATE_SAR }, 'm' } ++xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { ++ Opcode_bnall_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { ++ Opcode_bbc_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { +- { { STATE_LITBADDR }, 'i' }, +- { { STATE_LITBEN }, 'i' } ++xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { ++ Opcode_bbs_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { ++ Opcode_beqz_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { +- { { STATE_LITBADDR }, 'o' }, +- { { STATE_LITBEN }, 'o' } ++xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { ++ Opcode_bnez_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { ++ Opcode_bgez_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { +- { { STATE_LITBADDR }, 'm' }, +- { { STATE_LITBEN }, 'm' } ++xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { ++ Opcode_bltz_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { ++ Opcode_call0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } ++xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { ++ Opcode_callx0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { ++ Opcode_extui_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } ++xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { ++ Opcode_ill_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { ++ Opcode_j_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { +- { { STATE_PSWOE }, 'i' }, +- { { STATE_PSCALLINC }, 'i' }, +- { { STATE_PSOWB }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_PSUM }, 'i' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSINTLEVEL }, 'i' } ++xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { ++ Opcode_jx_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { ++ Opcode_l16ui_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { +- { { STATE_PSWOE }, 'o' }, +- { { STATE_PSCALLINC }, 'o' }, +- { { STATE_PSOWB }, 'o' }, +- { { STATE_PSRING }, 'm' }, +- { { STATE_PSUM }, 'o' }, +- { { STATE_PSEXCM }, 'm' }, +- { { STATE_PSINTLEVEL }, 'o' } ++xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { ++ Opcode_l16si_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { ++ Opcode_l32i_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { +- { { STATE_PSWOE }, 'm' }, +- { { STATE_PSCALLINC }, 'm' }, +- { { STATE_PSOWB }, 'm' }, +- { { STATE_PSRING }, 'm' }, +- { { STATE_PSUM }, 'm' }, +- { { STATE_PSEXCM }, 'm' }, +- { { STATE_PSINTLEVEL }, 'm' } ++xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { ++ Opcode_l32r_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { ++ Opcode_l8ui_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC1 }, 'i' } ++xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { ++ Opcode_movi_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { ++ Opcode_moveqz_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC1 }, 'o' } ++xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { ++ Opcode_movnez_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { ++ Opcode_movltz_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC1 }, 'm' } ++xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { ++ Opcode_movgez_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { ++ Opcode_neg_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE1 }, 'i' } ++xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { ++ Opcode_abs_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { ++ Opcode_nop_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE1 }, 'o' } ++xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { ++ Opcode_ret_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { ++ Opcode_s16i_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE1 }, 'm' } ++xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { ++ Opcode_s32i_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { ++ Opcode_s8i_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC2 }, 'i' } ++xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { ++ Opcode_ssr_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { ++ Opcode_ssl_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC2 }, 'o' } ++xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { ++ Opcode_ssa8l_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { ++ Opcode_ssa8b_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC2 }, 'm' } ++xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { ++ Opcode_ssai_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { ++ Opcode_sll_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE2 }, 'i' } ++xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { ++ Opcode_src_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { ++ Opcode_srl_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE2 }, 'o' } ++xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { ++ Opcode_sra_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { ++ Opcode_slli_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE2 }, 'm' } ++xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { ++ Opcode_srai_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { ++ Opcode_srli_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC3 }, 'i' } ++xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { ++ Opcode_memw_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { ++ Opcode_extw_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC3 }, 'o' } ++xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { ++ Opcode_isync_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { ++ Opcode_rsync_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC3 }, 'm' } ++xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { ++ Opcode_esync_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { ++ Opcode_dsync_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE3 }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { ++ Opcode_rsil_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { ++ Opcode_rsr_sar_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE3 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { ++ Opcode_wsr_sar_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { ++ Opcode_xsr_sar_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE3 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { ++ Opcode_rsr_litbase_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { ++ Opcode_wsr_litbase_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC4 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { ++ Opcode_xsr_litbase_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { ++ Opcode_rsr_176_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC4 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { ++ Opcode_wsr_176_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { ++ Opcode_rsr_208_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC4 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { ++ Opcode_rsr_ps_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { ++ Opcode_wsr_ps_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE4 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { ++ Opcode_xsr_ps_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { ++ Opcode_rsr_epc1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE4 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { ++ Opcode_wsr_epc1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { ++ Opcode_xsr_epc1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE4 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { ++ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { ++ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC5 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { ++ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { ++ Opcode_rsr_epc2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC5 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { ++ Opcode_wsr_epc2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { ++ Opcode_xsr_epc2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC5 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { ++ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { ++ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE5 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { ++ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { ++ Opcode_rsr_epc3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE5 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { ++ Opcode_wsr_epc3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { ++ Opcode_xsr_epc3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE5 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { ++ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { ++ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC6 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { ++ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { ++ Opcode_rsr_eps2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC6 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { ++ Opcode_wsr_eps2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { ++ Opcode_xsr_eps2_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC6 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { ++ Opcode_rsr_eps3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { ++ Opcode_wsr_eps3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE6 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { ++ Opcode_xsr_eps3_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { ++ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE6 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { ++ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { ++ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE6 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { ++ Opcode_rsr_depc_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { ++ Opcode_wsr_depc_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC7 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { ++ Opcode_xsr_depc_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { ++ Opcode_rsr_exccause_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC7 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { ++ Opcode_wsr_exccause_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { ++ Opcode_xsr_exccause_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPC7 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { ++ Opcode_rsr_prid_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { ++ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE7 }, 'i' } ++xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { ++ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { ++ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE7 }, 'o' } ++xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { ++ Opcode_mul16u_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { ++ Opcode_mul16s_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCSAVE7 }, 'm' } ++xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { ++ Opcode_mull_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { ++ Opcode_rfi_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS2 }, 'i' } ++xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { ++ Opcode_waiti_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { ++ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS2 }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { ++ Opcode_wsr_intset_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { ++ Opcode_wsr_intclear_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS2 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { ++ Opcode_rsr_intenable_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { ++ Opcode_wsr_intenable_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS3 }, 'i' } ++xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { ++ Opcode_xsr_intenable_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { ++ Opcode_break_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS3 }, 'o' } ++xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { ++ 0, 0, Opcode_break_n_Slot_inst16b_encode + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { ++ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS3 }, 'm' } ++xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { ++ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { ++ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS4 }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { ++ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { ++ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS4 }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { ++ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { ++ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS4 }, 'm' } ++xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { ++ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { ++ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS5 }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { ++ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { ++ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS5 }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { ++ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { ++ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS5 }, 'm' } ++xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { ++ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { ++ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS6 }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { ++ Opcode_rsr_icount_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { ++ Opcode_wsr_icount_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS6 }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { ++ Opcode_xsr_icount_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { ++ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS6 }, 'm' } ++xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { ++ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { ++ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS7 }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { ++ Opcode_rsr_ddr_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { ++ Opcode_wsr_ddr_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS7 }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { ++ Opcode_xsr_ddr_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { ++ Opcode_rfdo_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EPS7 }, 'm' } ++xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { ++ Opcode_rfdd_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { ++ Opcode_wsr_mmid_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCVADDR }, 'i' } ++xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { ++ Opcode_rsr_ccount_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { ++ Opcode_wsr_ccount_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCVADDR }, 'o' } ++xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { ++ Opcode_xsr_ccount_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { ++ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCVADDR }, 'm' } ++xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { ++ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DEPC }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DEPC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DEPC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCCAUSE }, 'i' }, +- { { STATE_XTSYNC }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCCAUSE }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_EXCCAUSE }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC0 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC0 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC0 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC1 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC1 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC2 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC2 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC2 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC3 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC3 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_MISC3 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_VECBASE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_VECBASE }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_VECBASE }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { +- { { STATE_ACC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 34 /* my */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { +- { { STATE_ACC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { +- { { 33 /* mx */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { +- { { STATE_ACC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { +- { { 33 /* mx */ }, 'i' }, +- { { 34 /* my */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { +- { { STATE_ACC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { +- { { STATE_ACC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 34 /* my */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { +- { { STATE_ACC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { +- { { 33 /* mx */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { +- { { STATE_ACC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { +- { { 33 /* mx */ }, 'i' }, +- { { 34 /* my */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { +- { { STATE_ACC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { +- { { 35 /* mw */ }, 'o' }, +- { { 4 /* ars */ }, 'm' }, +- { { 33 /* mx */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { +- { { STATE_ACC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { +- { { 35 /* mw */ }, 'o' }, +- { { 4 /* ars */ }, 'm' }, +- { { 33 /* mx */ }, 'i' }, +- { { 34 /* my */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { +- { { STATE_ACC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { +- { { 35 /* mw */ }, 'o' }, +- { { 4 /* ars */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 36 /* mr0 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 36 /* mr0 */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { +- { { 6 /* art */ }, 'm' }, +- { { 36 /* mr0 */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 37 /* mr1 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 37 /* mr1 */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { +- { { 6 /* art */ }, 'm' }, +- { { 37 /* mr1 */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 38 /* mr2 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 38 /* mr2 */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { +- { { 6 /* art */ }, 'm' }, +- { { 38 /* mr2 */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 39 /* mr3 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 39 /* mr3 */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { +- { { 6 /* art */ }, 'm' }, +- { { 39 /* mr3 */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { +- { { STATE_ACC }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { +- { { STATE_ACC }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { ++ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { +- { { STATE_ACC }, 'm' } ++xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { ++ Opcode_idtlb_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { ++ Opcode_pdtlb_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { +- { { STATE_ACC }, 'i' } ++xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { ++ Opcode_rdtlb0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { ++ Opcode_rdtlb1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { +- { { STATE_ACC }, 'm' } ++xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { ++ Opcode_wdtlb_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { +- { { 6 /* art */ }, 'm' } ++xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { ++ Opcode_iitlb_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { +- { { STATE_ACC }, 'm' } ++xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { ++ Opcode_pitlb_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { +- { { 70 /* s */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { ++ Opcode_ritlb0_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { +- { { STATE_PSWOE }, 'o' }, +- { { STATE_PSCALLINC }, 'o' }, +- { { STATE_PSOWB }, 'o' }, +- { { STATE_PSRING }, 'm' }, +- { { STATE_PSUM }, 'o' }, +- { { STATE_PSEXCM }, 'm' }, +- { { STATE_PSINTLEVEL }, 'o' }, +- { { STATE_EPC1 }, 'i' }, +- { { STATE_EPC2 }, 'i' }, +- { { STATE_EPC3 }, 'i' }, +- { { STATE_EPC4 }, 'i' }, +- { { STATE_EPC5 }, 'i' }, +- { { STATE_EPC6 }, 'i' }, +- { { STATE_EPC7 }, 'i' }, +- { { STATE_EPS2 }, 'i' }, +- { { STATE_EPS3 }, 'i' }, +- { { STATE_EPS4 }, 'i' }, +- { { STATE_EPS5 }, 'i' }, +- { { STATE_EPS6 }, 'i' }, +- { { STATE_EPS7 }, 'i' }, +- { { STATE_InOCDMode }, 'm' } ++xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { ++ Opcode_ritlb1_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { +- { { 70 /* s */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { ++ Opcode_witlb_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_PSINTLEVEL }, 'o' } ++xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { ++ Opcode_nsa_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { +- { { 6 /* art */ }, 'o' } ++xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { ++ Opcode_nsau_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_INTERRUPT }, 'i' } ++xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { ++ Opcode_rer_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { +- { { 6 /* art */ }, 'i' } ++xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { ++ Opcode_wer_Slot_inst_encode, 0, 0 + }; + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_INTERRUPT }, 'm' } +-}; ++ ++/* Opcode table. */ + +-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_INTERRUPT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_INTENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_INTENABLE }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_INTENABLE }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { +- { { 41 /* imms */ }, 'i' }, +- { { 40 /* immt */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSINTLEVEL }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { +- { { 41 /* imms */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSINTLEVEL }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKA0 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKA0 }, 'o' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKA0 }, 'm' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKC0 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKC0 }, 'o' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKC0 }, 'm' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKA1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKA1 }, 'o' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKA1 }, 'm' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKC1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKC1 }, 'o' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DBREAKC1 }, 'm' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKA0 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKA0 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKA0 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKA1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKA1 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKA1 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKENABLE }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_IBREAKENABLE }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DEBUGCAUSE }, 'i' }, +- { { STATE_DBNUM }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DEBUGCAUSE }, 'o' }, +- { { STATE_DBNUM }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DEBUGCAUSE }, 'm' }, +- { { STATE_DBNUM }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_ICOUNT }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_ICOUNT }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_ICOUNT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_ICOUNTLEVEL }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_ICOUNTLEVEL }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_ICOUNTLEVEL }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DDR }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_DDR }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_DDR }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { +- { { 41 /* imms */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { +- { { STATE_InOCDMode }, 'm' }, +- { { STATE_EPC6 }, 'i' }, +- { { STATE_PSWOE }, 'o' }, +- { { STATE_PSCALLINC }, 'o' }, +- { { STATE_PSOWB }, 'o' }, +- { { STATE_PSRING }, 'o' }, +- { { STATE_PSUM }, 'o' }, +- { { STATE_PSEXCM }, 'o' }, +- { { STATE_PSINTLEVEL }, 'o' }, +- { { STATE_EPS6 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { +- { { STATE_InOCDMode }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { +- { { 44 /* br */ }, 'o' }, +- { { 43 /* bs */ }, 'i' }, +- { { 42 /* bt */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { +- { { 42 /* bt */ }, 'o' }, +- { { 49 /* bs4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { +- { { 42 /* bt */ }, 'o' }, +- { { 52 /* bs8 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { +- { { 43 /* bs */ }, 'i' }, +- { { 28 /* label8 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { +- { { 3 /* arr */ }, 'm' }, +- { { 4 /* ars */ }, 'i' }, +- { { 42 /* bt */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 57 /* brall */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 57 /* brall */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { +- { { 6 /* art */ }, 'm' }, +- { { 57 /* brall */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOUNT }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_CCOUNT }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_CCOUNT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE0 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE0 }, 'o' }, +- { { STATE_INTERRUPT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE0 }, 'm' }, +- { { STATE_INTERRUPT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE1 }, 'o' }, +- { { STATE_INTERRUPT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE1 }, 'm' }, +- { { STATE_INTERRUPT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE2 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE2 }, 'o' }, +- { { STATE_INTERRUPT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CCOMPARE2 }, 'm' }, +- { { STATE_INTERRUPT }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 22 /* uimm4x16 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 22 /* uimm4x16 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 22 /* uimm4x16 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_PTBASE }, 'o' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_PTBASE }, 'i' }, +- { { STATE_EXCVADDR }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_PTBASE }, 'm' }, +- { { STATE_EXCVADDR }, 'i' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_ASID3 }, 'i' }, +- { { STATE_ASID2 }, 'i' }, +- { { STATE_ASID1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_ASID3 }, 'o' }, +- { { STATE_ASID2 }, 'o' }, +- { { STATE_ASID1 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_ASID3 }, 'm' }, +- { { STATE_ASID2 }, 'm' }, +- { { STATE_ASID1 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_INSTPGSZID4 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_INSTPGSZID4 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_INSTPGSZID4 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DATAPGSZID4 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DATAPGSZID4 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { +- { { STATE_XTSYNC }, 'o' }, +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_DATAPGSZID4 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_XTSYNC }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { +- { { STATE_PTBASE }, 'i' }, +- { { STATE_EXCVADDR }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { +- { { STATE_EXCVADDR }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { +- { { STATE_EXCVADDR }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CPENABLE }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { +- { { STATE_PSEXCM }, 'i' }, +- { { STATE_PSRING }, 'i' }, +- { { STATE_CPENABLE }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 58 /* tp7 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 58 /* tp7 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { +- { { 6 /* art */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { +- { { 6 /* art */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { +- { { 6 /* art */ }, 'm' }, +- { { 4 /* ars */ }, 'i' }, +- { { 21 /* uimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { +- { { STATE_SCOMPARE1 }, 'i' }, +- { { STATE_SCOMPARE1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { +- { { 6 /* art */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { +- { { STATE_SCOMPARE1 }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { +- { { STATE_SCOMPARE1 }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { +- { { 6 /* art */ }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { +- { { STATE_SCOMPARE1 }, 'm' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_mul32_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_rur_fcr_args[] = { +- { { 3 /* arr */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { +- { { STATE_RoundMode }, 'i' }, +- { { STATE_InvalidEnable }, 'i' }, +- { { STATE_DivZeroEnable }, 'i' }, +- { { STATE_OverflowEnable }, 'i' }, +- { { STATE_UnderflowEnable }, 'i' }, +- { { STATE_InexactEnable }, 'i' }, +- { { STATE_FPreserved20 }, 'i' }, +- { { STATE_FPreserved5 }, 'i' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_wur_fcr_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { +- { { STATE_RoundMode }, 'o' }, +- { { STATE_InvalidEnable }, 'o' }, +- { { STATE_DivZeroEnable }, 'o' }, +- { { STATE_OverflowEnable }, 'o' }, +- { { STATE_UnderflowEnable }, 'o' }, +- { { STATE_InexactEnable }, 'o' }, +- { { STATE_FPreserved20 }, 'o' }, +- { { STATE_FPreserved5 }, 'o' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_rur_fsr_args[] = { +- { { 3 /* arr */ }, 'o' } +-}; +- +-static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { +- { { STATE_InvalidFlag }, 'i' }, +- { { STATE_DivZeroFlag }, 'i' }, +- { { STATE_OverflowFlag }, 'i' }, +- { { STATE_UnderflowFlag }, 'i' }, +- { { STATE_InexactFlag }, 'i' }, +- { { STATE_FPreserved20a }, 'i' }, +- { { STATE_FPreserved7 }, 'i' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_wur_fsr_args[] = { +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { +- { { STATE_InvalidFlag }, 'o' }, +- { { STATE_DivZeroFlag }, 'o' }, +- { { STATE_OverflowFlag }, 'o' }, +- { { STATE_UnderflowFlag }, 'o' }, +- { { STATE_InexactFlag }, 'o' }, +- { { STATE_FPreserved20a }, 'o' }, +- { { STATE_FPreserved7 }, 'o' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_args[] = { +- { { 62 /* frr */ }, 'o' }, +- { { 63 /* frs */ }, 'i' }, +- { { 64 /* frt */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_stateArgs[] = { +- { { STATE_RoundMode }, 'i' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_mac_args[] = { +- { { 62 /* frr */ }, 'm' }, +- { { 63 /* frs */ }, 'i' }, +- { { 64 /* frt */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = { +- { { STATE_RoundMode }, 'i' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_cmov_args[] = { +- { { 62 /* frr */ }, 'm' }, +- { { 63 /* frs */ }, 'i' }, +- { { 42 /* bt */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_mov_args[] = { +- { { 62 /* frr */ }, 'm' }, +- { { 63 /* frs */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_mov2_args[] = { +- { { 62 /* frr */ }, 'o' }, +- { { 63 /* frs */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_cmp_args[] = { +- { { 44 /* br */ }, 'o' }, +- { { 63 /* frs */ }, 'i' }, +- { { 64 /* frt */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_float_args[] = { +- { { 62 /* frr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 65 /* t */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_float_stateArgs[] = { +- { { STATE_RoundMode }, 'i' }, +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_int_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 63 /* frs */ }, 'i' }, +- { { 65 /* t */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_int_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_rfr_args[] = { +- { { 3 /* arr */ }, 'o' }, +- { { 63 /* frs */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_wfr_args[] = { +- { { 62 /* frr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsi_args[] = { +- { { 64 /* frt */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 61 /* cimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsiu_args[] = { +- { { 64 /* frt */ }, 'o' }, +- { { 4 /* ars */ }, 'm' }, +- { { 61 /* cimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsx_args[] = { +- { { 62 /* frr */ }, 'o' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsxu_args[] = { +- { { 62 /* frr */ }, 'o' }, +- { { 4 /* ars */ }, 'm' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssi_args[] = { +- { { 64 /* frt */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 61 /* cimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssiu_args[] = { +- { { 64 /* frt */ }, 'i' }, +- { { 4 /* ars */ }, 'm' }, +- { { 61 /* cimm8x4 */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssx_args[] = { +- { { 62 /* frr */ }, 'i' }, +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssxu_args[] = { +- { { 62 /* frr */ }, 'i' }, +- { { 4 /* ars */ }, 'm' }, +- { { 6 /* art */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = { +- { { STATE_CPENABLE }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 60 /* xt_wbr18_label */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 17 /* b4const */ }, 'i' }, +- { { 60 /* xt_wbr18_label */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 18 /* b4constu */ }, 'i' }, +- { { 60 /* xt_wbr18_label */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 67 /* bbi */ }, 'i' }, +- { { 60 /* xt_wbr18_label */ }, 'i' } +-}; +- +-static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = { +- { { 4 /* ars */ }, 'i' }, +- { { 6 /* art */ }, 'i' }, +- { { 60 /* xt_wbr18_label */ }, 'i' } +-}; +- +-static xtensa_iclass_internal iclasses[] = { +- { 0, 0 /* xt_iclass_excw */, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_rfe */, +- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, +- { 0, 0 /* xt_iclass_rfde */, +- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, +- { 0, 0 /* xt_iclass_syscall */, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_simcall */, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_call12_args, +- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_call8_args, +- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_call4_args, +- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_callx12_args, +- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_callx8_args, +- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_callx4_args, +- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_entry_args, +- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_movsp_args, +- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rotw_args, +- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_retw_args, +- 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, +- { 0, 0 /* xt_iclass_rfwou */, +- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_l32e_args, +- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_s32e_args, +- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_windowbase_args, +- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_windowbase_args, +- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_windowbase_args, +- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_windowstart_args, +- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_windowstart_args, +- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_windowstart_args, +- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_add_n_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_addi_n_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_bz6_args, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_ill_n */, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_loadi4_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_mov_n_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_movi_n_args, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_nopn */, +- 0, 0, 0, 0 }, +- { 1, Iclass_xt_iclass_retn_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_storei4_args, +- 0, 0, 0, 0 }, +- { 1, Iclass_rur_threadptr_args, +- 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, +- { 1, Iclass_wur_threadptr_args, +- 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_addi_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_addmi_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_addsub_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_bit_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_bsi8_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_bsi8b_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_bsi8u_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_bst8_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_bsz12_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_call0_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_callx0_args, +- 0, 0, 0, 0 }, +- { 4, Iclass_xt_iclass_exti_args, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_ill */, +- 0, 0, 0, 0 }, +- { 1, Iclass_xt_iclass_jump_args, +- 0, 0, 0, 0 }, +- { 1, Iclass_xt_iclass_jumpx_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_l16ui_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_l16si_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_l32i_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_l32r_args, +- 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_l8i_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_loop_args, +- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_loopz_args, +- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_movi_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_movz_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_neg_args, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_nop */, +- 0, 0, 0, 0 }, +- { 1, Iclass_xt_iclass_return_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_s16i_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_s32i_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_s8i_args, +- 0, 0, 0, 0 }, +- { 1, Iclass_xt_iclass_sar_args, +- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_sari_args, +- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_shifts_args, +- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_shiftst_args, +- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_shiftt_args, +- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_slli_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_srai_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_srli_args, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_memw */, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_extw */, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_isync */, +- 0, 0, 0, 0 }, +- { 0, 0 /* xt_iclass_sync */, +- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_rsil_args, +- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_lend_args, +- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_lend_args, +- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_lend_args, +- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_lcount_args, +- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_lcount_args, +- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_lcount_args, +- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_lbeg_args, +- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_lbeg_args, +- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_lbeg_args, +- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_sar_args, +- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_sar_args, +- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_sar_args, +- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_litbase_args, +- 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_litbase_args, +- 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_litbase_args, +- 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_176_args, +- 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_208_args, +- 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ps_args, +- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ps_args, +- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ps_args, +- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_epc1_args, +- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_epc1_args, +- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_epc1_args, +- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_excsave1_args, +- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_excsave1_args, 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{ 1, Iclass_xt_iclass_rsr_excsave3_args, +- 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_excsave3_args, +- 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_excsave3_args, +- 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_epc4_args, +- 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_epc4_args, +- 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_epc4_args, +- 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_excsave4_args, +- 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_excsave4_args, +- 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_excsave4_args, +- 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_epc5_args, +- 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_epc5_args, +- 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_epc5_args, +- 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_excsave5_args, +- 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_excsave5_args, +- 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_excsave5_args, +- 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_epc6_args, +- 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_epc6_args, +- 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_epc6_args, +- 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_excsave6_args, +- 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_excsave6_args, +- 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_excsave6_args, +- 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_epc7_args, +- 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_epc7_args, +- 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_epc7_args, +- 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_excsave7_args, +- 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_excsave7_args, +- 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_excsave7_args, +- 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_eps2_args, +- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_eps2_args, +- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_eps2_args, +- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_eps3_args, +- 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_eps3_args, +- 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_eps3_args, +- 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_eps4_args, +- 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_eps4_args, +- 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_eps4_args, +- 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_eps5_args, +- 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_eps5_args, +- 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_eps5_args, +- 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_eps6_args, +- 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_eps6_args, +- 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_eps6_args, +- 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_eps7_args, +- 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_eps7_args, +- 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_eps7_args, +- 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_excvaddr_args, +- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_excvaddr_args, +- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_excvaddr_args, +- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_depc_args, +- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_depc_args, +- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_depc_args, +- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_exccause_args, +- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_exccause_args, +- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_exccause_args, +- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_misc0_args, +- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_misc0_args, +- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_misc0_args, +- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_misc1_args, +- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_misc1_args, +- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_misc1_args, +- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_misc2_args, +- 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_misc2_args, +- 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_misc2_args, +- 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_misc3_args, +- 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_misc3_args, +- 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_misc3_args, +- 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_prid_args, +- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_vecbase_args, +- 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_vecbase_args, +- 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_vecbase_args, +- 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16_aa_args, +- 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16_ad_args, +- 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16_da_args, +- 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16_dd_args, +- 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16a_aa_args, +- 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16a_ad_args, +- 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16a_da_args, +- 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16a_dd_args, +- 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, +- { 4, Iclass_xt_iclass_mac16al_da_args, +- 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, +- { 4, Iclass_xt_iclass_mac16al_dd_args, +- 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_mac16_l_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_mul16_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_rsr_m0_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_wsr_m0_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_xsr_m0_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_rsr_m1_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_wsr_m1_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_xsr_m1_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_rsr_m2_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_wsr_m2_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_xsr_m2_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_rsr_m3_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_wsr_m3_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_xsr_m3_args, +- 0, 0, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_acclo_args, +- 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_acclo_args, +- 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_acclo_args, +- 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_acchi_args, +- 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_acchi_args, +- 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_acchi_args, +- 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rfi_args, +- 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wait_args, +- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_interrupt_args, +- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_intset_args, +- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_intclear_args, +- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_intenable_args, +- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_intenable_args, +- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_intenable_args, +- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_break_args, +- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_break_n_args, +- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_dbreaka0_args, +- 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_dbreaka0_args, +- 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_dbreaka0_args, +- 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_dbreakc0_args, +- 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_dbreakc0_args, +- 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_dbreakc0_args, +- 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_dbreaka1_args, +- 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_dbreaka1_args, +- 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_dbreaka1_args, +- 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_dbreakc1_args, +- 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_dbreakc1_args, +- 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_dbreakc1_args, +- 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ibreaka0_args, +- 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ibreaka0_args, +- 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ibreaka0_args, +- 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ibreaka1_args, +- 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ibreaka1_args, +- 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ibreaka1_args, +- 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ibreakenable_args, +- 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ibreakenable_args, +- 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ibreakenable_args, +- 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_debugcause_args, +- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_debugcause_args, +- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_debugcause_args, +- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_icount_args, +- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_icount_args, +- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_icount_args, +- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_icountlevel_args, +- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_icountlevel_args, +- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_icountlevel_args, +- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ddr_args, +- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ddr_args, +- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ddr_args, +- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rfdo_args, +- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, +- { 0, 0 /* xt_iclass_rfdd */, +- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_mmid_args, +- 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_bbool1_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_bbool4_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_bbool8_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_bbranch_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_bmove_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_RSR_BR_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_WSR_BR_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_XSR_BR_args, +- 0, 0, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ccount_args, +- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ccount_args, +- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ccount_args, +- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ccompare0_args, +- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ccompare0_args, +- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ccompare0_args, +- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ccompare1_args, +- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ccompare1_args, +- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ccompare1_args, +- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ccompare2_args, +- 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ccompare2_args, +- 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ccompare2_args, +- 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_icache_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_icache_lock_args, +- 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_icache_inv_args, +- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_licx_args, +- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_sicx_args, +- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_dcache_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_dcache_ind_args, +- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_dcache_inv_args, +- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_dpf_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_dcache_lock_args, +- 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_sdct_args, +- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_ldct_args, +- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_ptevaddr_args, +- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_ptevaddr_args, +- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_ptevaddr_args, +- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_rasid_args, +- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_rasid_args, +- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_rasid_args, +- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_itlbcfg_args, +- 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_itlbcfg_args, +- 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_itlbcfg_args, +- 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, +- 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, +- 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, +- 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_idtlb_args, +- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_rdtlb_args, +- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_wdtlb_args, +- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_iitlb_args, +- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_ritlb_args, +- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_witlb_args, +- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, +- { 0, 0 /* xt_iclass_ldpte */, +- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, +- { 0, 0 /* xt_iclass_hwwitlba */, +- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, +- { 0, 0 /* xt_iclass_hwwdtlba */, +- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_cpenable_args, +- 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_cpenable_args, +- 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_cpenable_args, +- 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_clamp_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_minmax_args, +- 0, 0, 0, 0 }, +- { 2, Iclass_xt_iclass_nsa_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_sx_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_l32ai_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_s32ri_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_s32c1i_args, +- 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_rsr_scompare1_args, +- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_wsr_scompare1_args, +- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, +- { 1, Iclass_xt_iclass_xsr_scompare1_args, +- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, +- { 3, Iclass_xt_iclass_div_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_mul32_args, +- 0, 0, 0, 0 }, +- { 1, Iclass_rur_fcr_args, +- 9, Iclass_rur_fcr_stateArgs, 0, 0 }, +- { 1, Iclass_wur_fcr_args, +- 9, Iclass_wur_fcr_stateArgs, 0, 0 }, +- { 1, Iclass_rur_fsr_args, +- 8, Iclass_rur_fsr_stateArgs, 0, 0 }, +- { 1, Iclass_wur_fsr_args, +- 8, Iclass_wur_fsr_stateArgs, 0, 0 }, +- { 3, Iclass_fp_args, +- 2, Iclass_fp_stateArgs, 0, 0 }, +- { 3, Iclass_fp_mac_args, +- 2, Iclass_fp_mac_stateArgs, 0, 0 }, +- { 3, Iclass_fp_cmov_args, +- 1, Iclass_fp_cmov_stateArgs, 0, 0 }, +- { 3, Iclass_fp_mov_args, +- 1, Iclass_fp_mov_stateArgs, 0, 0 }, +- { 2, Iclass_fp_mov2_args, +- 1, Iclass_fp_mov2_stateArgs, 0, 0 }, +- { 3, Iclass_fp_cmp_args, +- 1, Iclass_fp_cmp_stateArgs, 0, 0 }, +- { 3, Iclass_fp_float_args, +- 2, Iclass_fp_float_stateArgs, 0, 0 }, +- { 3, Iclass_fp_int_args, +- 1, Iclass_fp_int_stateArgs, 0, 0 }, +- { 2, Iclass_fp_rfr_args, +- 1, Iclass_fp_rfr_stateArgs, 0, 0 }, +- { 2, Iclass_fp_wfr_args, +- 1, Iclass_fp_wfr_stateArgs, 0, 0 }, +- { 3, Iclass_fp_lsi_args, +- 1, Iclass_fp_lsi_stateArgs, 0, 0 }, +- { 3, Iclass_fp_lsiu_args, +- 1, Iclass_fp_lsiu_stateArgs, 0, 0 }, +- { 3, Iclass_fp_lsx_args, +- 1, Iclass_fp_lsx_stateArgs, 0, 0 }, +- { 3, Iclass_fp_lsxu_args, +- 1, Iclass_fp_lsxu_stateArgs, 0, 0 }, +- { 3, Iclass_fp_ssi_args, +- 1, Iclass_fp_ssi_stateArgs, 0, 0 }, +- { 3, Iclass_fp_ssiu_args, +- 1, Iclass_fp_ssiu_stateArgs, 0, 0 }, +- { 3, Iclass_fp_ssx_args, +- 1, Iclass_fp_ssx_stateArgs, 0, 0 }, +- { 3, Iclass_fp_ssxu_args, +- 1, Iclass_fp_ssxu_stateArgs, 0, 0 }, +- { 2, Iclass_xt_iclass_wb18_0_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_wb18_1_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_wb18_2_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_wb18_3_args, +- 0, 0, 0, 0 }, +- { 3, Iclass_xt_iclass_wb18_4_args, +- 0, 0, 0, 0 } +-}; +- +- +-/* Opcode encodings. */ +- +-static void +-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2080; +-} +- +-static void +-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3000; +-} +- +-static void +-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3200; +-} +- +-static void +-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5000; +-} +- +-static void +-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5100; +-} +- +-static void +-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x35; +-} +- +-static void +-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x25; +-} +- +-static void +-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x15; +-} +- +-static void +-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf0; +-} +- +-static void +-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe0; +-} +- +-static void +-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd0; +-} +- +-static void +-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x36; +-} +- +-static void +-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1000; +-} +- +-static void +-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x408000; +-} +- +-static void +-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x90; +-} +- +-static void +-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf01d; +-} +- +-static void +-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3400; +-} +- +-static void +-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3500; +-} +- +-static void +-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x90000; +-} +- +-static void +-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x490000; +-} +- +-static void +-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x34800; +-} +- +-static void +-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x134800; +-} +- +-static void +-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x614800; +-} +- +-static void +-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x34900; +-} +- +-static void +-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x134900; +-} +- +-static void +-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x614900; +-} +- +-static void +-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa; +-} +- +-static void +-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb; +-} +- +-static void +-Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3000; +-} +- +-static void +-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8c; +-} +- +-static void +-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xcc; +-} +- +-static void +-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf06d; +-} +- +-static void +-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8; +-} +- +-static void +-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd; +-} +- +-static void +-Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6000; +-} +- +-static void +-Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa3000; +-} +- +-static void +-Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc080; +-} +- +-static void +-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc; +-} +- +-static void +-Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc000; +-} +- +-static void +-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf03d; +-} +- +-static void +-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf00d; +-} +- +-static void +-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9; +-} +- +-static void +-Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe30e70; +-} +- +-static void +-Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf3e700; +-} +- +-static void +-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc002; +-} +- +-static void +-Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x60000; +-} +- +-static void +-Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200c00; +-} +- +-static void +-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd002; +-} +- +-static void +-Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x70000; +-} +- +-static void +-Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200d00; +-} +- +-static void +-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x800000; +-} +- +-static void +-Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x92000; +-} +- +-static void +-Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2000; +-} +- +-static void +-Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x80000; +-} +- +-static void +-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc00000; +-} +- +-static void +-Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa8000; +-} +- +-static void +-Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa000; +-} +- +-static void +-Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc0000; +-} +- +-static void +-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x900000; +-} +- +-static void +-Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x94000; +-} +- +-static void +-Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4000; +-} +- +-static void +-Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x90000; +-} +- +-static void +-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa00000; +-} +- +-static void +-Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x98000; +-} +- +-static void +-Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5000; +-} +- +-static void +-Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa0000; +-} +- +-static void +-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb00000; +-} +- +-static void +-Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x93000; +-} +- +-static void +-Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb0000; +-} +- +-static void +-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd00000; +-} +- +-static void +-Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd0000; +-} +- +-static void +-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe00000; +-} +- +-static void +-Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe0000; +-} +- +-static void +-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf00000; +-} +- +-static void +-Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf0000; +-} +- +-static void +-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x100000; +-} +- +-static void +-Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x95000; +-} +- +-static void +-Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6000; +-} +- +-static void +-Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x10000; +-} +- +-static void +-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200000; +-} +- +-static void +-Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9e000; +-} +- +-static void +-Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7000; +-} +- +-static void +-Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x20000; +-} +- +-static void +-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x300000; +-} +- +-static void +-Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb0000; +-} +- +-static void +-Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb000; +-} +- +-static void +-Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30000; +-} +- +-static void +-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x26; +-} +- +-static void +-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x66; +-} +- +-static void +-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe6; +-} +- +-static void +-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa6; +-} +- +-static void +-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6007; +-} +- +-static void +-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe007; +-} +- +-static void +-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf6; +-} +- +-static void +-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb6; +-} +- +-static void +-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1007; +-} +- +-static void +-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9007; +-} +- +-static void +-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa007; +-} +- +-static void +-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2007; +-} +- +-static void +-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb007; +-} +- +-static void +-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3007; +-} +- +-static void +-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8007; +-} +- +-static void +-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7; +-} +- +-static void +-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4007; +-} +- +-static void +-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc007; +-} +- +-static void +-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5007; +-} +- +-static void +-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd007; +-} +- +-static void +-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x16; +-} +- +-static void +-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x56; +-} +- +-static void +-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd6; +-} +- +-static void +-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x96; +-} +- +-static void +-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5; +-} +- +-static void +-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc0; +-} +- +-static void +-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40000; +-} +- +-static void +-Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40000; +-} +- +-static void +-Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4000; +-} +- +-static void +-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0; +-} +- +-static void +-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6; +-} +- +-static void +-Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc0000; +-} +- +-static void +-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa0; +-} +- +-static void +-Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa3010; +-} +- +-static void +-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1002; +-} +- +-static void +-Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200100; +-} +- +-static void +-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9002; +-} +- +-static void +-Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200900; +-} +- +-static void +-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2002; +-} +- +-static void +-Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200200; +-} +- +-static void +-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1; +-} +- +-static void +-Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x100000; +-} +- +-static void +-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2; +-} +- +-static void +-Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200000; +-} +- +-static void +-Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8076; +-} +- +-static void +-Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9076; +-} +- +-static void +-Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa076; +-} +- +-static void +-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa002; +-} +- +-static void +-Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x80000; +-} +- +-static void +-Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200a00; +-} +- +-static void +-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x830000; +-} +- +-static void +-Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x96000; +-} +- +-static void +-Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x83000; +-} +- +-static void +-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x930000; +-} +- +-static void +-Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9a000; +-} +- +-static void +-Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x93000; +-} +- +-static void +-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa30000; +-} +- +-static void +-Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x99000; +-} +- +-static void +-Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa3000; +-} +- +-static void +-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb30000; +-} +- +-static void +-Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x97000; +-} +- +-static void +-Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb3000; +-} +- +-static void +-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x600000; +-} +- +-static void +-Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa5000; +-} +- +-static void +-Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd100; +-} +- +-static void +-Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x60000; +-} +- +-static void +-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x600100; +-} +- +-static void +-Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd000; +-} +- +-static void +-Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x60010; +-} +- +-static void +-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x20f0; +-} +- +-static void +-Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa3040; +-} +- +-static void +-Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc090; +-} +- +-static void +-Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc8000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x20f; +-} +- +-static void +-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x80; +-} +- +-static void +-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5002; +-} +- +-static void +-Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200500; +-} +- +-static void +-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6002; +-} +- +-static void +-Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200600; +-} +- +-static void +-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4002; +-} +- +-static void +-Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x200400; +-} +- +-static void +-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x400000; +-} +- +-static void +-Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40000; +-} +- +-static void +-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x401000; +-} +- +-static void +-Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa3020; +-} +- +-static void +-Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40100; +-} +- +-static void +-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x402000; +-} +- +-static void +-Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40200; +-} +- +-static void +-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x403000; +-} +- +-static void +-Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40300; +-} +- +-static void +-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x404000; +-} +- +-static void +-Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40400; +-} +- +-static void +-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa10000; +-} +- +-static void +-Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa6000; +-} +- +-static void +-Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa1000; +-} +- +-static void +-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x810000; +-} +- +-static void +-Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa2000; +-} +- +-static void +-Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x81000; +-} +- +-static void +-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x910000; +-} +- +-static void +-Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa5200; +-} +- +-static void +-Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd400; +-} +- +-static void +-Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x91000; +-} +- +-static void +-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb10000; +-} +- +-static void +-Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa5100; +-} +- +-static void +-Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd200; +-} +- +-static void +-Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb1000; +-} +- +-static void +-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x10000; +-} +- +-static void +-Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x90000; +-} +- +-static void +-Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1000; +-} +- +-static void +-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x210000; +-} +- +-static void +-Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa0000; +-} +- +-static void +-Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe000; +-} +- +-static void +-Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x21000; +-} +- +-static void +-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x410000; +-} +- +-static void +-Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa4000; +-} +- +-static void +-Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9000; +-} +- +-static void +-Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x41000; +-} +- +-static void +-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x20c0; +-} +- +-static void +-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x20d0; +-} +- +-static void +-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2000; +-} +- +-static void +-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2010; +-} +- +-static void +-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2020; +-} +- +-static void +-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2030; +-} +- +-static void +-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6000; +-} +- +-static void +-Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30100; +-} +- +-static void +-Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x130100; +-} +- +-static void +-Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x610100; +-} +- +-static void +-Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30200; +-} +- +-static void +-Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x130200; +-} +- +-static void +-Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x610200; +-} +- +-static void +-Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30000; +-} +- +-static void +-Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x130000; +-} +- +-static void +-Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x610000; +-} +- +-static void +-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30300; +-} +- +-static void +-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x130300; +-} +- +-static void +-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x610300; +-} +- +-static void +-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30500; +-} +- +-static void +-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x130500; +-} +- +-static void +-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x610500; +-} +- +-static void +-Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b000; +-} +- +-static void +-Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d000; +-} +- +-static void +-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e600; +-} +- +-static void +-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e600; +-} +- +-static void +-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61e600; +-} +- +-static void +-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b100; +-} +- +-static void +-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13b100; +-} +- +-static void +-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61b100; +-} +- +-static void +-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d100; +-} +- +-static void +-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13d100; +-} +- +-static void +-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61d100; +-} +- +-static void +-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b200; +-} +- +-static void +-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13b200; +-} +- +-static void +-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61b200; +-} +- +-static void +-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d200; +-} +- +-static void +-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13d200; +-} +- +-static void +-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61d200; +-} +- +-static void +-Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b300; +-} +- +-static void +-Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13b300; +-} +- +-static void +-Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61b300; +-} +- +-static void +-Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d300; +-} +- +-static void +-Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13d300; +-} +- +-static void +-Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61d300; +-} +- +-static void +-Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b400; +-} +- +-static void +-Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13b400; +-} +- +-static void +-Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61b400; +-} +- +-static void +-Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d400; +-} +- +-static void +-Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13d400; +-} +- +-static void +-Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61d400; +-} +- +-static void +-Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b500; +-} +- +-static void +-Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13b500; +-} +- +-static void +-Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61b500; +-} +- +-static void +-Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d500; +-} +- +-static void +-Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13d500; +-} +- +-static void +-Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61d500; +-} +- +-static void +-Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b600; +-} +- +-static void +-Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13b600; +-} +- +-static void +-Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61b600; +-} +- +-static void +-Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d600; +-} +- +-static void +-Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13d600; +-} +- +-static void +-Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61d600; +-} +- +-static void +-Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b700; +-} +- +-static void +-Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13b700; +-} +- +-static void +-Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61b700; +-} +- +-static void +-Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d700; +-} +- +-static void +-Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13d700; +-} +- +-static void +-Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61d700; +-} +- +-static void +-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c200; +-} +- +-static void +-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13c200; +-} +- +-static void +-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61c200; +-} +- +-static void +-Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c300; +-} +- +-static void +-Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13c300; +-} +- +-static void +-Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61c300; +-} +- +-static void +-Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c400; +-} +- +-static void +-Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13c400; +-} +- +-static void +-Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61c400; +-} +- +-static void +-Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c500; +-} +- +-static void +-Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13c500; +-} +- +-static void +-Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61c500; +-} +- +-static void +-Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c600; +-} +- +-static void +-Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13c600; +-} +- +-static void +-Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61c600; +-} +- +-static void +-Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c700; +-} +- +-static void +-Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13c700; +-} +- +-static void +-Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61c700; +-} +- +-static void +-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3ee00; +-} +- +-static void +-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13ee00; +-} +- +-static void +-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61ee00; +-} +- +-static void +-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c000; +-} +- +-static void +-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13c000; +-} +- +-static void +-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61c000; +-} +- +-static void +-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e800; +-} +- +-static void +-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e800; +-} +- +-static void +-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61e800; +-} +- +-static void +-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f400; +-} +- +-static void +-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13f400; +-} +- +-static void +-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61f400; +-} +- +-static void +-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f500; +-} +- +-static void +-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13f500; +-} +- +-static void +-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61f500; +-} +- +-static void +-Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f600; +-} +- +-static void +-Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13f600; +-} +- +-static void +-Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61f600; +-} +- +-static void +-Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f700; +-} +- +-static void +-Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13f700; +-} +- +-static void +-Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61f700; +-} +- +-static void +-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3eb00; +-} +- +-static void +-Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e700; +-} +- +-static void +-Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e700; +-} +- +-static void +-Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61e700; +-} +- +-static void +-Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x740004; +-} +- +-static void +-Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x750004; +-} +- +-static void +-Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x760004; +-} +- +-static void +-Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x770004; +-} +- +-static void +-Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x700004; +-} +- +-static void +-Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x710004; +-} +- +-static void +-Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x720004; +-} +- +-static void +-Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x730004; +-} +- +-static void +-Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x340004; +-} +- +-static void +-Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x350004; +-} +- +-static void +-Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x360004; +-} +- +-static void +-Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x370004; +-} +- +-static void +-Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x640004; +-} +- +-static void +-Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x650004; +-} +- +-static void +-Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x660004; +-} +- +-static void +-Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x670004; +-} +- +-static void +-Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x240004; +-} +- +-static void +-Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x250004; +-} +- +-static void +-Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x260004; +-} +- +-static void +-Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x270004; +-} +- +-static void +-Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x780004; +-} +- +-static void +-Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x790004; +-} +- +-static void +-Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7a0004; +-} +- +-static void +-Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7b0004; +-} +- +-static void +-Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7c0004; +-} +- +-static void +-Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7d0004; +-} +- +-static void +-Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7e0004; +-} +- +-static void +-Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7f0004; +-} +- +-static void +-Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x380004; +-} +- +-static void +-Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x390004; +-} +- +-static void +-Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3a0004; +-} +- +-static void +-Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b0004; +-} +- +-static void +-Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3c0004; +-} +- +-static void +-Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3d0004; +-} +- +-static void +-Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e0004; +-} +- +-static void +-Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f0004; +-} +- +-static void +-Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x680004; +-} +- +-static void +-Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x690004; +-} +- +-static void +-Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6a0004; +-} +- +-static void +-Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6b0004; +-} +- +-static void +-Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6c0004; +-} +- +-static void +-Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6d0004; +-} +- +-static void +-Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6e0004; +-} +- +-static void +-Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6f0004; +-} +- +-static void +-Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x280004; +-} +- +-static void +-Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x290004; +-} +- +-static void +-Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2a0004; +-} +- +-static void +-Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2b0004; +-} +- +-static void +-Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2c0004; +-} +- +-static void +-Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2d0004; +-} +- +-static void +-Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2e0004; +-} +- +-static void +-Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2f0004; +-} +- +-static void +-Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x580004; +-} +- +-static void +-Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x480004; +-} +- +-static void +-Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x590004; +-} +- +-static void +-Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x490004; +-} +- +-static void +-Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5a0004; +-} +- +-static void +-Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4a0004; +-} +- +-static void +-Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5b0004; +-} +- +-static void +-Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4b0004; +-} +- +-static void +-Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x180004; +-} +- +-static void +-Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x80004; +-} +- +-static void +-Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x190004; +-} +- +-static void +-Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x90004; +-} +- +-static void +-Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1a0004; +-} +- +-static void +-Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa0004; +-} +- +-static void +-Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1b0004; +-} +- +-static void +-Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb0004; +-} +- +-static void +-Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x900004; +-} +- +-static void +-Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x800004; +-} +- +-static void +-Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc10000; +-} +- +-static void +-Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9b000; +-} +- +-static void +-Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc1000; +-} +- +-static void +-Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd10000; +-} +- +-static void +-Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9c000; +-} +- +-static void +-Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd1000; +-} +- +-static void +-Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x32000; +-} +- +-static void +-Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x132000; +-} +- +-static void +-Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x612000; +-} +- +-static void +-Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x32100; +-} +- +-static void +-Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x132100; +-} +- +-static void +-Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x612100; +-} +- +-static void +-Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x32200; +-} +- +-static void +-Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x132200; +-} +- +-static void +-Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x612200; +-} +- +-static void +-Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x32300; +-} +- +-static void +-Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x132300; +-} +- +-static void +-Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x612300; +-} +- +-static void +-Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x31000; +-} +- +-static void +-Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x131000; +-} +- +-static void +-Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x611000; +-} +- +-static void +-Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x31100; +-} +- +-static void +-Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x131100; +-} +- +-static void +-Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x611100; +-} +- +-static void +-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3010; +-} +- +-static void +-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7000; +-} +- +-static void +-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e200; +-} +- +-static void +-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e200; +-} +- +-static void +-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e300; +-} +- +-static void +-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e400; +-} +- +-static void +-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e400; +-} +- +-static void +-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61e400; +-} +- +-static void +-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4000; +-} +- +-static void +-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf02d; +-} +- +-static void +-Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x39000; +-} +- +-static void +-Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x139000; +-} +- +-static void +-Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x619000; +-} +- +-static void +-Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3a000; +-} +- +-static void +-Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13a000; +-} +- +-static void +-Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61a000; +-} +- +-static void +-Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x39100; +-} +- +-static void +-Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x139100; +-} +- +-static void +-Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x619100; +-} +- +-static void +-Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3a100; +-} +- +-static void +-Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13a100; +-} +- +-static void +-Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61a100; +-} +- +-static void +-Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x38000; +-} +- +-static void +-Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x138000; +-} +- +-static void +-Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x618000; +-} +- +-static void +-Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x38100; +-} +- +-static void +-Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x138100; +-} +- +-static void +-Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x618100; +-} +- +-static void +-Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x36000; +-} +- +-static void +-Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x136000; +-} +- +-static void +-Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x616000; +-} +- +-static void +-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e900; +-} +- +-static void +-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e900; +-} +- +-static void +-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61e900; +-} +- +-static void +-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3ec00; +-} +- +-static void +-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13ec00; +-} +- +-static void +-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61ec00; +-} +- +-static void +-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3ed00; +-} +- +-static void +-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13ed00; +-} +- +-static void +-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61ed00; +-} +- +-static void +-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x36800; +-} +- +-static void +-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x136800; +-} +- +-static void +-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x616800; +-} +- +-static void +-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf1e000; +-} +- +-static void +-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf1e010; +-} +- +-static void +-Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x135900; +-} +- +-static void +-Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x20000; +-} +- +-static void +-Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x120000; +-} +- +-static void +-Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x220000; +-} +- +-static void +-Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x320000; +-} +- +-static void +-Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x420000; +-} +- +-static void +-Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8000; +-} +- +-static void +-Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9000; +-} +- +-static void +-Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa000; +-} +- +-static void +-Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb000; +-} +- +-static void +-Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x76; +-} +- +-static void +-Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1076; +-} +- +-static void +-Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc30000; +-} +- +-static void +-Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd30000; +-} +- +-static void +-Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30400; +-} +- +-static void +-Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x130400; +-} +- +-static void +-Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x610400; +-} +- +-static void +-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3ea00; +-} +- +-static void +-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13ea00; +-} +- +-static void +-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61ea00; +-} +- +-static void +-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f000; +-} +- +-static void +-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13f000; +-} +- +-static void +-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61f000; +-} +- +-static void +-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f100; +-} +- +-static void +-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13f100; +-} +- +-static void +-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61f100; +-} +- +-static void +-Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3f200; +-} +- +-static void +-Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13f200; +-} +- +-static void +-Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61f200; +-} +- +-static void +-Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x70c2; +-} +- +-static void +-Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x70e2; +-} +- +-static void +-Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x70d2; +-} +- +-static void +-Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x270d2; +-} +- +-static void +-Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x370d2; +-} +- +-static void +-Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x70f2; +-} +- +-static void +-Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf10000; +-} +- +-static void +-Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf12000; +-} +- +-static void +-Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf11000; +-} +- +-static void +-Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf13000; +-} +- +-static void +-Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7042; +-} +- +-static void +-Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7052; +-} +- +-static void +-Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x47082; +-} +- +-static void +-Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x57082; +-} +- +-static void +-Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7062; +-} +- +-static void +-Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7072; +-} +- +-static void +-Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7002; +-} +- +-static void +-Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7012; +-} +- +-static void +-Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7022; +-} +- +-static void +-Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7032; +-} +- +-static void +-Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7082; +-} +- +-static void +-Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x27082; +-} +- +-static void +-Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x37082; +-} +- +-static void +-Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf19000; +-} +- +-static void +-Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf18000; +-} +- +-static void +-Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x135300; +-} +- +-static void +-Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x35300; +-} +- +-static void +-Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x615300; +-} +- +-static void +-Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x35a00; +-} +- +-static void +-Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x135a00; +-} +- +-static void +-Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x615a00; +-} +- +-static void +-Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x35b00; +-} +- +-static void +-Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x135b00; +-} +- +-static void +-Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x615b00; +-} +- +-static void +-Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x35c00; +-} +- +-static void +-Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x135c00; +-} +- +-static void +-Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x615c00; +-} +- +-static void +-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x50c000; +-} +- +-static void +-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x50d000; +-} +- +-static void +-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x50b000; +-} +- +-static void +-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x50f000; +-} +- +-static void +-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x50e000; +-} +- +-static void +-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x504000; +-} +- +-static void +-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x505000; +-} +- +-static void +-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x503000; +-} +- +-static void +-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x507000; +-} +- +-static void +-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x506000; +-} +- +-static void +-Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf1f000; +-} +- +-static void +-Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x501000; +-} +- +-static void +-Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x509000; +-} +- +-static void +-Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3e000; +-} +- +-static void +-Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x13e000; +-} +- +-static void +-Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x61e000; +-} +- +-static void +-Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x330000; +-} +- +-static void +-Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x33000; +-} +- +-static void +-Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x430000; +-} +- +-static void +-Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x43000; +-} +- +-static void +-Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x530000; +-} +- +-static void +-Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x53000; +-} +- +-static void +-Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x630000; +-} +- +-static void +-Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x63000; +-} +- +-static void +-Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x730000; +-} +- +-static void +-Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x73000; +-} +- +-static void +-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40e000; +-} +- +-static void +-Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40e00; +-} +- +-static void +-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40f000; +-} +- +-static void +-Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40f00; +-} +- +-static void +-Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x230000; +-} +- +-static void +-Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9f000; +-} +- +-static void +-Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8000; +-} +- +-static void +-Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x23000; +-} +- +-static void +-Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb002; +-} +- +-static void +-Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf002; +-} +- +-static void +-Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe002; +-} +- +-static void +-Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30c00; +-} +- +-static void +-Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x130c00; +-} +- +-static void +-Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x610c00; +-} +- +-static void +-Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc20000; +-} +- +-static void +-Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xd20000; +-} +- +-static void +-Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe20000; +-} +- +-static void +-Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf20000; +-} +- +-static void +-Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x820000; +-} +- +-static void +-Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9d000; +-} +- +-static void +-Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x82000; +-} +- +-static void +-Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa20000; +-} +- +-static void +-Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb20000; +-} +- +-static void +-Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe30e80; +-} +- +-static void +-Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf3e800; +-} +- +-static void +-Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xe30e90; +-} +- +-static void +-Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xf3e900; +-} +- +-static void +-Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa0000; +-} +- +-static void +-Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1a0000; +-} +- +-static void +-Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2a0000; +-} +- +-static void +-Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4a0000; +-} +- +-static void +-Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5a0000; +-} +- +-static void +-Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xcb0000; +-} +- +-static void +-Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xdb0000; +-} +- +-static void +-Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8b0000; +-} +- +-static void +-Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9b0000; +-} +- +-static void +-Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xab0000; +-} +- +-static void +-Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xbb0000; +-} +- +-static void +-Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xfa0010; +-} +- +-static void +-Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xfa0000; +-} +- +-static void +-Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xfa0060; +-} +- +-static void +-Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x1b0000; +-} +- +-static void +-Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x2b0000; +-} +- +-static void +-Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3b0000; +-} +- +-static void +-Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4b0000; +-} +- +-static void +-Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x5b0000; +-} +- +-static void +-Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x6b0000; +-} +- +-static void +-Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x7b0000; +-} +- +-static void +-Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xca0000; +-} +- +-static void +-Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xda0000; +-} +- +-static void +-Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8a0000; +-} +- +-static void +-Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xba0000; +-} +- +-static void +-Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xaa0000; +-} +- +-static void +-Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x9a0000; +-} +- +-static void +-Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xea0000; +-} +- +-static void +-Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xfa0040; +-} +- +-static void +-Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xfa0050; +-} +- +-static void +-Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x3; +-} +- +-static void +-Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8003; +-} +- +-static void +-Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x80000; +-} +- +-static void +-Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x180000; +-} +- +-static void +-Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x4003; +-} +- +-static void +-Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc003; +-} +- +-static void +-Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x480000; +-} +- +-static void +-Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x580000; +-} +- +-static void +-Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa8000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xc0000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb0000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xb8000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x40000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x98000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x50000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x70000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x60000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x80000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x8000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x10000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x38000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x90000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x48000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x68000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x58000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x78000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x20000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0xa0000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x18000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x88000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x28000000; +- slotbuf[1] = 0; +-} +- +-static void +-Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = 0x30000000; +- slotbuf[1] = 0; +-} +- +-xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { +- Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { +- Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { +- Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { +- Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { +- Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { +- Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { +- Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { +- Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { +- Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { +- Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { +- Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { +- Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { +- Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { +- Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { +- Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { +- 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { +- Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { +- Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { +- Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { +- Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { +- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { +- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { +- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { +- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { +- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { +- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { +- 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { +- 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { +- 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { +- 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { +- 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { +- 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { +- 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { +- 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { +- 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { +- 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { +- 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { +- Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { +- Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { +- Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { +- Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { +- Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { +- Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { +- Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { +- Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { +- Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { +- Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { +- Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { +- Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { +- Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { +- Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { +- Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { +- Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { +- Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { +- Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { +- Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { +- Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { +- Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { +- Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { +- Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { +- Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { +- Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { +- Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { +- Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { +- Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { +- Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { +- Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { +- Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { +- Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { +- Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { +- Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { +- Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { +- Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { +- Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { +- Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { +- Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { +- Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { +- Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { +- Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { +- Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { +- Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { +- Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { +- Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { +- Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { +- Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { +- Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { +- Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { +- Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { +- Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { +- Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { +- Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { +- Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { +- Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { +- Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { +- Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { +- Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { +- Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { +- Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { +- Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { +- Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { +- Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { +- Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { +- Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { +- Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { +- Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { +- Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { +- Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { +- Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { +- Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { +- Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { +- Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { +- Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { +- Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { +- Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { +- Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { +- Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { +- Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { +- Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { +- Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { +- Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { +- Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { +- Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { +- Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { +- Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { +- Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { +- Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { +- Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { +- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { +- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { +- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { +- Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { +- Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { +- Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { +- Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { +- Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { +- Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { +- Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { +- Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { +- Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { +- Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { +- Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { +- Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { +- Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { +- Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { +- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { +- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { +- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { +- Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { +- Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { +- Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { +- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { +- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { +- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { +- Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { +- Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { +- Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { +- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { +- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { +- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { +- Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { +- Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { +- Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { +- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { +- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { +- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { +- Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { +- Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { +- Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { +- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { +- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { +- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { +- Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { +- Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { +- Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { +- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { +- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { +- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { +- Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { +- Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { +- Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { +- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { +- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { +- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { +- Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { +- Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { +- Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { +- Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { +- Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { +- Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { +- Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { +- Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { +- Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { +- Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { +- Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { +- Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { +- Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { +- Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { +- Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { +- Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { +- Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { +- Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { +- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { +- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { +- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { +- Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { +- Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { +- Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { +- Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { +- Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { +- Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { +- Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { +- Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { +- Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { +- Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { +- Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { +- Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { +- Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { +- Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { +- Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { +- Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { +- Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { +- Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { +- Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { +- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { +- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { +- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { +- Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { +- Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { +- Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { +- Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { +- Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { +- Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { +- Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { +- Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { +- Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { +- Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { +- Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { +- Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { +- Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { +- Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { +- Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { +- Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { +- Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { +- Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { +- Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { +- Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { +- Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { +- Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { +- Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { +- Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { +- Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { +- Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { +- Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { +- Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { +- Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { +- Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { +- Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { +- Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { +- Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { +- Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { +- Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { +- Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { +- Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { +- Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { +- Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { +- Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { +- Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { +- Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { +- Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { +- Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { +- Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { +- Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { +- Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { +- Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { +- Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { +- Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { +- Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { +- Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { +- Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { +- Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { +- Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { +- Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { +- Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { +- Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { +- Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { +- Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { +- Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { +- Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { +- Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { +- Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { +- Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { +- Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { +- Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { +- Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { +- Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { +- Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { +- Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { +- Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { +- Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { +- Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { +- Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { +- Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { +- Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { +- Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { +- Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { +- Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { +- Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { +- Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { +- Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { +- Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { +- Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { +- Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { +- Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { +- Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { +- Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { +- Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { +- Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { +- Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { +- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { +- Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { +- Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { +- Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { +- Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { +- Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { +- Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { +- 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { +- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { +- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { +- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { +- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { +- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { +- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { +- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { +- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { +- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { +- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { +- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { +- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { +- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { +- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { +- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { +- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { +- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { +- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { +- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { +- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { +- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { +- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { +- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { +- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { +- Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { +- Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { +- Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { +- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { +- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { +- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { +- Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { +- Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { +- Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { +- Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { +- Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { +- Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { +- Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { +- Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { +- Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { +- Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { +- Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { +- Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { +- Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { +- Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { +- Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { +- Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { +- Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { +- Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { +- Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { +- Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { +- Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { +- Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { +- Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { +- Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { +- Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { +- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { +- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { +- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { +- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { +- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { +- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { +- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { +- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { +- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { +- Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { +- Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { +- Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { +- Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { +- Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { +- Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { +- Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { +- Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { +- Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { +- Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { +- Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { +- Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { +- Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { +- Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { +- Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { +- Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { +- Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { +- Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { +- Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { +- Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { +- Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { +- Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { +- Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { +- Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { +- Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { +- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { +- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { +- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { +- Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { +- Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { +- Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { +- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { +- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { +- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { +- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { +- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { +- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { +- Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { +- Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { +- Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { +- Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { +- Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { +- Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { +- Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { +- Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { +- Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { +- Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { +- Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { +- Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { +- Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { +- Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { +- Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { +- Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { +- Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { +- Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { +- Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { +- Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { +- Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { +- Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { +- Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { +- Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { +- Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { +- Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { +- Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { +- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { +- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { +- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { +- Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { +- Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { +- Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { +- Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { +- Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { +- Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { +- Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { +- Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { +- Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { +- Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { +- Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { +- Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { +- Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { +- Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { +- Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { +- Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { +- Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { +- Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { +- Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { +- Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { +- Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { +- Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { +- Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = { +- Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { +- Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { +- Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { +- Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { +- Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { +- Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { +- Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { +- Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { +- Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { +- Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { +- Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = { +- Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = { +- Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = { +- Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { +- Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { +- Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { +- Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { +- Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = { +- Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = { +- Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = { +- Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = { +- Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = { +- Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = { +- Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = { +- Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = { +- Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 +-}; +- +-xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode +-}; +- +-xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = { +- 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode +-}; +- +- +-/* Opcode table. */ +- +-static xtensa_opcode_internal opcodes[] = { +- { "excw", 0 /* xt_iclass_excw */, +- 0, +- Opcode_excw_encode_fns, 0, 0 }, +- { "rfe", 1 /* xt_iclass_rfe */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_rfe_encode_fns, 0, 0 }, +- { "rfde", 2 /* xt_iclass_rfde */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_rfde_encode_fns, 0, 0 }, +- { "syscall", 3 /* xt_iclass_syscall */, +- 0, +- Opcode_syscall_encode_fns, 0, 0 }, +- { "simcall", 4 /* xt_iclass_simcall */, +- 0, +- Opcode_simcall_encode_fns, 0, 0 }, +- { "call12", 5 /* xt_iclass_call12 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_call12_encode_fns, 0, 0 }, +- { "call8", 6 /* xt_iclass_call8 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_call8_encode_fns, 0, 0 }, +- { "call4", 7 /* xt_iclass_call4 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_call4_encode_fns, 0, 0 }, +- { "callx12", 8 /* xt_iclass_callx12 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_callx12_encode_fns, 0, 0 }, +- { "callx8", 9 /* xt_iclass_callx8 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_callx8_encode_fns, 0, 0 }, +- { "callx4", 10 /* xt_iclass_callx4 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_callx4_encode_fns, 0, 0 }, +- { "entry", 11 /* xt_iclass_entry */, +- 0, +- Opcode_entry_encode_fns, 0, 0 }, +- { "movsp", 12 /* xt_iclass_movsp */, +- 0, +- Opcode_movsp_encode_fns, 0, 0 }, +- { "rotw", 13 /* xt_iclass_rotw */, +- 0, +- Opcode_rotw_encode_fns, 0, 0 }, +- { "retw", 14 /* xt_iclass_retw */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_retw_encode_fns, 0, 0 }, +- { "retw.n", 14 /* xt_iclass_retw */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_retw_n_encode_fns, 0, 0 }, +- { "rfwo", 15 /* xt_iclass_rfwou */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_rfwo_encode_fns, 0, 0 }, +- { "rfwu", 15 /* xt_iclass_rfwou */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_rfwu_encode_fns, 0, 0 }, +- { "l32e", 16 /* xt_iclass_l32e */, +- 0, +- Opcode_l32e_encode_fns, 0, 0 }, +- { "s32e", 17 /* xt_iclass_s32e */, +- 0, +- Opcode_s32e_encode_fns, 0, 0 }, +- { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, +- 0, +- Opcode_rsr_windowbase_encode_fns, 0, 0 }, +- { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, +- 0, +- Opcode_wsr_windowbase_encode_fns, 0, 0 }, +- { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, +- 0, +- Opcode_xsr_windowbase_encode_fns, 0, 0 }, +- { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, +- 0, +- Opcode_rsr_windowstart_encode_fns, 0, 0 }, +- { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, +- 0, +- Opcode_wsr_windowstart_encode_fns, 0, 0 }, +- { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, +- 0, +- Opcode_xsr_windowstart_encode_fns, 0, 0 }, +- { "add.n", 24 /* xt_iclass_add.n */, +- 0, +- Opcode_add_n_encode_fns, 0, 0 }, +- { "addi.n", 25 /* xt_iclass_addi.n */, +- 0, +- Opcode_addi_n_encode_fns, 0, 0 }, +- { "beqz.n", 26 /* xt_iclass_bz6 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_beqz_n_encode_fns, 0, 0 }, +- { "bnez.n", 26 /* xt_iclass_bz6 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnez_n_encode_fns, 0, 0 }, +- { "ill.n", 27 /* xt_iclass_ill.n */, +- 0, +- Opcode_ill_n_encode_fns, 0, 0 }, +- { "l32i.n", 28 /* xt_iclass_loadi4 */, +- 0, +- Opcode_l32i_n_encode_fns, 0, 0 }, +- { "mov.n", 29 /* xt_iclass_mov.n */, +- 0, +- Opcode_mov_n_encode_fns, 0, 0 }, +- { "movi.n", 30 /* xt_iclass_movi.n */, +- 0, +- Opcode_movi_n_encode_fns, 0, 0 }, +- { "nop.n", 31 /* xt_iclass_nopn */, +- 0, +- Opcode_nop_n_encode_fns, 0, 0 }, +- { "ret.n", 32 /* xt_iclass_retn */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_ret_n_encode_fns, 0, 0 }, +- { "s32i.n", 33 /* xt_iclass_storei4 */, +- 0, +- Opcode_s32i_n_encode_fns, 0, 0 }, +- { "rur.threadptr", 34 /* rur_threadptr */, +- 0, +- Opcode_rur_threadptr_encode_fns, 0, 0 }, +- { "wur.threadptr", 35 /* wur_threadptr */, +- 0, +- Opcode_wur_threadptr_encode_fns, 0, 0 }, +- { "addi", 36 /* xt_iclass_addi */, +- 0, +- Opcode_addi_encode_fns, 0, 0 }, +- { "addmi", 37 /* xt_iclass_addmi */, +- 0, +- Opcode_addmi_encode_fns, 0, 0 }, +- { "add", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_add_encode_fns, 0, 0 }, +- { "sub", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_sub_encode_fns, 0, 0 }, +- { "addx2", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_addx2_encode_fns, 0, 0 }, +- { "addx4", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_addx4_encode_fns, 0, 0 }, +- { "addx8", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_addx8_encode_fns, 0, 0 }, +- { "subx2", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_subx2_encode_fns, 0, 0 }, +- { "subx4", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_subx4_encode_fns, 0, 0 }, +- { "subx8", 38 /* xt_iclass_addsub */, +- 0, +- Opcode_subx8_encode_fns, 0, 0 }, +- { "and", 39 /* xt_iclass_bit */, +- 0, +- Opcode_and_encode_fns, 0, 0 }, +- { "or", 39 /* xt_iclass_bit */, +- 0, +- Opcode_or_encode_fns, 0, 0 }, +- { "xor", 39 /* xt_iclass_bit */, +- 0, +- Opcode_xor_encode_fns, 0, 0 }, +- { "beqi", 40 /* xt_iclass_bsi8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_beqi_encode_fns, 0, 0 }, +- { "bnei", 40 /* xt_iclass_bsi8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnei_encode_fns, 0, 0 }, +- { "bgei", 40 /* xt_iclass_bsi8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgei_encode_fns, 0, 0 }, +- { "blti", 40 /* xt_iclass_bsi8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_blti_encode_fns, 0, 0 }, +- { "bbci", 41 /* xt_iclass_bsi8b */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbci_encode_fns, 0, 0 }, +- { "bbsi", 41 /* xt_iclass_bsi8b */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbsi_encode_fns, 0, 0 }, +- { "bgeui", 42 /* xt_iclass_bsi8u */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgeui_encode_fns, 0, 0 }, +- { "bltui", 42 /* xt_iclass_bsi8u */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bltui_encode_fns, 0, 0 }, +- { "beq", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_beq_encode_fns, 0, 0 }, +- { "bne", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bne_encode_fns, 0, 0 }, +- { "bge", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bge_encode_fns, 0, 0 }, +- { "blt", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_blt_encode_fns, 0, 0 }, +- { "bgeu", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgeu_encode_fns, 0, 0 }, +- { "bltu", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bltu_encode_fns, 0, 0 }, +- { "bany", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bany_encode_fns, 0, 0 }, +- { "bnone", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnone_encode_fns, 0, 0 }, +- { "ball", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_ball_encode_fns, 0, 0 }, +- { "bnall", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnall_encode_fns, 0, 0 }, +- { "bbc", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbc_encode_fns, 0, 0 }, +- { "bbs", 43 /* xt_iclass_bst8 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbs_encode_fns, 0, 0 }, +- { "beqz", 44 /* xt_iclass_bsz12 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_beqz_encode_fns, 0, 0 }, +- { "bnez", 44 /* xt_iclass_bsz12 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnez_encode_fns, 0, 0 }, +- { "bgez", 44 /* xt_iclass_bsz12 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgez_encode_fns, 0, 0 }, +- { "bltz", 44 /* xt_iclass_bsz12 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bltz_encode_fns, 0, 0 }, +- { "call0", 45 /* xt_iclass_call0 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_call0_encode_fns, 0, 0 }, +- { "callx0", 46 /* xt_iclass_callx0 */, +- XTENSA_OPCODE_IS_CALL, +- Opcode_callx0_encode_fns, 0, 0 }, +- { "extui", 47 /* xt_iclass_exti */, +- 0, +- Opcode_extui_encode_fns, 0, 0 }, +- { "ill", 48 /* xt_iclass_ill */, +- 0, +- Opcode_ill_encode_fns, 0, 0 }, +- { "j", 49 /* xt_iclass_jump */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_j_encode_fns, 0, 0 }, +- { "jx", 50 /* xt_iclass_jumpx */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_jx_encode_fns, 0, 0 }, +- { "l16ui", 51 /* xt_iclass_l16ui */, +- 0, +- Opcode_l16ui_encode_fns, 0, 0 }, +- { "l16si", 52 /* xt_iclass_l16si */, +- 0, +- Opcode_l16si_encode_fns, 0, 0 }, +- { "l32i", 53 /* xt_iclass_l32i */, +- 0, +- Opcode_l32i_encode_fns, 0, 0 }, +- { "l32r", 54 /* xt_iclass_l32r */, +- 0, +- Opcode_l32r_encode_fns, 0, 0 }, +- { "l8ui", 55 /* xt_iclass_l8i */, +- 0, +- Opcode_l8ui_encode_fns, 0, 0 }, +- { "loop", 56 /* xt_iclass_loop */, +- XTENSA_OPCODE_IS_LOOP, +- Opcode_loop_encode_fns, 0, 0 }, +- { "loopnez", 57 /* xt_iclass_loopz */, +- XTENSA_OPCODE_IS_LOOP, +- Opcode_loopnez_encode_fns, 0, 0 }, +- { "loopgtz", 57 /* xt_iclass_loopz */, +- XTENSA_OPCODE_IS_LOOP, +- Opcode_loopgtz_encode_fns, 0, 0 }, +- { "movi", 58 /* xt_iclass_movi */, +- 0, +- Opcode_movi_encode_fns, 0, 0 }, +- { "moveqz", 59 /* xt_iclass_movz */, +- 0, +- Opcode_moveqz_encode_fns, 0, 0 }, +- { "movnez", 59 /* xt_iclass_movz */, +- 0, +- Opcode_movnez_encode_fns, 0, 0 }, +- { "movltz", 59 /* xt_iclass_movz */, +- 0, +- Opcode_movltz_encode_fns, 0, 0 }, +- { "movgez", 59 /* xt_iclass_movz */, +- 0, +- Opcode_movgez_encode_fns, 0, 0 }, +- { "neg", 60 /* xt_iclass_neg */, +- 0, +- Opcode_neg_encode_fns, 0, 0 }, +- { "abs", 60 /* xt_iclass_neg */, +- 0, +- Opcode_abs_encode_fns, 0, 0 }, +- { "nop", 61 /* xt_iclass_nop */, +- 0, +- Opcode_nop_encode_fns, 0, 0 }, +- { "ret", 62 /* xt_iclass_return */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_ret_encode_fns, 0, 0 }, +- { "s16i", 63 /* xt_iclass_s16i */, +- 0, +- Opcode_s16i_encode_fns, 0, 0 }, +- { "s32i", 64 /* xt_iclass_s32i */, +- 0, +- Opcode_s32i_encode_fns, 0, 0 }, +- { "s8i", 65 /* xt_iclass_s8i */, +- 0, +- Opcode_s8i_encode_fns, 0, 0 }, +- { "ssr", 66 /* xt_iclass_sar */, +- 0, +- Opcode_ssr_encode_fns, 0, 0 }, +- { "ssl", 66 /* xt_iclass_sar */, +- 0, +- Opcode_ssl_encode_fns, 0, 0 }, +- { "ssa8l", 66 /* xt_iclass_sar */, +- 0, +- Opcode_ssa8l_encode_fns, 0, 0 }, +- { "ssa8b", 66 /* xt_iclass_sar */, +- 0, +- Opcode_ssa8b_encode_fns, 0, 0 }, +- { "ssai", 67 /* xt_iclass_sari */, +- 0, +- Opcode_ssai_encode_fns, 0, 0 }, +- { "sll", 68 /* xt_iclass_shifts */, +- 0, +- Opcode_sll_encode_fns, 0, 0 }, +- { "src", 69 /* xt_iclass_shiftst */, +- 0, +- Opcode_src_encode_fns, 0, 0 }, +- { "srl", 70 /* xt_iclass_shiftt */, +- 0, +- Opcode_srl_encode_fns, 0, 0 }, +- { "sra", 70 /* xt_iclass_shiftt */, +- 0, +- Opcode_sra_encode_fns, 0, 0 }, +- { "slli", 71 /* xt_iclass_slli */, +- 0, +- Opcode_slli_encode_fns, 0, 0 }, +- { "srai", 72 /* xt_iclass_srai */, +- 0, +- Opcode_srai_encode_fns, 0, 0 }, +- { "srli", 73 /* xt_iclass_srli */, +- 0, +- Opcode_srli_encode_fns, 0, 0 }, +- { "memw", 74 /* xt_iclass_memw */, +- 0, +- Opcode_memw_encode_fns, 0, 0 }, +- { "extw", 75 /* xt_iclass_extw */, +- 0, +- Opcode_extw_encode_fns, 0, 0 }, +- { "isync", 76 /* xt_iclass_isync */, +- 0, +- Opcode_isync_encode_fns, 0, 0 }, +- { "rsync", 77 /* xt_iclass_sync */, +- 0, +- Opcode_rsync_encode_fns, 0, 0 }, +- { "esync", 77 /* xt_iclass_sync */, +- 0, +- Opcode_esync_encode_fns, 0, 0 }, +- { "dsync", 77 /* xt_iclass_sync */, +- 0, +- Opcode_dsync_encode_fns, 0, 0 }, +- { "rsil", 78 /* xt_iclass_rsil */, +- 0, +- Opcode_rsil_encode_fns, 0, 0 }, +- { "rsr.lend", 79 /* xt_iclass_rsr.lend */, +- 0, +- Opcode_rsr_lend_encode_fns, 0, 0 }, +- { "wsr.lend", 80 /* xt_iclass_wsr.lend */, +- 0, +- Opcode_wsr_lend_encode_fns, 0, 0 }, +- { "xsr.lend", 81 /* xt_iclass_xsr.lend */, +- 0, +- Opcode_xsr_lend_encode_fns, 0, 0 }, +- { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, +- 0, +- Opcode_rsr_lcount_encode_fns, 0, 0 }, +- { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, +- 0, +- Opcode_wsr_lcount_encode_fns, 0, 0 }, +- { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, +- 0, +- Opcode_xsr_lcount_encode_fns, 0, 0 }, +- { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, +- 0, +- Opcode_rsr_lbeg_encode_fns, 0, 0 }, +- { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, +- 0, +- Opcode_wsr_lbeg_encode_fns, 0, 0 }, +- { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, +- 0, +- Opcode_xsr_lbeg_encode_fns, 0, 0 }, +- { "rsr.sar", 88 /* xt_iclass_rsr.sar */, +- 0, +- Opcode_rsr_sar_encode_fns, 0, 0 }, +- { "wsr.sar", 89 /* xt_iclass_wsr.sar */, +- 0, +- Opcode_wsr_sar_encode_fns, 0, 0 }, +- { "xsr.sar", 90 /* xt_iclass_xsr.sar */, +- 0, +- Opcode_xsr_sar_encode_fns, 0, 0 }, +- { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, +- 0, +- Opcode_rsr_litbase_encode_fns, 0, 0 }, +- { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, +- 0, +- Opcode_wsr_litbase_encode_fns, 0, 0 }, +- { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, +- 0, +- Opcode_xsr_litbase_encode_fns, 0, 0 }, +- { "rsr.176", 94 /* xt_iclass_rsr.176 */, +- 0, +- Opcode_rsr_176_encode_fns, 0, 0 }, +- { "rsr.208", 95 /* xt_iclass_rsr.208 */, +- 0, +- Opcode_rsr_208_encode_fns, 0, 0 }, +- { "rsr.ps", 96 /* xt_iclass_rsr.ps */, +- 0, +- Opcode_rsr_ps_encode_fns, 0, 0 }, +- { "wsr.ps", 97 /* xt_iclass_wsr.ps */, +- 0, +- Opcode_wsr_ps_encode_fns, 0, 0 }, +- { "xsr.ps", 98 /* xt_iclass_xsr.ps */, +- 0, +- Opcode_xsr_ps_encode_fns, 0, 0 }, +- { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, +- 0, +- Opcode_rsr_epc1_encode_fns, 0, 0 }, +- { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, +- 0, +- Opcode_wsr_epc1_encode_fns, 0, 0 }, +- { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, +- 0, +- Opcode_xsr_epc1_encode_fns, 0, 0 }, +- { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, +- 0, +- Opcode_rsr_excsave1_encode_fns, 0, 0 }, +- { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, +- 0, +- Opcode_wsr_excsave1_encode_fns, 0, 0 }, +- { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, +- 0, +- Opcode_xsr_excsave1_encode_fns, 0, 0 }, +- { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, +- 0, +- Opcode_rsr_epc2_encode_fns, 0, 0 }, +- { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, +- 0, +- Opcode_wsr_epc2_encode_fns, 0, 0 }, +- { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, +- 0, +- Opcode_xsr_epc2_encode_fns, 0, 0 }, +- { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, +- 0, +- Opcode_rsr_excsave2_encode_fns, 0, 0 }, +- { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, +- 0, +- Opcode_wsr_excsave2_encode_fns, 0, 0 }, +- { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, +- 0, +- Opcode_xsr_excsave2_encode_fns, 0, 0 }, +- { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, +- 0, +- Opcode_rsr_epc3_encode_fns, 0, 0 }, +- { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, +- 0, +- Opcode_wsr_epc3_encode_fns, 0, 0 }, +- { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, +- 0, +- Opcode_xsr_epc3_encode_fns, 0, 0 }, +- { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, +- 0, +- Opcode_rsr_excsave3_encode_fns, 0, 0 }, +- { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, +- 0, +- Opcode_wsr_excsave3_encode_fns, 0, 0 }, +- { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, +- 0, +- Opcode_xsr_excsave3_encode_fns, 0, 0 }, +- { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, +- 0, +- Opcode_rsr_epc4_encode_fns, 0, 0 }, +- { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, +- 0, +- Opcode_wsr_epc4_encode_fns, 0, 0 }, +- { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, +- 0, +- Opcode_xsr_epc4_encode_fns, 0, 0 }, +- { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, +- 0, +- Opcode_rsr_excsave4_encode_fns, 0, 0 }, +- { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, +- 0, +- Opcode_wsr_excsave4_encode_fns, 0, 0 }, +- { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, +- 0, +- Opcode_xsr_excsave4_encode_fns, 0, 0 }, +- { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, +- 0, +- Opcode_rsr_epc5_encode_fns, 0, 0 }, +- { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, +- 0, +- Opcode_wsr_epc5_encode_fns, 0, 0 }, +- { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, +- 0, +- Opcode_xsr_epc5_encode_fns, 0, 0 }, +- { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, +- 0, +- Opcode_rsr_excsave5_encode_fns, 0, 0 }, +- { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, +- 0, +- Opcode_wsr_excsave5_encode_fns, 0, 0 }, +- { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, +- 0, +- Opcode_xsr_excsave5_encode_fns, 0, 0 }, +- { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, +- 0, +- Opcode_rsr_epc6_encode_fns, 0, 0 }, +- { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, +- 0, +- Opcode_wsr_epc6_encode_fns, 0, 0 }, +- { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, +- 0, +- Opcode_xsr_epc6_encode_fns, 0, 0 }, +- { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, +- 0, +- Opcode_rsr_excsave6_encode_fns, 0, 0 }, +- { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, +- 0, +- Opcode_wsr_excsave6_encode_fns, 0, 0 }, +- { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, +- 0, +- Opcode_xsr_excsave6_encode_fns, 0, 0 }, +- { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, +- 0, +- Opcode_rsr_epc7_encode_fns, 0, 0 }, +- { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, +- 0, +- Opcode_wsr_epc7_encode_fns, 0, 0 }, +- { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, +- 0, +- Opcode_xsr_epc7_encode_fns, 0, 0 }, +- { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, +- 0, +- Opcode_rsr_excsave7_encode_fns, 0, 0 }, +- { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, +- 0, +- Opcode_wsr_excsave7_encode_fns, 0, 0 }, +- { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, +- 0, +- Opcode_xsr_excsave7_encode_fns, 0, 0 }, +- { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, +- 0, +- Opcode_rsr_eps2_encode_fns, 0, 0 }, +- { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, +- 0, +- Opcode_wsr_eps2_encode_fns, 0, 0 }, +- { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, +- 0, +- Opcode_xsr_eps2_encode_fns, 0, 0 }, +- { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, +- 0, +- Opcode_rsr_eps3_encode_fns, 0, 0 }, +- { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, +- 0, +- Opcode_wsr_eps3_encode_fns, 0, 0 }, +- { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, +- 0, +- Opcode_xsr_eps3_encode_fns, 0, 0 }, +- { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, +- 0, +- Opcode_rsr_eps4_encode_fns, 0, 0 }, +- { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, +- 0, +- Opcode_wsr_eps4_encode_fns, 0, 0 }, +- { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, +- 0, +- Opcode_xsr_eps4_encode_fns, 0, 0 }, +- { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, +- 0, +- Opcode_rsr_eps5_encode_fns, 0, 0 }, +- { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, +- 0, +- Opcode_wsr_eps5_encode_fns, 0, 0 }, +- { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, +- 0, +- Opcode_xsr_eps5_encode_fns, 0, 0 }, +- { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, +- 0, +- Opcode_rsr_eps6_encode_fns, 0, 0 }, +- { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, +- 0, +- Opcode_wsr_eps6_encode_fns, 0, 0 }, +- { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, +- 0, +- Opcode_xsr_eps6_encode_fns, 0, 0 }, +- { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, +- 0, +- Opcode_rsr_eps7_encode_fns, 0, 0 }, +- { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, +- 0, +- Opcode_wsr_eps7_encode_fns, 0, 0 }, +- { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, +- 0, +- Opcode_xsr_eps7_encode_fns, 0, 0 }, +- { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, +- 0, +- Opcode_rsr_excvaddr_encode_fns, 0, 0 }, +- { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, +- 0, +- Opcode_wsr_excvaddr_encode_fns, 0, 0 }, +- { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, +- 0, +- Opcode_xsr_excvaddr_encode_fns, 0, 0 }, +- { "rsr.depc", 162 /* xt_iclass_rsr.depc */, +- 0, +- Opcode_rsr_depc_encode_fns, 0, 0 }, +- { "wsr.depc", 163 /* xt_iclass_wsr.depc */, +- 0, +- Opcode_wsr_depc_encode_fns, 0, 0 }, +- { "xsr.depc", 164 /* xt_iclass_xsr.depc */, +- 0, +- Opcode_xsr_depc_encode_fns, 0, 0 }, +- { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, +- 0, +- Opcode_rsr_exccause_encode_fns, 0, 0 }, +- { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, +- 0, +- Opcode_wsr_exccause_encode_fns, 0, 0 }, +- { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, +- 0, +- Opcode_xsr_exccause_encode_fns, 0, 0 }, +- { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, +- 0, +- Opcode_rsr_misc0_encode_fns, 0, 0 }, +- { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, +- 0, +- Opcode_wsr_misc0_encode_fns, 0, 0 }, +- { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, +- 0, +- Opcode_xsr_misc0_encode_fns, 0, 0 }, +- { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, +- 0, +- Opcode_rsr_misc1_encode_fns, 0, 0 }, +- { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, +- 0, +- Opcode_wsr_misc1_encode_fns, 0, 0 }, +- { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, +- 0, +- Opcode_xsr_misc1_encode_fns, 0, 0 }, +- { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */, +- 0, +- Opcode_rsr_misc2_encode_fns, 0, 0 }, +- { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */, +- 0, +- Opcode_wsr_misc2_encode_fns, 0, 0 }, +- { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */, +- 0, +- Opcode_xsr_misc2_encode_fns, 0, 0 }, +- { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */, +- 0, +- Opcode_rsr_misc3_encode_fns, 0, 0 }, +- { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */, +- 0, +- Opcode_wsr_misc3_encode_fns, 0, 0 }, +- { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */, +- 0, +- Opcode_xsr_misc3_encode_fns, 0, 0 }, +- { "rsr.prid", 180 /* xt_iclass_rsr.prid */, +- 0, +- Opcode_rsr_prid_encode_fns, 0, 0 }, +- { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */, +- 0, +- Opcode_rsr_vecbase_encode_fns, 0, 0 }, +- { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */, +- 0, +- Opcode_wsr_vecbase_encode_fns, 0, 0 }, +- { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */, +- 0, +- Opcode_xsr_vecbase_encode_fns, 0, 0 }, +- { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_mul_aa_ll_encode_fns, 0, 0 }, +- { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_mul_aa_hl_encode_fns, 0, 0 }, +- { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_mul_aa_lh_encode_fns, 0, 0 }, +- { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_mul_aa_hh_encode_fns, 0, 0 }, +- { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_umul_aa_ll_encode_fns, 0, 0 }, +- { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_umul_aa_hl_encode_fns, 0, 0 }, +- { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_umul_aa_lh_encode_fns, 0, 0 }, +- { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */, +- 0, +- Opcode_umul_aa_hh_encode_fns, 0, 0 }, +- { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */, +- 0, +- Opcode_mul_ad_ll_encode_fns, 0, 0 }, +- { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */, +- 0, +- Opcode_mul_ad_hl_encode_fns, 0, 0 }, +- { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */, +- 0, +- Opcode_mul_ad_lh_encode_fns, 0, 0 }, +- { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */, +- 0, +- Opcode_mul_ad_hh_encode_fns, 0, 0 }, +- { "mul.da.ll", 186 /* xt_iclass_mac16_da */, +- 0, +- Opcode_mul_da_ll_encode_fns, 0, 0 }, +- { "mul.da.hl", 186 /* xt_iclass_mac16_da */, +- 0, +- Opcode_mul_da_hl_encode_fns, 0, 0 }, +- { "mul.da.lh", 186 /* xt_iclass_mac16_da */, +- 0, +- Opcode_mul_da_lh_encode_fns, 0, 0 }, +- { "mul.da.hh", 186 /* xt_iclass_mac16_da */, +- 0, +- Opcode_mul_da_hh_encode_fns, 0, 0 }, +- { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */, +- 0, +- Opcode_mul_dd_ll_encode_fns, 0, 0 }, +- { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */, +- 0, +- Opcode_mul_dd_hl_encode_fns, 0, 0 }, +- { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */, +- 0, +- Opcode_mul_dd_lh_encode_fns, 0, 0 }, +- { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */, +- 0, +- Opcode_mul_dd_hh_encode_fns, 0, 0 }, +- { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_mula_aa_ll_encode_fns, 0, 0 }, +- { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_mula_aa_hl_encode_fns, 0, 0 }, +- { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_mula_aa_lh_encode_fns, 0, 0 }, +- { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_mula_aa_hh_encode_fns, 0, 0 }, +- { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_muls_aa_ll_encode_fns, 0, 0 }, +- { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_muls_aa_hl_encode_fns, 0, 0 }, +- { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_muls_aa_lh_encode_fns, 0, 0 }, +- { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */, +- 0, +- Opcode_muls_aa_hh_encode_fns, 0, 0 }, +- { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_mula_ad_ll_encode_fns, 0, 0 }, +- { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_mula_ad_hl_encode_fns, 0, 0 }, +- { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_mula_ad_lh_encode_fns, 0, 0 }, +- { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_mula_ad_hh_encode_fns, 0, 0 }, +- { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_muls_ad_ll_encode_fns, 0, 0 }, +- { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_muls_ad_hl_encode_fns, 0, 0 }, +- { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_muls_ad_lh_encode_fns, 0, 0 }, +- { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */, +- 0, +- Opcode_muls_ad_hh_encode_fns, 0, 0 }, +- { "mula.da.ll", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_mula_da_ll_encode_fns, 0, 0 }, +- { "mula.da.hl", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_mula_da_hl_encode_fns, 0, 0 }, +- { "mula.da.lh", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_mula_da_lh_encode_fns, 0, 0 }, +- { "mula.da.hh", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_mula_da_hh_encode_fns, 0, 0 }, +- { "muls.da.ll", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_muls_da_ll_encode_fns, 0, 0 }, +- { "muls.da.hl", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_muls_da_hl_encode_fns, 0, 0 }, +- { "muls.da.lh", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_muls_da_lh_encode_fns, 0, 0 }, +- { "muls.da.hh", 190 /* xt_iclass_mac16a_da */, +- 0, +- Opcode_muls_da_hh_encode_fns, 0, 0 }, +- { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_mula_dd_ll_encode_fns, 0, 0 }, +- { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_mula_dd_hl_encode_fns, 0, 0 }, +- { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_mula_dd_lh_encode_fns, 0, 0 }, +- { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_mula_dd_hh_encode_fns, 0, 0 }, +- { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_muls_dd_ll_encode_fns, 0, 0 }, +- { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_muls_dd_hl_encode_fns, 0, 0 }, +- { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_muls_dd_lh_encode_fns, 0, 0 }, +- { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */, +- 0, +- Opcode_muls_dd_hh_encode_fns, 0, 0 }, +- { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, +- { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, +- { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, +- { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, +- { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, +- { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, +- { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, +- { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */, +- 0, +- Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, +- { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, +- { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, +- { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, +- { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, +- { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, +- { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, +- { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, +- { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */, +- 0, +- Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, +- { "lddec", 194 /* xt_iclass_mac16_l */, +- 0, +- Opcode_lddec_encode_fns, 0, 0 }, +- { "ldinc", 194 /* xt_iclass_mac16_l */, +- 0, +- Opcode_ldinc_encode_fns, 0, 0 }, +- { "mul16u", 195 /* xt_iclass_mul16 */, +- 0, +- Opcode_mul16u_encode_fns, 0, 0 }, +- { "mul16s", 195 /* xt_iclass_mul16 */, +- 0, +- Opcode_mul16s_encode_fns, 0, 0 }, +- { "rsr.m0", 196 /* xt_iclass_rsr.m0 */, +- 0, +- Opcode_rsr_m0_encode_fns, 0, 0 }, +- { "wsr.m0", 197 /* xt_iclass_wsr.m0 */, +- 0, +- Opcode_wsr_m0_encode_fns, 0, 0 }, +- { "xsr.m0", 198 /* xt_iclass_xsr.m0 */, +- 0, +- Opcode_xsr_m0_encode_fns, 0, 0 }, +- { "rsr.m1", 199 /* xt_iclass_rsr.m1 */, +- 0, +- Opcode_rsr_m1_encode_fns, 0, 0 }, +- { "wsr.m1", 200 /* xt_iclass_wsr.m1 */, +- 0, +- Opcode_wsr_m1_encode_fns, 0, 0 }, +- { "xsr.m1", 201 /* xt_iclass_xsr.m1 */, +- 0, +- Opcode_xsr_m1_encode_fns, 0, 0 }, +- { "rsr.m2", 202 /* xt_iclass_rsr.m2 */, +- 0, +- Opcode_rsr_m2_encode_fns, 0, 0 }, +- { "wsr.m2", 203 /* xt_iclass_wsr.m2 */, +- 0, +- Opcode_wsr_m2_encode_fns, 0, 0 }, +- { "xsr.m2", 204 /* xt_iclass_xsr.m2 */, +- 0, +- Opcode_xsr_m2_encode_fns, 0, 0 }, +- { "rsr.m3", 205 /* xt_iclass_rsr.m3 */, +- 0, +- Opcode_rsr_m3_encode_fns, 0, 0 }, +- { "wsr.m3", 206 /* xt_iclass_wsr.m3 */, +- 0, +- Opcode_wsr_m3_encode_fns, 0, 0 }, +- { "xsr.m3", 207 /* xt_iclass_xsr.m3 */, +- 0, +- Opcode_xsr_m3_encode_fns, 0, 0 }, +- { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */, +- 0, +- Opcode_rsr_acclo_encode_fns, 0, 0 }, +- { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */, +- 0, +- Opcode_wsr_acclo_encode_fns, 0, 0 }, +- { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */, +- 0, +- Opcode_xsr_acclo_encode_fns, 0, 0 }, +- { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */, +- 0, +- Opcode_rsr_acchi_encode_fns, 0, 0 }, +- { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */, +- 0, +- Opcode_wsr_acchi_encode_fns, 0, 0 }, +- { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */, +- 0, +- Opcode_xsr_acchi_encode_fns, 0, 0 }, +- { "rfi", 214 /* xt_iclass_rfi */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_rfi_encode_fns, 0, 0 }, +- { "waiti", 215 /* xt_iclass_wait */, +- 0, +- Opcode_waiti_encode_fns, 0, 0 }, +- { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */, +- 0, +- Opcode_rsr_interrupt_encode_fns, 0, 0 }, +- { "wsr.intset", 217 /* xt_iclass_wsr.intset */, +- 0, +- Opcode_wsr_intset_encode_fns, 0, 0 }, +- { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */, +- 0, +- Opcode_wsr_intclear_encode_fns, 0, 0 }, +- { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */, +- 0, +- Opcode_rsr_intenable_encode_fns, 0, 0 }, +- { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */, +- 0, +- Opcode_wsr_intenable_encode_fns, 0, 0 }, +- { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */, +- 0, +- Opcode_xsr_intenable_encode_fns, 0, 0 }, +- { "break", 222 /* xt_iclass_break */, +- 0, +- Opcode_break_encode_fns, 0, 0 }, +- { "break.n", 223 /* xt_iclass_break.n */, +- 0, +- Opcode_break_n_encode_fns, 0, 0 }, +- { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */, +- 0, +- Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, +- { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */, +- 0, +- Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, +- { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */, +- 0, +- Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, +- { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */, +- 0, +- Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, +- { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */, +- 0, +- Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, +- { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */, +- 0, +- Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, +- { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */, +- 0, +- Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, +- { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */, +- 0, +- Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, +- { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */, +- 0, +- Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, +- { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */, +- 0, +- Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, +- { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */, +- 0, +- Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, +- { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */, +- 0, +- Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, +- { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */, +- 0, +- Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, +- { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */, +- 0, +- Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, +- { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */, +- 0, +- Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, +- { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */, +- 0, +- Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, +- { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */, +- 0, +- Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, +- { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */, +- 0, +- Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, +- { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */, +- 0, +- Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, +- { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */, +- 0, +- Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, +- { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */, +- 0, +- Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, +- { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */, +- 0, +- Opcode_rsr_debugcause_encode_fns, 0, 0 }, +- { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */, +- 0, +- Opcode_wsr_debugcause_encode_fns, 0, 0 }, +- { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */, +- 0, +- Opcode_xsr_debugcause_encode_fns, 0, 0 }, +- { "rsr.icount", 248 /* xt_iclass_rsr.icount */, +- 0, +- Opcode_rsr_icount_encode_fns, 0, 0 }, +- { "wsr.icount", 249 /* xt_iclass_wsr.icount */, +- 0, +- Opcode_wsr_icount_encode_fns, 0, 0 }, +- { "xsr.icount", 250 /* xt_iclass_xsr.icount */, +- 0, +- Opcode_xsr_icount_encode_fns, 0, 0 }, +- { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */, +- 0, +- Opcode_rsr_icountlevel_encode_fns, 0, 0 }, +- { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */, +- 0, +- Opcode_wsr_icountlevel_encode_fns, 0, 0 }, +- { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */, +- 0, +- Opcode_xsr_icountlevel_encode_fns, 0, 0 }, +- { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */, +- 0, +- Opcode_rsr_ddr_encode_fns, 0, 0 }, +- { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */, +- 0, +- Opcode_wsr_ddr_encode_fns, 0, 0 }, +- { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */, +- 0, +- Opcode_xsr_ddr_encode_fns, 0, 0 }, +- { "rfdo", 257 /* xt_iclass_rfdo */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_rfdo_encode_fns, 0, 0 }, +- { "rfdd", 258 /* xt_iclass_rfdd */, +- XTENSA_OPCODE_IS_JUMP, +- Opcode_rfdd_encode_fns, 0, 0 }, +- { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */, +- 0, +- Opcode_wsr_mmid_encode_fns, 0, 0 }, +- { "andb", 260 /* xt_iclass_bbool1 */, +- 0, +- Opcode_andb_encode_fns, 0, 0 }, +- { "andbc", 260 /* xt_iclass_bbool1 */, +- 0, +- Opcode_andbc_encode_fns, 0, 0 }, +- { "orb", 260 /* xt_iclass_bbool1 */, +- 0, +- Opcode_orb_encode_fns, 0, 0 }, +- { "orbc", 260 /* xt_iclass_bbool1 */, +- 0, +- Opcode_orbc_encode_fns, 0, 0 }, +- { "xorb", 260 /* xt_iclass_bbool1 */, +- 0, +- Opcode_xorb_encode_fns, 0, 0 }, +- { "any4", 261 /* xt_iclass_bbool4 */, +- 0, +- Opcode_any4_encode_fns, 0, 0 }, +- { "all4", 261 /* xt_iclass_bbool4 */, +- 0, +- Opcode_all4_encode_fns, 0, 0 }, +- { "any8", 262 /* xt_iclass_bbool8 */, +- 0, +- Opcode_any8_encode_fns, 0, 0 }, +- { "all8", 262 /* xt_iclass_bbool8 */, +- 0, +- Opcode_all8_encode_fns, 0, 0 }, +- { "bf", 263 /* xt_iclass_bbranch */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bf_encode_fns, 0, 0 }, +- { "bt", 263 /* xt_iclass_bbranch */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bt_encode_fns, 0, 0 }, +- { "movf", 264 /* xt_iclass_bmove */, +- 0, +- Opcode_movf_encode_fns, 0, 0 }, +- { "movt", 264 /* xt_iclass_bmove */, +- 0, +- Opcode_movt_encode_fns, 0, 0 }, +- { "rsr.br", 265 /* xt_iclass_RSR.BR */, +- 0, +- Opcode_rsr_br_encode_fns, 0, 0 }, +- { "wsr.br", 266 /* xt_iclass_WSR.BR */, +- 0, +- Opcode_wsr_br_encode_fns, 0, 0 }, +- { "xsr.br", 267 /* xt_iclass_XSR.BR */, +- 0, +- Opcode_xsr_br_encode_fns, 0, 0 }, +- { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */, +- 0, +- Opcode_rsr_ccount_encode_fns, 0, 0 }, +- { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */, +- 0, +- Opcode_wsr_ccount_encode_fns, 0, 0 }, +- { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */, +- 0, +- Opcode_xsr_ccount_encode_fns, 0, 0 }, +- { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */, +- 0, +- Opcode_rsr_ccompare0_encode_fns, 0, 0 }, +- { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */, +- 0, +- Opcode_wsr_ccompare0_encode_fns, 0, 0 }, +- { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */, +- 0, +- Opcode_xsr_ccompare0_encode_fns, 0, 0 }, +- { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */, +- 0, +- Opcode_rsr_ccompare1_encode_fns, 0, 0 }, +- { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */, +- 0, +- Opcode_wsr_ccompare1_encode_fns, 0, 0 }, +- { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */, +- 0, +- Opcode_xsr_ccompare1_encode_fns, 0, 0 }, +- { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */, +- 0, +- Opcode_rsr_ccompare2_encode_fns, 0, 0 }, +- { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */, +- 0, +- Opcode_wsr_ccompare2_encode_fns, 0, 0 }, +- { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */, +- 0, +- Opcode_xsr_ccompare2_encode_fns, 0, 0 }, +- { "ipf", 280 /* xt_iclass_icache */, +- 0, +- Opcode_ipf_encode_fns, 0, 0 }, +- { "ihi", 280 /* xt_iclass_icache */, +- 0, +- Opcode_ihi_encode_fns, 0, 0 }, +- { "ipfl", 281 /* xt_iclass_icache_lock */, +- 0, +- Opcode_ipfl_encode_fns, 0, 0 }, +- { "ihu", 281 /* xt_iclass_icache_lock */, +- 0, +- Opcode_ihu_encode_fns, 0, 0 }, +- { "iiu", 281 /* xt_iclass_icache_lock */, +- 0, +- Opcode_iiu_encode_fns, 0, 0 }, +- { "iii", 282 /* xt_iclass_icache_inv */, +- 0, +- Opcode_iii_encode_fns, 0, 0 }, +- { "lict", 283 /* xt_iclass_licx */, +- 0, +- Opcode_lict_encode_fns, 0, 0 }, +- { "licw", 283 /* xt_iclass_licx */, +- 0, +- Opcode_licw_encode_fns, 0, 0 }, +- { "sict", 284 /* xt_iclass_sicx */, +- 0, +- Opcode_sict_encode_fns, 0, 0 }, +- { "sicw", 284 /* xt_iclass_sicx */, +- 0, +- Opcode_sicw_encode_fns, 0, 0 }, +- { "dhwb", 285 /* xt_iclass_dcache */, +- 0, +- Opcode_dhwb_encode_fns, 0, 0 }, +- { "dhwbi", 285 /* xt_iclass_dcache */, +- 0, +- Opcode_dhwbi_encode_fns, 0, 0 }, +- { "diwb", 286 /* xt_iclass_dcache_ind */, +- 0, +- Opcode_diwb_encode_fns, 0, 0 }, +- { "diwbi", 286 /* xt_iclass_dcache_ind */, +- 0, +- Opcode_diwbi_encode_fns, 0, 0 }, +- { "dhi", 287 /* xt_iclass_dcache_inv */, +- 0, +- Opcode_dhi_encode_fns, 0, 0 }, +- { "dii", 287 /* xt_iclass_dcache_inv */, +- 0, +- Opcode_dii_encode_fns, 0, 0 }, +- { "dpfr", 288 /* xt_iclass_dpf */, +- 0, +- Opcode_dpfr_encode_fns, 0, 0 }, +- { "dpfw", 288 /* xt_iclass_dpf */, +- 0, +- Opcode_dpfw_encode_fns, 0, 0 }, +- { "dpfro", 288 /* xt_iclass_dpf */, +- 0, +- Opcode_dpfro_encode_fns, 0, 0 }, +- { "dpfwo", 288 /* xt_iclass_dpf */, +- 0, +- Opcode_dpfwo_encode_fns, 0, 0 }, +- { "dpfl", 289 /* xt_iclass_dcache_lock */, +- 0, +- Opcode_dpfl_encode_fns, 0, 0 }, +- { "dhu", 289 /* xt_iclass_dcache_lock */, +- 0, +- Opcode_dhu_encode_fns, 0, 0 }, +- { "diu", 289 /* xt_iclass_dcache_lock */, +- 0, +- Opcode_diu_encode_fns, 0, 0 }, +- { "sdct", 290 /* xt_iclass_sdct */, +- 0, +- Opcode_sdct_encode_fns, 0, 0 }, +- { "ldct", 291 /* xt_iclass_ldct */, +- 0, +- Opcode_ldct_encode_fns, 0, 0 }, +- { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */, +- 0, +- Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, +- { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */, +- 0, +- Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, +- { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */, +- 0, +- Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, +- { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */, +- 0, +- Opcode_rsr_rasid_encode_fns, 0, 0 }, +- { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */, +- 0, +- Opcode_wsr_rasid_encode_fns, 0, 0 }, +- { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */, +- 0, +- Opcode_xsr_rasid_encode_fns, 0, 0 }, +- { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */, +- 0, +- Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, +- { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */, +- 0, +- Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, +- { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */, +- 0, +- Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, +- { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */, +- 0, +- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, +- { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */, +- 0, +- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, +- { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */, +- 0, +- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, +- { "idtlb", 304 /* xt_iclass_idtlb */, +- 0, +- Opcode_idtlb_encode_fns, 0, 0 }, +- { "pdtlb", 305 /* xt_iclass_rdtlb */, +- 0, +- Opcode_pdtlb_encode_fns, 0, 0 }, +- { "rdtlb0", 305 /* xt_iclass_rdtlb */, +- 0, +- Opcode_rdtlb0_encode_fns, 0, 0 }, +- { "rdtlb1", 305 /* xt_iclass_rdtlb */, +- 0, +- Opcode_rdtlb1_encode_fns, 0, 0 }, +- { "wdtlb", 306 /* xt_iclass_wdtlb */, +- 0, +- Opcode_wdtlb_encode_fns, 0, 0 }, +- { "iitlb", 307 /* xt_iclass_iitlb */, +- 0, +- Opcode_iitlb_encode_fns, 0, 0 }, +- { "pitlb", 308 /* xt_iclass_ritlb */, +- 0, +- Opcode_pitlb_encode_fns, 0, 0 }, +- { "ritlb0", 308 /* xt_iclass_ritlb */, +- 0, +- Opcode_ritlb0_encode_fns, 0, 0 }, +- { "ritlb1", 308 /* xt_iclass_ritlb */, +- 0, +- Opcode_ritlb1_encode_fns, 0, 0 }, +- { "witlb", 309 /* xt_iclass_witlb */, +- 0, +- Opcode_witlb_encode_fns, 0, 0 }, +- { "ldpte", 310 /* xt_iclass_ldpte */, +- 0, +- Opcode_ldpte_encode_fns, 0, 0 }, +- { "hwwitlba", 311 /* xt_iclass_hwwitlba */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_hwwitlba_encode_fns, 0, 0 }, +- { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */, +- 0, +- Opcode_hwwdtlba_encode_fns, 0, 0 }, +- { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */, +- 0, +- Opcode_rsr_cpenable_encode_fns, 0, 0 }, +- { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */, +- 0, +- Opcode_wsr_cpenable_encode_fns, 0, 0 }, +- { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */, +- 0, +- Opcode_xsr_cpenable_encode_fns, 0, 0 }, +- { "clamps", 316 /* xt_iclass_clamp */, +- 0, +- Opcode_clamps_encode_fns, 0, 0 }, +- { "min", 317 /* xt_iclass_minmax */, +- 0, +- Opcode_min_encode_fns, 0, 0 }, +- { "max", 317 /* xt_iclass_minmax */, +- 0, +- Opcode_max_encode_fns, 0, 0 }, +- { "minu", 317 /* xt_iclass_minmax */, +- 0, +- Opcode_minu_encode_fns, 0, 0 }, +- { "maxu", 317 /* xt_iclass_minmax */, +- 0, +- Opcode_maxu_encode_fns, 0, 0 }, +- { "nsa", 318 /* xt_iclass_nsa */, +- 0, +- Opcode_nsa_encode_fns, 0, 0 }, +- { "nsau", 318 /* xt_iclass_nsa */, +- 0, +- Opcode_nsau_encode_fns, 0, 0 }, +- { "sext", 319 /* xt_iclass_sx */, +- 0, +- Opcode_sext_encode_fns, 0, 0 }, +- { "l32ai", 320 /* xt_iclass_l32ai */, +- 0, +- Opcode_l32ai_encode_fns, 0, 0 }, +- { "s32ri", 321 /* xt_iclass_s32ri */, +- 0, +- Opcode_s32ri_encode_fns, 0, 0 }, +- { "s32c1i", 322 /* xt_iclass_s32c1i */, +- 0, +- Opcode_s32c1i_encode_fns, 0, 0 }, +- { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */, +- 0, +- Opcode_rsr_scompare1_encode_fns, 0, 0 }, +- { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */, +- 0, +- Opcode_wsr_scompare1_encode_fns, 0, 0 }, +- { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */, +- 0, +- Opcode_xsr_scompare1_encode_fns, 0, 0 }, +- { "quou", 326 /* xt_iclass_div */, +- 0, +- Opcode_quou_encode_fns, 0, 0 }, +- { "quos", 326 /* xt_iclass_div */, +- 0, +- Opcode_quos_encode_fns, 0, 0 }, +- { "remu", 326 /* xt_iclass_div */, +- 0, +- Opcode_remu_encode_fns, 0, 0 }, +- { "rems", 326 /* xt_iclass_div */, +- 0, +- Opcode_rems_encode_fns, 0, 0 }, +- { "mull", 327 /* xt_mul32 */, +- 0, +- Opcode_mull_encode_fns, 0, 0 }, +- { "muluh", 327 /* xt_mul32 */, +- 0, +- Opcode_muluh_encode_fns, 0, 0 }, +- { "mulsh", 327 /* xt_mul32 */, +- 0, +- Opcode_mulsh_encode_fns, 0, 0 }, +- { "rur.fcr", 328 /* rur_fcr */, +- 0, +- Opcode_rur_fcr_encode_fns, 0, 0 }, +- { "wur.fcr", 329 /* wur_fcr */, +- 0, +- Opcode_wur_fcr_encode_fns, 0, 0 }, +- { "rur.fsr", 330 /* rur_fsr */, +- 0, +- Opcode_rur_fsr_encode_fns, 0, 0 }, +- { "wur.fsr", 331 /* wur_fsr */, +- 0, +- Opcode_wur_fsr_encode_fns, 0, 0 }, +- { "add.s", 332 /* fp */, +- 0, +- Opcode_add_s_encode_fns, 0, 0 }, +- { "sub.s", 332 /* fp */, +- 0, +- Opcode_sub_s_encode_fns, 0, 0 }, +- { "mul.s", 332 /* fp */, +- 0, +- Opcode_mul_s_encode_fns, 0, 0 }, +- { "madd.s", 333 /* fp_mac */, +- 0, +- Opcode_madd_s_encode_fns, 0, 0 }, +- { "msub.s", 333 /* fp_mac */, +- 0, +- Opcode_msub_s_encode_fns, 0, 0 }, +- { "movf.s", 334 /* fp_cmov */, +- 0, +- Opcode_movf_s_encode_fns, 0, 0 }, +- { "movt.s", 334 /* fp_cmov */, +- 0, +- Opcode_movt_s_encode_fns, 0, 0 }, +- { "moveqz.s", 335 /* fp_mov */, +- 0, +- Opcode_moveqz_s_encode_fns, 0, 0 }, +- { "movnez.s", 335 /* fp_mov */, +- 0, +- Opcode_movnez_s_encode_fns, 0, 0 }, +- { "movltz.s", 335 /* fp_mov */, +- 0, +- Opcode_movltz_s_encode_fns, 0, 0 }, +- { "movgez.s", 335 /* fp_mov */, +- 0, +- Opcode_movgez_s_encode_fns, 0, 0 }, +- { "abs.s", 336 /* fp_mov2 */, +- 0, +- Opcode_abs_s_encode_fns, 0, 0 }, +- { "mov.s", 336 /* fp_mov2 */, +- 0, +- Opcode_mov_s_encode_fns, 0, 0 }, +- { "neg.s", 336 /* fp_mov2 */, +- 0, +- Opcode_neg_s_encode_fns, 0, 0 }, +- { "un.s", 337 /* fp_cmp */, +- 0, +- Opcode_un_s_encode_fns, 0, 0 }, +- { "oeq.s", 337 /* fp_cmp */, +- 0, +- Opcode_oeq_s_encode_fns, 0, 0 }, +- { "ueq.s", 337 /* fp_cmp */, +- 0, +- Opcode_ueq_s_encode_fns, 0, 0 }, +- { "olt.s", 337 /* fp_cmp */, +- 0, +- Opcode_olt_s_encode_fns, 0, 0 }, +- { "ult.s", 337 /* fp_cmp */, +- 0, +- Opcode_ult_s_encode_fns, 0, 0 }, +- { "ole.s", 337 /* fp_cmp */, +- 0, +- Opcode_ole_s_encode_fns, 0, 0 }, +- { "ule.s", 337 /* fp_cmp */, +- 0, +- Opcode_ule_s_encode_fns, 0, 0 }, +- { "float.s", 338 /* fp_float */, +- 0, +- Opcode_float_s_encode_fns, 0, 0 }, +- { "ufloat.s", 338 /* fp_float */, +- 0, +- Opcode_ufloat_s_encode_fns, 0, 0 }, +- { "round.s", 339 /* fp_int */, +- 0, +- Opcode_round_s_encode_fns, 0, 0 }, +- { "ceil.s", 339 /* fp_int */, +- 0, +- Opcode_ceil_s_encode_fns, 0, 0 }, +- { "floor.s", 339 /* fp_int */, +- 0, +- Opcode_floor_s_encode_fns, 0, 0 }, +- { "trunc.s", 339 /* fp_int */, +- 0, +- Opcode_trunc_s_encode_fns, 0, 0 }, +- { "utrunc.s", 339 /* fp_int */, +- 0, +- Opcode_utrunc_s_encode_fns, 0, 0 }, +- { "rfr", 340 /* fp_rfr */, +- 0, +- Opcode_rfr_encode_fns, 0, 0 }, +- { "wfr", 341 /* fp_wfr */, +- 0, +- Opcode_wfr_encode_fns, 0, 0 }, +- { "lsi", 342 /* fp_lsi */, +- 0, +- Opcode_lsi_encode_fns, 0, 0 }, +- { "lsiu", 343 /* fp_lsiu */, +- 0, +- Opcode_lsiu_encode_fns, 0, 0 }, +- { "lsx", 344 /* fp_lsx */, +- 0, +- Opcode_lsx_encode_fns, 0, 0 }, +- { "lsxu", 345 /* fp_lsxu */, +- 0, +- Opcode_lsxu_encode_fns, 0, 0 }, +- { "ssi", 346 /* fp_ssi */, +- 0, +- Opcode_ssi_encode_fns, 0, 0 }, +- { "ssiu", 347 /* fp_ssiu */, +- 0, +- Opcode_ssiu_encode_fns, 0, 0 }, +- { "ssx", 348 /* fp_ssx */, +- 0, +- Opcode_ssx_encode_fns, 0, 0 }, +- { "ssxu", 349 /* fp_ssxu */, +- 0, +- Opcode_ssxu_encode_fns, 0, 0 }, +- { "beqz.w18", 350 /* xt_iclass_wb18_0 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_beqz_w18_encode_fns, 0, 0 }, +- { "bnez.w18", 350 /* xt_iclass_wb18_0 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnez_w18_encode_fns, 0, 0 }, +- { "bgez.w18", 350 /* xt_iclass_wb18_0 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgez_w18_encode_fns, 0, 0 }, +- { "bltz.w18", 350 /* xt_iclass_wb18_0 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bltz_w18_encode_fns, 0, 0 }, +- { "beqi.w18", 351 /* xt_iclass_wb18_1 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_beqi_w18_encode_fns, 0, 0 }, +- { "bnei.w18", 351 /* xt_iclass_wb18_1 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnei_w18_encode_fns, 0, 0 }, +- { "bgei.w18", 351 /* xt_iclass_wb18_1 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgei_w18_encode_fns, 0, 0 }, +- { "blti.w18", 351 /* xt_iclass_wb18_1 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_blti_w18_encode_fns, 0, 0 }, +- { "bgeui.w18", 352 /* xt_iclass_wb18_2 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgeui_w18_encode_fns, 0, 0 }, +- { "bltui.w18", 352 /* xt_iclass_wb18_2 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bltui_w18_encode_fns, 0, 0 }, +- { "bbci.w18", 353 /* xt_iclass_wb18_3 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbci_w18_encode_fns, 0, 0 }, +- { "bbsi.w18", 353 /* xt_iclass_wb18_3 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbsi_w18_encode_fns, 0, 0 }, +- { "beq.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_beq_w18_encode_fns, 0, 0 }, +- { "bne.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bne_w18_encode_fns, 0, 0 }, +- { "bge.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bge_w18_encode_fns, 0, 0 }, +- { "blt.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_blt_w18_encode_fns, 0, 0 }, +- { "bgeu.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bgeu_w18_encode_fns, 0, 0 }, +- { "bltu.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bltu_w18_encode_fns, 0, 0 }, +- { "bany.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bany_w18_encode_fns, 0, 0 }, +- { "bnone.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnone_w18_encode_fns, 0, 0 }, +- { "ball.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_ball_w18_encode_fns, 0, 0 }, +- { "bnall.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bnall_w18_encode_fns, 0, 0 }, +- { "bbc.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbc_w18_encode_fns, 0, 0 }, +- { "bbs.w18", 354 /* xt_iclass_wb18_4 */, +- XTENSA_OPCODE_IS_BRANCH, +- Opcode_bbs_w18_encode_fns, 0, 0 } +-}; +- +- +-/* Slot-specific opcode decode functions. */ +- +-static int +-Slot_inst_decode (const xtensa_insnbuf insn) +-{ +- switch (Field_op0_Slot_inst_get (insn)) +- { +- case 0: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 0: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 0: +- switch (Field_m_Slot_inst_get (insn)) +- { +- case 0: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_n_Slot_inst_get (insn) == 0) +- return 79; /* ill */ +- break; +- case 2: +- switch (Field_n_Slot_inst_get (insn)) +- { +- case 0: +- return 98; /* ret */ +- case 1: +- return 14; /* retw */ +- case 2: +- return 81; /* jx */ +- } +- break; +- case 3: +- switch (Field_n_Slot_inst_get (insn)) +- { +- case 0: +- return 77; /* callx0 */ +- case 1: +- return 10; /* callx4 */ +- case 2: +- return 9; /* callx8 */ +- case 3: +- return 8; /* callx12 */ +- } +- break; +- } +- break; +- case 1: +- return 12; /* movsp */ +- case 2: +- if (Field_s_Slot_inst_get (insn) == 0) +- { +- switch (Field_t_Slot_inst_get (insn)) +- { +- case 0: +- return 116; /* isync */ +- case 1: +- return 117; /* rsync */ +- case 2: +- return 118; /* esync */ +- case 3: +- return 119; /* dsync */ +- case 8: +- return 0; /* excw */ +- case 12: +- return 114; /* memw */ +- case 13: +- return 115; /* extw */ +- case 15: +- return 97; /* nop */ +- } +- } +- break; +- case 3: +- switch (Field_t_Slot_inst_get (insn)) +- { +- case 0: +- switch (Field_s_Slot_inst_get (insn)) +- { +- case 0: +- return 1; /* rfe */ +- case 2: +- return 2; /* rfde */ +- case 4: +- return 16; /* rfwo */ +- case 5: +- return 17; /* rfwu */ +- } +- break; +- case 1: +- return 316; /* rfi */ +- } +- break; +- case 4: +- return 324; /* break */ +- case 5: +- switch (Field_s_Slot_inst_get (insn)) +- { +- case 0: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 3; /* syscall */ +- break; +- case 1: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 4; /* simcall */ +- break; +- } +- break; +- case 6: +- return 120; /* rsil */ +- case 7: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 317; /* waiti */ +- break; +- case 8: +- return 367; /* any4 */ +- case 9: +- return 368; /* all4 */ +- case 10: +- return 369; /* any8 */ +- case 11: +- return 370; /* all8 */ +- } +- break; +- case 1: +- return 49; /* and */ +- case 2: +- return 50; /* or */ +- case 3: +- return 51; /* xor */ +- case 4: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 0: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 102; /* ssr */ +- break; +- case 1: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 103; /* ssl */ +- break; +- case 2: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 104; /* ssa8l */ +- break; +- case 3: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 105; /* ssa8b */ +- break; +- case 4: +- if (Field_thi3_Slot_inst_get (insn) == 0) +- return 106; /* ssai */ +- break; +- case 8: +- if (Field_s_Slot_inst_get (insn) == 0) +- return 13; /* rotw */ +- break; +- case 14: +- return 448; /* nsa */ +- case 15: +- return 449; /* nsau */ +- } +- break; +- case 5: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 1: +- return 438; /* hwwitlba */ +- case 3: +- return 434; /* ritlb0 */ +- case 4: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 432; /* iitlb */ +- break; +- case 5: +- return 433; /* pitlb */ +- case 6: +- return 436; /* witlb */ +- case 7: +- return 435; /* ritlb1 */ +- case 9: +- return 439; /* hwwdtlba */ +- case 11: +- return 429; /* rdtlb0 */ +- case 12: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 427; /* idtlb */ +- break; +- case 13: +- return 428; /* pdtlb */ +- case 14: +- return 431; /* wdtlb */ +- case 15: +- return 430; /* rdtlb1 */ +- } +- break; +- case 6: +- switch (Field_s_Slot_inst_get (insn)) +- { +- case 0: +- return 95; /* neg */ +- case 1: +- return 96; /* abs */ +- } +- break; +- case 8: +- return 41; /* add */ +- case 9: +- return 43; /* addx2 */ +- case 10: +- return 44; /* addx4 */ +- case 11: +- return 45; /* addx8 */ +- case 12: +- return 42; /* sub */ +- case 13: +- return 46; /* subx2 */ +- case 14: +- return 47; /* subx4 */ +- case 15: +- return 48; /* subx8 */ +- } +- break; +- case 1: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- case 1: +- return 111; /* slli */ +- case 2: +- case 3: +- return 112; /* srai */ +- case 4: +- return 113; /* srli */ +- case 6: +- switch (Field_sr_Slot_inst_get (insn)) +- { +- case 0: +- return 129; /* xsr.lbeg */ +- case 1: +- return 123; /* xsr.lend */ +- case 2: +- return 126; /* xsr.lcount */ +- case 3: +- return 132; /* xsr.sar */ +- case 4: +- return 377; /* xsr.br */ +- case 5: +- return 135; /* xsr.litbase */ +- case 12: +- return 456; /* xsr.scompare1 */ +- case 16: +- return 312; /* xsr.acclo */ +- case 17: +- return 315; /* xsr.acchi */ +- case 32: +- return 300; /* xsr.m0 */ +- case 33: +- return 303; /* xsr.m1 */ +- case 34: +- return 306; /* xsr.m2 */ +- case 35: +- return 309; /* xsr.m3 */ +- case 72: +- return 22; /* xsr.windowbase */ +- case 73: +- return 25; /* xsr.windowstart */ +- case 83: +- return 417; /* xsr.ptevaddr */ +- case 90: +- return 420; /* xsr.rasid */ +- case 91: +- return 423; /* xsr.itlbcfg */ +- case 92: +- return 426; /* xsr.dtlbcfg */ +- case 96: +- return 346; /* xsr.ibreakenable */ +- case 104: +- return 358; /* xsr.ddr */ +- case 128: +- return 340; /* xsr.ibreaka0 */ +- case 129: +- return 343; /* xsr.ibreaka1 */ +- case 144: +- return 328; /* xsr.dbreaka0 */ +- case 145: +- return 334; /* xsr.dbreaka1 */ +- case 160: +- return 331; /* xsr.dbreakc0 */ +- case 161: +- return 337; /* xsr.dbreakc1 */ +- case 177: +- return 143; /* xsr.epc1 */ +- case 178: +- return 149; /* xsr.epc2 */ +- case 179: +- return 155; /* xsr.epc3 */ +- case 180: +- return 161; /* xsr.epc4 */ +- case 181: +- return 167; /* xsr.epc5 */ +- case 182: +- return 173; /* xsr.epc6 */ +- case 183: +- return 179; /* xsr.epc7 */ +- case 192: +- return 206; /* xsr.depc */ +- case 194: +- return 185; /* xsr.eps2 */ +- case 195: +- return 188; /* xsr.eps3 */ +- case 196: +- return 191; /* xsr.eps4 */ +- case 197: +- return 194; /* xsr.eps5 */ +- case 198: +- return 197; /* xsr.eps6 */ +- case 199: +- return 200; /* xsr.eps7 */ +- case 209: +- return 146; /* xsr.excsave1 */ +- case 210: +- return 152; /* xsr.excsave2 */ +- case 211: +- return 158; /* xsr.excsave3 */ +- case 212: +- return 164; /* xsr.excsave4 */ +- case 213: +- return 170; /* xsr.excsave5 */ +- case 214: +- return 176; /* xsr.excsave6 */ +- case 215: +- return 182; /* xsr.excsave7 */ +- case 224: +- return 442; /* xsr.cpenable */ +- case 228: +- return 323; /* xsr.intenable */ +- case 230: +- return 140; /* xsr.ps */ +- case 231: +- return 225; /* xsr.vecbase */ +- case 232: +- return 209; /* xsr.exccause */ +- case 233: +- return 349; /* xsr.debugcause */ +- case 234: +- return 380; /* xsr.ccount */ +- case 236: +- return 352; /* xsr.icount */ +- case 237: +- return 355; /* xsr.icountlevel */ +- case 238: +- return 203; /* xsr.excvaddr */ +- case 240: +- return 383; /* xsr.ccompare0 */ +- case 241: +- return 386; /* xsr.ccompare1 */ +- case 242: +- return 389; /* xsr.ccompare2 */ +- case 244: +- return 212; /* xsr.misc0 */ +- case 245: +- return 215; /* xsr.misc1 */ +- case 246: +- return 218; /* xsr.misc2 */ +- case 247: +- return 221; /* xsr.misc3 */ +- } +- break; +- case 8: +- return 108; /* src */ +- case 9: +- if (Field_s_Slot_inst_get (insn) == 0) +- return 109; /* srl */ +- break; +- case 10: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 107; /* sll */ +- break; +- case 11: +- if (Field_s_Slot_inst_get (insn) == 0) +- return 110; /* sra */ +- break; +- case 12: +- return 296; /* mul16u */ +- case 13: +- return 297; /* mul16s */ +- case 15: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 0: +- return 396; /* lict */ +- case 1: +- return 398; /* sict */ +- case 2: +- return 397; /* licw */ +- case 3: +- return 399; /* sicw */ +- case 8: +- return 414; /* ldct */ +- case 9: +- return 413; /* sdct */ +- case 14: +- if (Field_t_Slot_inst_get (insn) == 0) +- return 359; /* rfdo */ +- if (Field_t_Slot_inst_get (insn) == 1) +- return 360; /* rfdd */ +- break; +- case 15: +- return 437; /* ldpte */ +- } +- break; +- } +- break; +- case 2: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- return 362; /* andb */ +- case 1: +- return 363; /* andbc */ +- case 2: +- return 364; /* orb */ +- case 3: +- return 365; /* orbc */ +- case 4: +- return 366; /* xorb */ +- case 8: +- return 461; /* mull */ +- case 10: +- return 462; /* muluh */ +- case 11: +- return 463; /* mulsh */ +- case 12: +- return 457; /* quou */ +- case 13: +- return 458; /* quos */ +- case 14: +- return 459; /* remu */ +- case 15: +- return 460; /* rems */ +- } +- break; +- case 3: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- switch (Field_sr_Slot_inst_get (insn)) +- { +- case 0: +- return 127; /* rsr.lbeg */ +- case 1: +- return 121; /* rsr.lend */ +- case 2: +- return 124; /* rsr.lcount */ +- case 3: +- return 130; /* rsr.sar */ +- case 4: +- return 375; /* rsr.br */ +- case 5: +- return 133; /* rsr.litbase */ +- case 12: +- return 454; /* rsr.scompare1 */ +- case 16: +- return 310; /* rsr.acclo */ +- case 17: +- return 313; /* rsr.acchi */ +- case 32: +- return 298; /* rsr.m0 */ +- case 33: +- return 301; /* rsr.m1 */ +- case 34: +- return 304; /* rsr.m2 */ +- case 35: +- return 307; /* rsr.m3 */ +- case 72: +- return 20; /* rsr.windowbase */ +- case 73: +- return 23; /* rsr.windowstart */ +- case 83: +- return 416; /* rsr.ptevaddr */ +- case 90: +- return 418; /* rsr.rasid */ +- case 91: +- return 421; /* rsr.itlbcfg */ +- case 92: +- return 424; /* rsr.dtlbcfg */ +- case 96: +- return 344; /* rsr.ibreakenable */ +- case 104: +- return 356; /* rsr.ddr */ +- case 128: +- return 338; /* rsr.ibreaka0 */ +- case 129: +- return 341; /* rsr.ibreaka1 */ +- case 144: +- return 326; /* rsr.dbreaka0 */ +- case 145: +- return 332; /* rsr.dbreaka1 */ +- case 160: +- return 329; /* rsr.dbreakc0 */ +- case 161: +- return 335; /* rsr.dbreakc1 */ +- case 176: +- return 136; /* rsr.176 */ +- case 177: +- return 141; /* rsr.epc1 */ +- case 178: +- return 147; /* rsr.epc2 */ +- case 179: +- return 153; /* rsr.epc3 */ +- case 180: +- return 159; /* rsr.epc4 */ +- case 181: +- return 165; /* rsr.epc5 */ +- case 182: +- return 171; /* rsr.epc6 */ +- case 183: +- return 177; /* rsr.epc7 */ +- case 192: +- return 204; /* rsr.depc */ +- case 194: +- return 183; /* rsr.eps2 */ +- case 195: +- return 186; /* rsr.eps3 */ +- case 196: +- return 189; /* rsr.eps4 */ +- case 197: +- return 192; /* rsr.eps5 */ +- case 198: +- return 195; /* rsr.eps6 */ +- case 199: +- return 198; /* rsr.eps7 */ +- case 208: +- return 137; /* rsr.208 */ +- case 209: +- return 144; /* rsr.excsave1 */ +- case 210: +- return 150; /* rsr.excsave2 */ +- case 211: +- return 156; /* rsr.excsave3 */ +- case 212: +- return 162; /* rsr.excsave4 */ +- case 213: +- return 168; /* rsr.excsave5 */ +- case 214: +- return 174; /* rsr.excsave6 */ +- case 215: +- return 180; /* rsr.excsave7 */ +- case 224: +- return 440; /* rsr.cpenable */ +- case 226: +- return 318; /* rsr.interrupt */ +- case 228: +- return 321; /* rsr.intenable */ +- case 230: +- return 138; /* rsr.ps */ +- case 231: +- return 223; /* rsr.vecbase */ +- case 232: +- return 207; /* rsr.exccause */ +- case 233: +- return 347; /* rsr.debugcause */ +- case 234: +- return 378; /* rsr.ccount */ +- case 235: +- return 222; /* rsr.prid */ +- case 236: +- return 350; /* rsr.icount */ +- case 237: +- return 353; /* rsr.icountlevel */ +- case 238: +- return 201; /* rsr.excvaddr */ +- case 240: +- return 381; /* rsr.ccompare0 */ +- case 241: +- return 384; /* rsr.ccompare1 */ +- case 242: +- return 387; /* rsr.ccompare2 */ +- case 244: +- return 210; /* rsr.misc0 */ +- case 245: +- return 213; /* rsr.misc1 */ +- case 246: +- return 216; /* rsr.misc2 */ +- case 247: +- return 219; /* rsr.misc3 */ +- } +- break; +- case 1: +- switch (Field_sr_Slot_inst_get (insn)) +- { +- case 0: +- return 128; /* wsr.lbeg */ +- case 1: +- return 122; /* wsr.lend */ +- case 2: +- return 125; /* wsr.lcount */ +- case 3: +- return 131; /* wsr.sar */ +- case 4: +- return 376; /* wsr.br */ +- case 5: +- return 134; /* wsr.litbase */ +- case 12: +- return 455; /* wsr.scompare1 */ +- case 16: +- return 311; /* wsr.acclo */ +- case 17: +- return 314; /* wsr.acchi */ +- case 32: +- return 299; /* wsr.m0 */ +- case 33: +- return 302; /* wsr.m1 */ +- case 34: +- return 305; /* wsr.m2 */ +- case 35: +- return 308; /* wsr.m3 */ +- case 72: +- return 21; /* wsr.windowbase */ +- case 73: +- return 24; /* wsr.windowstart */ +- case 83: +- return 415; /* wsr.ptevaddr */ +- case 89: +- return 361; /* wsr.mmid */ +- case 90: +- return 419; /* wsr.rasid */ +- case 91: +- return 422; /* wsr.itlbcfg */ +- case 92: +- return 425; /* wsr.dtlbcfg */ +- case 96: +- return 345; /* wsr.ibreakenable */ +- case 104: +- return 357; /* wsr.ddr */ +- case 128: +- return 339; /* wsr.ibreaka0 */ +- case 129: +- return 342; /* wsr.ibreaka1 */ +- case 144: +- return 327; /* wsr.dbreaka0 */ +- case 145: +- return 333; /* wsr.dbreaka1 */ +- case 160: +- return 330; /* wsr.dbreakc0 */ +- case 161: +- return 336; /* wsr.dbreakc1 */ +- case 177: +- return 142; /* wsr.epc1 */ +- case 178: +- return 148; /* wsr.epc2 */ +- case 179: +- return 154; /* wsr.epc3 */ +- case 180: +- return 160; /* wsr.epc4 */ +- case 181: +- return 166; /* wsr.epc5 */ +- case 182: +- return 172; /* wsr.epc6 */ +- case 183: +- return 178; /* wsr.epc7 */ +- case 192: +- return 205; /* wsr.depc */ +- case 194: +- return 184; /* wsr.eps2 */ +- case 195: +- return 187; /* wsr.eps3 */ +- case 196: +- return 190; /* wsr.eps4 */ +- case 197: +- return 193; /* wsr.eps5 */ +- case 198: +- return 196; /* wsr.eps6 */ +- case 199: +- return 199; /* wsr.eps7 */ +- case 209: +- return 145; /* wsr.excsave1 */ +- case 210: +- return 151; /* wsr.excsave2 */ +- case 211: +- return 157; /* wsr.excsave3 */ +- case 212: +- return 163; /* wsr.excsave4 */ +- case 213: +- return 169; /* wsr.excsave5 */ +- case 214: +- return 175; /* wsr.excsave6 */ +- case 215: +- return 181; /* wsr.excsave7 */ +- case 224: +- return 441; /* wsr.cpenable */ +- case 226: +- return 319; /* wsr.intset */ +- case 227: +- return 320; /* wsr.intclear */ +- case 228: +- return 322; /* wsr.intenable */ +- case 230: +- return 139; /* wsr.ps */ +- case 231: +- return 224; /* wsr.vecbase */ +- case 232: +- return 208; /* wsr.exccause */ +- case 233: +- return 348; /* wsr.debugcause */ +- case 234: +- return 379; /* wsr.ccount */ +- case 236: +- return 351; /* wsr.icount */ +- case 237: +- return 354; /* wsr.icountlevel */ +- case 238: +- return 202; /* wsr.excvaddr */ +- case 240: +- return 382; /* wsr.ccompare0 */ +- case 241: +- return 385; /* wsr.ccompare1 */ +- case 242: +- return 388; /* wsr.ccompare2 */ +- case 244: +- return 211; /* wsr.misc0 */ +- case 245: +- return 214; /* wsr.misc1 */ +- case 246: +- return 217; /* wsr.misc2 */ +- case 247: +- return 220; /* wsr.misc3 */ +- } +- break; +- case 2: +- return 450; /* sext */ +- case 3: +- return 443; /* clamps */ +- case 4: +- return 444; /* min */ +- case 5: +- return 445; /* max */ +- case 6: +- return 446; /* minu */ +- case 7: +- return 447; /* maxu */ +- case 8: +- return 91; /* moveqz */ +- case 9: +- return 92; /* movnez */ +- case 10: +- return 93; /* movltz */ +- case 11: +- return 94; /* movgez */ +- case 12: +- return 373; /* movf */ +- case 13: +- return 374; /* movt */ +- case 14: +- switch (Field_st_Slot_inst_get (insn)) +- { +- case 231: +- return 37; /* rur.threadptr */ +- case 232: +- return 464; /* rur.fcr */ +- case 233: +- return 466; /* rur.fsr */ +- } +- break; +- case 15: +- switch (Field_sr_Slot_inst_get (insn)) +- { +- case 231: +- return 38; /* wur.threadptr */ +- case 232: +- return 465; /* wur.fcr */ +- case 233: +- return 467; /* wur.fsr */ +- } +- break; +- } +- break; +- case 4: +- case 5: +- return 78; /* extui */ +- case 8: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- return 500; /* lsx */ +- case 1: +- return 501; /* lsxu */ +- case 4: +- return 504; /* ssx */ +- case 5: +- return 505; /* ssxu */ +- } +- break; +- case 9: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- return 18; /* l32e */ +- case 4: +- return 19; /* s32e */ +- } +- break; +- case 10: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- return 468; /* add.s */ +- case 1: +- return 469; /* sub.s */ +- case 2: +- return 470; /* mul.s */ +- case 4: +- return 471; /* madd.s */ +- case 5: +- return 472; /* msub.s */ +- case 8: +- return 491; /* round.s */ +- case 9: +- return 494; /* trunc.s */ +- case 10: +- return 493; /* floor.s */ +- case 11: +- return 492; /* ceil.s */ +- case 12: +- return 489; /* float.s */ +- case 13: +- return 490; /* ufloat.s */ +- case 14: +- return 495; /* utrunc.s */ +- case 15: +- switch (Field_t_Slot_inst_get (insn)) +- { +- case 0: +- return 480; /* mov.s */ +- case 1: +- return 479; /* abs.s */ +- case 4: +- return 496; /* rfr */ +- case 5: +- return 497; /* wfr */ +- case 6: +- return 481; /* neg.s */ +- } +- break; +- } +- break; +- case 11: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 1: +- return 482; /* un.s */ +- case 2: +- return 483; /* oeq.s */ +- case 3: +- return 484; /* ueq.s */ +- case 4: +- return 485; /* olt.s */ +- case 5: +- return 486; /* ult.s */ +- case 6: +- return 487; /* ole.s */ +- case 7: +- return 488; /* ule.s */ +- case 8: +- return 475; /* moveqz.s */ +- case 9: +- return 476; /* movnez.s */ +- case 10: +- return 477; /* movltz.s */ +- case 11: +- return 478; /* movgez.s */ +- case 12: +- return 473; /* movf.s */ +- case 13: +- return 474; /* movt.s */ +- } +- break; +- } +- break; +- case 1: +- return 85; /* l32r */ +- case 2: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 0: +- return 86; /* l8ui */ +- case 1: +- return 82; /* l16ui */ +- case 2: +- return 84; /* l32i */ +- case 4: +- return 101; /* s8i */ +- case 5: +- return 99; /* s16i */ +- case 6: +- return 100; /* s32i */ +- case 7: +- switch (Field_t_Slot_inst_get (insn)) +- { +- case 0: +- return 406; /* dpfr */ +- case 1: +- return 407; /* dpfw */ +- case 2: +- return 408; /* dpfro */ +- case 3: +- return 409; /* dpfwo */ +- case 4: +- return 400; /* dhwb */ +- case 5: +- return 401; /* dhwbi */ +- case 6: +- return 404; /* dhi */ +- case 7: +- return 405; /* dii */ +- case 8: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 0: +- return 410; /* dpfl */ +- case 2: +- return 411; /* dhu */ +- case 3: +- return 412; /* diu */ +- case 4: +- return 402; /* diwb */ +- case 5: +- return 403; /* diwbi */ +- } +- break; +- case 12: +- return 390; /* ipf */ +- case 13: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 0: +- return 392; /* ipfl */ +- case 2: +- return 393; /* ihu */ +- case 3: +- return 394; /* iiu */ +- } +- break; +- case 14: +- return 391; /* ihi */ +- case 15: +- return 395; /* iii */ +- } +- break; +- case 9: +- return 83; /* l16si */ +- case 10: +- return 90; /* movi */ +- case 11: +- return 451; /* l32ai */ +- case 12: +- return 39; /* addi */ +- case 13: +- return 40; /* addmi */ +- case 14: +- return 453; /* s32c1i */ +- case 15: +- return 452; /* s32ri */ +- } +- break; +- case 3: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 0: +- return 498; /* lsi */ +- case 4: +- return 502; /* ssi */ +- case 8: +- return 499; /* lsiu */ +- case 12: +- return 503; /* ssiu */ +- } +- break; +- case 4: +- switch (Field_op2_Slot_inst_get (insn)) +- { +- case 0: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 8: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 287; /* mula.dd.ll.ldinc */ +- break; +- case 9: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 289; /* mula.dd.hl.ldinc */ +- break; +- case 10: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 291; /* mula.dd.lh.ldinc */ +- break; +- case 11: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 293; /* mula.dd.hh.ldinc */ +- break; +- } +- break; +- case 1: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 8: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 286; /* mula.dd.ll.lddec */ +- break; +- case 9: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 288; /* mula.dd.hl.lddec */ +- break; +- case 10: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 290; /* mula.dd.lh.lddec */ +- break; +- case 11: +- if (Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 292; /* mula.dd.hh.lddec */ +- break; +- } +- break; +- case 2: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 4: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 242; /* mul.dd.ll */ +- break; +- case 5: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 243; /* mul.dd.hl */ +- break; +- case 6: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 244; /* mul.dd.lh */ +- break; +- case 7: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 245; /* mul.dd.hh */ +- break; +- case 8: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 270; /* mula.dd.ll */ +- break; +- case 9: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 271; /* mula.dd.hl */ +- break; +- case 10: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 272; /* mula.dd.lh */ +- break; +- case 11: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 273; /* mula.dd.hh */ +- break; +- case 12: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 274; /* muls.dd.ll */ +- break; +- case 13: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 275; /* muls.dd.hl */ +- break; +- case 14: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 276; /* muls.dd.lh */ +- break; +- case 15: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 277; /* muls.dd.hh */ +- break; +- } +- break; +- case 3: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 4: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 234; /* mul.ad.ll */ +- break; +- case 5: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 235; /* mul.ad.hl */ +- break; +- case 6: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 236; /* mul.ad.lh */ +- break; +- case 7: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 237; /* mul.ad.hh */ +- break; +- case 8: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 254; /* mula.ad.ll */ +- break; +- case 9: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 255; /* mula.ad.hl */ +- break; +- case 10: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 256; /* mula.ad.lh */ +- break; +- case 11: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 257; /* mula.ad.hh */ +- break; +- case 12: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 258; /* muls.ad.ll */ +- break; +- case 13: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 259; /* muls.ad.hl */ +- break; +- case 14: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 260; /* muls.ad.lh */ +- break; +- case 15: +- if (Field_r_Slot_inst_get (insn) == 0 && +- Field_t3_Slot_inst_get (insn) == 0 && +- Field_tlo_Slot_inst_get (insn) == 0) +- return 261; /* muls.ad.hh */ +- break; +- } +- break; +- case 4: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 8: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 279; /* mula.da.ll.ldinc */ +- break; +- case 9: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 281; /* mula.da.hl.ldinc */ +- break; +- case 10: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 283; /* mula.da.lh.ldinc */ +- break; +- case 11: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 285; /* mula.da.hh.ldinc */ +- break; +- } +- break; +- case 5: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 8: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 278; /* mula.da.ll.lddec */ +- break; +- case 9: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 280; /* mula.da.hl.lddec */ +- break; +- case 10: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 282; /* mula.da.lh.lddec */ +- break; +- case 11: +- if (Field_r3_Slot_inst_get (insn) == 0) +- return 284; /* mula.da.hh.lddec */ +- break; +- } +- break; +- case 6: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 4: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 238; /* mul.da.ll */ +- break; +- case 5: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 239; /* mul.da.hl */ +- break; +- case 6: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 240; /* mul.da.lh */ +- break; +- case 7: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 241; /* mul.da.hh */ +- break; +- case 8: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 262; /* mula.da.ll */ +- break; +- case 9: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 263; /* mula.da.hl */ +- break; +- case 10: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 264; /* mula.da.lh */ +- break; +- case 11: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 265; /* mula.da.hh */ +- break; +- case 12: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 266; /* muls.da.ll */ +- break; +- case 13: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 267; /* muls.da.hl */ +- break; +- case 14: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 268; /* muls.da.lh */ +- break; +- case 15: +- if (Field_s_Slot_inst_get (insn) == 0 && +- Field_w_Slot_inst_get (insn) == 0 && +- Field_r3_Slot_inst_get (insn) == 0) +- return 269; /* muls.da.hh */ +- break; +- } +- break; +- case 7: +- switch (Field_op1_Slot_inst_get (insn)) +- { +- case 0: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 230; /* umul.aa.ll */ +- break; +- case 1: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 231; /* umul.aa.hl */ +- break; +- case 2: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 232; /* umul.aa.lh */ +- break; +- case 3: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 233; /* umul.aa.hh */ +- break; +- case 4: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 226; /* mul.aa.ll */ +- break; +- case 5: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 227; /* mul.aa.hl */ +- break; +- case 6: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 228; /* mul.aa.lh */ +- break; +- case 7: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 229; /* mul.aa.hh */ +- break; +- case 8: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 246; /* mula.aa.ll */ +- break; +- case 9: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 247; /* mula.aa.hl */ +- break; +- case 10: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 248; /* mula.aa.lh */ +- break; +- case 11: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 249; /* mula.aa.hh */ +- break; +- case 12: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 250; /* muls.aa.ll */ +- break; +- case 13: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 251; /* muls.aa.hl */ +- break; +- case 14: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 252; /* muls.aa.lh */ +- break; +- case 15: +- if (Field_r_Slot_inst_get (insn) == 0) +- return 253; /* muls.aa.hh */ +- break; +- } +- break; +- case 8: +- if (Field_op1_Slot_inst_get (insn) == 0 && +- Field_t_Slot_inst_get (insn) == 0 && +- Field_rhi_Slot_inst_get (insn) == 0) +- return 295; /* ldinc */ +- break; +- case 9: +- if (Field_op1_Slot_inst_get (insn) == 0 && +- Field_t_Slot_inst_get (insn) == 0 && +- Field_rhi_Slot_inst_get (insn) == 0) +- return 294; /* lddec */ +- break; +- } +- break; +- case 5: +- switch (Field_n_Slot_inst_get (insn)) +- { +- case 0: +- return 76; /* call0 */ +- case 1: +- return 7; /* call4 */ +- case 2: +- return 6; /* call8 */ +- case 3: +- return 5; /* call12 */ +- } +- break; +- case 6: +- switch (Field_n_Slot_inst_get (insn)) +- { +- case 0: +- return 80; /* j */ +- case 1: +- switch (Field_m_Slot_inst_get (insn)) +- { +- case 0: +- return 72; /* beqz */ +- case 1: +- return 73; /* bnez */ +- case 2: +- return 75; /* bltz */ +- case 3: +- return 74; /* bgez */ +- } +- break; +- case 2: +- switch (Field_m_Slot_inst_get (insn)) +- { +- case 0: +- return 52; /* beqi */ +- case 1: +- return 53; /* bnei */ +- case 2: +- return 55; /* blti */ +- case 3: +- return 54; /* bgei */ +- } +- break; +- case 3: +- switch (Field_m_Slot_inst_get (insn)) +- { +- case 0: +- return 11; /* entry */ +- case 1: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 0: +- return 371; /* bf */ +- case 1: +- return 372; /* bt */ +- case 8: +- return 87; /* loop */ +- case 9: +- return 88; /* loopnez */ +- case 10: +- return 89; /* loopgtz */ +- } +- break; +- case 2: +- return 59; /* bltui */ +- case 3: +- return 58; /* bgeui */ +- } +- break; +- } +- break; +- case 7: +- switch (Field_r_Slot_inst_get (insn)) +- { +- case 0: +- return 67; /* bnone */ +- case 1: +- return 60; /* beq */ +- case 2: +- return 63; /* blt */ +- case 3: +- return 65; /* bltu */ +- case 4: +- return 68; /* ball */ +- case 5: +- return 70; /* bbc */ +- case 6: +- case 7: +- return 56; /* bbci */ +- case 8: +- return 66; /* bany */ +- case 9: +- return 61; /* bne */ +- case 10: +- return 62; /* bge */ +- case 11: +- return 64; /* bgeu */ +- case 12: +- return 69; /* bnall */ +- case 13: +- return 71; /* bbs */ +- case 14: +- case 15: +- return 57; /* bbsi */ +- } +- break; +- } +- return 0; +-} +- +-static int +-Slot_inst16b_decode (const xtensa_insnbuf insn) +-{ +- switch (Field_op0_Slot_inst16b_get (insn)) +- { +- case 12: +- switch (Field_i_Slot_inst16b_get (insn)) +- { +- case 0: +- return 33; /* movi.n */ +- case 1: +- switch (Field_z_Slot_inst16b_get (insn)) +- { +- case 0: +- return 28; /* beqz.n */ +- case 1: +- return 29; /* bnez.n */ +- } +- break; +- } +- break; +- case 13: +- switch (Field_r_Slot_inst16b_get (insn)) +- { +- case 0: +- return 32; /* mov.n */ +- case 15: +- switch (Field_t_Slot_inst16b_get (insn)) +- { +- case 0: +- return 35; /* ret.n */ +- case 1: +- return 15; /* retw.n */ +- case 2: +- return 325; /* break.n */ +- case 3: +- if (Field_s_Slot_inst16b_get (insn) == 0) +- return 34; /* nop.n */ +- break; +- case 6: +- if (Field_s_Slot_inst16b_get (insn) == 0) +- return 30; /* ill.n */ +- break; +- } +- break; +- } +- break; +- } +- return 0; +-} +- +-static int +-Slot_inst16a_decode (const xtensa_insnbuf insn) +-{ +- switch (Field_op0_Slot_inst16a_get (insn)) +- { +- case 8: +- return 31; /* l32i.n */ +- case 9: +- return 36; /* s32i.n */ +- case 10: +- return 26; /* add.n */ +- case 11: +- return 27; /* addi.n */ +- } +- return 0; +-} +- +-static int +-Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn) +-{ +- switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn)) +- { +- case 0: +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1) +- return 41; /* add */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5) +- return 42; /* sub */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2) +- return 43; /* addx2 */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3) +- return 49; /* and */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4) +- return 450; /* sext */ +- break; +- case 1: +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1) +- return 27; /* addi.n */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2) +- return 44; /* addx4 */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3) +- return 50; /* or */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5) +- return 51; /* xor */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4) +- return 113; /* srli */ +- break; +- } +- if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 && +- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6) +- return 33; /* movi.n */ +- if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 && +- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && +- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) +- return 32; /* mov.n */ +- if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 && +- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && +- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) +- return 97; /* nop */ +- if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 && +- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && +- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) +- return 96; /* abs */ +- if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 && +- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && +- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) +- return 95; /* neg */ +- if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 && +- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && +- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) +- return 110; /* sra */ +- if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 && +- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && +- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) +- return 109; /* srl */ +- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7) +- return 112; /* srai */ +- return 0; +-} +- +-static int +-Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn) +-{ +- switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn)) +- { +- case 0: +- if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2) +- return 78; /* extui */ +- switch (Field_op1_Slot_xt_flix64_slot0_get (insn)) +- { +- case 0: +- switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) +- { +- case 0: +- if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2) +- { +- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) +- { +- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15) +- return 97; /* nop */ +- } +- } +- break; +- case 1: +- return 49; /* and */ +- case 2: +- return 50; /* or */ +- case 3: +- return 51; /* xor */ +- case 4: +- switch (Field_r_Slot_xt_flix64_slot0_get (insn)) +- { +- case 0: +- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) +- return 102; /* ssr */ +- break; +- case 1: +- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) +- return 103; /* ssl */ +- break; +- case 2: +- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) +- return 104; /* ssa8l */ +- break; +- case 3: +- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) +- return 105; /* ssa8b */ +- break; +- case 4: +- if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0) +- return 106; /* ssai */ +- break; +- case 14: +- return 448; /* nsa */ +- case 15: +- return 449; /* nsau */ +- } +- break; +- case 6: +- switch (Field_s_Slot_xt_flix64_slot0_get (insn)) +- { +- case 0: +- return 95; /* neg */ +- case 1: +- return 96; /* abs */ +- } +- break; +- case 8: +- return 41; /* add */ +- case 9: +- return 43; /* addx2 */ +- case 10: +- return 44; /* addx4 */ +- case 11: +- return 45; /* addx8 */ +- case 12: +- return 42; /* sub */ +- case 13: +- return 46; /* subx2 */ +- case 14: +- return 47; /* subx4 */ +- case 15: +- return 48; /* subx8 */ +- } +- break; +- case 1: +- if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1) +- return 112; /* srai */ +- if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0) +- return 111; /* slli */ +- switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) +- { +- case 4: +- return 113; /* srli */ +- case 8: +- return 108; /* src */ +- case 9: +- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) +- return 109; /* srl */ +- break; +- case 10: +- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) +- return 107; /* sll */ +- break; +- case 11: +- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) +- return 110; /* sra */ +- break; +- case 12: +- return 296; /* mul16u */ +- case 13: +- return 297; /* mul16s */ +- } +- break; +- case 2: +- if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8) +- return 461; /* mull */ +- break; +- case 3: +- switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) +- { +- case 2: +- return 450; /* sext */ +- case 3: +- return 443; /* clamps */ +- case 4: +- return 444; /* min */ +- case 5: +- return 445; /* max */ +- case 6: +- return 446; /* minu */ +- case 7: +- return 447; /* maxu */ +- case 8: +- return 91; /* moveqz */ +- case 9: +- return 92; /* movnez */ +- case 10: +- return 93; /* movltz */ +- case 11: +- return 94; /* movgez */ +- } +- break; +- } +- break; +- case 2: +- switch (Field_r_Slot_xt_flix64_slot0_get (insn)) +- { +- case 0: +- return 86; /* l8ui */ +- case 1: +- return 82; /* l16ui */ +- case 2: +- return 84; /* l32i */ +- case 4: +- return 101; /* s8i */ +- case 5: +- return 99; /* s16i */ +- case 6: +- return 100; /* s32i */ +- case 9: +- return 83; /* l16si */ +- case 10: +- return 90; /* movi */ +- case 12: +- return 39; /* addi */ +- case 13: +- return 40; /* addmi */ +- } +- break; +- } +- if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1) +- return 85; /* l32r */ +- if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 && +- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 && +- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 && +- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0) +- return 32; /* mov.n */ +- return 0; +-} +- +-static int +-Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn) +-{ +- if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) +- return 78; /* extui */ +- switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) +- { +- case 0: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 90; /* movi */ +- break; +- case 2: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) +- return 39; /* addi */ +- break; +- case 3: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) +- return 40; /* addmi */ +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0) +- return 51; /* xor */ +- break; +- } +- switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) +- { +- case 8: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 111; /* slli */ +- break; +- case 16: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 112; /* srai */ +- break; +- case 19: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 107; /* sll */ +- break; +- } +- switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) +- { +- case 18: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 41; /* add */ +- break; +- case 19: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 45; /* addx8 */ +- break; +- case 20: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 43; /* addx2 */ +- break; +- case 21: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 49; /* and */ +- break; +- case 22: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 91; /* moveqz */ +- break; +- case 23: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 94; /* movgez */ +- break; +- case 24: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 44; /* addx4 */ +- break; +- case 25: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 93; /* movltz */ +- break; +- case 26: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 92; /* movnez */ +- break; +- case 27: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 296; /* mul16u */ +- break; +- case 28: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 297; /* mul16s */ +- break; +- case 29: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 461; /* mull */ +- break; +- case 30: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 50; /* or */ +- break; +- case 31: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 450; /* sext */ +- break; +- case 34: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 108; /* src */ +- break; +- case 36: +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) +- return 113; /* srli */ +- break; +- } +- if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 32; /* mov.n */ +- if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 81; /* jx */ +- if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 103; /* ssl */ +- if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 97; /* nop */ +- if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 95; /* neg */ +- if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 110; /* sra */ +- if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 109; /* srl */ +- if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 && +- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && +- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) +- return 42; /* sub */ +- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3) +- return 80; /* j */ +- return 0; +-} +- +-static int +-Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn) +-{ +- switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn)) +- { +- case 1: +- if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0) +- return 516; /* bbci.w18 */ +- break; +- case 2: +- if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0) +- return 517; /* bbsi.w18 */ +- break; +- case 3: +- if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 526; /* ball.w18 */ +- break; +- case 4: +- if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 524; /* bany.w18 */ +- break; +- case 5: +- if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 528; /* bbc.w18 */ +- break; +- case 6: +- if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 529; /* bbs.w18 */ +- break; +- case 7: +- if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 518; /* beq.w18 */ +- break; +- case 8: +- if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 510; /* beqi.w18 */ +- break; +- case 9: +- if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 520; /* bge.w18 */ +- break; +- case 10: +- if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 512; /* bgei.w18 */ +- break; +- case 11: +- if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 522; /* bgeu.w18 */ +- break; +- case 12: +- if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 514; /* bgeui.w18 */ +- break; +- case 13: +- if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 521; /* blt.w18 */ +- break; +- case 14: +- if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 513; /* blti.w18 */ +- break; +- case 15: +- if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 523; /* bltu.w18 */ +- break; +- case 16: +- if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 515; /* bltui.w18 */ +- break; +- case 17: +- if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 527; /* bnall.w18 */ +- break; +- case 18: +- if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 519; /* bne.w18 */ +- break; +- case 19: +- if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 511; /* bnei.w18 */ +- break; +- case 20: +- if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 525; /* bnone.w18 */ +- break; +- case 21: +- if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 506; /* beqz.w18 */ +- break; +- case 22: +- if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 508; /* bgez.w18 */ +- break; +- case 23: +- if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 509; /* bltz.w18 */ +- break; +- case 24: +- if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 507; /* bnez.w18 */ +- break; +- case 25: +- if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) +- return 97; /* nop */ +- break; +- } +- return 0; +-} +- +- +-/* Instruction slots. */ +- +-static void +-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[1] = 0; +- slotbuf[0] = (insn[0] & 0xffffff); +-} +- +-static void +-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +-} +- +-static void +-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[1] = 0; +- slotbuf[0] = (insn[0] & 0xffff); +-} +- +-static void +-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +-} +- +-static void +-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[1] = 0; +- slotbuf[0] = (insn[0] & 0xffff); +-} +- +-static void +-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +-} +- +-static void +-Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[1] = 0; +- slotbuf[0] = ((insn[0] & 0xffffff0) >> 4); +-} +- +-static void +-Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4); +-} +- +-static void +-Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[1] = 0; +- slotbuf[0] = ((insn[0] & 0xffffff0) >> 4); +-} +- +-static void +-Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4); +-} +- +-static void +-Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[1] = 0; +- slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); +- slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4); +-} +- +-static void +-Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); +- insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4); +-} +- +-static void +-Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[1] = 0; +- slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); +-} +- +-static void +-Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); +-} +- +-static void +-Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn, +- xtensa_insnbuf slotbuf) +-{ +- slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); +- slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4); +- slotbuf[1] = ((insn[1] & 0x70000000) >> 28); +-} +- +-static void +-Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn, +- const xtensa_insnbuf slotbuf) +-{ +- insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); +- insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4); +- insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28); +-} +- +-static xtensa_get_field_fn +-Slot_inst_get_field_fns[] = { +- Field_t_Slot_inst_get, +- Field_bbi4_Slot_inst_get, +- Field_bbi_Slot_inst_get, +- Field_imm12_Slot_inst_get, +- Field_imm8_Slot_inst_get, +- Field_s_Slot_inst_get, +- Field_imm12b_Slot_inst_get, +- Field_imm16_Slot_inst_get, +- Field_m_Slot_inst_get, +- Field_n_Slot_inst_get, +- Field_offset_Slot_inst_get, +- Field_op0_Slot_inst_get, +- Field_op1_Slot_inst_get, +- Field_op2_Slot_inst_get, +- Field_r_Slot_inst_get, +- Field_sa4_Slot_inst_get, +- Field_sae4_Slot_inst_get, +- Field_sae_Slot_inst_get, +- Field_sal_Slot_inst_get, +- Field_sargt_Slot_inst_get, +- Field_sas4_Slot_inst_get, +- Field_sas_Slot_inst_get, +- Field_sr_Slot_inst_get, +- Field_st_Slot_inst_get, +- Field_thi3_Slot_inst_get, +- Field_imm4_Slot_inst_get, +- Field_mn_Slot_inst_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_r3_Slot_inst_get, +- Field_rbit2_Slot_inst_get, +- Field_rhi_Slot_inst_get, +- Field_t3_Slot_inst_get, +- Field_tbit2_Slot_inst_get, +- Field_tlo_Slot_inst_get, +- Field_w_Slot_inst_get, +- Field_y_Slot_inst_get, +- Field_x_Slot_inst_get, +- Field_t2_Slot_inst_get, +- Field_s2_Slot_inst_get, +- Field_r2_Slot_inst_get, +- Field_t4_Slot_inst_get, +- Field_s4_Slot_inst_get, +- Field_r4_Slot_inst_get, +- Field_t8_Slot_inst_get, +- Field_s8_Slot_inst_get, +- Field_r8_Slot_inst_get, +- Field_xt_wbr15_imm_Slot_inst_get, +- Field_xt_wbr18_imm_Slot_inst_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_ar0_get, +- Implicit_Field_ar4_get, +- Implicit_Field_ar8_get, +- Implicit_Field_ar12_get, +- Implicit_Field_mr0_get, +- Implicit_Field_mr1_get, +- Implicit_Field_mr2_get, +- Implicit_Field_mr3_get, +- Implicit_Field_bt16_get, +- Implicit_Field_bs16_get, +- Implicit_Field_br16_get, +- Implicit_Field_brall_get +-}; +- +-static xtensa_set_field_fn +-Slot_inst_set_field_fns[] = { +- Field_t_Slot_inst_set, +- Field_bbi4_Slot_inst_set, +- Field_bbi_Slot_inst_set, +- Field_imm12_Slot_inst_set, +- Field_imm8_Slot_inst_set, +- Field_s_Slot_inst_set, +- Field_imm12b_Slot_inst_set, +- Field_imm16_Slot_inst_set, +- Field_m_Slot_inst_set, +- Field_n_Slot_inst_set, +- Field_offset_Slot_inst_set, +- Field_op0_Slot_inst_set, +- Field_op1_Slot_inst_set, +- Field_op2_Slot_inst_set, +- Field_r_Slot_inst_set, +- Field_sa4_Slot_inst_set, +- Field_sae4_Slot_inst_set, +- Field_sae_Slot_inst_set, +- Field_sal_Slot_inst_set, +- Field_sargt_Slot_inst_set, +- Field_sas4_Slot_inst_set, +- Field_sas_Slot_inst_set, +- Field_sr_Slot_inst_set, +- Field_st_Slot_inst_set, +- Field_thi3_Slot_inst_set, +- Field_imm4_Slot_inst_set, +- Field_mn_Slot_inst_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_r3_Slot_inst_set, +- Field_rbit2_Slot_inst_set, +- Field_rhi_Slot_inst_set, +- Field_t3_Slot_inst_set, +- Field_tbit2_Slot_inst_set, +- Field_tlo_Slot_inst_set, +- Field_w_Slot_inst_set, +- Field_y_Slot_inst_set, +- Field_x_Slot_inst_set, +- Field_t2_Slot_inst_set, +- Field_s2_Slot_inst_set, +- Field_r2_Slot_inst_set, +- Field_t4_Slot_inst_set, +- Field_s4_Slot_inst_set, +- Field_r4_Slot_inst_set, +- Field_t8_Slot_inst_set, +- Field_s8_Slot_inst_set, +- Field_r8_Slot_inst_set, +- Field_xt_wbr15_imm_Slot_inst_set, +- Field_xt_wbr18_imm_Slot_inst_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set +-}; +- +-static xtensa_get_field_fn +-Slot_inst16a_get_field_fns[] = { +- Field_t_Slot_inst16a_get, +- 0, +- 0, +- 0, +- 0, +- Field_s_Slot_inst16a_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_Slot_inst16a_get, +- 0, +- 0, +- Field_r_Slot_inst16a_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_sr_Slot_inst16a_get, +- Field_st_Slot_inst16a_get, +- 0, +- Field_imm4_Slot_inst16a_get, +- 0, +- Field_i_Slot_inst16a_get, +- Field_imm6lo_Slot_inst16a_get, +- Field_imm6hi_Slot_inst16a_get, +- Field_imm7lo_Slot_inst16a_get, +- Field_imm7hi_Slot_inst16a_get, +- Field_z_Slot_inst16a_get, +- Field_imm6_Slot_inst16a_get, +- Field_imm7_Slot_inst16a_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_t2_Slot_inst16a_get, +- Field_s2_Slot_inst16a_get, +- Field_r2_Slot_inst16a_get, +- Field_t4_Slot_inst16a_get, +- Field_s4_Slot_inst16a_get, +- Field_r4_Slot_inst16a_get, +- Field_t8_Slot_inst16a_get, +- Field_s8_Slot_inst16a_get, +- Field_r8_Slot_inst16a_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_ar0_get, +- Implicit_Field_ar4_get, +- Implicit_Field_ar8_get, +- Implicit_Field_ar12_get, +- Implicit_Field_mr0_get, +- Implicit_Field_mr1_get, +- Implicit_Field_mr2_get, +- Implicit_Field_mr3_get, +- Implicit_Field_bt16_get, +- Implicit_Field_bs16_get, +- Implicit_Field_br16_get, +- Implicit_Field_brall_get +-}; +- +-static xtensa_set_field_fn +-Slot_inst16a_set_field_fns[] = { +- Field_t_Slot_inst16a_set, +- 0, +- 0, +- 0, +- 0, +- Field_s_Slot_inst16a_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_Slot_inst16a_set, +- 0, +- 0, +- Field_r_Slot_inst16a_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_sr_Slot_inst16a_set, +- Field_st_Slot_inst16a_set, +- 0, +- Field_imm4_Slot_inst16a_set, +- 0, +- Field_i_Slot_inst16a_set, +- Field_imm6lo_Slot_inst16a_set, +- Field_imm6hi_Slot_inst16a_set, +- Field_imm7lo_Slot_inst16a_set, +- Field_imm7hi_Slot_inst16a_set, +- Field_z_Slot_inst16a_set, +- Field_imm6_Slot_inst16a_set, +- Field_imm7_Slot_inst16a_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_t2_Slot_inst16a_set, +- Field_s2_Slot_inst16a_set, +- Field_r2_Slot_inst16a_set, +- Field_t4_Slot_inst16a_set, +- Field_s4_Slot_inst16a_set, +- Field_r4_Slot_inst16a_set, +- Field_t8_Slot_inst16a_set, +- Field_s8_Slot_inst16a_set, +- Field_r8_Slot_inst16a_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set +-}; +- +-static xtensa_get_field_fn +-Slot_inst16b_get_field_fns[] = { +- Field_t_Slot_inst16b_get, +- 0, +- 0, +- 0, +- 0, +- Field_s_Slot_inst16b_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_Slot_inst16b_get, +- 0, +- 0, +- Field_r_Slot_inst16b_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_sr_Slot_inst16b_get, +- Field_st_Slot_inst16b_get, +- 0, +- Field_imm4_Slot_inst16b_get, +- 0, +- Field_i_Slot_inst16b_get, +- Field_imm6lo_Slot_inst16b_get, +- Field_imm6hi_Slot_inst16b_get, +- Field_imm7lo_Slot_inst16b_get, +- Field_imm7hi_Slot_inst16b_get, +- Field_z_Slot_inst16b_get, +- Field_imm6_Slot_inst16b_get, +- Field_imm7_Slot_inst16b_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_t2_Slot_inst16b_get, +- Field_s2_Slot_inst16b_get, +- Field_r2_Slot_inst16b_get, +- Field_t4_Slot_inst16b_get, +- Field_s4_Slot_inst16b_get, +- Field_r4_Slot_inst16b_get, +- Field_t8_Slot_inst16b_get, +- Field_s8_Slot_inst16b_get, +- Field_r8_Slot_inst16b_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_ar0_get, +- Implicit_Field_ar4_get, +- Implicit_Field_ar8_get, +- Implicit_Field_ar12_get, +- Implicit_Field_mr0_get, +- Implicit_Field_mr1_get, +- Implicit_Field_mr2_get, +- Implicit_Field_mr3_get, +- Implicit_Field_bt16_get, +- Implicit_Field_bs16_get, +- Implicit_Field_br16_get, +- Implicit_Field_brall_get +-}; +- +-static xtensa_set_field_fn +-Slot_inst16b_set_field_fns[] = { +- Field_t_Slot_inst16b_set, +- 0, +- 0, +- 0, +- 0, +- Field_s_Slot_inst16b_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_Slot_inst16b_set, +- 0, +- 0, +- Field_r_Slot_inst16b_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_sr_Slot_inst16b_set, +- Field_st_Slot_inst16b_set, +- 0, +- Field_imm4_Slot_inst16b_set, +- 0, +- Field_i_Slot_inst16b_set, +- Field_imm6lo_Slot_inst16b_set, +- Field_imm6hi_Slot_inst16b_set, +- Field_imm7lo_Slot_inst16b_set, +- Field_imm7hi_Slot_inst16b_set, +- Field_z_Slot_inst16b_set, +- Field_imm6_Slot_inst16b_set, +- Field_imm7_Slot_inst16b_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_t2_Slot_inst16b_set, +- Field_s2_Slot_inst16b_set, +- Field_r2_Slot_inst16b_set, +- Field_t4_Slot_inst16b_set, +- Field_s4_Slot_inst16b_set, +- Field_r4_Slot_inst16b_set, +- Field_t8_Slot_inst16b_set, +- Field_s8_Slot_inst16b_set, +- Field_r8_Slot_inst16b_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set +-}; +- +-static xtensa_get_field_fn +-Slot_xt_flix64_slot0_get_field_fns[] = { +- Field_t_Slot_xt_flix64_slot0_get, +- 0, +- 0, +- 0, +- Field_imm8_Slot_xt_flix64_slot0_get, +- Field_s_Slot_xt_flix64_slot0_get, +- Field_imm12b_Slot_xt_flix64_slot0_get, +- Field_imm16_Slot_xt_flix64_slot0_get, +- Field_m_Slot_xt_flix64_slot0_get, +- Field_n_Slot_xt_flix64_slot0_get, +- 0, +- 0, +- Field_op1_Slot_xt_flix64_slot0_get, +- Field_op2_Slot_xt_flix64_slot0_get, +- Field_r_Slot_xt_flix64_slot0_get, +- 0, +- Field_sae4_Slot_xt_flix64_slot0_get, +- Field_sae_Slot_xt_flix64_slot0_get, +- Field_sal_Slot_xt_flix64_slot0_get, +- Field_sargt_Slot_xt_flix64_slot0_get, +- 0, +- Field_sas_Slot_xt_flix64_slot0_get, +- 0, +- 0, +- Field_thi3_Slot_xt_flix64_slot0_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get, +- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get, +- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get, +- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get, +- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get, +- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get, +- Implicit_Field_ar0_get, +- Implicit_Field_ar4_get, +- Implicit_Field_ar8_get, +- Implicit_Field_ar12_get, +- Implicit_Field_mr0_get, +- Implicit_Field_mr1_get, +- Implicit_Field_mr2_get, +- Implicit_Field_mr3_get, +- Implicit_Field_bt16_get, +- Implicit_Field_bs16_get, +- Implicit_Field_br16_get, +- Implicit_Field_brall_get ++static xtensa_opcode_internal opcodes[] = { ++ { "excw", ICLASS_xt_iclass_excw, ++ 0, ++ Opcode_excw_encode_fns, 0, 0 }, ++ { "rfe", ICLASS_xt_iclass_rfe, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfe_encode_fns, 0, 0 }, ++ { "rfde", ICLASS_xt_iclass_rfde, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfde_encode_fns, 0, 0 }, ++ { "syscall", ICLASS_xt_iclass_syscall, ++ 0, ++ Opcode_syscall_encode_fns, 0, 0 }, ++ { "simcall", ICLASS_xt_iclass_simcall, ++ 0, ++ Opcode_simcall_encode_fns, 0, 0 }, ++ { "add.n", ICLASS_xt_iclass_add_n, ++ 0, ++ Opcode_add_n_encode_fns, 0, 0 }, ++ { "addi.n", ICLASS_xt_iclass_addi_n, ++ 0, ++ Opcode_addi_n_encode_fns, 0, 0 }, ++ { "beqz.n", ICLASS_xt_iclass_bz6, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beqz_n_encode_fns, 0, 0 }, ++ { "bnez.n", ICLASS_xt_iclass_bz6, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnez_n_encode_fns, 0, 0 }, ++ { "ill.n", ICLASS_xt_iclass_ill_n, ++ 0, ++ Opcode_ill_n_encode_fns, 0, 0 }, ++ { "l32i.n", ICLASS_xt_iclass_loadi4, ++ 0, ++ Opcode_l32i_n_encode_fns, 0, 0 }, ++ { "mov.n", ICLASS_xt_iclass_mov_n, ++ 0, ++ Opcode_mov_n_encode_fns, 0, 0 }, ++ { "movi.n", ICLASS_xt_iclass_movi_n, ++ 0, ++ Opcode_movi_n_encode_fns, 0, 0 }, ++ { "nop.n", ICLASS_xt_iclass_nopn, ++ 0, ++ Opcode_nop_n_encode_fns, 0, 0 }, ++ { "ret.n", ICLASS_xt_iclass_retn, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_ret_n_encode_fns, 0, 0 }, ++ { "s32i.n", ICLASS_xt_iclass_storei4, ++ 0, ++ Opcode_s32i_n_encode_fns, 0, 0 }, ++ { "addi", ICLASS_xt_iclass_addi, ++ 0, ++ Opcode_addi_encode_fns, 0, 0 }, ++ { "addmi", ICLASS_xt_iclass_addmi, ++ 0, ++ Opcode_addmi_encode_fns, 0, 0 }, ++ { "add", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_add_encode_fns, 0, 0 }, ++ { "sub", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_sub_encode_fns, 0, 0 }, ++ { "addx2", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_addx2_encode_fns, 0, 0 }, ++ { "addx4", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_addx4_encode_fns, 0, 0 }, ++ { "addx8", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_addx8_encode_fns, 0, 0 }, ++ { "subx2", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_subx2_encode_fns, 0, 0 }, ++ { "subx4", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_subx4_encode_fns, 0, 0 }, ++ { "subx8", ICLASS_xt_iclass_addsub, ++ 0, ++ Opcode_subx8_encode_fns, 0, 0 }, ++ { "and", ICLASS_xt_iclass_bit, ++ 0, ++ Opcode_and_encode_fns, 0, 0 }, ++ { "or", ICLASS_xt_iclass_bit, ++ 0, ++ Opcode_or_encode_fns, 0, 0 }, ++ { "xor", ICLASS_xt_iclass_bit, ++ 0, ++ Opcode_xor_encode_fns, 0, 0 }, ++ { "beqi", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beqi_encode_fns, 0, 0 }, ++ { "bnei", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnei_encode_fns, 0, 0 }, ++ { "bgei", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgei_encode_fns, 0, 0 }, ++ { "blti", ICLASS_xt_iclass_bsi8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_blti_encode_fns, 0, 0 }, ++ { "bbci", ICLASS_xt_iclass_bsi8b, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbci_encode_fns, 0, 0 }, ++ { "bbsi", ICLASS_xt_iclass_bsi8b, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbsi_encode_fns, 0, 0 }, ++ { "bgeui", ICLASS_xt_iclass_bsi8u, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgeui_encode_fns, 0, 0 }, ++ { "bltui", ICLASS_xt_iclass_bsi8u, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bltui_encode_fns, 0, 0 }, ++ { "beq", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beq_encode_fns, 0, 0 }, ++ { "bne", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bne_encode_fns, 0, 0 }, ++ { "bge", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bge_encode_fns, 0, 0 }, ++ { "blt", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_blt_encode_fns, 0, 0 }, ++ { "bgeu", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgeu_encode_fns, 0, 0 }, ++ { "bltu", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bltu_encode_fns, 0, 0 }, ++ { "bany", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bany_encode_fns, 0, 0 }, ++ { "bnone", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnone_encode_fns, 0, 0 }, ++ { "ball", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_ball_encode_fns, 0, 0 }, ++ { "bnall", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnall_encode_fns, 0, 0 }, ++ { "bbc", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbc_encode_fns, 0, 0 }, ++ { "bbs", ICLASS_xt_iclass_bst8, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bbs_encode_fns, 0, 0 }, ++ { "beqz", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_beqz_encode_fns, 0, 0 }, ++ { "bnez", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bnez_encode_fns, 0, 0 }, ++ { "bgez", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bgez_encode_fns, 0, 0 }, ++ { "bltz", ICLASS_xt_iclass_bsz12, ++ XTENSA_OPCODE_IS_BRANCH, ++ Opcode_bltz_encode_fns, 0, 0 }, ++ { "call0", ICLASS_xt_iclass_call0, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_call0_encode_fns, 0, 0 }, ++ { "callx0", ICLASS_xt_iclass_callx0, ++ XTENSA_OPCODE_IS_CALL, ++ Opcode_callx0_encode_fns, 0, 0 }, ++ { "extui", ICLASS_xt_iclass_exti, ++ 0, ++ Opcode_extui_encode_fns, 0, 0 }, ++ { "ill", ICLASS_xt_iclass_ill, ++ 0, ++ Opcode_ill_encode_fns, 0, 0 }, ++ { "j", ICLASS_xt_iclass_jump, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_j_encode_fns, 0, 0 }, ++ { "jx", ICLASS_xt_iclass_jumpx, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_jx_encode_fns, 0, 0 }, ++ { "l16ui", ICLASS_xt_iclass_l16ui, ++ 0, ++ Opcode_l16ui_encode_fns, 0, 0 }, ++ { "l16si", ICLASS_xt_iclass_l16si, ++ 0, ++ Opcode_l16si_encode_fns, 0, 0 }, ++ { "l32i", ICLASS_xt_iclass_l32i, ++ 0, ++ Opcode_l32i_encode_fns, 0, 0 }, ++ { "l32r", ICLASS_xt_iclass_l32r, ++ 0, ++ Opcode_l32r_encode_fns, 0, 0 }, ++ { "l8ui", ICLASS_xt_iclass_l8i, ++ 0, ++ Opcode_l8ui_encode_fns, 0, 0 }, ++ { "movi", ICLASS_xt_iclass_movi, ++ 0, ++ Opcode_movi_encode_fns, 0, 0 }, ++ { "moveqz", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_moveqz_encode_fns, 0, 0 }, ++ { "movnez", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_movnez_encode_fns, 0, 0 }, ++ { "movltz", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_movltz_encode_fns, 0, 0 }, ++ { "movgez", ICLASS_xt_iclass_movz, ++ 0, ++ Opcode_movgez_encode_fns, 0, 0 }, ++ { "neg", ICLASS_xt_iclass_neg, ++ 0, ++ Opcode_neg_encode_fns, 0, 0 }, ++ { "abs", ICLASS_xt_iclass_neg, ++ 0, ++ Opcode_abs_encode_fns, 0, 0 }, ++ { "nop", ICLASS_xt_iclass_nop, ++ 0, ++ Opcode_nop_encode_fns, 0, 0 }, ++ { "ret", ICLASS_xt_iclass_return, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_ret_encode_fns, 0, 0 }, ++ { "s16i", ICLASS_xt_iclass_s16i, ++ 0, ++ Opcode_s16i_encode_fns, 0, 0 }, ++ { "s32i", ICLASS_xt_iclass_s32i, ++ 0, ++ Opcode_s32i_encode_fns, 0, 0 }, ++ { "s8i", ICLASS_xt_iclass_s8i, ++ 0, ++ Opcode_s8i_encode_fns, 0, 0 }, ++ { "ssr", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssr_encode_fns, 0, 0 }, ++ { "ssl", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssl_encode_fns, 0, 0 }, ++ { "ssa8l", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssa8l_encode_fns, 0, 0 }, ++ { "ssa8b", ICLASS_xt_iclass_sar, ++ 0, ++ Opcode_ssa8b_encode_fns, 0, 0 }, ++ { "ssai", ICLASS_xt_iclass_sari, ++ 0, ++ Opcode_ssai_encode_fns, 0, 0 }, ++ { "sll", ICLASS_xt_iclass_shifts, ++ 0, ++ Opcode_sll_encode_fns, 0, 0 }, ++ { "src", ICLASS_xt_iclass_shiftst, ++ 0, ++ Opcode_src_encode_fns, 0, 0 }, ++ { "srl", ICLASS_xt_iclass_shiftt, ++ 0, ++ Opcode_srl_encode_fns, 0, 0 }, ++ { "sra", ICLASS_xt_iclass_shiftt, ++ 0, ++ Opcode_sra_encode_fns, 0, 0 }, ++ { "slli", ICLASS_xt_iclass_slli, ++ 0, ++ Opcode_slli_encode_fns, 0, 0 }, ++ { "srai", ICLASS_xt_iclass_srai, ++ 0, ++ Opcode_srai_encode_fns, 0, 0 }, ++ { "srli", ICLASS_xt_iclass_srli, ++ 0, ++ Opcode_srli_encode_fns, 0, 0 }, ++ { "memw", ICLASS_xt_iclass_memw, ++ 0, ++ Opcode_memw_encode_fns, 0, 0 }, ++ { "extw", ICLASS_xt_iclass_extw, ++ 0, ++ Opcode_extw_encode_fns, 0, 0 }, ++ { "isync", ICLASS_xt_iclass_isync, ++ 0, ++ Opcode_isync_encode_fns, 0, 0 }, ++ { "rsync", ICLASS_xt_iclass_sync, ++ 0, ++ Opcode_rsync_encode_fns, 0, 0 }, ++ { "esync", ICLASS_xt_iclass_sync, ++ 0, ++ Opcode_esync_encode_fns, 0, 0 }, ++ { "dsync", ICLASS_xt_iclass_sync, ++ 0, ++ Opcode_dsync_encode_fns, 0, 0 }, ++ { "rsil", ICLASS_xt_iclass_rsil, ++ 0, ++ Opcode_rsil_encode_fns, 0, 0 }, ++ { "rsr.sar", ICLASS_xt_iclass_rsr_sar, ++ 0, ++ Opcode_rsr_sar_encode_fns, 0, 0 }, ++ { "wsr.sar", ICLASS_xt_iclass_wsr_sar, ++ 0, ++ Opcode_wsr_sar_encode_fns, 0, 0 }, ++ { "xsr.sar", ICLASS_xt_iclass_xsr_sar, ++ 0, ++ Opcode_xsr_sar_encode_fns, 0, 0 }, ++ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, ++ 0, ++ Opcode_rsr_litbase_encode_fns, 0, 0 }, ++ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, ++ 0, ++ Opcode_wsr_litbase_encode_fns, 0, 0 }, ++ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, ++ 0, ++ Opcode_xsr_litbase_encode_fns, 0, 0 }, ++ { "rsr.176", ICLASS_xt_iclass_rsr_176, ++ 0, ++ Opcode_rsr_176_encode_fns, 0, 0 }, ++ { "wsr.176", ICLASS_xt_iclass_wsr_176, ++ 0, ++ Opcode_wsr_176_encode_fns, 0, 0 }, ++ { "rsr.208", ICLASS_xt_iclass_rsr_208, ++ 0, ++ Opcode_rsr_208_encode_fns, 0, 0 }, ++ { "rsr.ps", ICLASS_xt_iclass_rsr_ps, ++ 0, ++ Opcode_rsr_ps_encode_fns, 0, 0 }, ++ { "wsr.ps", ICLASS_xt_iclass_wsr_ps, ++ 0, ++ Opcode_wsr_ps_encode_fns, 0, 0 }, ++ { "xsr.ps", ICLASS_xt_iclass_xsr_ps, ++ 0, ++ Opcode_xsr_ps_encode_fns, 0, 0 }, ++ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, ++ 0, ++ Opcode_rsr_epc1_encode_fns, 0, 0 }, ++ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, ++ 0, ++ Opcode_wsr_epc1_encode_fns, 0, 0 }, ++ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, ++ 0, ++ Opcode_xsr_epc1_encode_fns, 0, 0 }, ++ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, ++ 0, ++ Opcode_rsr_excsave1_encode_fns, 0, 0 }, ++ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, ++ 0, ++ Opcode_wsr_excsave1_encode_fns, 0, 0 }, ++ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, ++ 0, ++ Opcode_xsr_excsave1_encode_fns, 0, 0 }, ++ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, ++ 0, ++ Opcode_rsr_epc2_encode_fns, 0, 0 }, ++ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, ++ 0, ++ Opcode_wsr_epc2_encode_fns, 0, 0 }, ++ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, ++ 0, ++ Opcode_xsr_epc2_encode_fns, 0, 0 }, ++ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, ++ 0, ++ Opcode_rsr_excsave2_encode_fns, 0, 0 }, ++ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, ++ 0, ++ Opcode_wsr_excsave2_encode_fns, 0, 0 }, ++ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, ++ 0, ++ Opcode_xsr_excsave2_encode_fns, 0, 0 }, ++ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, ++ 0, ++ Opcode_rsr_epc3_encode_fns, 0, 0 }, ++ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, ++ 0, ++ Opcode_wsr_epc3_encode_fns, 0, 0 }, ++ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, ++ 0, ++ Opcode_xsr_epc3_encode_fns, 0, 0 }, ++ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, ++ 0, ++ Opcode_rsr_excsave3_encode_fns, 0, 0 }, ++ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, ++ 0, ++ Opcode_wsr_excsave3_encode_fns, 0, 0 }, ++ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, ++ 0, ++ Opcode_xsr_excsave3_encode_fns, 0, 0 }, ++ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, ++ 0, ++ Opcode_rsr_eps2_encode_fns, 0, 0 }, ++ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, ++ 0, ++ Opcode_wsr_eps2_encode_fns, 0, 0 }, ++ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, ++ 0, ++ Opcode_xsr_eps2_encode_fns, 0, 0 }, ++ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, ++ 0, ++ Opcode_rsr_eps3_encode_fns, 0, 0 }, ++ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, ++ 0, ++ Opcode_wsr_eps3_encode_fns, 0, 0 }, ++ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, ++ 0, ++ Opcode_xsr_eps3_encode_fns, 0, 0 }, ++ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, ++ 0, ++ Opcode_rsr_excvaddr_encode_fns, 0, 0 }, ++ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, ++ 0, ++ Opcode_wsr_excvaddr_encode_fns, 0, 0 }, ++ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, ++ 0, ++ Opcode_xsr_excvaddr_encode_fns, 0, 0 }, ++ { "rsr.depc", ICLASS_xt_iclass_rsr_depc, ++ 0, ++ Opcode_rsr_depc_encode_fns, 0, 0 }, ++ { "wsr.depc", ICLASS_xt_iclass_wsr_depc, ++ 0, ++ Opcode_wsr_depc_encode_fns, 0, 0 }, ++ { "xsr.depc", ICLASS_xt_iclass_xsr_depc, ++ 0, ++ Opcode_xsr_depc_encode_fns, 0, 0 }, ++ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, ++ 0, ++ Opcode_rsr_exccause_encode_fns, 0, 0 }, ++ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, ++ 0, ++ Opcode_wsr_exccause_encode_fns, 0, 0 }, ++ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, ++ 0, ++ Opcode_xsr_exccause_encode_fns, 0, 0 }, ++ { "rsr.prid", ICLASS_xt_iclass_rsr_prid, ++ 0, ++ Opcode_rsr_prid_encode_fns, 0, 0 }, ++ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, ++ 0, ++ Opcode_rsr_vecbase_encode_fns, 0, 0 }, ++ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, ++ 0, ++ Opcode_wsr_vecbase_encode_fns, 0, 0 }, ++ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, ++ 0, ++ Opcode_xsr_vecbase_encode_fns, 0, 0 }, ++ { "mul16u", ICLASS_xt_mul16, ++ 0, ++ Opcode_mul16u_encode_fns, 0, 0 }, ++ { "mul16s", ICLASS_xt_mul16, ++ 0, ++ Opcode_mul16s_encode_fns, 0, 0 }, ++ { "mull", ICLASS_xt_mul32, ++ 0, ++ Opcode_mull_encode_fns, 0, 0 }, ++ { "rfi", ICLASS_xt_iclass_rfi, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfi_encode_fns, 0, 0 }, ++ { "waiti", ICLASS_xt_iclass_wait, ++ 0, ++ Opcode_waiti_encode_fns, 0, 0 }, ++ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, ++ 0, ++ Opcode_rsr_interrupt_encode_fns, 0, 0 }, ++ { "wsr.intset", ICLASS_xt_iclass_wsr_intset, ++ 0, ++ Opcode_wsr_intset_encode_fns, 0, 0 }, ++ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, ++ 0, ++ Opcode_wsr_intclear_encode_fns, 0, 0 }, ++ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, ++ 0, ++ Opcode_rsr_intenable_encode_fns, 0, 0 }, ++ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, ++ 0, ++ Opcode_wsr_intenable_encode_fns, 0, 0 }, ++ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, ++ 0, ++ Opcode_xsr_intenable_encode_fns, 0, 0 }, ++ { "break", ICLASS_xt_iclass_break, ++ 0, ++ Opcode_break_encode_fns, 0, 0 }, ++ { "break.n", ICLASS_xt_iclass_break_n, ++ 0, ++ Opcode_break_n_encode_fns, 0, 0 }, ++ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, ++ 0, ++ Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, ++ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, ++ 0, ++ Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, ++ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, ++ 0, ++ Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, ++ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, ++ 0, ++ Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, ++ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, ++ 0, ++ Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, ++ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, ++ 0, ++ Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, ++ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, ++ 0, ++ Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, ++ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, ++ 0, ++ Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, ++ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, ++ 0, ++ Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, ++ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, ++ 0, ++ Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, ++ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, ++ 0, ++ Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, ++ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, ++ 0, ++ Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, ++ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, ++ 0, ++ Opcode_rsr_debugcause_encode_fns, 0, 0 }, ++ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, ++ 0, ++ Opcode_wsr_debugcause_encode_fns, 0, 0 }, ++ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, ++ 0, ++ Opcode_xsr_debugcause_encode_fns, 0, 0 }, ++ { "rsr.icount", ICLASS_xt_iclass_rsr_icount, ++ 0, ++ Opcode_rsr_icount_encode_fns, 0, 0 }, ++ { "wsr.icount", ICLASS_xt_iclass_wsr_icount, ++ 0, ++ Opcode_wsr_icount_encode_fns, 0, 0 }, ++ { "xsr.icount", ICLASS_xt_iclass_xsr_icount, ++ 0, ++ Opcode_xsr_icount_encode_fns, 0, 0 }, ++ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, ++ 0, ++ Opcode_rsr_icountlevel_encode_fns, 0, 0 }, ++ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, ++ 0, ++ Opcode_wsr_icountlevel_encode_fns, 0, 0 }, ++ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, ++ 0, ++ Opcode_xsr_icountlevel_encode_fns, 0, 0 }, ++ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, ++ 0, ++ Opcode_rsr_ddr_encode_fns, 0, 0 }, ++ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, ++ 0, ++ Opcode_wsr_ddr_encode_fns, 0, 0 }, ++ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, ++ 0, ++ Opcode_xsr_ddr_encode_fns, 0, 0 }, ++ { "rfdo", ICLASS_xt_iclass_rfdo, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfdo_encode_fns, 0, 0 }, ++ { "rfdd", ICLASS_xt_iclass_rfdd, ++ XTENSA_OPCODE_IS_JUMP, ++ Opcode_rfdd_encode_fns, 0, 0 }, ++ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, ++ 0, ++ Opcode_wsr_mmid_encode_fns, 0, 0 }, ++ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, ++ 0, ++ Opcode_rsr_ccount_encode_fns, 0, 0 }, ++ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, ++ 0, ++ Opcode_wsr_ccount_encode_fns, 0, 0 }, ++ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, ++ 0, ++ Opcode_xsr_ccount_encode_fns, 0, 0 }, ++ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, ++ 0, ++ Opcode_rsr_ccompare0_encode_fns, 0, 0 }, ++ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, ++ 0, ++ Opcode_wsr_ccompare0_encode_fns, 0, 0 }, ++ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, ++ 0, ++ Opcode_xsr_ccompare0_encode_fns, 0, 0 }, ++ { "idtlb", ICLASS_xt_iclass_idtlb, ++ 0, ++ Opcode_idtlb_encode_fns, 0, 0 }, ++ { "pdtlb", ICLASS_xt_iclass_rdtlb, ++ 0, ++ Opcode_pdtlb_encode_fns, 0, 0 }, ++ { "rdtlb0", ICLASS_xt_iclass_rdtlb, ++ 0, ++ Opcode_rdtlb0_encode_fns, 0, 0 }, ++ { "rdtlb1", ICLASS_xt_iclass_rdtlb, ++ 0, ++ Opcode_rdtlb1_encode_fns, 0, 0 }, ++ { "wdtlb", ICLASS_xt_iclass_wdtlb, ++ 0, ++ Opcode_wdtlb_encode_fns, 0, 0 }, ++ { "iitlb", ICLASS_xt_iclass_iitlb, ++ 0, ++ Opcode_iitlb_encode_fns, 0, 0 }, ++ { "pitlb", ICLASS_xt_iclass_ritlb, ++ 0, ++ Opcode_pitlb_encode_fns, 0, 0 }, ++ { "ritlb0", ICLASS_xt_iclass_ritlb, ++ 0, ++ Opcode_ritlb0_encode_fns, 0, 0 }, ++ { "ritlb1", ICLASS_xt_iclass_ritlb, ++ 0, ++ Opcode_ritlb1_encode_fns, 0, 0 }, ++ { "witlb", ICLASS_xt_iclass_witlb, ++ 0, ++ Opcode_witlb_encode_fns, 0, 0 }, ++ { "nsa", ICLASS_xt_iclass_nsa, ++ 0, ++ Opcode_nsa_encode_fns, 0, 0 }, ++ { "nsau", ICLASS_xt_iclass_nsa, ++ 0, ++ Opcode_nsau_encode_fns, 0, 0 }, ++ { "rer", ICLASS_xt_iclass_rer, ++ 0, ++ Opcode_rer_encode_fns, 0, 0 }, ++ { "wer", ICLASS_xt_iclass_wer, ++ 0, ++ Opcode_wer_encode_fns, 0, 0 } + }; + +-static xtensa_set_field_fn +-Slot_xt_flix64_slot0_set_field_fns[] = { +- Field_t_Slot_xt_flix64_slot0_set, +- 0, +- 0, +- 0, +- Field_imm8_Slot_xt_flix64_slot0_set, +- Field_s_Slot_xt_flix64_slot0_set, +- Field_imm12b_Slot_xt_flix64_slot0_set, +- Field_imm16_Slot_xt_flix64_slot0_set, +- Field_m_Slot_xt_flix64_slot0_set, +- Field_n_Slot_xt_flix64_slot0_set, +- 0, +- 0, +- Field_op1_Slot_xt_flix64_slot0_set, +- Field_op2_Slot_xt_flix64_slot0_set, +- Field_r_Slot_xt_flix64_slot0_set, +- 0, +- Field_sae4_Slot_xt_flix64_slot0_set, +- Field_sae_Slot_xt_flix64_slot0_set, +- Field_sal_Slot_xt_flix64_slot0_set, +- Field_sargt_Slot_xt_flix64_slot0_set, +- 0, +- Field_sas_Slot_xt_flix64_slot0_set, +- 0, +- 0, +- Field_thi3_Slot_xt_flix64_slot0_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set, +- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set, +- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set, +- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set, +- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set, +- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set ++enum xtensa_opcode_id { ++ OPCODE_EXCW, ++ OPCODE_RFE, ++ OPCODE_RFDE, ++ OPCODE_SYSCALL, ++ OPCODE_SIMCALL, ++ OPCODE_ADD_N, ++ OPCODE_ADDI_N, ++ OPCODE_BEQZ_N, ++ OPCODE_BNEZ_N, ++ OPCODE_ILL_N, ++ OPCODE_L32I_N, ++ OPCODE_MOV_N, ++ OPCODE_MOVI_N, ++ OPCODE_NOP_N, ++ OPCODE_RET_N, ++ OPCODE_S32I_N, ++ OPCODE_ADDI, ++ OPCODE_ADDMI, ++ OPCODE_ADD, ++ OPCODE_SUB, ++ OPCODE_ADDX2, ++ OPCODE_ADDX4, ++ OPCODE_ADDX8, ++ OPCODE_SUBX2, ++ OPCODE_SUBX4, ++ OPCODE_SUBX8, ++ OPCODE_AND, ++ OPCODE_OR, ++ OPCODE_XOR, ++ OPCODE_BEQI, ++ OPCODE_BNEI, ++ OPCODE_BGEI, ++ OPCODE_BLTI, ++ OPCODE_BBCI, ++ OPCODE_BBSI, ++ OPCODE_BGEUI, ++ OPCODE_BLTUI, ++ OPCODE_BEQ, ++ OPCODE_BNE, ++ OPCODE_BGE, ++ OPCODE_BLT, ++ OPCODE_BGEU, ++ OPCODE_BLTU, ++ OPCODE_BANY, ++ OPCODE_BNONE, ++ OPCODE_BALL, ++ OPCODE_BNALL, ++ OPCODE_BBC, ++ OPCODE_BBS, ++ OPCODE_BEQZ, ++ OPCODE_BNEZ, ++ OPCODE_BGEZ, ++ OPCODE_BLTZ, ++ OPCODE_CALL0, ++ OPCODE_CALLX0, ++ OPCODE_EXTUI, ++ OPCODE_ILL, ++ OPCODE_J, ++ OPCODE_JX, ++ OPCODE_L16UI, ++ OPCODE_L16SI, ++ OPCODE_L32I, ++ OPCODE_L32R, ++ OPCODE_L8UI, ++ OPCODE_MOVI, ++ OPCODE_MOVEQZ, ++ OPCODE_MOVNEZ, ++ OPCODE_MOVLTZ, ++ OPCODE_MOVGEZ, ++ OPCODE_NEG, ++ OPCODE_ABS, ++ OPCODE_NOP, ++ OPCODE_RET, ++ OPCODE_S16I, ++ OPCODE_S32I, ++ OPCODE_S8I, ++ OPCODE_SSR, ++ OPCODE_SSL, ++ OPCODE_SSA8L, ++ OPCODE_SSA8B, ++ OPCODE_SSAI, ++ OPCODE_SLL, ++ OPCODE_SRC, ++ OPCODE_SRL, ++ OPCODE_SRA, ++ OPCODE_SLLI, ++ OPCODE_SRAI, ++ OPCODE_SRLI, ++ OPCODE_MEMW, ++ OPCODE_EXTW, ++ OPCODE_ISYNC, ++ OPCODE_RSYNC, ++ OPCODE_ESYNC, ++ OPCODE_DSYNC, ++ OPCODE_RSIL, ++ OPCODE_RSR_SAR, ++ OPCODE_WSR_SAR, ++ OPCODE_XSR_SAR, ++ OPCODE_RSR_LITBASE, ++ OPCODE_WSR_LITBASE, ++ OPCODE_XSR_LITBASE, ++ OPCODE_RSR_176, ++ OPCODE_WSR_176, ++ OPCODE_RSR_208, ++ OPCODE_RSR_PS, ++ OPCODE_WSR_PS, ++ OPCODE_XSR_PS, ++ OPCODE_RSR_EPC1, ++ OPCODE_WSR_EPC1, ++ OPCODE_XSR_EPC1, ++ OPCODE_RSR_EXCSAVE1, ++ OPCODE_WSR_EXCSAVE1, ++ OPCODE_XSR_EXCSAVE1, ++ OPCODE_RSR_EPC2, ++ OPCODE_WSR_EPC2, ++ OPCODE_XSR_EPC2, ++ OPCODE_RSR_EXCSAVE2, ++ OPCODE_WSR_EXCSAVE2, ++ OPCODE_XSR_EXCSAVE2, ++ OPCODE_RSR_EPC3, ++ OPCODE_WSR_EPC3, ++ OPCODE_XSR_EPC3, ++ OPCODE_RSR_EXCSAVE3, ++ OPCODE_WSR_EXCSAVE3, ++ OPCODE_XSR_EXCSAVE3, ++ OPCODE_RSR_EPS2, ++ OPCODE_WSR_EPS2, ++ OPCODE_XSR_EPS2, ++ OPCODE_RSR_EPS3, ++ OPCODE_WSR_EPS3, ++ OPCODE_XSR_EPS3, ++ OPCODE_RSR_EXCVADDR, ++ OPCODE_WSR_EXCVADDR, ++ OPCODE_XSR_EXCVADDR, ++ OPCODE_RSR_DEPC, ++ OPCODE_WSR_DEPC, ++ OPCODE_XSR_DEPC, ++ OPCODE_RSR_EXCCAUSE, ++ OPCODE_WSR_EXCCAUSE, ++ OPCODE_XSR_EXCCAUSE, ++ OPCODE_RSR_PRID, ++ OPCODE_RSR_VECBASE, ++ OPCODE_WSR_VECBASE, ++ OPCODE_XSR_VECBASE, ++ OPCODE_MUL16U, ++ OPCODE_MUL16S, ++ OPCODE_MULL, ++ OPCODE_RFI, ++ OPCODE_WAITI, ++ OPCODE_RSR_INTERRUPT, ++ OPCODE_WSR_INTSET, ++ OPCODE_WSR_INTCLEAR, ++ OPCODE_RSR_INTENABLE, ++ OPCODE_WSR_INTENABLE, ++ OPCODE_XSR_INTENABLE, ++ OPCODE_BREAK, ++ OPCODE_BREAK_N, ++ OPCODE_RSR_DBREAKA0, ++ OPCODE_WSR_DBREAKA0, ++ OPCODE_XSR_DBREAKA0, ++ OPCODE_RSR_DBREAKC0, ++ OPCODE_WSR_DBREAKC0, ++ OPCODE_XSR_DBREAKC0, ++ OPCODE_RSR_IBREAKA0, ++ OPCODE_WSR_IBREAKA0, ++ OPCODE_XSR_IBREAKA0, ++ OPCODE_RSR_IBREAKENABLE, ++ OPCODE_WSR_IBREAKENABLE, ++ OPCODE_XSR_IBREAKENABLE, ++ OPCODE_RSR_DEBUGCAUSE, ++ OPCODE_WSR_DEBUGCAUSE, ++ OPCODE_XSR_DEBUGCAUSE, ++ OPCODE_RSR_ICOUNT, ++ OPCODE_WSR_ICOUNT, ++ OPCODE_XSR_ICOUNT, ++ OPCODE_RSR_ICOUNTLEVEL, ++ OPCODE_WSR_ICOUNTLEVEL, ++ OPCODE_XSR_ICOUNTLEVEL, ++ OPCODE_RSR_DDR, ++ OPCODE_WSR_DDR, ++ OPCODE_XSR_DDR, ++ OPCODE_RFDO, ++ OPCODE_RFDD, ++ OPCODE_WSR_MMID, ++ OPCODE_RSR_CCOUNT, ++ OPCODE_WSR_CCOUNT, ++ OPCODE_XSR_CCOUNT, ++ OPCODE_RSR_CCOMPARE0, ++ OPCODE_WSR_CCOMPARE0, ++ OPCODE_XSR_CCOMPARE0, ++ OPCODE_IDTLB, ++ OPCODE_PDTLB, ++ OPCODE_RDTLB0, ++ OPCODE_RDTLB1, ++ OPCODE_WDTLB, ++ OPCODE_IITLB, ++ OPCODE_PITLB, ++ OPCODE_RITLB0, ++ OPCODE_RITLB1, ++ OPCODE_WITLB, ++ OPCODE_NSA, ++ OPCODE_NSAU, ++ OPCODE_RER, ++ OPCODE_WER + }; + +-static xtensa_get_field_fn +-Slot_xt_flix64_slot1_get_field_fns[] = { +- Field_t_Slot_xt_flix64_slot1_get, +- 0, +- 0, +- 0, +- Field_imm8_Slot_xt_flix64_slot1_get, +- Field_s_Slot_xt_flix64_slot1_get, +- Field_imm12b_Slot_xt_flix64_slot1_get, +- 0, +- 0, +- 0, +- Field_offset_Slot_xt_flix64_slot1_get, +- 0, +- 0, +- Field_op2_Slot_xt_flix64_slot1_get, +- Field_r_Slot_xt_flix64_slot1_get, +- 0, +- 0, +- Field_sae_Slot_xt_flix64_slot1_get, +- Field_sal_Slot_xt_flix64_slot1_get, +- Field_sargt_Slot_xt_flix64_slot1_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_s4_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_ar0_get, +- Implicit_Field_ar4_get, +- Implicit_Field_ar8_get, +- Implicit_Field_ar12_get, +- Implicit_Field_mr0_get, +- Implicit_Field_mr1_get, +- Implicit_Field_mr2_get, +- Implicit_Field_mr3_get, +- Implicit_Field_bt16_get, +- Implicit_Field_bs16_get, +- Implicit_Field_br16_get, +- Implicit_Field_brall_get +-}; ++ ++/* Slot-specific opcode decode functions. */ ++ ++static int ++Slot_inst_decode (const xtensa_insnbuf insn) ++{ ++ switch (Field_op0_Slot_inst_get (insn)) ++ { ++ case 0: ++ switch (Field_op1_Slot_inst_get (insn)) ++ { ++ case 0: ++ switch (Field_op2_Slot_inst_get (insn)) ++ { ++ case 0: ++ switch (Field_r_Slot_inst_get (insn)) ++ { ++ case 0: ++ switch (Field_m_Slot_inst_get (insn)) ++ { ++ case 0: ++ if (Field_s_Slot_inst_get (insn) == 0 && ++ Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_ILL; ++ break; ++ case 2: ++ switch (Field_n_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_RET; ++ case 2: ++ return OPCODE_JX; ++ } ++ break; ++ case 3: ++ if (Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_CALLX0; ++ break; ++ } ++ break; ++ case 2: ++ if (Field_s_Slot_inst_get (insn) == 0) ++ { ++ switch (Field_t_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_ISYNC; ++ case 1: ++ return OPCODE_RSYNC; ++ case 2: ++ return OPCODE_ESYNC; ++ case 3: ++ return OPCODE_DSYNC; ++ case 8: ++ return OPCODE_EXCW; ++ case 12: ++ return OPCODE_MEMW; ++ case 13: ++ return OPCODE_EXTW; ++ case 15: ++ return OPCODE_NOP; ++ } ++ } ++ break; ++ case 3: ++ switch (Field_t_Slot_inst_get (insn)) ++ { ++ case 0: ++ switch (Field_s_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_RFE; ++ case 2: ++ return OPCODE_RFDE; ++ } ++ break; ++ case 1: ++ return OPCODE_RFI; ++ } ++ break; ++ case 4: ++ return OPCODE_BREAK; ++ case 5: ++ switch (Field_s_Slot_inst_get (insn)) ++ { ++ case 0: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SYSCALL; ++ break; ++ case 1: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SIMCALL; ++ break; ++ } ++ break; ++ case 6: ++ return OPCODE_RSIL; ++ case 7: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_WAITI; ++ break; ++ } ++ break; ++ case 1: ++ return OPCODE_AND; ++ case 2: ++ return OPCODE_OR; ++ case 3: ++ return OPCODE_XOR; ++ case 4: ++ switch (Field_r_Slot_inst_get (insn)) ++ { ++ case 0: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSR; ++ break; ++ case 1: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSL; ++ break; ++ case 2: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSA8L; ++ break; ++ case 3: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SSA8B; ++ break; ++ case 4: ++ if (Field_thi3_Slot_inst_get (insn) == 0) ++ return OPCODE_SSAI; ++ break; ++ case 6: ++ return OPCODE_RER; ++ case 7: ++ return OPCODE_WER; ++ case 14: ++ return OPCODE_NSA; ++ case 15: ++ return OPCODE_NSAU; ++ } ++ break; ++ case 5: ++ switch (Field_r_Slot_inst_get (insn)) ++ { ++ case 3: ++ return OPCODE_RITLB0; ++ case 4: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_IITLB; ++ break; ++ case 5: ++ return OPCODE_PITLB; ++ case 6: ++ return OPCODE_WITLB; ++ case 7: ++ return OPCODE_RITLB1; ++ case 11: ++ return OPCODE_RDTLB0; ++ case 12: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_IDTLB; ++ break; ++ case 13: ++ return OPCODE_PDTLB; ++ case 14: ++ return OPCODE_WDTLB; ++ case 15: ++ return OPCODE_RDTLB1; ++ } ++ break; ++ case 6: ++ switch (Field_s_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_NEG; ++ case 1: ++ return OPCODE_ABS; ++ } ++ break; ++ case 8: ++ return OPCODE_ADD; ++ case 9: ++ return OPCODE_ADDX2; ++ case 10: ++ return OPCODE_ADDX4; ++ case 11: ++ return OPCODE_ADDX8; ++ case 12: ++ return OPCODE_SUB; ++ case 13: ++ return OPCODE_SUBX2; ++ case 14: ++ return OPCODE_SUBX4; ++ case 15: ++ return OPCODE_SUBX8; ++ } ++ break; ++ case 1: ++ switch (Field_op2_Slot_inst_get (insn)) ++ { ++ case 0: ++ case 1: ++ return OPCODE_SLLI; ++ case 2: ++ case 3: ++ return OPCODE_SRAI; ++ case 4: ++ return OPCODE_SRLI; ++ case 6: ++ switch (Field_sr_Slot_inst_get (insn)) ++ { ++ case 3: ++ return OPCODE_XSR_SAR; ++ case 5: ++ return OPCODE_XSR_LITBASE; ++ case 96: ++ return OPCODE_XSR_IBREAKENABLE; ++ case 104: ++ return OPCODE_XSR_DDR; ++ case 128: ++ return OPCODE_XSR_IBREAKA0; ++ case 144: ++ return OPCODE_XSR_DBREAKA0; ++ case 160: ++ return OPCODE_XSR_DBREAKC0; ++ case 177: ++ return OPCODE_XSR_EPC1; ++ case 178: ++ return OPCODE_XSR_EPC2; ++ case 179: ++ return OPCODE_XSR_EPC3; ++ case 192: ++ return OPCODE_XSR_DEPC; ++ case 194: ++ return OPCODE_XSR_EPS2; ++ case 195: ++ return OPCODE_XSR_EPS3; ++ case 209: ++ return OPCODE_XSR_EXCSAVE1; ++ case 210: ++ return OPCODE_XSR_EXCSAVE2; ++ case 211: ++ return OPCODE_XSR_EXCSAVE3; ++ case 228: ++ return OPCODE_XSR_INTENABLE; ++ case 230: ++ return OPCODE_XSR_PS; ++ case 231: ++ return OPCODE_XSR_VECBASE; ++ case 232: ++ return OPCODE_XSR_EXCCAUSE; ++ case 233: ++ return OPCODE_XSR_DEBUGCAUSE; ++ case 234: ++ return OPCODE_XSR_CCOUNT; ++ case 236: ++ return OPCODE_XSR_ICOUNT; ++ case 237: ++ return OPCODE_XSR_ICOUNTLEVEL; ++ case 238: ++ return OPCODE_XSR_EXCVADDR; ++ case 240: ++ return OPCODE_XSR_CCOMPARE0; ++ } ++ break; ++ case 8: ++ return OPCODE_SRC; ++ case 9: ++ if (Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_SRL; ++ break; ++ case 10: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_SLL; ++ break; ++ case 11: ++ if (Field_s_Slot_inst_get (insn) == 0) ++ return OPCODE_SRA; ++ break; ++ case 12: ++ return OPCODE_MUL16U; ++ case 13: ++ return OPCODE_MUL16S; ++ case 15: ++ switch (Field_r_Slot_inst_get (insn)) ++ { ++ case 14: ++ if (Field_t_Slot_inst_get (insn) == 0) ++ return OPCODE_RFDO; ++ if (Field_t_Slot_inst_get (insn) == 1) ++ return OPCODE_RFDD; ++ break; ++ } ++ break; ++ } ++ break; ++ case 2: ++ if (Field_op2_Slot_inst_get (insn) == 8) ++ return OPCODE_MULL; ++ break; ++ case 3: ++ switch (Field_op2_Slot_inst_get (insn)) ++ { ++ case 0: ++ switch (Field_sr_Slot_inst_get (insn)) ++ { ++ case 3: ++ return OPCODE_RSR_SAR; ++ case 5: ++ return OPCODE_RSR_LITBASE; ++ case 96: ++ return OPCODE_RSR_IBREAKENABLE; ++ case 104: ++ return OPCODE_RSR_DDR; ++ case 128: ++ return OPCODE_RSR_IBREAKA0; ++ case 144: ++ return OPCODE_RSR_DBREAKA0; ++ case 160: ++ return OPCODE_RSR_DBREAKC0; ++ case 176: ++ return OPCODE_RSR_176; ++ case 177: ++ return OPCODE_RSR_EPC1; ++ case 178: ++ return OPCODE_RSR_EPC2; ++ case 179: ++ return OPCODE_RSR_EPC3; ++ case 192: ++ return OPCODE_RSR_DEPC; ++ case 194: ++ return OPCODE_RSR_EPS2; ++ case 195: ++ return OPCODE_RSR_EPS3; ++ case 208: ++ return OPCODE_RSR_208; ++ case 209: ++ return OPCODE_RSR_EXCSAVE1; ++ case 210: ++ return OPCODE_RSR_EXCSAVE2; ++ case 211: ++ return OPCODE_RSR_EXCSAVE3; ++ case 226: ++ return OPCODE_RSR_INTERRUPT; ++ case 228: ++ return OPCODE_RSR_INTENABLE; ++ case 230: ++ return OPCODE_RSR_PS; ++ case 231: ++ return OPCODE_RSR_VECBASE; ++ case 232: ++ return OPCODE_RSR_EXCCAUSE; ++ case 233: ++ return OPCODE_RSR_DEBUGCAUSE; ++ case 234: ++ return OPCODE_RSR_CCOUNT; ++ case 235: ++ return OPCODE_RSR_PRID; ++ case 236: ++ return OPCODE_RSR_ICOUNT; ++ case 237: ++ return OPCODE_RSR_ICOUNTLEVEL; ++ case 238: ++ return OPCODE_RSR_EXCVADDR; ++ case 240: ++ return OPCODE_RSR_CCOMPARE0; ++ } ++ break; ++ case 1: ++ switch (Field_sr_Slot_inst_get (insn)) ++ { ++ case 3: ++ return OPCODE_WSR_SAR; ++ case 5: ++ return OPCODE_WSR_LITBASE; ++ case 89: ++ return OPCODE_WSR_MMID; ++ case 96: ++ return OPCODE_WSR_IBREAKENABLE; ++ case 104: ++ return OPCODE_WSR_DDR; ++ case 128: ++ return OPCODE_WSR_IBREAKA0; ++ case 144: ++ return OPCODE_WSR_DBREAKA0; ++ case 160: ++ return OPCODE_WSR_DBREAKC0; ++ case 176: ++ return OPCODE_WSR_176; ++ case 177: ++ return OPCODE_WSR_EPC1; ++ case 178: ++ return OPCODE_WSR_EPC2; ++ case 179: ++ return OPCODE_WSR_EPC3; ++ case 192: ++ return OPCODE_WSR_DEPC; ++ case 194: ++ return OPCODE_WSR_EPS2; ++ case 195: ++ return OPCODE_WSR_EPS3; ++ case 209: ++ return OPCODE_WSR_EXCSAVE1; ++ case 210: ++ return OPCODE_WSR_EXCSAVE2; ++ case 211: ++ return OPCODE_WSR_EXCSAVE3; ++ case 226: ++ return OPCODE_WSR_INTSET; ++ case 227: ++ return OPCODE_WSR_INTCLEAR; ++ case 228: ++ return OPCODE_WSR_INTENABLE; ++ case 230: ++ return OPCODE_WSR_PS; ++ case 231: ++ return OPCODE_WSR_VECBASE; ++ case 232: ++ return OPCODE_WSR_EXCCAUSE; ++ case 233: ++ return OPCODE_WSR_DEBUGCAUSE; ++ case 234: ++ return OPCODE_WSR_CCOUNT; ++ case 236: ++ return OPCODE_WSR_ICOUNT; ++ case 237: ++ return OPCODE_WSR_ICOUNTLEVEL; ++ case 238: ++ return OPCODE_WSR_EXCVADDR; ++ case 240: ++ return OPCODE_WSR_CCOMPARE0; ++ } ++ break; ++ case 8: ++ return OPCODE_MOVEQZ; ++ case 9: ++ return OPCODE_MOVNEZ; ++ case 10: ++ return OPCODE_MOVLTZ; ++ case 11: ++ return OPCODE_MOVGEZ; ++ } ++ break; ++ case 4: ++ case 5: ++ return OPCODE_EXTUI; ++ } ++ break; ++ case 1: ++ return OPCODE_L32R; ++ case 2: ++ switch (Field_r_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_L8UI; ++ case 1: ++ return OPCODE_L16UI; ++ case 2: ++ return OPCODE_L32I; ++ case 4: ++ return OPCODE_S8I; ++ case 5: ++ return OPCODE_S16I; ++ case 6: ++ return OPCODE_S32I; ++ case 9: ++ return OPCODE_L16SI; ++ case 10: ++ return OPCODE_MOVI; ++ case 12: ++ return OPCODE_ADDI; ++ case 13: ++ return OPCODE_ADDMI; ++ } ++ break; ++ case 5: ++ if (Field_n_Slot_inst_get (insn) == 0) ++ return OPCODE_CALL0; ++ break; ++ case 6: ++ switch (Field_n_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_J; ++ case 1: ++ switch (Field_m_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_BEQZ; ++ case 1: ++ return OPCODE_BNEZ; ++ case 2: ++ return OPCODE_BLTZ; ++ case 3: ++ return OPCODE_BGEZ; ++ } ++ break; ++ case 2: ++ switch (Field_m_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_BEQI; ++ case 1: ++ return OPCODE_BNEI; ++ case 2: ++ return OPCODE_BLTI; ++ case 3: ++ return OPCODE_BGEI; ++ } ++ break; ++ case 3: ++ switch (Field_m_Slot_inst_get (insn)) ++ { ++ case 2: ++ return OPCODE_BLTUI; ++ case 3: ++ return OPCODE_BGEUI; ++ } ++ break; ++ } ++ break; ++ case 7: ++ switch (Field_r_Slot_inst_get (insn)) ++ { ++ case 0: ++ return OPCODE_BNONE; ++ case 1: ++ return OPCODE_BEQ; ++ case 2: ++ return OPCODE_BLT; ++ case 3: ++ return OPCODE_BLTU; ++ case 4: ++ return OPCODE_BALL; ++ case 5: ++ return OPCODE_BBC; ++ case 6: ++ case 7: ++ return OPCODE_BBCI; ++ case 8: ++ return OPCODE_BANY; ++ case 9: ++ return OPCODE_BNE; ++ case 10: ++ return OPCODE_BGE; ++ case 11: ++ return OPCODE_BGEU; ++ case 12: ++ return OPCODE_BNALL; ++ case 13: ++ return OPCODE_BBS; ++ case 14: ++ case 15: ++ return OPCODE_BBSI; ++ } ++ break; ++ } ++ return 0; ++} ++ ++static int ++Slot_inst16a_decode (const xtensa_insnbuf insn) ++{ ++ switch (Field_op0_Slot_inst16a_get (insn)) ++ { ++ case 8: ++ return OPCODE_L32I_N; ++ case 9: ++ return OPCODE_S32I_N; ++ case 10: ++ return OPCODE_ADD_N; ++ case 11: ++ return OPCODE_ADDI_N; ++ } ++ return 0; ++} + +-static xtensa_set_field_fn +-Slot_xt_flix64_slot1_set_field_fns[] = { +- Field_t_Slot_xt_flix64_slot1_set, +- 0, +- 0, +- 0, +- Field_imm8_Slot_xt_flix64_slot1_set, +- Field_s_Slot_xt_flix64_slot1_set, +- Field_imm12b_Slot_xt_flix64_slot1_set, +- 0, +- 0, +- 0, +- Field_offset_Slot_xt_flix64_slot1_set, +- 0, +- 0, +- Field_op2_Slot_xt_flix64_slot1_set, +- Field_r_Slot_xt_flix64_slot1_set, +- 0, +- 0, +- Field_sae_Slot_xt_flix64_slot1_set, +- Field_sal_Slot_xt_flix64_slot1_set, +- Field_sargt_Slot_xt_flix64_slot1_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_s4_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set +-}; ++static int ++Slot_inst16b_decode (const xtensa_insnbuf insn) ++{ ++ switch (Field_op0_Slot_inst16b_get (insn)) ++ { ++ case 12: ++ switch (Field_i_Slot_inst16b_get (insn)) ++ { ++ case 0: ++ return OPCODE_MOVI_N; ++ case 1: ++ switch (Field_z_Slot_inst16b_get (insn)) ++ { ++ case 0: ++ return OPCODE_BEQZ_N; ++ case 1: ++ return OPCODE_BNEZ_N; ++ } ++ break; ++ } ++ break; ++ case 13: ++ switch (Field_r_Slot_inst16b_get (insn)) ++ { ++ case 0: ++ return OPCODE_MOV_N; ++ case 15: ++ switch (Field_t_Slot_inst16b_get (insn)) ++ { ++ case 0: ++ return OPCODE_RET_N; ++ case 2: ++ return OPCODE_BREAK_N; ++ case 3: ++ if (Field_s_Slot_inst16b_get (insn) == 0) ++ return OPCODE_NOP_N; ++ break; ++ case 6: ++ if (Field_s_Slot_inst16b_get (insn) == 0) ++ return OPCODE_ILL_N; ++ break; ++ } ++ break; ++ } ++ break; ++ } ++ return 0; ++} + +-static xtensa_get_field_fn +-Slot_xt_flix64_slot2_get_field_fns[] = { +- Field_t_Slot_xt_flix64_slot2_get, +- 0, +- 0, +- 0, +- 0, +- Field_s_Slot_xt_flix64_slot2_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_r_Slot_xt_flix64_slot2_get, +- 0, +- 0, +- 0, +- 0, +- Field_sargt_Slot_xt_flix64_slot2_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_imm7_Slot_xt_flix64_slot2_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_s5_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Implicit_Field_ar0_get, +- Implicit_Field_ar4_get, +- Implicit_Field_ar8_get, +- Implicit_Field_ar12_get, +- Implicit_Field_mr0_get, +- Implicit_Field_mr1_get, +- Implicit_Field_mr2_get, +- Implicit_Field_mr3_get, +- Implicit_Field_bt16_get, +- Implicit_Field_bs16_get, +- Implicit_Field_br16_get, +- Implicit_Field_brall_get +-}; ++ ++/* Instruction slots. */ + +-static xtensa_set_field_fn +-Slot_xt_flix64_slot2_set_field_fns[] = { +- Field_t_Slot_xt_flix64_slot2_set, +- 0, +- 0, +- 0, +- 0, +- Field_s_Slot_xt_flix64_slot2_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_r_Slot_xt_flix64_slot2_set, +- 0, +- 0, +- 0, +- 0, +- Field_sargt_Slot_xt_flix64_slot2_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_imm7_Slot_xt_flix64_slot2_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_op0_s5_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, ++static void ++Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, ++ xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = (insn[0] & 0xffffff); ++} ++ ++static void ++Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, ++ const xtensa_insnbuf slotbuf) ++{ ++ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); ++} ++ ++static void ++Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, ++ xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = (insn[0] & 0xffff); ++} ++ ++static void ++Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, ++ const xtensa_insnbuf slotbuf) ++{ ++ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); ++} ++ ++static void ++Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, ++ xtensa_insnbuf slotbuf) ++{ ++ slotbuf[0] = (insn[0] & 0xffff); ++} ++ ++static void ++Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, ++ const xtensa_insnbuf slotbuf) ++{ ++ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); ++} ++ ++static xtensa_get_field_fn ++Slot_inst_get_field_fns[] = { ++ Field_t_Slot_inst_get, ++ Field_bbi4_Slot_inst_get, ++ Field_bbi_Slot_inst_get, ++ Field_imm12_Slot_inst_get, ++ Field_imm8_Slot_inst_get, ++ Field_s_Slot_inst_get, ++ Field_imm12b_Slot_inst_get, ++ Field_imm16_Slot_inst_get, ++ Field_m_Slot_inst_get, ++ Field_n_Slot_inst_get, ++ Field_offset_Slot_inst_get, ++ Field_op0_Slot_inst_get, ++ Field_op1_Slot_inst_get, ++ Field_op2_Slot_inst_get, ++ Field_r_Slot_inst_get, ++ Field_sa4_Slot_inst_get, ++ Field_sae4_Slot_inst_get, ++ Field_sae_Slot_inst_get, ++ Field_sal_Slot_inst_get, ++ Field_sargt_Slot_inst_get, ++ Field_sas4_Slot_inst_get, ++ Field_sas_Slot_inst_get, ++ Field_sr_Slot_inst_get, ++ Field_st_Slot_inst_get, ++ Field_thi3_Slot_inst_get, ++ Field_imm4_Slot_inst_get, + 0, + 0, + 0, +@@ -20837,6 +7351,39 @@ + 0, + 0, + 0, ++ Field_xt_wbr15_imm_Slot_inst_get, ++ Field_xt_wbr18_imm_Slot_inst_get, ++ Implicit_Field_ar0_get ++}; ++ ++static xtensa_set_field_fn ++Slot_inst_set_field_fns[] = { ++ Field_t_Slot_inst_set, ++ Field_bbi4_Slot_inst_set, ++ Field_bbi_Slot_inst_set, ++ Field_imm12_Slot_inst_set, ++ Field_imm8_Slot_inst_set, ++ Field_s_Slot_inst_set, ++ Field_imm12b_Slot_inst_set, ++ Field_imm16_Slot_inst_set, ++ Field_m_Slot_inst_set, ++ Field_n_Slot_inst_set, ++ Field_offset_Slot_inst_set, ++ Field_op0_Slot_inst_set, ++ Field_op1_Slot_inst_set, ++ Field_op2_Slot_inst_set, ++ Field_r_Slot_inst_set, ++ Field_sa4_Slot_inst_set, ++ Field_sae4_Slot_inst_set, ++ Field_sae_Slot_inst_set, ++ Field_sal_Slot_inst_set, ++ Field_sargt_Slot_inst_set, ++ Field_sas4_Slot_inst_set, ++ Field_sas_Slot_inst_set, ++ Field_sr_Slot_inst_set, ++ Field_st_Slot_inst_set, ++ Field_thi3_Slot_inst_set, ++ Field_imm4_Slot_inst_set, + 0, + 0, + 0, +@@ -20845,110 +7392,28 @@ + 0, + 0, + 0, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, ++ Field_xt_wbr15_imm_Slot_inst_set, ++ Field_xt_wbr18_imm_Slot_inst_set, + Implicit_Field_set + }; + + static xtensa_get_field_fn +-Slot_xt_flix64_slot3_get_field_fns[] = { +- Field_t_Slot_xt_flix64_slot3_get, +- 0, +- Field_bbi_Slot_xt_flix64_slot3_get, +- 0, +- 0, +- Field_s_Slot_xt_flix64_slot3_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_r_Slot_xt_flix64_slot3_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, ++Slot_inst16a_get_field_fns[] = { ++ Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, ++ Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, ++ Field_op0_Slot_inst16a_get, + 0, + 0, ++ Field_r_Slot_inst16a_get, + 0, + 0, + 0, +@@ -20956,95 +7421,40 @@ + 0, + 0, + 0, ++ Field_sr_Slot_inst16a_get, ++ Field_st_Slot_inst16a_get, + 0, ++ Field_imm4_Slot_inst16a_get, ++ Field_i_Slot_inst16a_get, ++ Field_imm6lo_Slot_inst16a_get, ++ Field_imm6hi_Slot_inst16a_get, ++ Field_imm7lo_Slot_inst16a_get, ++ Field_imm7hi_Slot_inst16a_get, ++ Field_z_Slot_inst16a_get, ++ Field_imm6_Slot_inst16a_get, ++ Field_imm7_Slot_inst16a_get, + 0, +- Field_op0_s6_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get, +- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get, + 0, +- Implicit_Field_ar0_get, +- Implicit_Field_ar4_get, +- Implicit_Field_ar8_get, +- Implicit_Field_ar12_get, +- Implicit_Field_mr0_get, +- Implicit_Field_mr1_get, +- Implicit_Field_mr2_get, +- Implicit_Field_mr3_get, +- Implicit_Field_bt16_get, +- Implicit_Field_bs16_get, +- Implicit_Field_br16_get, +- Implicit_Field_brall_get ++ Implicit_Field_ar0_get + }; + + static xtensa_set_field_fn +-Slot_xt_flix64_slot3_set_field_fns[] = { +- Field_t_Slot_xt_flix64_slot3_set, +- 0, +- Field_bbi_Slot_xt_flix64_slot3_set, +- 0, +- 0, +- Field_s_Slot_xt_flix64_slot3_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- Field_r_Slot_xt_flix64_slot3_set, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, +- 0, ++Slot_inst16a_set_field_fns[] = { ++ Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, ++ Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, ++ Field_op0_Slot_inst16a_set, + 0, + 0, ++ Field_r_Slot_inst16a_set, + 0, + 0, + 0, +@@ -21052,21 +7462,40 @@ + 0, + 0, + 0, ++ Field_sr_Slot_inst16a_set, ++ Field_st_Slot_inst16a_set, + 0, ++ Field_imm4_Slot_inst16a_set, ++ Field_i_Slot_inst16a_set, ++ Field_imm6lo_Slot_inst16a_set, ++ Field_imm6hi_Slot_inst16a_set, ++ Field_imm7lo_Slot_inst16a_set, ++ Field_imm7hi_Slot_inst16a_set, ++ Field_z_Slot_inst16a_set, ++ Field_imm6_Slot_inst16a_set, ++ Field_imm7_Slot_inst16a_set, + 0, +- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set, + 0, ++ Implicit_Field_set ++}; ++ ++static xtensa_get_field_fn ++Slot_inst16b_get_field_fns[] = { ++ Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, ++ Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, ++ Field_op0_Slot_inst16b_get, + 0, + 0, ++ Field_r_Slot_inst16b_get, + 0, + 0, + 0, +@@ -21074,20 +7503,40 @@ + 0, + 0, + 0, ++ Field_sr_Slot_inst16b_get, ++ Field_st_Slot_inst16b_get, + 0, ++ Field_imm4_Slot_inst16b_get, ++ Field_i_Slot_inst16b_get, ++ Field_imm6lo_Slot_inst16b_get, ++ Field_imm6hi_Slot_inst16b_get, ++ Field_imm7lo_Slot_inst16b_get, ++ Field_imm7hi_Slot_inst16b_get, ++ Field_z_Slot_inst16b_get, ++ Field_imm6_Slot_inst16b_get, ++ Field_imm7_Slot_inst16b_get, + 0, + 0, ++ Implicit_Field_ar0_get ++}; ++ ++static xtensa_set_field_fn ++Slot_inst16b_set_field_fns[] = { ++ Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, ++ Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, ++ Field_op0_Slot_inst16b_set, + 0, + 0, ++ Field_r_Slot_inst16b_set, + 0, + 0, + 0, +@@ -21095,45 +7544,20 @@ + 0, + 0, + 0, ++ Field_sr_Slot_inst16b_set, ++ Field_st_Slot_inst16b_set, + 0, ++ Field_imm4_Slot_inst16b_set, ++ Field_i_Slot_inst16b_set, ++ Field_imm6lo_Slot_inst16b_set, ++ Field_imm6hi_Slot_inst16b_set, ++ Field_imm7lo_Slot_inst16b_set, ++ Field_imm7hi_Slot_inst16b_set, ++ Field_z_Slot_inst16b_set, ++ Field_imm6_Slot_inst16b_set, ++ Field_imm7_Slot_inst16b_set, + 0, +- Field_op0_s6_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set, +- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set, + 0, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, +- Implicit_Field_set, + Implicit_Field_set + }; + +@@ -21149,27 +7573,7 @@ + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, +- Slot_inst16b_decode, "nop.n" }, +- { "xt_flix64_slot0", "xt_format1", 0, +- Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set, +- Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns, +- Slot_xt_flix64_slot0_decode, "nop" }, +- { "xt_flix64_slot0", "xt_format2", 0, +- Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set, +- Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns, +- Slot_xt_flix64_slot0_decode, "nop" }, +- { "xt_flix64_slot1", "xt_format1", 1, +- Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set, +- Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns, +- Slot_xt_flix64_slot1_decode, "nop" }, +- { "xt_flix64_slot2", "xt_format1", 2, +- Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set, +- Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns, +- Slot_xt_flix64_slot2_decode, "nop" }, +- { "xt_flix64_slot3", "xt_format2", 1, +- Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set, +- Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns, +- Slot_xt_flix64_slot3_decode, "nop" } ++ Slot_inst16b_decode, "nop.n" } + }; + + +@@ -21179,35 +7583,18 @@ + Format_x24_encode (xtensa_insnbuf insn) + { + insn[0] = 0; +- insn[1] = 0; + } + + static void + Format_x16a_encode (xtensa_insnbuf insn) + { + insn[0] = 0x8; +- insn[1] = 0; + } + + static void + Format_x16b_encode (xtensa_insnbuf insn) + { + insn[0] = 0xc; +- insn[1] = 0; +-} +- +-static void +-Format_xt_format1_encode (xtensa_insnbuf insn) +-{ +- insn[0] = 0xe; +- insn[1] = 0; +-} +- +-static void +-Format_xt_format2_encode (xtensa_insnbuf insn) +-{ +- insn[0] = 0xf; +- insn[1] = 0; + } + + static int Format_x24_slots[] = { 0 }; +@@ -21216,32 +7603,22 @@ + + static int Format_x16b_slots[] = { 2 }; + +-static int Format_xt_format1_slots[] = { 3, 5, 6 }; +- +-static int Format_xt_format2_slots[] = { 4, 7 }; +- + static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, +- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, +- { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots }, +- { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots } ++ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } + }; + + + static int + format_decoder (const xtensa_insnbuf insn) + { +- if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) ++ if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ +- if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) ++ if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ +- if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) ++ if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ +- if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0) +- return 3; /* xt_format1 */ +- if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0) +- return 4; /* xt_format2 */ + return -1; + } + +@@ -21260,8 +7637,8 @@ + 2, + 2, + 2, +- 8, +- 8 ++ -1, ++ -1 + }; + + static int +@@ -21276,14 +7653,14 @@ + + xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, +- 8 /* insn_size */, 0, +- 5, formats, format_decoder, length_decoder, +- 8, slots, +- 135 /* num_fields */, +- 188, operands, +- 355, iclasses, +- 530, opcodes, 0, +- 8, regfiles, ++ 3 /* insn_size */, 0, ++ 3, formats, format_decoder, length_decoder, ++ 3, slots, ++ 37 /* num_fields */, ++ 65, operands, ++ 159, iclasses, ++ 204, opcodes, 0, ++ 1, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, +diff -urN gdb-7.5.1-orig/config.guess gdb-7.5.1/config.guess +--- gdb-7.5.1-orig/config.guess 2011-06-06 03:36:06.000000000 -0700 ++++ gdb-7.5.1/config.guess 2015-08-04 11:34:36.037584800 -0700 +@@ -1,14 +1,12 @@ + #! /bin/sh + # Attempt to guess a canonical system name. +-# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +-# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, +-# 2011 Free Software Foundation, Inc. ++# Copyright 1992-2014 Free Software Foundation, Inc. + +-timestamp='2011-06-03' ++timestamp='2014-03-23' + + # This file is free software; you can redistribute it and/or modify it + # under the terms of the GNU General Public License as published by +-# the Free Software Foundation; either version 2 of the License, or ++# the Free Software Foundation; either version 3 of the License, or + # (at your option) any later version. + # + # This program is distributed in the hope that it will be useful, but +@@ -17,26 +15,22 @@ + # General Public License for more details. + # + # You should have received a copy of the GNU General Public License +-# along with this program; if not, write to the Free Software +-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +-# 02110-1301, USA. ++# along with this program; if not, see . + # + # As a special exception to the GNU General Public License, if you + # distribute this file as part of a program that contains a + # configuration script generated by Autoconf, you may include it under +-# the same distribution terms that you use for the rest of that program. +- +- +-# Originally written by Per Bothner. Please send patches (context +-# diff format) to and include a ChangeLog +-# entry. ++# the same distribution terms that you use for the rest of that ++# program. This Exception is an additional permission under section 7 ++# of the GNU General Public License, version 3 ("GPLv3"). + # +-# This script attempts to guess a canonical system name similar to +-# config.sub. If it succeeds, it prints the system name on stdout, and +-# exits with 0. Otherwise, it exits with 1. ++# Originally written by Per Bothner. + # + # You can get the latest version of this script from: + # http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD ++# ++# Please send patches with a ChangeLog entry to config-patches@gnu.org. ++ + + me=`echo "$0" | sed -e 's,.*/,,'` + +@@ -56,9 +50,7 @@ + GNU config.guess ($timestamp) + + Originally written by Per Bothner. +-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, +-2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free +-Software Foundation, Inc. ++Copyright 1992-2014 Free Software Foundation, Inc. + + This is free software; see the source for copying conditions. There is NO + warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." +@@ -140,12 +132,33 @@ + UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown + UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + ++case "${UNAME_SYSTEM}" in ++Linux|GNU|GNU/*) ++ # If the system lacks a compiler, then just pick glibc. ++ # We could probably try harder. ++ LIBC=gnu ++ ++ eval $set_cc_for_build ++ cat <<-EOF > $dummy.c ++ #include ++ #if defined(__UCLIBC__) ++ LIBC=uclibc ++ #elif defined(__dietlibc__) ++ LIBC=dietlibc ++ #else ++ LIBC=gnu ++ #endif ++ EOF ++ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'` ++ ;; ++esac ++ + # Note: order is significant - the case branches are not exclusive. + + case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or +- # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, ++ # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward +@@ -202,6 +215,10 @@ + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "${machine}-${os}${release}" + exit ;; ++ *:Bitrig:*:*) ++ UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'` ++ echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE} ++ exit ;; + *:OpenBSD:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} +@@ -304,7 +321,7 @@ + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix${UNAME_RELEASE} + exit ;; +- arm:riscos:*:*|arm:RISCOS:*:*) ++ arm*:riscos:*:*|arm*:RISCOS:*:*) + echo arm-unknown-riscos + exit ;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) +@@ -792,21 +809,26 @@ + echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:FreeBSD:*:*) +- case ${UNAME_MACHINE} in +- pc98) +- echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; ++ UNAME_PROCESSOR=`/usr/bin/uname -p` ++ case ${UNAME_PROCESSOR} in + amd64) + echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + *) +- echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; ++ echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + esac + exit ;; + i*:CYGWIN*:*) + echo ${UNAME_MACHINE}-pc-cygwin + exit ;; ++ *:MINGW64*:*) ++ echo ${UNAME_MACHINE}-pc-mingw64 ++ exit ;; + *:MINGW*:*) + echo ${UNAME_MACHINE}-pc-mingw32 + exit ;; ++ *:MSYS*:*) ++ echo ${UNAME_MACHINE}-pc-msys ++ exit ;; + i*:windows32*:*) + # uname -m includes "-pc" on this system. + echo ${UNAME_MACHINE}-mingw32 +@@ -852,15 +874,22 @@ + exit ;; + *:GNU:*:*) + # the GNU system +- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` ++ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland +- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu ++ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} + exit ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit ;; ++ aarch64:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ aarch64_be:Linux:*:*) ++ UNAME_MACHINE=aarch64_be ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in + EV5) UNAME_MACHINE=alphaev5 ;; +@@ -872,56 +901,54 @@ + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep -q ld.so.1 +- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi +- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} ++ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ arc:Linux:*:* | arceb:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + arm*:Linux:*:*) + eval $set_cc_for_build + if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_EABI__ + then +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + else + if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_PCS_VFP + then +- echo ${UNAME_MACHINE}-unknown-linux-gnueabi ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi + else +- echo ${UNAME_MACHINE}-unknown-linux-gnueabihf ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf + fi + fi + exit ;; + avr32*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + cris:Linux:*:*) +- echo cris-axis-linux-gnu ++ echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + crisv32:Linux:*:*) +- echo crisv32-axis-linux-gnu ++ echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + frv:Linux:*:*) +- echo frv-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ hexagon:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:Linux:*:*) +- LIBC=gnu +- eval $set_cc_for_build +- sed 's/^ //' << EOF >$dummy.c +- #ifdef __dietlibc__ +- LIBC=dietlibc +- #endif +-EOF +- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` +- echo "${UNAME_MACHINE}-pc-linux-${LIBC}" ++ echo ${UNAME_MACHINE}-pc-linux-${LIBC} + exit ;; + ia64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m32r*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m68*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + mips:Linux:*:* | mips64:Linux:*:*) + eval $set_cc_for_build +@@ -940,54 +967,63 @@ + #endif + EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` +- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ++ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } + ;; +- or32:Linux:*:*) +- echo or32-unknown-linux-gnu ++ openrisc*:Linux:*:*) ++ echo or1k-unknown-linux-${LIBC} ++ exit ;; ++ or32:Linux:*:* | or1k*:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + padre:Linux:*:*) +- echo sparc-unknown-linux-gnu ++ echo sparc-unknown-linux-${LIBC} + exit ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) +- echo hppa64-unknown-linux-gnu ++ echo hppa64-unknown-linux-${LIBC} + exit ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in +- PA7*) echo hppa1.1-unknown-linux-gnu ;; +- PA8*) echo hppa2.0-unknown-linux-gnu ;; +- *) echo hppa-unknown-linux-gnu ;; ++ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; ++ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; ++ *) echo hppa-unknown-linux-${LIBC} ;; + esac + exit ;; + ppc64:Linux:*:*) +- echo powerpc64-unknown-linux-gnu ++ echo powerpc64-unknown-linux-${LIBC} + exit ;; + ppc:Linux:*:*) +- echo powerpc-unknown-linux-gnu ++ echo powerpc-unknown-linux-${LIBC} ++ exit ;; ++ ppc64le:Linux:*:*) ++ echo powerpc64le-unknown-linux-${LIBC} ++ exit ;; ++ ppcle:Linux:*:*) ++ echo powerpcle-unknown-linux-${LIBC} + exit ;; + s390:Linux:*:* | s390x:Linux:*:*) +- echo ${UNAME_MACHINE}-ibm-linux ++ echo ${UNAME_MACHINE}-ibm-linux-${LIBC} + exit ;; + sh64*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sh*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sparc:Linux:*:* | sparc64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + tile*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + vax:Linux:*:*) +- echo ${UNAME_MACHINE}-dec-linux-gnu ++ echo ${UNAME_MACHINE}-dec-linux-${LIBC} + exit ;; + x86_64:Linux:*:*) +- echo x86_64-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + xtensa*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. +@@ -1191,6 +1227,9 @@ + BePC:Haiku:*:*) # Haiku running on Intel PC compatible. + echo i586-pc-haiku + exit ;; ++ x86_64:Haiku:*:*) ++ echo x86_64-unknown-haiku ++ exit ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux${UNAME_RELEASE} + exit ;; +@@ -1217,19 +1256,31 @@ + exit ;; + *:Darwin:*:*) + UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown +- case $UNAME_PROCESSOR in +- i386) +- eval $set_cc_for_build +- if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then +- if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ +- (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ +- grep IS_64BIT_ARCH >/dev/null +- then +- UNAME_PROCESSOR="x86_64" +- fi +- fi ;; +- unknown) UNAME_PROCESSOR=powerpc ;; +- esac ++ eval $set_cc_for_build ++ if test "$UNAME_PROCESSOR" = unknown ; then ++ UNAME_PROCESSOR=powerpc ++ fi ++ if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then ++ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then ++ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ ++ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ ++ grep IS_64BIT_ARCH >/dev/null ++ then ++ case $UNAME_PROCESSOR in ++ i386) UNAME_PROCESSOR=x86_64 ;; ++ powerpc) UNAME_PROCESSOR=powerpc64 ;; ++ esac ++ fi ++ fi ++ elif test "$UNAME_PROCESSOR" = i386 ; then ++ # Avoid executing cc on OS X 10.9, as it ships with a stub ++ # that puts up a graphical alert prompting to install ++ # developer tools. Any system running Mac OS X 10.7 or ++ # later (Darwin 11 and later) is required to have a 64-bit ++ # processor. This is not true of the ARM version of Darwin ++ # that Apple uses in portable devices. ++ UNAME_PROCESSOR=x86_64 ++ fi + echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} + exit ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) +@@ -1246,7 +1297,7 @@ + NEO-?:NONSTOP_KERNEL:*:*) + echo neo-tandem-nsk${UNAME_RELEASE} + exit ;; +- NSE-?:NONSTOP_KERNEL:*:*) ++ NSE-*:NONSTOP_KERNEL:*:*) + echo nse-tandem-nsk${UNAME_RELEASE} + exit ;; + NSR-?:NONSTOP_KERNEL:*:*) +@@ -1315,158 +1366,10 @@ + i*86:AROS:*:*) + echo ${UNAME_MACHINE}-pc-aros + exit ;; +-esac +- +-#echo '(No uname command or uname output not recognized.)' 1>&2 +-#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 +- +-eval $set_cc_for_build +-cat >$dummy.c < +-# include +-#endif +-main () +-{ +-#if defined (sony) +-#if defined (MIPSEB) +- /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, +- I don't know.... */ +- printf ("mips-sony-bsd\n"); exit (0); +-#else +-#include +- printf ("m68k-sony-newsos%s\n", +-#ifdef NEWSOS4 +- "4" +-#else +- "" +-#endif +- ); exit (0); +-#endif +-#endif +- +-#if defined (__arm) && defined (__acorn) && defined (__unix) +- printf ("arm-acorn-riscix\n"); exit (0); +-#endif +- +-#if defined (hp300) && !defined (hpux) +- printf ("m68k-hp-bsd\n"); exit (0); +-#endif +- +-#if defined (NeXT) +-#if !defined (__ARCHITECTURE__) +-#define __ARCHITECTURE__ "m68k" +-#endif +- int version; +- version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; +- if (version < 4) +- printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); +- else +- printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); +- exit (0); +-#endif +- +-#if defined (MULTIMAX) || defined (n16) +-#if defined (UMAXV) +- printf ("ns32k-encore-sysv\n"); exit (0); +-#else +-#if defined (CMU) +- printf ("ns32k-encore-mach\n"); exit (0); +-#else +- printf ("ns32k-encore-bsd\n"); exit (0); +-#endif +-#endif +-#endif +- +-#if defined (__386BSD__) +- printf ("i386-pc-bsd\n"); exit (0); +-#endif +- +-#if defined (sequent) +-#if defined (i386) +- printf ("i386-sequent-dynix\n"); exit (0); +-#endif +-#if defined (ns32000) +- printf ("ns32k-sequent-dynix\n"); exit (0); +-#endif +-#endif +- +-#if defined (_SEQUENT_) +- struct utsname un; +- +- uname(&un); +- +- if (strncmp(un.version, "V2", 2) == 0) { +- printf ("i386-sequent-ptx2\n"); exit (0); +- } +- if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ +- printf ("i386-sequent-ptx1\n"); exit (0); +- } +- printf ("i386-sequent-ptx\n"); exit (0); +- +-#endif +- +-#if defined (vax) +-# if !defined (ultrix) +-# include +-# if defined (BSD) +-# if BSD == 43 +- printf ("vax-dec-bsd4.3\n"); exit (0); +-# else +-# if BSD == 199006 +- printf ("vax-dec-bsd4.3reno\n"); exit (0); +-# else +- printf ("vax-dec-bsd\n"); exit (0); +-# endif +-# endif +-# else +- printf ("vax-dec-bsd\n"); exit (0); +-# endif +-# else +- printf ("vax-dec-ultrix\n"); exit (0); +-# endif +-#endif +- +-#if defined (alliant) && defined (i860) +- printf ("i860-alliant-bsd\n"); exit (0); +-#endif +- +- exit (1); +-} +-EOF +- +-$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && +- { echo "$SYSTEM_NAME"; exit; } +- +-# Apollos put the system type in the environment. +- +-test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } +- +-# Convex versions that predate uname can use getsysinfo(1) +- +-if [ -x /usr/convex/getsysinfo ] +-then +- case `getsysinfo -f cpu_type` in +- c1*) +- echo c1-convex-bsd ++ x86_64:VMkernel:*:*) ++ echo ${UNAME_MACHINE}-unknown-esx + exit ;; +- c2*) +- if getsysinfo -f scalar_acc +- then echo c32-convex-bsd +- else echo c2-convex-bsd +- fi +- exit ;; +- c34*) +- echo c34-convex-bsd +- exit ;; +- c38*) +- echo c38-convex-bsd +- exit ;; +- c4*) +- echo c4-convex-bsd +- exit ;; +- esac +-fi ++esac + + cat >&2 <. +@@ -26,11 +20,12 @@ + # As a special exception to the GNU General Public License, if you + # distribute this file as part of a program that contains a + # configuration script generated by Autoconf, you may include it under +-# the same distribution terms that you use for the rest of that program. ++# the same distribution terms that you use for the rest of that ++# program. This Exception is an additional permission under section 7 ++# of the GNU General Public License, version 3 ("GPLv3"). + + +-# Please send patches to . Submit a context +-# diff and a properly formatted GNU ChangeLog entry. ++# Please send patches with a ChangeLog entry to config-patches@gnu.org. + # + # Configuration subroutine to validate and canonicalize a configuration type. + # Supply the specified configuration type as an argument. +@@ -73,9 +68,7 @@ + version="\ + GNU config.sub ($timestamp) + +-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, +-2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 +-Free Software Foundation, Inc. ++Copyright 1992-2014 Free Software Foundation, Inc. + + This is free software; see the source for copying conditions. There is NO + warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." +@@ -123,7 +116,7 @@ + maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` + case $maybe_os in + nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ +- linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ ++ linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ + knetbsd*-gnu* | netbsd*-gnu* | \ + kopensolaris*-gnu* | \ + storm-chaos* | os2-emx* | rtmk-nova*) +@@ -156,7 +149,7 @@ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ +- -apple | -axis | -knuth | -cray | -microblaze) ++ -apple | -axis | -knuth | -cray | -microblaze*) + os= + basic_machine=$1 + ;; +@@ -259,10 +252,12 @@ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ +- | be32 | be64 \ ++ | arc | arceb \ ++ | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \ ++ | avr | avr32 \ ++ | be32 | be64 \ + | bfin \ +- | c4x | clipper \ ++ | c4x | c8051 | clipper \ + | d10v | d30v | dlx | dsp16xx \ + | epiphany \ + | fido | fr30 | frv \ +@@ -270,10 +265,11 @@ + | hexagon \ + | i370 | i860 | i960 | ia64 \ + | ip2k | iq2000 \ ++ | k1om \ + | le32 | le64 \ + | lm32 \ + | m32c | m32r | m32rle | m68000 | m68k | m88k \ +- | maxq | mb | microblaze | mcore | mep | metag \ ++ | maxq | mb | microblaze | microblazeel | mcore | mep | metag \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64el \ +@@ -287,20 +283,22 @@ + | mips64vr5900 | mips64vr5900el \ + | mipsisa32 | mipsisa32el \ + | mipsisa32r2 | mipsisa32r2el \ ++ | mipsisa32r6 | mipsisa32r6el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64r2 | mipsisa64r2el \ ++ | mipsisa64r6 | mipsisa64r6el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ ++ | mipsr5900 | mipsr5900el \ + | mipstx39 | mipstx39el \ + | mn10200 | mn10300 \ + | moxie \ + | mt \ + | msp430 \ + | nds32 | nds32le | nds32be \ +- | nios | nios2 \ ++ | nios | nios2 | nios2eb | nios2el \ + | ns16k | ns32k \ +- | open8 \ +- | or32 \ ++ | open8 | or1k | or1knd | or32 \ + | pdp10 | pdp11 | pj | pjl \ + | powerpc | powerpc64 | powerpc64le | powerpcle \ + | pyramid \ +@@ -328,7 +326,7 @@ + c6x) + basic_machine=tic6x-unknown + ;; +- m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | picochip) ++ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip) + basic_machine=$basic_machine-unknown + os=-none + ;; +@@ -370,13 +368,13 @@ + | aarch64-* | aarch64_be-* \ + | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ + | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ +- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ ++ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \ + | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ + | avr-* | avr32-* \ + | be32-* | be64-* \ + | bfin-* | bs2000-* \ + | c[123]* | c30-* | [cjt]90-* | c4x-* \ +- | clipper-* | craynv-* | cydra-* \ ++ | c8051-* | clipper-* | craynv-* | cydra-* \ + | d10v-* | d30v-* | dlx-* \ + | elxsi-* \ + | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ +@@ -385,11 +383,13 @@ + | hexagon-* \ + | i*86-* | i860-* | i960-* | ia64-* \ + | ip2k-* | iq2000-* \ ++ | k1om-* \ + | le32-* | le64-* \ + | lm32-* \ + | m32c-* | m32r-* | m32rle-* \ + | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ +- | m88110-* | m88k-* | maxq-* | mcore-* | metag-* | microblaze-* \ ++ | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \ ++ | microblaze-* | microblazeel-* \ + | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ + | mips16-* \ + | mips64-* | mips64el-* \ +@@ -403,18 +403,22 @@ + | mips64vr5900-* | mips64vr5900el-* \ + | mipsisa32-* | mipsisa32el-* \ + | mipsisa32r2-* | mipsisa32r2el-* \ ++ | mipsisa32r6-* | mipsisa32r6el-* \ + | mipsisa64-* | mipsisa64el-* \ + | mipsisa64r2-* | mipsisa64r2el-* \ ++ | mipsisa64r6-* | mipsisa64r6el-* \ + | mipsisa64sb1-* | mipsisa64sb1el-* \ + | mipsisa64sr71k-* | mipsisa64sr71kel-* \ ++ | mipsr5900-* | mipsr5900el-* \ + | mipstx39-* | mipstx39el-* \ + | mmix-* \ + | mt-* \ + | msp430-* \ + | nds32-* | nds32le-* | nds32be-* \ +- | nios-* | nios2-* \ ++ | nios-* | nios2-* | nios2eb-* | nios2el-* \ + | none-* | np1-* | ns16k-* | ns32k-* \ + | open8-* \ ++ | or1k*-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ +@@ -788,11 +792,15 @@ + basic_machine=ns32k-utek + os=-sysv + ;; +- microblaze) ++ microblaze*) + basic_machine=microblaze-xilinx + ;; ++ mingw64) ++ basic_machine=x86_64-pc ++ os=-mingw64 ++ ;; + mingw32) +- basic_machine=i386-pc ++ basic_machine=i686-pc + os=-mingw32 + ;; + mingw32ce) +@@ -828,7 +836,7 @@ + basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` + ;; + msys) +- basic_machine=i386-pc ++ basic_machine=i686-pc + os=-msys + ;; + mvs) +@@ -1019,7 +1027,11 @@ + basic_machine=i586-unknown + os=-pw32 + ;; +- rdos) ++ rdos | rdos64) ++ basic_machine=x86_64-pc ++ os=-rdos ++ ;; ++ rdos32) + basic_machine=i386-pc + os=-rdos + ;; +@@ -1346,21 +1358,21 @@ + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \ +- | -sym* | -kopensolaris* \ ++ | -sym* | -kopensolaris* | -plan9* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* | -aros* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ +- | -openbsd* | -solidbsd* \ ++ | -bitrig* | -openbsd* | -solidbsd* \ + | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ + | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -chorusos* | -chorusrdb* | -cegcc* \ + | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ +- | -mingw32* | -linux-gnu* | -linux-android* \ +- | -linux-newlib* | -linux-uclibc* \ ++ | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ ++ | -linux-newlib* | -linux-musl* | -linux-uclibc* \ + | -uxpv* | -beos* | -mpeix* | -udk* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ +@@ -1368,7 +1380,7 @@ + | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ + | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ + | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ +- | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es*) ++ | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -qnx*) +@@ -1492,9 +1504,6 @@ + -aros*) + os=-aros + ;; +- -kaos*) +- os=-kaos +- ;; + -zvmoe) + os=-zvmoe + ;; +@@ -1543,6 +1552,12 @@ + c4x-* | tic4x-*) + os=-coff + ;; ++ c8051-*) ++ os=-elf ++ ;; ++ hexagon-*) ++ os=-elf ++ ;; + tic54x-*) + os=-coff + ;; +diff -urN gdb-7.5.1-orig/gdb/configure gdb-7.5.1/gdb/configure +--- gdb-7.5.1-orig/gdb/configure 2012-07-17 20:43:41.000000000 -0700 ++++ gdb-7.5.1/gdb/configure 2015-08-18 17:02:34.366940800 -0700 +@@ -4443,6 +4443,8 @@ + + am_cv_CC_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then ++ echo $am_depcomp ++ echo xxxxxxxxxxxxxxxxx + am_compiler_list=`sed -n 's/^\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + for depmode in $am_compiler_list; do +diff -urN gdb-7.5.1-orig/gdb/dwarf2-frame.c gdb-7.5.1/gdb/dwarf2-frame.c +--- gdb-7.5.1-orig/gdb/dwarf2-frame.c 2012-08-06 12:21:51.000000000 -0700 ++++ gdb-7.5.1/gdb/dwarf2-frame.c 2015-08-23 18:57:53.906408800 -0700 +@@ -1493,22 +1493,30 @@ + the DWARF unwinder. This is used to implement + DW_OP_call_frame_cfa. */ + ++ + CORE_ADDR + dwarf2_frame_cfa (struct frame_info *this_frame) + { ++ CORE_ADDR cfa; + while (get_frame_type (this_frame) == INLINE_FRAME) + this_frame = get_prev_frame (this_frame); + /* This restriction could be lifted if other unwinders are known to + compute the frame base in a way compatible with the DWARF + unwinder. */ ++#if 0 + if (!frame_unwinder_is (this_frame, &dwarf2_frame_unwind) + && !frame_unwinder_is (this_frame, &dwarf2_tailcall_frame_unwind)) + error (_("can't compute CFA for this frame")); ++#endif ++ + if (get_frame_unwind_stop_reason (this_frame) == UNWIND_UNAVAILABLE) + throw_error (NOT_AVAILABLE_ERROR, + _("can't compute CFA for this frame: " + "required registers or memory are unavailable")); +- return get_frame_base (this_frame); ++ cfa = get_frame_base (this_frame); ++ if (!cfa) ++ error("Cannot determine frame base. Please call the current function from a function compiled with frame pointer to allow viewing local variables."); ++ return cfa; + } + + const struct objfile_data *dwarf2_frame_objfile_data; +diff -urN gdb-7.5.1-orig/gdb/gdbserver/xtensa-xtregs.c gdb-7.5.1/gdb/gdbserver/xtensa-xtregs.c +--- gdb-7.5.1-orig/gdb/gdbserver/xtensa-xtregs.c 2012-01-04 00:17:24.000000000 -0800 ++++ gdb-7.5.1/gdb/gdbserver/xtensa-xtregs.c 2015-08-04 11:34:10.500831300 -0700 +@@ -1,37 +1,42 @@ +-/* Table mapping between kernel xtregset and GDB register cache. +- Copyright 2007-2012 Free Software Foundation, Inc. +- +- This file is part of GDB. +- +- This program is free software; you can redistribute it and/or +- modify it under the terms of the GNU General Public License as +- published by the Free Software Foundation; either version 3 of the +- License, or (at your option) any later version. +- +- This program is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program. If not, see . */ +- +- +-typedef struct { +- int gdb_regnum; +- int gdb_offset; +- int ptrace_cp_offset; +- int ptrace_offset; +- int size; +- int coproc; +- int dbnum; +- char* name +-;} xtensa_regtable_t; +- +-#define XTENSA_ELF_XTREG_SIZE 4 +- +-const xtensa_regtable_t xtensa_regmap_table[] = { +- /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ +- { 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" }, +- { 0 } +-}; ++/* Customized table mapping between kernel xtregset and GDB register cache. ++ ++ Copyright (c) 2007-2010 Tensilica Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++ ++typedef struct { ++ int gdb_regnum; ++ int gdb_offset; ++ int ptrace_cp_offset; ++ int ptrace_offset; ++ int size; ++ int coproc; ++ int dbnum; ++ char* name ++;} xtensa_regtable_t; ++ ++#define XTENSA_ELF_XTREG_SIZE 0 ++ ++const xtensa_regtable_t xtensa_regmap_table[] = { ++ /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ ++ { 0 } ++}; ++ +diff -urN gdb-7.5.1-orig/gdb/regformats/reg-xtensa.dat gdb-7.5.1/gdb/regformats/reg-xtensa.dat +--- gdb-7.5.1-orig/gdb/regformats/reg-xtensa.dat 2008-11-19 10:29:47.000000000 -0800 ++++ gdb-7.5.1/gdb/regformats/reg-xtensa.dat 2015-08-04 11:34:12.301911300 -0700 +@@ -1,47 +1,24 @@ +-name:xtensa +-expedite:pc,windowbase,windowstart +-32:pc +-32:ar0 +-32:ar1 +-32:ar2 +-32:ar3 +-32:ar4 +-32:ar5 +-32:ar6 +-32:ar7 +-32:ar8 +-32:ar9 +-32:ar10 +-32:ar11 +-32:ar12 +-32:ar13 +-32:ar14 +-32:ar15 +-32:ar16 +-32:ar17 +-32:ar18 +-32:ar19 +-32:ar20 +-32:ar21 +-32:ar22 +-32:ar23 +-32:ar24 +-32:ar25 +-32:ar26 +-32:ar27 +-32:ar28 +-32:ar29 +-32:ar30 +-32:ar31 +-32:lbeg +-32:lend +-32:lcount +-32:sar +-32:litbase +-32:windowbase +-32:windowstart +-32:sr176 +-32:sr208 +-32:ps +-32:threadptr +-32:scompare1 ++name:xtensa ++expedite:pc,windowbase,windowstart ++32:a0 ++32:a1 ++32:a2 ++32:a3 ++32:a4 ++32:a5 ++32:a6 ++32:a7 ++32:a8 ++32:a9 ++32:a10 ++32:a11 ++32:a12 ++32:a13 ++32:a14 ++32:a15 ++32:pc ++32:sar ++32:litbase ++32:sr176 ++32:sr208 ++32:ps +diff -urN gdb-7.5.1-orig/gdb/xtensa-config.c gdb-7.5.1/gdb/xtensa-config.c +--- gdb-7.5.1-orig/gdb/xtensa-config.c 2012-01-04 00:27:58.000000000 -0800 ++++ gdb-7.5.1/gdb/xtensa-config.c 2015-08-18 17:06:01.571940800 -0700 +@@ -1,219 +1,118 @@ +-/* Configuration for the Xtensa architecture for GDB, the GNU debugger. +- +- Copyright (C) 2003, 2005-2012 Free Software Foundation, Inc. +- +- This file is part of GDB. +- +- This program is free software; you can redistribute it and/or modify +- it under the terms of the GNU General Public License as published by +- the Free Software Foundation; either version 3 of the License, or +- (at your option) any later version. +- +- This program is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- GNU General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program. If not, see . */ +- +-#define XTENSA_CONFIG_VERSION 0x60 +- +-#include "xtensa-config.h" +-#include "xtensa-tdep.h" +- +- +- +-/* Masked registers. */ +-xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } }; +-const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; +-xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } }; +-const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; +-xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } }; +-const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; +-xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } }; +-const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; +-xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } }; +-const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; +-xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } }; +-const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; +-xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } }; +-const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; +-xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } }; +-const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; +-xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } }; +-const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; +-xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } }; +-const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; +-xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } }; +-const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; +-xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } }; +-const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; +-xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } }; +-const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; +-xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } }; +-const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; +-xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } }; +-const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; +-xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } }; +-const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; +- +- +-/* Register map. */ +-xtensa_register_t rmap[] = +-{ +- /* idx ofs bi sz al targno flags cp typ group name */ +- XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) +- XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) +- XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) +- XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) +- XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) +- XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) +- XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) +- XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) +- XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) +- XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) +- XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) +- XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) +- XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) +- XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) +- XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) +- XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) +- XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) +- XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) +- XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) +- XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) +- XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) +- XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) +- XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) +- XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) +- XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) +- XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) +- XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) +- XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) +- XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) +- XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) +- XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) +- XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) +- XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) +- XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) +- XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) +- XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) +- XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) +- XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0) +- XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) +- XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) +- XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0) +- XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0) +- XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) +- XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) +- XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) +- XTREG( 45,180,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0) +- XTREG( 46,184,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) +- XTREG( 47,188,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0) +- XTREG( 48,192,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0) +- XTREG( 49,196,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0) +- XTREG( 50,200, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) +- XTREG( 51,204,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) +- XTREG( 52,208,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) +- XTREG( 53,212,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) +- XTREG( 54,216,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) +- XTREG( 55,220,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) +- XTREG( 56,224,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) +- XTREG( 57,228,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) +- XTREG( 58,232,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) +- XTREG( 59,236,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) +- XTREG( 60,240,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) +- XTREG( 61,244,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) +- XTREG( 62,248,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) +- XTREG( 63,252,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) +- XTREG( 64,256,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) +- XTREG( 65,260,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) +- XTREG( 66,264,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) +- XTREG( 67,268,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) +- XTREG( 68,272,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) +- XTREG( 69,276,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) +- XTREG( 70,280,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) +- XTREG( 71,284,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) +- XTREG( 72,288,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) +- XTREG( 73,292,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) +- XTREG( 74,296,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) +- XTREG( 75,300,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) +- XTREG( 76,304,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) +- XTREG( 77,308,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) +- XTREG( 78,312,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) +- XTREG( 79,316, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) +- XTREG( 80,320,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) +- XTREG( 81,324,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) +- XTREG( 82,328,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) +- XTREG( 83,332,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) +- XTREG( 84,336,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) +- XTREG( 85,340, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) +- XTREG( 86,344,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) +- XTREG( 87,348,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) +- XTREG( 88,352,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) +- XTREG( 89,356,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) +- XTREG( 90,360, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) +- XTREG( 91,364,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) +- XTREG( 92,368,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) +- XTREG( 93,372,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) +- XTREG( 94,376,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) +- XTREG( 95,380,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) +- XTREG( 96,384,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) +- XTREG( 97,388,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) +- XTREG( 98,392,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) +- XTREG( 99,396,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) +- XTREG(100,400,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) +- XTREG(101,404,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) +- XTREG(102,408,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) +- XTREG(103,412,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) +- XTREG(104,416,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) +- XTREG(105,420,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) +- XTREG(106,424,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) +- XTREG(107,428,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) +- XTREG(108,432,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) +- XTREG(109,436,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) +- XTREG(110,440,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) +- XTREG(111,444,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) +- XTREG(112,448,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) +- XTREG(113,452, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, +- 0,0,&xtensa_mask0,0,0,0) +- XTREG(114,456, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, +- 0,0,&xtensa_mask1,0,0,0) +- XTREG(115,460, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, +- 0,0,&xtensa_mask2,0,0,0) +- XTREG(116,464, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, +- 0,0,&xtensa_mask3,0,0,0) +- XTREG(117,468, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, +- 0,0,&xtensa_mask4,0,0,0) +- XTREG(118,472, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, +- 0,0,&xtensa_mask5,0,0,0) +- XTREG(119,476, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, +- 0,0,&xtensa_mask6,0,0,0) +- XTREG(120,480,20, 4, 4,0x200f,0x0006,-2, 6,0x1010,litbaddr, +- 0,0,&xtensa_mask7,0,0,0) +- XTREG(121,484, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,litben, +- 0,0,&xtensa_mask8,0,0,0) +- XTREG(122,488, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum, +- 0,0,&xtensa_mask9,0,0,0) +- XTREG(123,492, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3, +- 0,0,&xtensa_mask10,0,0,0) +- XTREG(124,496, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2, +- 0,0,&xtensa_mask11,0,0,0) +- XTREG(125,500, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1, +- 0,0,&xtensa_mask12,0,0,0) +- XTREG(126,504, 2, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid4, +- 0,0,&xtensa_mask13,0,0,0) +- XTREG(127,508, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,datapgszid4, +- 0,0,&xtensa_mask14,0,0,0) +- XTREG(128,512,10, 4, 4,0x201b,0x0006,-2, 6,0x1010,ptbase, +- 0,0,&xtensa_mask15,0,0,0) +- XTREG_END +-}; +- +- +- +-#ifdef XTENSA_CONFIG_INSTANTIATE +-XTENSA_CONFIG_INSTANTIATE(rmap,0) +-#endif +- ++/* Configuration for the Xtensa architecture for GDB, the GNU debugger. ++ ++ Copyright (c) 2003-2010 Tensilica Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ++ ++#define XTENSA_CONFIG_VERSION 0x60 ++ ++#include "xtensa-config.h" ++#include "xtensa-tdep.h" ++ ++ ++ ++/* Masked registers. */ ++xtensa_reg_mask_t xtensa_submask0[] = { { 21, 0, 4 } }; ++const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; ++xtensa_reg_mask_t xtensa_submask1[] = { { 21, 5, 1 } }; ++const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; ++xtensa_reg_mask_t xtensa_submask2[] = { { 21, 4, 1 } }; ++const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; ++xtensa_reg_mask_t xtensa_submask3[] = { { 18, 12, 20 } }; ++const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; ++xtensa_reg_mask_t xtensa_submask4[] = { { 18, 0, 1 } }; ++const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; ++xtensa_reg_mask_t xtensa_submask5[] = { { 43, 8, 4 } }; ++const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; ++ ++ ++/* Register map. */ ++xtensa_register_t rmap[] = ++{ ++ /* idx ofs bi sz al targno flags cp typ group name */ ++ XTREG( 0, 0,32, 4, 4,0x0000,0x0006 & ~1,-2, 8,0x0100,a0, 0,0,0,0,0,0) ++ XTREG( 1, 4,32, 4, 4,0x0001,0x0006 & ~1,-2, 8,0x0100,a1, 0,0,0,0,0,0) ++ XTREG( 2, 8,32, 4, 4,0x0002,0x0006 & ~1,-2, 8,0x0100,a2, 0,0,0,0,0,0) ++ XTREG( 3, 12,32, 4, 4,0x0003,0x0006 & ~1,-2, 8,0x0100,a3, 0,0,0,0,0,0) ++ XTREG( 4, 16,32, 4, 4,0x0004,0x0006 & ~1,-2, 8,0x0100,a4, 0,0,0,0,0,0) ++ XTREG( 5, 20,32, 4, 4,0x0005,0x0006 & ~1,-2, 8,0x0100,a5, 0,0,0,0,0,0) ++ XTREG( 6, 24,32, 4, 4,0x0006,0x0006 & ~1,-2, 8,0x0100,a6, 0,0,0,0,0,0) ++ XTREG( 7, 28,32, 4, 4,0x0007,0x0006 & ~1,-2, 8,0x0100,a7, 0,0,0,0,0,0) ++ XTREG( 8, 32,32, 4, 4,0x0008,0x0006 & ~1,-2, 8,0x0100,a8, 0,0,0,0,0,0) ++ XTREG( 9, 36,32, 4, 4,0x0009,0x0006 & ~1,-2, 8,0x0100,a9, 0,0,0,0,0,0) ++ XTREG( 10, 40,32, 4, 4,0x000a,0x0006 & ~1,-2, 8,0x0100,a10, 0,0,0,0,0,0) ++ XTREG( 11, 44,32, 4, 4,0x000b,0x0006 & ~1,-2, 8,0x0100,a11, 0,0,0,0,0,0) ++ XTREG( 12, 48,32, 4, 4,0x000c,0x0006 & ~1,-2, 8,0x0100,a12, 0,0,0,0,0,0) ++ XTREG( 13, 52,32, 4, 4,0x000d,0x0006 & ~1,-2, 8,0x0100,a13, 0,0,0,0,0,0) ++ XTREG( 14, 56,32, 4, 4,0x000e,0x0006 & ~1,-2, 8,0x0100,a14, 0,0,0,0,0,0) ++ XTREG( 15, 60,32, 4, 4,0x000f,0x0006 & ~1,-2, 8,0x0100,a15, 0,0,0,0,0,0) ++ XTREG( 16, 64,32, 4, 4,0x0020,0x0006 & ~1,-2, 9,0x0100,pc, 0,0,0,0,0,0) ++ XTREG( 17, 68, 6, 4, 4,0x0203,0x0006 & ~1,-2, 2,0x1100,sar, 0,0,0,0,0,0) ++ XTREG( 18, 72,32, 4, 4,0x0205,0x0006 & ~1,-2, 2,0x1100,litbase, 0,0,0,0,0,0) ++ XTREG( 19, 76,32, 4, 4,0x02b0,0x0002 & ~1,-2, 2,0x1000,sr176, 0,0,0,0,0,0) ++ XTREG( 20, 80,32, 4, 4,0x02d0,0x0002 & ~1,-2, 2,0x1000,sr208, 0,0,0,0,0,0) ++ XTREG( 21, 84, 6, 4, 4,0x02e6,0x0006 & ~1,-2, 2,0x1100,ps, 0,0,0,0,0,0) ++ XTREG( 22, 88,32, 4, 4,0x0259,0x000d & ~1,-2, 2,0x1000,mmid, 0,0,0,0,0,0) ++ XTREG( 23, 92, 1, 4, 4,0x0260,0x0007 & ~1,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) ++ XTREG( 24, 96,32, 4, 4,0x0268,0x0007 & ~1,-2, 2,0x1000,ddr, 0,0,0,0,0,0) ++ XTREG( 25,100,32, 4, 4,0x0280,0x0007 & ~1,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) ++ XTREG( 26,104,32, 4, 4,0x0290,0x0007 & ~1,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) ++ XTREG( 27,108,32, 4, 4,0x02a0,0x0007 & ~1,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) ++ XTREG( 28,112,32, 4, 4,0x02b1,0x0007 & ~1,-2, 2,0x1000,epc1, 0,0,0,0,0,0) ++ XTREG( 29,116,32, 4, 4,0x02b2,0x0007 & ~1,-2, 2,0x1000,epc2, 0,0,0,0,0,0) ++ XTREG( 30,120,32, 4, 4,0x02b3,0x0007 & ~1,-2, 2,0x1000,epc3, 0,0,0,0,0,0) ++ XTREG( 31,124,32, 4, 4,0x02c0,0x0007 & ~1,-2, 2,0x1000,depc, 0,0,0,0,0,0) ++ XTREG( 32,128, 6, 4, 4,0x02c2,0x0007 & ~1,-2, 2,0x1000,eps2, 0,0,0,0,0,0) ++ XTREG( 33,132, 6, 4, 4,0x02c3,0x0007 & ~1,-2, 2,0x1000,eps3, 0,0,0,0,0,0) ++ XTREG( 34,136,32, 4, 4,0x02d1,0x0007 & ~1,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) ++ XTREG( 35,140,32, 4, 4,0x02d2,0x0007 & ~1,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) ++ XTREG( 36,144,32, 4, 4,0x02d3,0x0007 & ~1,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) ++ XTREG( 37,148,15, 4, 4,0x02e2,0x000b & ~1,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) ++ XTREG( 38,152,15, 4, 4,0x02e2,0x000d & ~1,-2, 2,0x1000,intset, 0,0,0,0,0,0) ++ XTREG( 39,156,15, 4, 4,0x02e3,0x000d & ~1,-2, 2,0x1000,intclear, 0,0,0,0,0,0) ++ XTREG( 40,160,15, 4, 4,0x02e4,0x0007 & ~1,-2, 2,0x1000,intenable, 0,0,0,0,0,0) ++ XTREG( 41,164,32, 4, 4,0x02e7,0x0007 & ~1,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) ++ XTREG( 42,168, 6, 4, 4,0x02e8,0x0007 & ~1,-2, 2,0x1000,exccause, 0,0,0,0,0,0) ++ XTREG( 43,172,12, 4, 4,0x02e9,0x0003 & ~1,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) ++ XTREG( 44,176,32, 4, 4,0x02ea,0x000f & ~1,-2, 2,0x1000,ccount, 0,0,0,0,0,0) ++ XTREG( 45,180,32, 4, 4,0x02eb,0x0003 & ~1,-2, 2,0x1000,prid, 0,0,0,0,0,0) ++ XTREG( 46,184,32, 4, 4,0x02ec,0x000f & ~1,-2, 2,0x1000,icount, 0,0,0,0,0,0) ++ XTREG( 47,188, 4, 4, 4,0x02ed,0x0007 & ~1,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) ++ XTREG( 48,192,32, 4, 4,0x02ee,0x0007 & ~1,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) ++ XTREG( 49,196,32, 4, 4,0x02f0,0x000f & ~1,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) ++ XTREG( 50,200, 4, 4, 4,0x2002,0x0006,-2, 6,0x1010,psintlevel, ++ 0,0,&xtensa_mask0,0,0,0) ++ XTREG( 51,204, 1, 4, 4,0x2003,0x0006,-2, 6,0x1010,psum, ++ 0,0,&xtensa_mask1,0,0,0) ++ XTREG( 52,208, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psexcm, ++ 0,0,&xtensa_mask2,0,0,0) ++ XTREG( 53,212,20, 4, 4,0x2005,0x0006,-2, 6,0x1010,litbaddr, ++ 0,0,&xtensa_mask3,0,0,0) ++ XTREG( 54,216, 1, 4, 4,0x2006,0x0006,-2, 6,0x1010,litben, ++ 0,0,&xtensa_mask4,0,0,0) ++ XTREG_END ++}; ++ ++ ++ ++#ifdef XTENSA_CONFIG_INSTANTIATE ++XTENSA_CONFIG_INSTANTIATE(rmap,0) ++#endif ++ +diff -urN gdb-7.5.1-orig/gdb/xtensa-tdep.c gdb-7.5.1/gdb/xtensa-tdep.c +--- gdb-7.5.1-orig/gdb/xtensa-tdep.c 2012-05-18 14:02:51.000000000 -0700 ++++ gdb-7.5.1/gdb/xtensa-tdep.c 2015-08-18 17:50:12.374935700 -0700 +@@ -555,10 +555,6 @@ + DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", + regnum, xtensa_register_name (gdbarch, regnum)); + +- if (regnum == gdbarch_num_regs (gdbarch) +- + gdbarch_num_pseudo_regs (gdbarch) - 1) +- regnum = gdbarch_tdep (gdbarch)->a0_base + 1; +- + /* Read aliases a0..a15, if this is a Windowed ABI. */ + if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers + && (regnum >= gdbarch_tdep (gdbarch)->a0_base) +@@ -655,10 +651,6 @@ + DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", + regnum, xtensa_register_name (gdbarch, regnum)); + +- if (regnum == gdbarch_num_regs (gdbarch) +- + gdbarch_num_pseudo_regs (gdbarch) -1) +- regnum = gdbarch_tdep (gdbarch)->a0_base + 1; +- + /* Renumber register, if aliase a0..a15 on Windowed ABI. */ + if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers + && (regnum >= gdbarch_tdep (gdbarch)->a0_base) +@@ -2040,6 +2032,8 @@ + const char *opcname; + int found_ret = 0; + ++ if (!xtensa_default_isa) ++ xtensa_default_isa = xtensa_isa_init(0, 0); + isa = xtensa_default_isa; + gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); + ins = xtensa_insnbuf_alloc (isa); +@@ -2425,7 +2419,7 @@ + /* Find out, if we have an information about the prologue from DWARF. */ + prologue_sal = find_pc_line (start, 0); + if (prologue_sal.line != 0) /* Found debug info. */ +- body_pc = prologue_sal.end; ++ body_pc = prologue_sal.end + 40; + + /* If we are going to analyze the prologue in general without knowing about + the current PC, make the best assumtion for the end of the prologue. */ +@@ -2819,6 +2813,8 @@ + /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */ + int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140; + ++ if (!xtensa_default_isa) ++ xtensa_default_isa = xtensa_isa_init(0, 0); + isa = xtensa_default_isa; + gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); + ins = xtensa_insnbuf_alloc (isa); +@@ -3190,6 +3186,9 @@ + tdep->num_regs = n; + } + ++ if (tdep->ar_base == -1) ++ tdep->ar_base = tdep->a0_base; ++ + /* Number of pseudo registers. */ + tdep->num_pseudo_regs = n - tdep->num_regs; + +diff -urN gdb-7.5.1-orig/gdb/xtensa-tdep.h gdb-7.5.1/gdb/xtensa-tdep.h +--- gdb-7.5.1-orig/gdb/xtensa-tdep.h 2012-01-04 00:27:58.000000000 -0800 ++++ gdb-7.5.1/gdb/xtensa-tdep.h 2015-08-18 17:06:02.796940800 -0700 +@@ -244,7 +244,8 @@ + .spill_location = -1, \ + .spill_size = (spillsz), \ + .unused = 0, \ +- .call_abi = 0, \ ++ .call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0) ? \ ++ CallAbiCall0Only : CallAbiDefault, \ + .debug_interrupt_level = XCHAL_DEBUGLEVEL, \ + .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \ + .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ +diff -urN gdb-7.5.1-orig/include/xtensa-config.h gdb-7.5.1/include/xtensa-config.h +--- gdb-7.5.1-orig/include/xtensa-config.h 2011-01-03 13:05:50.000000000 -0800 ++++ gdb-7.5.1/include/xtensa-config.h 2015-08-04 11:34:09.056465200 -0700 +@@ -1,177 +1,171 @@ +-/* Xtensa configuration settings. +- Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 +- Free Software Foundation, Inc. +- Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. +- +- This program is free software; you can redistribute it and/or modify +- it under the terms of the GNU General Public License as published by +- the Free Software Foundation; either version 2, or (at your option) +- any later version. +- +- This program is distributed in the hope that it will be useful, but +- WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program; if not, write to the Free Software +- Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ +- +-#ifndef XTENSA_CONFIG_H +-#define XTENSA_CONFIG_H +- +-/* The macros defined here match those with the same names in the Xtensa +- compile-time HAL (Hardware Abstraction Layer). Please refer to the +- Xtensa System Software Reference Manual for documentation of these +- macros. */ +- +-#undef XCHAL_HAVE_BE +-#define XCHAL_HAVE_BE 1 +- +-#undef XCHAL_HAVE_DENSITY +-#define XCHAL_HAVE_DENSITY 1 +- +-#undef XCHAL_HAVE_CONST16 +-#define XCHAL_HAVE_CONST16 0 +- +-#undef XCHAL_HAVE_ABS +-#define XCHAL_HAVE_ABS 1 +- +-#undef XCHAL_HAVE_ADDX +-#define XCHAL_HAVE_ADDX 1 +- +-#undef XCHAL_HAVE_L32R +-#define XCHAL_HAVE_L32R 1 +- +-#undef XSHAL_USE_ABSOLUTE_LITERALS +-#define XSHAL_USE_ABSOLUTE_LITERALS 0 +- +-#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ +- +-#undef XCHAL_HAVE_MAC16 +-#define XCHAL_HAVE_MAC16 0 +- +-#undef XCHAL_HAVE_MUL16 +-#define XCHAL_HAVE_MUL16 1 +- +-#undef XCHAL_HAVE_MUL32 +-#define XCHAL_HAVE_MUL32 1 +- +-#undef XCHAL_HAVE_MUL32_HIGH +-#define XCHAL_HAVE_MUL32_HIGH 0 +- +-#undef XCHAL_HAVE_DIV32 +-#define XCHAL_HAVE_DIV32 1 +- +-#undef XCHAL_HAVE_NSA +-#define XCHAL_HAVE_NSA 1 +- +-#undef XCHAL_HAVE_MINMAX +-#define XCHAL_HAVE_MINMAX 1 +- +-#undef XCHAL_HAVE_SEXT +-#define XCHAL_HAVE_SEXT 1 +- +-#undef XCHAL_HAVE_LOOPS +-#define XCHAL_HAVE_LOOPS 1 +- +-#undef XCHAL_HAVE_THREADPTR +-#define XCHAL_HAVE_THREADPTR 1 +- +-#undef XCHAL_HAVE_RELEASE_SYNC +-#define XCHAL_HAVE_RELEASE_SYNC 1 +- +-#undef XCHAL_HAVE_S32C1I +-#define XCHAL_HAVE_S32C1I 1 +- +-#undef XCHAL_HAVE_BOOLEANS +-#define XCHAL_HAVE_BOOLEANS 0 +- +-#undef XCHAL_HAVE_FP +-#define XCHAL_HAVE_FP 0 +- +-#undef XCHAL_HAVE_FP_DIV +-#define XCHAL_HAVE_FP_DIV 0 +- +-#undef XCHAL_HAVE_FP_RECIP +-#define XCHAL_HAVE_FP_RECIP 0 +- +-#undef XCHAL_HAVE_FP_SQRT +-#define XCHAL_HAVE_FP_SQRT 0 +- +-#undef XCHAL_HAVE_FP_RSQRT +-#define XCHAL_HAVE_FP_RSQRT 0 +- +-#undef XCHAL_HAVE_DFP_accel +-#define XCHAL_HAVE_DFP_accel 0 +-#undef XCHAL_HAVE_WINDOWED +-#define XCHAL_HAVE_WINDOWED 1 +- +-#undef XCHAL_NUM_AREGS +-#define XCHAL_NUM_AREGS 32 +- +-#undef XCHAL_HAVE_WIDE_BRANCHES +-#define XCHAL_HAVE_WIDE_BRANCHES 0 +- +-#undef XCHAL_HAVE_PREDICTED_BRANCHES +-#define XCHAL_HAVE_PREDICTED_BRANCHES 0 +- +- +-#undef XCHAL_ICACHE_SIZE +-#define XCHAL_ICACHE_SIZE 16384 +- +-#undef XCHAL_DCACHE_SIZE +-#define XCHAL_DCACHE_SIZE 16384 +- +-#undef XCHAL_ICACHE_LINESIZE +-#define XCHAL_ICACHE_LINESIZE 32 +- +-#undef XCHAL_DCACHE_LINESIZE +-#define XCHAL_DCACHE_LINESIZE 32 +- +-#undef XCHAL_ICACHE_LINEWIDTH +-#define XCHAL_ICACHE_LINEWIDTH 5 +- +-#undef XCHAL_DCACHE_LINEWIDTH +-#define XCHAL_DCACHE_LINEWIDTH 5 +- +-#undef XCHAL_DCACHE_IS_WRITEBACK +-#define XCHAL_DCACHE_IS_WRITEBACK 1 +- +- +-#undef XCHAL_HAVE_MMU +-#define XCHAL_HAVE_MMU 1 +- +-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE +-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 +- +- +-#undef XCHAL_HAVE_DEBUG +-#define XCHAL_HAVE_DEBUG 1 +- +-#undef XCHAL_NUM_IBREAK +-#define XCHAL_NUM_IBREAK 2 +- +-#undef XCHAL_NUM_DBREAK +-#define XCHAL_NUM_DBREAK 2 +- +-#undef XCHAL_DEBUGLEVEL +-#define XCHAL_DEBUGLEVEL 6 +- +- +-#undef XCHAL_MAX_INSTRUCTION_SIZE +-#define XCHAL_MAX_INSTRUCTION_SIZE 3 +- +-#undef XCHAL_INST_FETCH_WIDTH +-#define XCHAL_INST_FETCH_WIDTH 4 +- +- +-#undef XSHAL_ABI +-#undef XTHAL_ABI_WINDOWED +-#undef XTHAL_ABI_CALL0 +-#define XSHAL_ABI XTHAL_ABI_WINDOWED +-#define XTHAL_ABI_WINDOWED 0 +-#define XTHAL_ABI_CALL0 1 +- +-#endif /* !XTENSA_CONFIG_H */ ++/* Xtensa configuration settings. ++ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 ++ Free Software Foundation, Inc. ++ Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2, or (at your option) ++ any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ ++ ++#ifndef XTENSA_CONFIG_H ++#define XTENSA_CONFIG_H ++ ++/* The macros defined here match those with the same names in the Xtensa ++ compile-time HAL (Hardware Abstraction Layer). Please refer to the ++ Xtensa System Software Reference Manual for documentation of these ++ macros. */ ++ ++#undef XCHAL_HAVE_BE ++#define XCHAL_HAVE_BE 0 ++ ++#undef XCHAL_HAVE_DENSITY ++#define XCHAL_HAVE_DENSITY 1 ++ ++#undef XCHAL_HAVE_CONST16 ++#define XCHAL_HAVE_CONST16 0 ++ ++#undef XCHAL_HAVE_ABS ++#define XCHAL_HAVE_ABS 1 ++ ++#undef XCHAL_HAVE_ADDX ++#define XCHAL_HAVE_ADDX 1 ++ ++#undef XCHAL_HAVE_L32R ++#define XCHAL_HAVE_L32R 1 ++ ++#undef XSHAL_USE_ABSOLUTE_LITERALS ++#define XSHAL_USE_ABSOLUTE_LITERALS 0 ++ ++#undef XCHAL_HAVE_MAC16 ++#define XCHAL_HAVE_MAC16 0 ++ ++#undef XCHAL_HAVE_MUL16 ++#define XCHAL_HAVE_MUL16 1 ++ ++#undef XCHAL_HAVE_MUL32 ++#define XCHAL_HAVE_MUL32 1 ++ ++#undef XCHAL_HAVE_MUL32_HIGH ++#define XCHAL_HAVE_MUL32_HIGH 0 ++ ++#undef XCHAL_HAVE_DIV32 ++#define XCHAL_HAVE_DIV32 0 ++ ++#undef XCHAL_HAVE_NSA ++#define XCHAL_HAVE_NSA 1 ++ ++#undef XCHAL_HAVE_MINMAX ++#define XCHAL_HAVE_MINMAX 0 ++ ++#undef XCHAL_HAVE_SEXT ++#define XCHAL_HAVE_SEXT 0 ++ ++#undef XCHAL_HAVE_LOOPS ++#define XCHAL_HAVE_LOOPS 0 ++ ++#undef XCHAL_HAVE_THREADPTR ++#define XCHAL_HAVE_THREADPTR 0 ++ ++#undef XCHAL_HAVE_RELEASE_SYNC ++#define XCHAL_HAVE_RELEASE_SYNC 0 ++ ++#undef XCHAL_HAVE_S32C1I ++#define XCHAL_HAVE_S32C1I 0 ++ ++#undef XCHAL_HAVE_BOOLEANS ++#define XCHAL_HAVE_BOOLEANS 0 ++ ++#undef XCHAL_HAVE_FP ++#define XCHAL_HAVE_FP 0 ++ ++#undef XCHAL_HAVE_FP_DIV ++#define XCHAL_HAVE_FP_DIV 0 ++ ++#undef XCHAL_HAVE_FP_RECIP ++#define XCHAL_HAVE_FP_RECIP 0 ++ ++#undef XCHAL_HAVE_FP_SQRT ++#define XCHAL_HAVE_FP_SQRT 0 ++ ++#undef XCHAL_HAVE_FP_RSQRT ++#define XCHAL_HAVE_FP_RSQRT 0 ++ ++#undef XCHAL_HAVE_DFP_accel ++#define XCHAL_HAVE_DFP_accel 0 ++#undef XCHAL_HAVE_WINDOWED ++#define XCHAL_HAVE_WINDOWED 0 ++ ++#undef XCHAL_NUM_AREGS ++#define XCHAL_NUM_AREGS 16 ++ ++#undef XCHAL_HAVE_WIDE_BRANCHES ++#define XCHAL_HAVE_WIDE_BRANCHES 0 ++ ++#undef XCHAL_HAVE_PREDICTED_BRANCHES ++#define XCHAL_HAVE_PREDICTED_BRANCHES 0 ++ ++ ++#undef XCHAL_ICACHE_SIZE ++#define XCHAL_ICACHE_SIZE 0 ++ ++#undef XCHAL_DCACHE_SIZE ++#define XCHAL_DCACHE_SIZE 0 ++ ++#undef XCHAL_ICACHE_LINESIZE ++#define XCHAL_ICACHE_LINESIZE 16 ++ ++#undef XCHAL_DCACHE_LINESIZE ++#define XCHAL_DCACHE_LINESIZE 16 ++ ++#undef XCHAL_ICACHE_LINEWIDTH ++#define XCHAL_ICACHE_LINEWIDTH 4 ++ ++#undef XCHAL_DCACHE_LINEWIDTH ++#define XCHAL_DCACHE_LINEWIDTH 4 ++ ++#undef XCHAL_DCACHE_IS_WRITEBACK ++#define XCHAL_DCACHE_IS_WRITEBACK 0 ++ ++ ++#undef XCHAL_HAVE_MMU ++#define XCHAL_HAVE_MMU 0 ++ ++ ++#undef XCHAL_HAVE_DEBUG ++#define XCHAL_HAVE_DEBUG 1 ++ ++#undef XCHAL_NUM_IBREAK ++#define XCHAL_NUM_IBREAK 1 ++ ++#undef XCHAL_NUM_DBREAK ++#define XCHAL_NUM_DBREAK 1 ++ ++#undef XCHAL_DEBUGLEVEL ++#define XCHAL_DEBUGLEVEL 2 ++ ++ ++#undef XCHAL_MAX_INSTRUCTION_SIZE ++#define XCHAL_MAX_INSTRUCTION_SIZE 3 ++ ++#undef XCHAL_INST_FETCH_WIDTH ++#define XCHAL_INST_FETCH_WIDTH 4 ++ ++ ++#undef XSHAL_ABI ++#undef XTHAL_ABI_WINDOWED ++#undef XTHAL_ABI_CALL0 ++#define XSHAL_ABI XTHAL_ABI_CALL0 ++#define XTHAL_ABI_WINDOWED 0 ++#define XTHAL_ABI_CALL0 1 ++ ++#endif /* !XTENSA_CONFIG_H */ +diff -urN gdb-7.5.1-orig/readline/support/config.guess gdb-7.5.1/readline/support/config.guess +--- gdb-7.5.1-orig/readline/support/config.guess 2011-05-11 16:38:44.000000000 -0700 ++++ gdb-7.5.1/readline/support/config.guess 2015-08-04 11:34:36.368217000 -0700 +@@ -1,14 +1,12 @@ + #! /bin/sh + # Attempt to guess a canonical system name. +-# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +-# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 +-# Free Software Foundation, Inc. ++# Copyright 1992-2014 Free Software Foundation, Inc. + +-timestamp='2008-03-12' ++timestamp='2014-03-23' + + # This file is free software; you can redistribute it and/or modify it + # under the terms of the GNU General Public License as published by +-# the Free Software Foundation; either version 2 of the License, or ++# the Free Software Foundation; either version 3 of the License, or + # (at your option) any later version. + # + # This program is distributed in the hope that it will be useful, but +@@ -17,26 +15,22 @@ + # General Public License for more details. + # + # You should have received a copy of the GNU General Public License +-# along with this program; if not, write to the Free Software +-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +-# 02110-1301, USA. ++# along with this program; if not, see . + # + # As a special exception to the GNU General Public License, if you + # distribute this file as part of a program that contains a + # configuration script generated by Autoconf, you may include it under +-# the same distribution terms that you use for the rest of that program. +- +- +-# Originally written by Per Bothner . +-# Please send patches to . Submit a context +-# diff and a properly formatted ChangeLog entry. ++# the same distribution terms that you use for the rest of that ++# program. This Exception is an additional permission under section 7 ++# of the GNU General Public License, version 3 ("GPLv3"). ++# ++# Originally written by Per Bothner. + # +-# This script attempts to guess a canonical system name similar to +-# config.sub. If it succeeds, it prints the system name on stdout, and +-# exits with 0. Otherwise, it exits with 1. ++# You can get the latest version of this script from: ++# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD + # +-# The plan is that this can be called by configure scripts if you +-# don't specify an explicit build system type. ++# Please send patches with a ChangeLog entry to config-patches@gnu.org. ++ + + me=`echo "$0" | sed -e 's,.*/,,'` + +@@ -56,8 +50,7 @@ + GNU config.guess ($timestamp) + + Originally written by Per Bothner. +-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, +-2002, 2003, 2004, 2005, 2006, 2007, 2008,2009 Free Software Foundation, Inc. ++Copyright 1992-2014 Free Software Foundation, Inc. + + This is free software; see the source for copying conditions. There is NO + warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." +@@ -139,12 +132,33 @@ + UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown + UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + ++case "${UNAME_SYSTEM}" in ++Linux|GNU|GNU/*) ++ # If the system lacks a compiler, then just pick glibc. ++ # We could probably try harder. ++ LIBC=gnu ++ ++ eval $set_cc_for_build ++ cat <<-EOF > $dummy.c ++ #include ++ #if defined(__UCLIBC__) ++ LIBC=uclibc ++ #elif defined(__dietlibc__) ++ LIBC=dietlibc ++ #else ++ LIBC=gnu ++ #endif ++ EOF ++ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'` ++ ;; ++esac ++ + # Note: order is significant - the case branches are not exclusive. + + case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or +- # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, ++ # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward +@@ -170,7 +184,7 @@ + arm*|i386|m68k|ns32k|sh3*|sparc|vax) + eval $set_cc_for_build + if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ +- | grep __ELF__ >/dev/null ++ | grep -q __ELF__ + then + # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). + # Return netbsd for either. FIX? +@@ -180,7 +194,7 @@ + fi + ;; + *) +- os=netbsd ++ os=netbsd + ;; + esac + # The OS release +@@ -201,6 +215,10 @@ + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "${machine}-${os}${release}" + exit ;; ++ *:Bitrig:*:*) ++ UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'` ++ echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE} ++ exit ;; + *:OpenBSD:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} +@@ -223,7 +241,7 @@ + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` + ;; + *5.*) +- UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` ++ UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` + ;; + esac + # According to Compaq, /usr/sbin/psrinfo has been available on +@@ -269,7 +287,10 @@ + # A Xn.n version is an unreleased experimental baselevel. + # 1.2 uses "1.2" for uname -r. + echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` +- exit ;; ++ # Reset EXIT trap before exiting to avoid spurious non-zero exit code. ++ exitcode=$? ++ trap '' 0 ++ exit $exitcode ;; + Alpha\ *:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # Should we change UNAME_MACHINE based on the output of uname instead +@@ -295,12 +316,12 @@ + echo s390-ibm-zvmoe + exit ;; + *:OS400:*:*) +- echo powerpc-ibm-os400 ++ echo powerpc-ibm-os400 + exit ;; + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix${UNAME_RELEASE} + exit ;; +- arm:riscos:*:*|arm:RISCOS:*:*) ++ arm*:riscos:*:*|arm*:RISCOS:*:*) + echo arm-unknown-riscos + exit ;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) +@@ -324,14 +345,33 @@ + case `/usr/bin/uname -p` in + sparc) echo sparc-icl-nx7; exit ;; + esac ;; ++ s390x:SunOS:*:*) ++ echo ${UNAME_MACHINE}-ibm-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` ++ exit ;; + sun4H:SunOS:5.*:*) + echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) + echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; ++ i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*) ++ echo i386-pc-auroraux${UNAME_RELEASE} ++ exit ;; + i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) +- echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` ++ eval $set_cc_for_build ++ SUN_ARCH="i386" ++ # If there is a compiler, see if it is configured for 64-bit objects. ++ # Note that the Sun cc does not turn __LP64__ into 1 like gcc does. ++ # This test works for both compilers. ++ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then ++ if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \ ++ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ ++ grep IS_64BIT_ARCH >/dev/null ++ then ++ SUN_ARCH="x86_64" ++ fi ++ fi ++ echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:6*:*) + # According to config.sub, this is the proper way to canonicalize +@@ -375,23 +415,23 @@ + # MiNT. But MiNT is downward compatible to TOS, so this should + # be no problem. + atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) +- echo m68k-atari-mint${UNAME_RELEASE} ++ echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} +- exit ;; ++ exit ;; + *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) +- echo m68k-atari-mint${UNAME_RELEASE} ++ echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) +- echo m68k-milan-mint${UNAME_RELEASE} +- exit ;; ++ echo m68k-milan-mint${UNAME_RELEASE} ++ exit ;; + hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) +- echo m68k-hades-mint${UNAME_RELEASE} +- exit ;; ++ echo m68k-hades-mint${UNAME_RELEASE} ++ exit ;; + *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) +- echo m68k-unknown-mint${UNAME_RELEASE} +- exit ;; ++ echo m68k-unknown-mint${UNAME_RELEASE} ++ exit ;; + m68k:machten:*:*) + echo m68k-apple-machten${UNAME_RELEASE} + exit ;; +@@ -461,8 +501,8 @@ + echo m88k-motorola-sysv3 + exit ;; + AViiON:dgux:*:*) +- # DG/UX returns AViiON for all architectures +- UNAME_PROCESSOR=`/usr/bin/uname -p` ++ # DG/UX returns AViiON for all architectures ++ UNAME_PROCESSOR=`/usr/bin/uname -p` + if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] + then + if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ +@@ -475,7 +515,7 @@ + else + echo i586-dg-dgux${UNAME_RELEASE} + fi +- exit ;; ++ exit ;; + M88*:DolphinOS:*:*) # DolphinOS (SVR3) + echo m88k-dolphin-sysv3 + exit ;; +@@ -532,7 +572,7 @@ + echo rs6000-ibm-aix3.2 + fi + exit ;; +- *:AIX:*:[456]) ++ *:AIX:*:[4567]) + IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` + if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then + IBM_ARCH=rs6000 +@@ -575,52 +615,52 @@ + 9000/[678][0-9][0-9]) + if [ -x /usr/bin/getconf ]; then + sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` +- sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` +- case "${sc_cpu_version}" in +- 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 +- 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 +- 532) # CPU_PA_RISC2_0 +- case "${sc_kernel_bits}" in +- 32) HP_ARCH="hppa2.0n" ;; +- 64) HP_ARCH="hppa2.0w" ;; ++ sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` ++ case "${sc_cpu_version}" in ++ 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 ++ 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 ++ 532) # CPU_PA_RISC2_0 ++ case "${sc_kernel_bits}" in ++ 32) HP_ARCH="hppa2.0n" ;; ++ 64) HP_ARCH="hppa2.0w" ;; + '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 +- esac ;; +- esac ++ esac ;; ++ esac + fi + if [ "${HP_ARCH}" = "" ]; then + eval $set_cc_for_build +- sed 's/^ //' << EOF >$dummy.c ++ sed 's/^ //' << EOF >$dummy.c + +- #define _HPUX_SOURCE +- #include +- #include +- +- int main () +- { +- #if defined(_SC_KERNEL_BITS) +- long bits = sysconf(_SC_KERNEL_BITS); +- #endif +- long cpu = sysconf (_SC_CPU_VERSION); +- +- switch (cpu) +- { +- case CPU_PA_RISC1_0: puts ("hppa1.0"); break; +- case CPU_PA_RISC1_1: puts ("hppa1.1"); break; +- case CPU_PA_RISC2_0: +- #if defined(_SC_KERNEL_BITS) +- switch (bits) +- { +- case 64: puts ("hppa2.0w"); break; +- case 32: puts ("hppa2.0n"); break; +- default: puts ("hppa2.0"); break; +- } break; +- #else /* !defined(_SC_KERNEL_BITS) */ +- puts ("hppa2.0"); break; +- #endif +- default: puts ("hppa1.0"); break; +- } +- exit (0); +- } ++ #define _HPUX_SOURCE ++ #include ++ #include ++ ++ int main () ++ { ++ #if defined(_SC_KERNEL_BITS) ++ long bits = sysconf(_SC_KERNEL_BITS); ++ #endif ++ long cpu = sysconf (_SC_CPU_VERSION); ++ ++ switch (cpu) ++ { ++ case CPU_PA_RISC1_0: puts ("hppa1.0"); break; ++ case CPU_PA_RISC1_1: puts ("hppa1.1"); break; ++ case CPU_PA_RISC2_0: ++ #if defined(_SC_KERNEL_BITS) ++ switch (bits) ++ { ++ case 64: puts ("hppa2.0w"); break; ++ case 32: puts ("hppa2.0n"); break; ++ default: puts ("hppa2.0"); break; ++ } break; ++ #else /* !defined(_SC_KERNEL_BITS) */ ++ puts ("hppa2.0"); break; ++ #endif ++ default: puts ("hppa1.0"); break; ++ } ++ exit (0); ++ } + EOF + (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` + test -z "$HP_ARCH" && HP_ARCH=hppa +@@ -640,7 +680,7 @@ + # => hppa64-hp-hpux11.23 + + if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | +- grep __LP64__ >/dev/null ++ grep -q __LP64__ + then + HP_ARCH="hppa2.0w" + else +@@ -711,22 +751,22 @@ + exit ;; + C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) + echo c1-convex-bsd +- exit ;; ++ exit ;; + C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi +- exit ;; ++ exit ;; + C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) + echo c34-convex-bsd +- exit ;; ++ exit ;; + C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) + echo c38-convex-bsd +- exit ;; ++ exit ;; + C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) + echo c4-convex-bsd +- exit ;; ++ exit ;; + CRAY*Y-MP:*:*:*) + echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; +@@ -750,14 +790,14 @@ + exit ;; + F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) + FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` +- FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` +- FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` +- echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" +- exit ;; ++ FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` ++ FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` ++ echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" ++ exit ;; + 5000:UNIX_System_V:4.*:*) +- FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` +- FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` +- echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" ++ FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` ++ FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` ++ echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) + echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} +@@ -769,34 +809,39 @@ + echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:FreeBSD:*:*) +- case ${UNAME_MACHINE} in +- pc98) +- echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; ++ UNAME_PROCESSOR=`/usr/bin/uname -p` ++ case ${UNAME_PROCESSOR} in + amd64) + echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + *) +- echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; ++ echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + esac + exit ;; + i*:CYGWIN*:*) + echo ${UNAME_MACHINE}-pc-cygwin + exit ;; ++ *:MINGW64*:*) ++ echo ${UNAME_MACHINE}-pc-mingw64 ++ exit ;; + *:MINGW*:*) + echo ${UNAME_MACHINE}-pc-mingw32 + exit ;; ++ *:MSYS*:*) ++ echo ${UNAME_MACHINE}-pc-msys ++ exit ;; + i*:windows32*:*) +- # uname -m includes "-pc" on this system. +- echo ${UNAME_MACHINE}-mingw32 ++ # uname -m includes "-pc" on this system. ++ echo ${UNAME_MACHINE}-mingw32 + exit ;; + i*:PW*:*) + echo ${UNAME_MACHINE}-pc-pw32 + exit ;; +- *:Interix*:[3456]*) +- case ${UNAME_MACHINE} in ++ *:Interix*:*) ++ case ${UNAME_MACHINE} in + x86) + echo i586-pc-interix${UNAME_RELEASE} + exit ;; +- EM64T | authenticamd) ++ authenticamd | genuineintel | EM64T) + echo x86_64-unknown-interix${UNAME_RELEASE} + exit ;; + IA64) +@@ -806,6 +851,9 @@ + [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) + echo i${UNAME_MACHINE}-pc-mks + exit ;; ++ 8664:Windows_NT:*) ++ echo x86_64-pc-mks ++ exit ;; + i*:Windows_NT*:* | Pentium*:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we +@@ -826,210 +874,157 @@ + exit ;; + *:GNU:*:*) + # the GNU system +- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` ++ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland +- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu ++ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} + exit ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit ;; ++ aarch64:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ aarch64_be:Linux:*:*) ++ UNAME_MACHINE=aarch64_be ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ alpha:Linux:*:*) ++ case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in ++ EV5) UNAME_MACHINE=alphaev5 ;; ++ EV56) UNAME_MACHINE=alphaev56 ;; ++ PCA56) UNAME_MACHINE=alphapca56 ;; ++ PCA57) UNAME_MACHINE=alphapca56 ;; ++ EV6) UNAME_MACHINE=alphaev6 ;; ++ EV67) UNAME_MACHINE=alphaev67 ;; ++ EV68*) UNAME_MACHINE=alphaev68 ;; ++ esac ++ objdump --private-headers /bin/sh | grep -q ld.so.1 ++ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ arc:Linux:*:* | arceb:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; + arm*:Linux:*:*) + eval $set_cc_for_build + if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_EABI__ + then +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + else +- echo ${UNAME_MACHINE}-unknown-linux-gnueabi ++ if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ ++ | grep -q __ARM_PCS_VFP ++ then ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi ++ else ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf ++ fi + fi + exit ;; + avr32*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + cris:Linux:*:*) +- echo cris-axis-linux-gnu ++ echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + crisv32:Linux:*:*) +- echo crisv32-axis-linux-gnu ++ echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + frv:Linux:*:*) +- echo frv-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ hexagon:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ i*86:Linux:*:*) ++ echo ${UNAME_MACHINE}-pc-linux-${LIBC} + exit ;; + ia64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m32r*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m68*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; +- mips:Linux:*:*) +- eval $set_cc_for_build +- sed 's/^ //' << EOF >$dummy.c +- #undef CPU +- #undef mips +- #undef mipsel +- #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) +- CPU=mipsel +- #else +- #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) +- CPU=mips +- #else +- CPU= +- #endif +- #endif +-EOF +- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' +- /^CPU/{ +- s: ::g +- p +- }'`" +- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } +- ;; +- mips64:Linux:*:*) ++ mips:Linux:*:* | mips64:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU +- #undef mips64 +- #undef mips64el ++ #undef ${UNAME_MACHINE} ++ #undef ${UNAME_MACHINE}el + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) +- CPU=mips64el ++ CPU=${UNAME_MACHINE}el + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) +- CPU=mips64 ++ CPU=${UNAME_MACHINE} + #else + CPU= + #endif + #endif + EOF +- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' +- /^CPU/{ +- s: ::g +- p +- }'`" +- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ++ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` ++ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } + ;; +- or32:Linux:*:*) +- echo or32-unknown-linux-gnu ++ openrisc*:Linux:*:*) ++ echo or1k-unknown-linux-${LIBC} + exit ;; +- ppc:Linux:*:*) +- echo powerpc-unknown-linux-gnu ++ or32:Linux:*:* | or1k*:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; +- ppc64:Linux:*:*) +- echo powerpc64-unknown-linux-gnu ++ padre:Linux:*:*) ++ echo sparc-unknown-linux-${LIBC} + exit ;; +- alpha:Linux:*:*) +- case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in +- EV5) UNAME_MACHINE=alphaev5 ;; +- EV56) UNAME_MACHINE=alphaev56 ;; +- PCA56) UNAME_MACHINE=alphapca56 ;; +- PCA57) UNAME_MACHINE=alphapca56 ;; +- EV6) UNAME_MACHINE=alphaev6 ;; +- EV67) UNAME_MACHINE=alphaev67 ;; +- EV68*) UNAME_MACHINE=alphaev68 ;; +- esac +- objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null +- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi +- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} ++ parisc64:Linux:*:* | hppa64:Linux:*:*) ++ echo hppa64-unknown-linux-${LIBC} + exit ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in +- PA7*) echo hppa1.1-unknown-linux-gnu ;; +- PA8*) echo hppa2.0-unknown-linux-gnu ;; +- *) echo hppa-unknown-linux-gnu ;; ++ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; ++ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; ++ *) echo hppa-unknown-linux-${LIBC} ;; + esac + exit ;; +- parisc64:Linux:*:* | hppa64:Linux:*:*) +- echo hppa64-unknown-linux-gnu ++ ppc64:Linux:*:*) ++ echo powerpc64-unknown-linux-${LIBC} ++ exit ;; ++ ppc:Linux:*:*) ++ echo powerpc-unknown-linux-${LIBC} ++ exit ;; ++ ppc64le:Linux:*:*) ++ echo powerpc64le-unknown-linux-${LIBC} ++ exit ;; ++ ppcle:Linux:*:*) ++ echo powerpcle-unknown-linux-${LIBC} + exit ;; + s390:Linux:*:* | s390x:Linux:*:*) +- echo ${UNAME_MACHINE}-ibm-linux ++ echo ${UNAME_MACHINE}-ibm-linux-${LIBC} + exit ;; + sh64*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sh*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sparc:Linux:*:* | sparc64:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} ++ exit ;; ++ tile*:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + vax:Linux:*:*) +- echo ${UNAME_MACHINE}-dec-linux-gnu ++ echo ${UNAME_MACHINE}-dec-linux-${LIBC} + exit ;; + x86_64:Linux:*:*) +- echo x86_64-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + xtensa*:Linux:*:*) +- echo ${UNAME_MACHINE}-unknown-linux-gnu ++ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; +- i*86:Linux:*:*) +- # The BFD linker knows what the default object file format is, so +- # first see if it will tell us. cd to the root directory to prevent +- # problems with other programs or directories called `ld' in the path. +- # Set LC_ALL=C to ensure ld outputs messages in English. +- ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ +- | sed -ne '/supported targets:/!d +- s/[ ][ ]*/ /g +- s/.*supported targets: *// +- s/ .*// +- p'` +- case "$ld_supported_targets" in +- elf32-i386) +- TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" +- ;; +- a.out-i386-linux) +- echo "${UNAME_MACHINE}-pc-linux-gnuaout" +- exit ;; +- coff-i386) +- echo "${UNAME_MACHINE}-pc-linux-gnucoff" +- exit ;; +- "") +- # Either a pre-BFD a.out linker (linux-gnuoldld) or +- # one that does not give us useful --help. +- echo "${UNAME_MACHINE}-pc-linux-gnuoldld" +- exit ;; +- esac +- # Determine whether the default compiler is a.out or elf +- eval $set_cc_for_build +- sed 's/^ //' << EOF >$dummy.c +- #include +- #ifdef __ELF__ +- # ifdef __GLIBC__ +- # if __GLIBC__ >= 2 +- LIBC=gnu +- # else +- LIBC=gnulibc1 +- # endif +- # else +- LIBC=gnulibc1 +- # endif +- #else +- #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) +- LIBC=gnu +- #else +- LIBC=gnuaout +- #endif +- #endif +- #ifdef __dietlibc__ +- LIBC=dietlibc +- #endif +-EOF +- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' +- /^LIBC/{ +- s: ::g +- p +- }'`" +- test x"${LIBC}" != x && { +- echo "${UNAME_MACHINE}-pc-linux-${LIBC}" +- exit +- } +- test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; } +- ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. + # earlier versions are messed up and put the nodename in both +@@ -1037,11 +1032,11 @@ + echo i386-sequent-sysv4 + exit ;; + i*86:UNIX_SV:4.2MP:2.*) +- # Unixware is an offshoot of SVR4, but it has its own version +- # number series starting with 2... +- # I am not positive that other SVR4 systems won't match this, ++ # Unixware is an offshoot of SVR4, but it has its own version ++ # number series starting with 2... ++ # I am not positive that other SVR4 systems won't match this, + # I just have to hope. -- rms. +- # Use sysv4.2uw... so that sysv4* matches it. ++ # Use sysv4.2uw... so that sysv4* matches it. + echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} + exit ;; + i*86:OS/2:*:*) +@@ -1058,7 +1053,7 @@ + i*86:syllable:*:*) + echo ${UNAME_MACHINE}-pc-syllable + exit ;; +- i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) ++ i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*) + echo i386-unknown-lynxos${UNAME_RELEASE} + exit ;; + i*86:*DOS:*:*) +@@ -1073,7 +1068,7 @@ + fi + exit ;; + i*86:*:5:[678]*) +- # UnixWare 7.x, OpenUNIX and OpenServer 6. ++ # UnixWare 7.x, OpenUNIX and OpenServer 6. + case `/bin/uname -X | grep "^Machine"` in + *486*) UNAME_MACHINE=i486 ;; + *Pentium) UNAME_MACHINE=i586 ;; +@@ -1101,10 +1096,13 @@ + exit ;; + pc:*:*:*) + # Left here for compatibility: +- # uname -m prints for DJGPP always 'pc', but it prints nothing about +- # the processor, so we play safe by assuming i386. +- echo i386-pc-msdosdjgpp +- exit ;; ++ # uname -m prints for DJGPP always 'pc', but it prints nothing about ++ # the processor, so we play safe by assuming i586. ++ # Note: whatever this is, it MUST be the same as what config.sub ++ # prints for the "djgpp" host, or else GDB configury will decide that ++ # this is a cross-build. ++ echo i586-pc-msdosdjgpp ++ exit ;; + Intel:Mach:3*:*) + echo i386-pc-mach3 + exit ;; +@@ -1139,8 +1137,18 @@ + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; + 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) +- /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ +- && { echo i486-ncr-sysv4; exit; } ;; ++ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ ++ && { echo i486-ncr-sysv4; exit; } ;; ++ NCR*:*:4.2:* | MPRAS*:*:4.2:*) ++ OS_REL='.3' ++ test -r /etc/.relid \ ++ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` ++ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ ++ && { echo i486-ncr-sysv4.3${OS_REL}; exit; } ++ /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ ++ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ++ /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \ ++ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; + m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) + echo m68k-unknown-lynxos${UNAME_RELEASE} + exit ;; +@@ -1153,7 +1161,7 @@ + rs6000:LynxOS:2.*:*) + echo rs6000-unknown-lynxos${UNAME_RELEASE} + exit ;; +- PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) ++ PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*) + echo powerpc-unknown-lynxos${UNAME_RELEASE} + exit ;; + SM[BE]S:UNIX_SV:*:*) +@@ -1173,10 +1181,10 @@ + echo ns32k-sni-sysv + fi + exit ;; +- PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort +- # says +- echo i586-unisys-sysv4 +- exit ;; ++ PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort ++ # says ++ echo i586-unisys-sysv4 ++ exit ;; + *:UNIX_System_V:4*:FTX*) + # From Gerald Hewes . + # How about differentiating between stratus architectures? -djm +@@ -1202,11 +1210,11 @@ + exit ;; + R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) + if [ -d /usr/nec ]; then +- echo mips-nec-sysv${UNAME_RELEASE} ++ echo mips-nec-sysv${UNAME_RELEASE} + else +- echo mips-unknown-sysv${UNAME_RELEASE} ++ echo mips-unknown-sysv${UNAME_RELEASE} + fi +- exit ;; ++ exit ;; + BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. + echo powerpc-be-beos + exit ;; +@@ -1219,6 +1227,9 @@ + BePC:Haiku:*:*) # Haiku running on Intel PC compatible. + echo i586-pc-haiku + exit ;; ++ x86_64:Haiku:*:*) ++ echo x86_64-unknown-haiku ++ exit ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux${UNAME_RELEASE} + exit ;; +@@ -1245,9 +1256,31 @@ + exit ;; + *:Darwin:*:*) + UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown +- case $UNAME_PROCESSOR in +- unknown) UNAME_PROCESSOR=powerpc ;; +- esac ++ eval $set_cc_for_build ++ if test "$UNAME_PROCESSOR" = unknown ; then ++ UNAME_PROCESSOR=powerpc ++ fi ++ if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then ++ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then ++ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ ++ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ ++ grep IS_64BIT_ARCH >/dev/null ++ then ++ case $UNAME_PROCESSOR in ++ i386) UNAME_PROCESSOR=x86_64 ;; ++ powerpc) UNAME_PROCESSOR=powerpc64 ;; ++ esac ++ fi ++ fi ++ elif test "$UNAME_PROCESSOR" = i386 ; then ++ # Avoid executing cc on OS X 10.9, as it ships with a stub ++ # that puts up a graphical alert prompting to install ++ # developer tools. Any system running Mac OS X 10.7 or ++ # later (Darwin 11 and later) is required to have a 64-bit ++ # processor. This is not true of the ARM version of Darwin ++ # that Apple uses in portable devices. ++ UNAME_PROCESSOR=x86_64 ++ fi + echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} + exit ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) +@@ -1261,7 +1294,10 @@ + *:QNX:*:4*) + echo i386-pc-qnx + exit ;; +- NSE-?:NONSTOP_KERNEL:*:*) ++ NEO-?:NONSTOP_KERNEL:*:*) ++ echo neo-tandem-nsk${UNAME_RELEASE} ++ exit ;; ++ NSE-*:NONSTOP_KERNEL:*:*) + echo nse-tandem-nsk${UNAME_RELEASE} + exit ;; + NSR-?:NONSTOP_KERNEL:*:*) +@@ -1306,13 +1342,13 @@ + echo pdp10-unknown-its + exit ;; + SEI:*:*:SEIUX) +- echo mips-sei-seiux${UNAME_RELEASE} ++ echo mips-sei-seiux${UNAME_RELEASE} + exit ;; + *:DragonFly:*:*) + echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` + exit ;; + *:*VMS:*:*) +- UNAME_MACHINE=`(uname -p) 2>/dev/null` ++ UNAME_MACHINE=`(uname -p) 2>/dev/null` + case "${UNAME_MACHINE}" in + A*) echo alpha-dec-vms ; exit ;; + I*) echo ia64-dec-vms ; exit ;; +@@ -1327,158 +1363,13 @@ + i*86:rdos:*:*) + echo ${UNAME_MACHINE}-pc-rdos + exit ;; +-esac +- +-#echo '(No uname command or uname output not recognized.)' 1>&2 +-#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 +- +-eval $set_cc_for_build +-cat >$dummy.c < +-# include +-#endif +-main () +-{ +-#if defined (sony) +-#if defined (MIPSEB) +- /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, +- I don't know.... */ +- printf ("mips-sony-bsd\n"); exit (0); +-#else +-#include +- printf ("m68k-sony-newsos%s\n", +-#ifdef NEWSOS4 +- "4" +-#else +- "" +-#endif +- ); exit (0); +-#endif +-#endif +- +-#if defined (__arm) && defined (__acorn) && defined (__unix) +- printf ("arm-acorn-riscix\n"); exit (0); +-#endif +- +-#if defined (hp300) && !defined (hpux) +- printf ("m68k-hp-bsd\n"); exit (0); +-#endif +- +-#if defined (NeXT) +-#if !defined (__ARCHITECTURE__) +-#define __ARCHITECTURE__ "m68k" +-#endif +- int version; +- version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; +- if (version < 4) +- printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); +- else +- printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); +- exit (0); +-#endif +- +-#if defined (MULTIMAX) || defined (n16) +-#if defined (UMAXV) +- printf ("ns32k-encore-sysv\n"); exit (0); +-#else +-#if defined (CMU) +- printf ("ns32k-encore-mach\n"); exit (0); +-#else +- printf ("ns32k-encore-bsd\n"); exit (0); +-#endif +-#endif +-#endif +- +-#if defined (__386BSD__) +- printf ("i386-pc-bsd\n"); exit (0); +-#endif +- +-#if defined (sequent) +-#if defined (i386) +- printf ("i386-sequent-dynix\n"); exit (0); +-#endif +-#if defined (ns32000) +- printf ("ns32k-sequent-dynix\n"); exit (0); +-#endif +-#endif +- +-#if defined (_SEQUENT_) +- struct utsname un; +- +- uname(&un); +- +- if (strncmp(un.version, "V2", 2) == 0) { +- printf ("i386-sequent-ptx2\n"); exit (0); +- } +- if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ +- printf ("i386-sequent-ptx1\n"); exit (0); +- } +- printf ("i386-sequent-ptx\n"); exit (0); +- +-#endif +- +-#if defined (vax) +-# if !defined (ultrix) +-# include +-# if defined (BSD) +-# if BSD == 43 +- printf ("vax-dec-bsd4.3\n"); exit (0); +-# else +-# if BSD == 199006 +- printf ("vax-dec-bsd4.3reno\n"); exit (0); +-# else +- printf ("vax-dec-bsd\n"); exit (0); +-# endif +-# endif +-# else +- printf ("vax-dec-bsd\n"); exit (0); +-# endif +-# else +- printf ("vax-dec-ultrix\n"); exit (0); +-# endif +-#endif +- +-#if defined (alliant) && defined (i860) +- printf ("i860-alliant-bsd\n"); exit (0); +-#endif +- +- exit (1); +-} +-EOF +- +-$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && +- { echo "$SYSTEM_NAME"; exit; } +- +-# Apollos put the system type in the environment. +- +-test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } +- +-# Convex versions that predate uname can use getsysinfo(1) +- +-if [ -x /usr/convex/getsysinfo ] +-then +- case `getsysinfo -f cpu_type` in +- c1*) +- echo c1-convex-bsd ++ i*86:AROS:*:*) ++ echo ${UNAME_MACHINE}-pc-aros + exit ;; +- c2*) +- if getsysinfo -f scalar_acc +- then echo c32-convex-bsd +- else echo c2-convex-bsd +- fi ++ x86_64:VMkernel:*:*) ++ echo ${UNAME_MACHINE}-unknown-esx + exit ;; +- c34*) +- echo c34-convex-bsd +- exit ;; +- c38*) +- echo c38-convex-bsd +- exit ;; +- c4*) +- echo c4-convex-bsd +- exit ;; +- esac +-fi ++esac + + cat >&2 <. + # + # As a special exception to the GNU General Public License, if you + # distribute this file as part of a program that contains a + # configuration script generated by Autoconf, you may include it under +-# the same distribution terms that you use for the rest of that program. ++# the same distribution terms that you use for the rest of that ++# program. This Exception is an additional permission under section 7 ++# of the GNU General Public License, version 3 ("GPLv3"). + + +-# Please send patches to . Submit a context +-# diff and a properly formatted ChangeLog entry. ++# Please send patches with a ChangeLog entry to config-patches@gnu.org. + # + # Configuration subroutine to validate and canonicalize a configuration type. + # Supply the specified configuration type as an argument. + # If it is invalid, we print an error message on stderr and exit with code 1. + # Otherwise, we print the canonical config type on stdout and succeed. + ++# You can get the latest version of this script from: ++# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD ++ + # This file is supposed to be the same for all GNU packages + # and recognize all the CPU types, system types and aliases + # that are meaningful with *any* GNU software. +@@ -72,8 +68,7 @@ + version="\ + GNU config.sub ($timestamp) + +-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, +-2002, 2003, 2004, 2005, 2006, 2007, 2008,2009 Free Software Foundation, Inc. ++Copyright 1992-2014 Free Software Foundation, Inc. + + This is free software; see the source for copying conditions. There is NO + warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." +@@ -120,12 +115,18 @@ + # Here we must recognize all the valid KERNEL-OS combinations. + maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` + case $maybe_os in +- nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ +- uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \ ++ nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ ++ linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ ++ knetbsd*-gnu* | netbsd*-gnu* | \ ++ kopensolaris*-gnu* | \ + storm-chaos* | os2-emx* | rtmk-nova*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; ++ android-linux) ++ os=-linux-android ++ basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown ++ ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] +@@ -148,10 +149,13 @@ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ +- -apple | -axis | -knuth | -cray) ++ -apple | -axis | -knuth | -cray | -microblaze*) + os= + basic_machine=$1 + ;; ++ -bluegene*) ++ os=-cnk ++ ;; + -sim | -cisco | -oki | -wec | -winbond) + os= + basic_machine=$1 +@@ -166,10 +170,10 @@ + os=-chorusos + basic_machine=$1 + ;; +- -chorusrdb) +- os=-chorusrdb ++ -chorusrdb) ++ os=-chorusrdb + basic_machine=$1 +- ;; ++ ;; + -hiux*) + os=-hiuxwe2 + ;; +@@ -214,6 +218,12 @@ + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; ++ -lynx*178) ++ os=-lynxos178 ++ ;; ++ -lynx*5) ++ os=-lynxos5 ++ ;; + -lynx*) + os=-lynxos + ;; +@@ -238,19 +248,28 @@ + # Some are omitted here because they have special meanings below. + 1750a | 580 \ + | a29k \ ++ | aarch64 | aarch64_be \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ ++ | arc | arceb \ ++ | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \ ++ | avr | avr32 \ ++ | be32 | be64 \ + | bfin \ +- | c4x | clipper \ ++ | c4x | c8051 | clipper \ + | d10v | d30v | dlx | dsp16xx \ ++ | epiphany \ + | fido | fr30 | frv \ + | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ ++ | hexagon \ + | i370 | i860 | i960 | ia64 \ + | ip2k | iq2000 \ ++ | k1om \ ++ | le32 | le64 \ ++ | lm32 \ + | m32c | m32r | m32rle | m68000 | m68k | m88k \ +- | maxq | mb | microblaze | mcore | mep | metag \ ++ | maxq | mb | microblaze | microblazeel | mcore | mep | metag \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64el \ +@@ -264,35 +283,50 @@ + | mips64vr5900 | mips64vr5900el \ + | mipsisa32 | mipsisa32el \ + | mipsisa32r2 | mipsisa32r2el \ ++ | mipsisa32r6 | mipsisa32r6el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64r2 | mipsisa64r2el \ ++ | mipsisa64r6 | mipsisa64r6el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ ++ | mipsr5900 | mipsr5900el \ + | mipstx39 | mipstx39el \ + | mn10200 | mn10300 \ ++ | moxie \ + | mt \ + | msp430 \ +- | nios | nios2 \ ++ | nds32 | nds32le | nds32be \ ++ | nios | nios2 | nios2eb | nios2el \ + | ns16k | ns32k \ +- | or32 \ ++ | open8 | or1k | or1knd | or32 \ + | pdp10 | pdp11 | pj | pjl \ +- | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ ++ | powerpc | powerpc64 | powerpc64le | powerpcle \ + | pyramid \ ++ | rl78 | rx \ + | score \ +- | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ ++ | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ + | sh64 | sh64le \ + | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ + | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ +- | spu | strongarm \ +- | tahoe | thumb | tic4x | tic80 | tron \ +- | v850 | v850e \ ++ | spu \ ++ | tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ ++ | ubicom32 \ ++ | v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \ + | we32k \ +- | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ +- | z8k) ++ | x86 | xc16x | xstormy16 | xtensa \ ++ | z8k | z80) + basic_machine=$basic_machine-unknown + ;; +- m6811 | m68hc11 | m6812 | m68hc12) +- # Motorola 68HC11/12. ++ c54x) ++ basic_machine=tic54x-unknown ++ ;; ++ c55x) ++ basic_machine=tic55x-unknown ++ ;; ++ c6x) ++ basic_machine=tic6x-unknown ++ ;; ++ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip) + basic_machine=$basic_machine-unknown + os=-none + ;; +@@ -302,6 +336,21 @@ + basic_machine=mt-unknown + ;; + ++ strongarm | thumb | xscale) ++ basic_machine=arm-unknown ++ ;; ++ xgate) ++ basic_machine=$basic_machine-unknown ++ os=-none ++ ;; ++ xscaleeb) ++ basic_machine=armeb-unknown ++ ;; ++ ++ xscaleel) ++ basic_machine=armel-unknown ++ ;; ++ + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. +@@ -316,24 +365,31 @@ + # Recognize the basic CPU types with company name. + 580-* \ + | a29k-* \ ++ | aarch64-* | aarch64_be-* \ + | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ + | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ +- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ ++ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \ + | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ + | avr-* | avr32-* \ ++ | be32-* | be64-* \ + | bfin-* | bs2000-* \ +- | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ +- | clipper-* | craynv-* | cydra-* \ ++ | c[123]* | c30-* | [cjt]90-* | c4x-* \ ++ | c8051-* | clipper-* | craynv-* | cydra-* \ + | d10v-* | d30v-* | dlx-* \ + | elxsi-* \ + | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ + | h8300-* | h8500-* \ + | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ ++ | hexagon-* \ + | i*86-* | i860-* | i960-* | ia64-* \ + | ip2k-* | iq2000-* \ ++ | k1om-* \ ++ | le32-* | le64-* \ ++ | lm32-* \ + | m32c-* | m32r-* | m32rle-* \ + | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ + | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \ ++ | microblaze-* | microblazeel-* \ + | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ + | mips16-* \ + | mips64-* | mips64el-* \ +@@ -347,35 +403,44 @@ + | mips64vr5900-* | mips64vr5900el-* \ + | mipsisa32-* | mipsisa32el-* \ + | mipsisa32r2-* | mipsisa32r2el-* \ ++ | mipsisa32r6-* | mipsisa32r6el-* \ + | mipsisa64-* | mipsisa64el-* \ + | mipsisa64r2-* | mipsisa64r2el-* \ ++ | mipsisa64r6-* | mipsisa64r6el-* \ + | mipsisa64sb1-* | mipsisa64sb1el-* \ + | mipsisa64sr71k-* | mipsisa64sr71kel-* \ ++ | mipsr5900-* | mipsr5900el-* \ + | mipstx39-* | mipstx39el-* \ + | mmix-* \ + | mt-* \ + | msp430-* \ +- | nios-* | nios2-* \ ++ | nds32-* | nds32le-* | nds32be-* \ ++ | nios-* | nios2-* | nios2eb-* | nios2el-* \ + | none-* | np1-* | ns16k-* | ns32k-* \ ++ | open8-* \ ++ | or1k*-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ +- | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ ++ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ + | pyramid-* \ +- | romp-* | rs6000-* \ +- | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ ++ | rl78-* | romp-* | rs6000-* | rx-* \ ++ | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ + | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ + | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ + | sparclite-* \ +- | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \ +- | tahoe-* | thumb-* \ +- | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \ ++ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \ ++ | tahoe-* \ ++ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ ++ | tile*-* \ + | tron-* \ +- | v850-* | v850e-* | vax-* \ ++ | ubicom32-* \ ++ | v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \ ++ | vax-* \ + | we32k-* \ +- | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ ++ | x86-* | x86_64-* | xc16x-* | xps100-* \ + | xstormy16-* | xtensa*-* \ + | ymp-* \ +- | z8k-*) ++ | z8k-* | z80-*) + ;; + # Recognize the basic CPU types without company name, with glob match. + xtensa*) +@@ -397,7 +462,7 @@ + basic_machine=a29k-amd + os=-udi + ;; +- abacus) ++ abacus) + basic_machine=abacus-unknown + ;; + adobe68k) +@@ -443,6 +508,10 @@ + basic_machine=m68k-apollo + os=-bsd + ;; ++ aros) ++ basic_machine=i386-pc ++ os=-aros ++ ;; + aux) + basic_machine=m68k-apple + os=-aux +@@ -459,10 +528,27 @@ + basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'` + os=-linux + ;; ++ bluegene*) ++ basic_machine=powerpc-ibm ++ os=-cnk ++ ;; ++ c54x-*) ++ basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'` ++ ;; ++ c55x-*) ++ basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'` ++ ;; ++ c6x-*) ++ basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'` ++ ;; + c90) + basic_machine=c90-cray + os=-unicos + ;; ++ cegcc) ++ basic_machine=arm-unknown ++ os=-cegcc ++ ;; + convex-c1) + basic_machine=c1-convex + os=-bsd +@@ -491,7 +577,7 @@ + basic_machine=craynv-cray + os=-unicosmp + ;; +- cr16) ++ cr16 | cr16-*) + basic_machine=cr16-unknown + os=-elf + ;; +@@ -530,6 +616,10 @@ + basic_machine=m88k-motorola + os=-sysv3 + ;; ++ dicos) ++ basic_machine=i686-pc ++ os=-dicos ++ ;; + djgpp) + basic_machine=i586-pc + os=-msdosdjgpp +@@ -645,7 +735,6 @@ + i370-ibm* | ibm*) + basic_machine=i370-ibm + ;; +-# I'm not sure what "Sysv32" means. Should this be sysv3.2? + i*86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 +@@ -703,8 +792,15 @@ + basic_machine=ns32k-utek + os=-sysv + ;; ++ microblaze*) ++ basic_machine=microblaze-xilinx ++ ;; ++ mingw64) ++ basic_machine=x86_64-pc ++ os=-mingw64 ++ ;; + mingw32) +- basic_machine=i386-pc ++ basic_machine=i686-pc + os=-mingw32 + ;; + mingw32ce) +@@ -739,10 +835,18 @@ + ms1-*) + basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` + ;; ++ msys) ++ basic_machine=i686-pc ++ os=-msys ++ ;; + mvs) + basic_machine=i370-ibm + os=-mvs + ;; ++ nacl) ++ basic_machine=le32-unknown ++ os=-nacl ++ ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 +@@ -807,6 +911,9 @@ + np1) + basic_machine=np1-gould + ;; ++ neo-tandem) ++ basic_machine=neo-tandem ++ ;; + nse-tandem) + basic_machine=nse-tandem + ;; +@@ -892,9 +999,10 @@ + ;; + power) basic_machine=power-ibm + ;; +- ppc) basic_machine=powerpc-unknown ++ ppc | ppcbe) basic_machine=powerpc-unknown + ;; +- ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ++ ppc-* | ppcbe-*) ++ basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle | ppc-le | powerpc-little) + basic_machine=powerpcle-unknown +@@ -919,7 +1027,11 @@ + basic_machine=i586-unknown + os=-pw32 + ;; +- rdos) ++ rdos | rdos64) ++ basic_machine=x86_64-pc ++ os=-rdos ++ ;; ++ rdos32) + basic_machine=i386-pc + os=-rdos + ;; +@@ -988,6 +1100,9 @@ + basic_machine=i860-stratus + os=-sysv4 + ;; ++ strongarm-* | thumb-*) ++ basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'` ++ ;; + sun2) + basic_machine=m68000-sun + ;; +@@ -1044,20 +1159,8 @@ + basic_machine=t90-cray + os=-unicos + ;; +- tic54x | c54x*) +- basic_machine=tic54x-unknown +- os=-coff +- ;; +- tic55x | c55x*) +- basic_machine=tic55x-unknown +- os=-coff +- ;; +- tic6x | c6x*) +- basic_machine=tic6x-unknown +- os=-coff +- ;; + tile*) +- basic_machine=tile-unknown ++ basic_machine=$basic_machine-unknown + os=-linux-gnu + ;; + tx39) +@@ -1127,6 +1230,9 @@ + xps | xps100) + basic_machine=xps100-honeywell + ;; ++ xscale-* | xscalee[bl]-*) ++ basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'` ++ ;; + ymp) + basic_machine=ymp-cray + os=-unicos +@@ -1135,6 +1241,10 @@ + basic_machine=z8k-unknown + os=-sim + ;; ++ z80-*-coff) ++ basic_machine=z80-unknown ++ os=-sim ++ ;; + none) + basic_machine=none-none + os=-none +@@ -1173,7 +1283,7 @@ + we32k) + basic_machine=we32k-att + ;; +- sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele) ++ sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele) + basic_machine=sh-unknown + ;; + sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) +@@ -1220,9 +1330,12 @@ + if [ x"$os" != x"" ] + then + case $os in +- # First match some system type aliases +- # that might get confused with valid system types. ++ # First match some system type aliases ++ # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. ++ -auroraux) ++ os=-auroraux ++ ;; + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; +@@ -1243,21 +1356,23 @@ + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ +- | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ +- | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ ++ | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\ ++ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \ ++ | -sym* | -kopensolaris* | -plan9* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ +- | -aos* \ ++ | -aos* | -aros* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ +- | -openbsd* | -solidbsd* \ ++ | -bitrig* | -openbsd* | -solidbsd* \ + | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ + | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ +- | -chorusos* | -chorusrdb* \ +- | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ +- | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \ ++ | -chorusos* | -chorusrdb* | -cegcc* \ ++ | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ ++ | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ ++ | -linux-newlib* | -linux-musl* | -linux-uclibc* \ + | -uxpv* | -beos* | -mpeix* | -udk* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ +@@ -1265,7 +1380,7 @@ + | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ + | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ + | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ +- | -skyos* | -haiku* | -rdos* | -toppers* | -drops*) ++ | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -qnx*) +@@ -1304,7 +1419,7 @@ + -opened*) + os=-openedition + ;; +- -os400*) ++ -os400*) + os=-os400 + ;; + -wince*) +@@ -1353,7 +1468,7 @@ + -sinix*) + os=-sysv4 + ;; +- -tpf*) ++ -tpf*) + os=-tpf + ;; + -triton*) +@@ -1389,12 +1504,14 @@ + -aros*) + os=-aros + ;; +- -kaos*) +- os=-kaos +- ;; + -zvmoe) + os=-zvmoe + ;; ++ -dicos*) ++ os=-dicos ++ ;; ++ -nacl*) ++ ;; + -none) + ;; + *) +@@ -1417,10 +1534,10 @@ + # system, and we'll never get to this point. + + case $basic_machine in +- score-*) ++ score-*) + os=-elf + ;; +- spu-*) ++ spu-*) + os=-elf + ;; + *-acorn) +@@ -1432,8 +1549,23 @@ + arm*-semi) + os=-aout + ;; +- c4x-* | tic4x-*) +- os=-coff ++ c4x-* | tic4x-*) ++ os=-coff ++ ;; ++ c8051-*) ++ os=-elf ++ ;; ++ hexagon-*) ++ os=-elf ++ ;; ++ tic54x-*) ++ os=-coff ++ ;; ++ tic55x-*) ++ os=-coff ++ ;; ++ tic6x-*) ++ os=-coff + ;; + # This must come before the *-dec entry. + pdp10-*) +@@ -1453,14 +1585,11 @@ + ;; + m68000-sun) + os=-sunos3 +- # This also exists in the configure program, but was not the +- # default. +- # os=-sunos4 + ;; + m68*-cisco) + os=-aout + ;; +- mep-*) ++ mep-*) + os=-elf + ;; + mips*-cisco) +@@ -1487,7 +1616,7 @@ + *-ibm) + os=-aix + ;; +- *-knuth) ++ *-knuth) + os=-mmixware + ;; + *-wec) +@@ -1592,7 +1721,7 @@ + -sunos*) + vendor=sun + ;; +- -aix*) ++ -cnk*|-aix*) + vendor=ibm + ;; + -beos*) +diff -urN gdb-7.5.1-orig/readline/util.c gdb-7.5.1/readline/util.c +--- gdb-7.5.1-orig/readline/util.c 2011-05-11 16:38:39.000000000 -0700 ++++ gdb-7.5.1/readline/util.c 2015-08-18 16:53:44.102940800 -0700 +@@ -389,7 +389,7 @@ + break; + s2++; + } +- while (--count != 0) ++ while (--count != 0); + + return (0); + } diff --git a/Makefile b/Makefile index f6d50392e..4e3c1d400 100644 --- a/Makefile +++ b/Makefile @@ -1,12 +1,14 @@ TOP = $(PWD) TOOLCHAIN = $(TOP)/xtensa-lx106-elf -VENDOR_SDK = 1.4.1 +VENDOR_SDK = 1.5.0 UNZIP = unzip -q -o VENDOR_SDK_ZIP = $(VENDOR_SDK_ZIP_$(VENDOR_SDK)) VENDOR_SDK_DIR = $(VENDOR_SDK_DIR_$(VENDOR_SDK)) +VENDOR_SDK_ZIP_1.5.0 = esp_iot_sdk_v1.5.0_15_11_27.zip +VENDOR_SDK_DIR_1.5.0 = esp_iot_sdk_v1.5.0 VENDOR_SDK_ZIP_1.4.1 = esp_iot_sdk_v1.4.1_pre5_15_10_27.zip VENDOR_SDK_DIR_1.4.1 = esp_iot_sdk_v1.4.1_pre5 VENDOR_SDK_ZIP_1.4.0 = esp_iot_sdk_v1.4.0_15_09_18.zip @@ -78,6 +80,10 @@ esptool: toolchain done @touch $@ +.sdk_patch_1.5.0: + patch -N -d $(VENDOR_SDK_DIR_1.5.0) -p1 < c_types-c99.patch + @touch $@ + .sdk_patch_1.4.1: patch -N -d $(VENDOR_SDK_DIR_1.4.1) -p1 < c_types-c99.patch @touch $@ @@ -213,6 +219,9 @@ $(VENDOR_SDK_DIR)/.dir: $(VENDOR_SDK_ZIP) -mv License $(VENDOR_SDK_DIR) touch $@ +esp_iot_sdk_v1.5.0_15_11_27.zip: + wget --content-disposition "http://bbs.espressif.com/download/file.php?id=989" + esp_iot_sdk_v1.4.1_pre5_15_10_27.zip: wget --content-disposition "http://bbs.espressif.com/download/file.php?id=917" @@ -298,6 +307,8 @@ _toolchain: sed -r -i.org s%CT_PREFIX_DIR=.*%CT_PREFIX_DIR="$(TOOLCHAIN)"% .config sed -r -i s%CT_INSTALL_DIR_RO=y%"#"CT_INSTALL_DIR_RO=y% .config cat ../crosstool-config-overrides >> .config + rm -f local-patches/gdb/7.5.1/* + cp ../0000-gdb-7.5.1-sysprogs.patch local-patches/gdb/7.5.1 ./ct-ng build From be1c7576ea5a7e5cc7239a2e0c5854ca58452c61 Mon Sep 17 00:00:00 2001 From: rojer Date: Mon, 22 Feb 2016 13:46:41 +0000 Subject: [PATCH 06/10] SDK 1.5.2 --- Makefile | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4e3c1d400..acaa2fb97 100644 --- a/Makefile +++ b/Makefile @@ -1,12 +1,14 @@ TOP = $(PWD) TOOLCHAIN = $(TOP)/xtensa-lx106-elf -VENDOR_SDK = 1.5.0 +VENDOR_SDK = 1.5.2 UNZIP = unzip -q -o VENDOR_SDK_ZIP = $(VENDOR_SDK_ZIP_$(VENDOR_SDK)) VENDOR_SDK_DIR = $(VENDOR_SDK_DIR_$(VENDOR_SDK)) +VENDOR_SDK_ZIP_1.5.2 = ESP8266_NONOS_SDK_V1.5.2_16_01_29.zip +VENDOR_SDK_DIR_1.5.2 = esp_iot_sdk_v1.5.2 VENDOR_SDK_ZIP_1.5.0 = esp_iot_sdk_v1.5.0_15_11_27.zip VENDOR_SDK_DIR_1.5.0 = esp_iot_sdk_v1.5.0 VENDOR_SDK_ZIP_1.4.1 = esp_iot_sdk_v1.4.1_pre5_15_10_27.zip @@ -80,6 +82,11 @@ esptool: toolchain done @touch $@ +.sdk_patch_1.5.2: + echo -e "#undef ESP_SDK_VERSION\n#define ESP_SDK_VERSION 010502" >>$(VENDOR_SDK_DIR)/include/esp_sdk_ver.h + patch -N -d $(VENDOR_SDK_DIR_1.5.2) -p1 < c_types-c99.patch + @touch $@ + .sdk_patch_1.5.0: patch -N -d $(VENDOR_SDK_DIR_1.5.0) -p1 < c_types-c99.patch @touch $@ @@ -219,6 +226,9 @@ $(VENDOR_SDK_DIR)/.dir: $(VENDOR_SDK_ZIP) -mv License $(VENDOR_SDK_DIR) touch $@ +ESP8266_NONOS_SDK_V1.5.2_16_01_29.zip: + wget --content-disposition "http://bbs.espressif.com/download/file.php?id=1079" + esp_iot_sdk_v1.5.0_15_11_27.zip: wget --content-disposition "http://bbs.espressif.com/download/file.php?id=989" From c18ea05dfb90d4a15c6517a1bfeda3892f7e25dd Mon Sep 17 00:00:00 2001 From: rojer Date: Fri, 8 Jul 2016 11:28:23 +0100 Subject: [PATCH 07/10] Enable long long, float and C99 formats in Newlib In other words, %ll, %f and %z. --- crosstool-config-overrides | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/crosstool-config-overrides b/crosstool-config-overrides index a021795d3..f65cdce83 100644 --- a/crosstool-config-overrides +++ b/crosstool-config-overrides @@ -2,4 +2,6 @@ # by default don't install static libs for all required dependencies #CT_STATIC_TOOLCHAIN=y CT_LIBC_NEWLIB_ENABLE_TARGET_OPTSPACE=y - +CT_LIBC_NEWLIB_IO_LL=y +CT_LIBC_NEWLIB_IO_FLOAT=y +CT_LIBC_NEWLIB_IO_C99FMT=y From a730696c913dc420489b3c723581cd6d72161c3d Mon Sep 17 00:00:00 2001 From: rojer Date: Wed, 10 Aug 2016 00:39:27 +0100 Subject: [PATCH 08/10] Update to new Crosstool-NG, SDK 2.0.0, -mforce-l32 --- .gitmodules | 4 +- 0000-gdb-7.5.1-sysprogs.patch | 30286 -------------------------------- 1000-mforce-l32.patch | 253 + Makefile | 16 +- c_types-c99_sdk_2.patch | 34 + crosstool-NG | 2 +- esptool | 2 +- lx106-hal | 2 +- 8 files changed, 305 insertions(+), 30294 deletions(-) delete mode 100644 0000-gdb-7.5.1-sysprogs.patch create mode 100644 1000-mforce-l32.patch create mode 100644 c_types-c99_sdk_2.patch diff --git a/.gitmodules b/.gitmodules index 154c825bb..764ec1cad 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,10 +1,10 @@ [submodule "crosstool-NG"] path = crosstool-NG url = https://github.com/jcmvbkbc/crosstool-NG - branch = lx106-g++ + branch = xtensa-1.22.x [submodule "lx106-hal"] path = lx106-hal url = https://github.com/tommie/lx106-hal [submodule "esptool"] path = esptool - url = https://github.com/pfalcon/esptool + url = https://github.com/themadinventor/esptool diff --git a/0000-gdb-7.5.1-sysprogs.patch b/0000-gdb-7.5.1-sysprogs.patch deleted file mode 100644 index e25660914..000000000 --- a/0000-gdb-7.5.1-sysprogs.patch +++ /dev/null @@ -1,30286 +0,0 @@ -diff -urN gdb-7.5.1-orig/bfd/xtensa-modules.c gdb-7.5.1/bfd/xtensa-modules.c ---- gdb-7.5.1-orig/bfd/xtensa-modules.c 2010-05-28 11:10:45.000000000 -0700 -+++ gdb-7.5.1/bfd/xtensa-modules.c 2015-08-23 19:30:39.181635000 -0700 -@@ -1,22 +1,25 @@ - /* Xtensa configuration-specific ISA information. -- Copyright 2003, 2004, 2005 Free Software Foundation, Inc. - -- This file is part of BFD, the Binary File Descriptor library. -+ Copyright (c) 2003-2010 Tensilica Inc. - -- This program is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License as -- published by the Free Software Foundation; either version 2 of the -- License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -- 02110-1301, USA. */ -+ Permission is hereby granted, free of charge, to any person obtaining -+ a copy of this software and associated documentation files (the -+ "Software"), to deal in the Software without restriction, including -+ without limitation the rights to use, copy, modify, merge, publish, -+ distribute, sublicense, and/or sell copies of the Software, and to -+ permit persons to whom the Software is furnished to do so, subject to -+ the following conditions: -+ -+ The above copyright notice and this permission notice shall be included -+ in all copies or substantial portions of the Software. -+ -+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - #include "ansidecl.h" - #include -@@ -26,17 +29,6 @@ - /* Sysregs. */ - - static xtensa_sysreg_internal sysregs[] = { -- { "LBEG", 0, 0 }, -- { "LEND", 1, 0 }, -- { "LCOUNT", 2, 0 }, -- { "BR", 4, 0 }, -- { "ACCLO", 16, 0 }, -- { "ACCHI", 17, 0 }, -- { "M0", 32, 0 }, -- { "M1", 33, 0 }, -- { "M2", 34, 0 }, -- { "M3", 35, 0 }, -- { "PTEVADDR", 83, 0 }, - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "176", 176, 0 }, -@@ -47,254 +39,112 @@ - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, -- { "CCOMPARE1", 241, 0 }, -- { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, -- { "EPC4", 180, 0 }, -- { "EPC5", 181, 0 }, -- { "EPC6", 182, 0 }, -- { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, -- { "EXCSAVE4", 212, 0 }, -- { "EXCSAVE5", 213, 0 }, -- { "EXCSAVE6", 214, 0 }, -- { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, -- { "EPS4", 196, 0 }, -- { "EPS5", 197, 0 }, -- { "EPS6", 198, 0 }, -- { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, -- { "WINDOWBASE", 72, 0 }, -- { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "LITBASE", 5, 0 }, - { "PS", 230, 0 }, -- { "MISC0", 244, 0 }, -- { "MISC1", 245, 0 }, -- { "MISC2", 246, 0 }, -- { "MISC3", 247, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, -- { "DBREAKA1", 145, 0 }, -- { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, -- { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, -- { "DEBUGCAUSE", 233, 0 }, -- { "RASID", 90, 0 }, -- { "ITLBCFG", 91, 0 }, -- { "DTLBCFG", 92, 0 }, -- { "CPENABLE", 224, 0 }, -- { "SCOMPARE1", 12, 0 }, -- { "THREADPTR", 231, 1 }, -- { "FCR", 232, 1 }, -- { "FSR", 233, 1 } -+ { "DEBUGCAUSE", 233, 0 } - }; - --#define NUM_SYSREGS 74 --#define MAX_SPECIAL_REG 247 --#define MAX_USER_REG 233 -+#define NUM_SYSREGS 32 -+#define MAX_SPECIAL_REG 240 -+#define MAX_USER_REG 0 - - - /* Processor states. */ - - static xtensa_state_internal states[] = { -- { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, -- { "INTERRUPT", 32, 0 }, -+ { "INTERRUPT", 15, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, -- { "VECBASE", 22, 0 }, -+ { "VECBASE", 25, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, -- { "EPC4", 32, 0 }, -- { "EPC5", 32, 0 }, -- { "EPC6", 32, 0 }, -- { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, -- { "EXCSAVE4", 32, 0 }, -- { "EXCSAVE5", 32, 0 }, -- { "EXCSAVE6", 32, 0 }, -- { "EXCSAVE7", 32, 0 }, -- { "EPS2", 15, 0 }, -- { "EPS3", 15, 0 }, -- { "EPS4", 15, 0 }, -- { "EPS5", 15, 0 }, -- { "EPS6", 15, 0 }, -- { "EPS7", 15, 0 }, -+ { "EPS2", 6, 0 }, -+ { "EPS3", 6, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, -- { "PSWOE", 1, 0 }, -- { "PSRING", 2, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, -- { "WindowBase", 4, 0 }, -- { "WindowStart", 16, 0 }, -- { "PSCALLINC", 2, 0 }, -- { "PSOWB", 4, 0 }, -- { "LBEG", 32, 0 }, -- { "LEND", 32, 0 }, - { "SAR", 6, 0 }, -- { "THREADPTR", 32, 0 }, - { "LITBADDR", 20, 0 }, - { "LITBEN", 1, 0 }, -- { "MISC0", 32, 0 }, -- { "MISC1", 32, 0 }, -- { "MISC2", 32, 0 }, -- { "MISC3", 32, 0 }, -- { "ACC", 40, 0 }, - { "InOCDMode", 1, 0 }, -- { "INTENABLE", 32, 0 }, -+ { "INTENABLE", 15, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, -- { "DBREAKA1", 32, 0 }, -- { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, -- { "IBREAKA1", 32, 0 }, -- { "IBREAKENABLE", 2, 0 }, -+ { "IBREAKENABLE", 1, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, -- { "CCOMPARE0", 32, 0 }, -- { "CCOMPARE1", 32, 0 }, -- { "CCOMPARE2", 32, 0 }, -- { "ASID3", 8, 0 }, -- { "ASID2", 8, 0 }, -- { "ASID1", 8, 0 }, -- { "INSTPGSZID4", 2, 0 }, -- { "DATAPGSZID4", 2, 0 }, -- { "PTBASE", 10, 0 }, -- { "CPENABLE", 1, 0 }, -- { "SCOMPARE1", 32, 0 }, -- { "RoundMode", 2, 0 }, -- { "InvalidEnable", 1, 0 }, -- { "DivZeroEnable", 1, 0 }, -- { "OverflowEnable", 1, 0 }, -- { "UnderflowEnable", 1, 0 }, -- { "InexactEnable", 1, 0 }, -- { "InvalidFlag", 1, 0 }, -- { "DivZeroFlag", 1, 0 }, -- { "OverflowFlag", 1, 0 }, -- { "UnderflowFlag", 1, 0 }, -- { "InexactFlag", 1, 0 }, -- { "FPreserved20", 20, 0 }, -- { "FPreserved20a", 20, 0 }, -- { "FPreserved5", 5, 0 }, -- { "FPreserved7", 7, 0 } --}; -- --#define NUM_STATES 89 -- --/* Macros for xtensa_state numbers (for use in iclasses because the -- state numbers are not available when the iclass table is generated). */ -- --#define STATE_LCOUNT 0 --#define STATE_PC 1 --#define STATE_ICOUNT 2 --#define STATE_DDR 3 --#define STATE_INTERRUPT 4 --#define STATE_CCOUNT 5 --#define STATE_XTSYNC 6 --#define STATE_VECBASE 7 --#define STATE_EPC1 8 --#define STATE_EPC2 9 --#define STATE_EPC3 10 --#define STATE_EPC4 11 --#define STATE_EPC5 12 --#define STATE_EPC6 13 --#define STATE_EPC7 14 --#define STATE_EXCSAVE1 15 --#define STATE_EXCSAVE2 16 --#define STATE_EXCSAVE3 17 --#define STATE_EXCSAVE4 18 --#define STATE_EXCSAVE5 19 --#define STATE_EXCSAVE6 20 --#define STATE_EXCSAVE7 21 --#define STATE_EPS2 22 --#define STATE_EPS3 23 --#define STATE_EPS4 24 --#define STATE_EPS5 25 --#define STATE_EPS6 26 --#define STATE_EPS7 27 --#define STATE_EXCCAUSE 28 --#define STATE_PSINTLEVEL 29 --#define STATE_PSUM 30 --#define STATE_PSWOE 31 --#define STATE_PSRING 32 --#define STATE_PSEXCM 33 --#define STATE_DEPC 34 --#define STATE_EXCVADDR 35 --#define STATE_WindowBase 36 --#define STATE_WindowStart 37 --#define STATE_PSCALLINC 38 --#define STATE_PSOWB 39 --#define STATE_LBEG 40 --#define STATE_LEND 41 --#define STATE_SAR 42 --#define STATE_THREADPTR 43 --#define STATE_LITBADDR 44 --#define STATE_LITBEN 45 --#define STATE_MISC0 46 --#define STATE_MISC1 47 --#define STATE_MISC2 48 --#define STATE_MISC3 49 --#define STATE_ACC 50 --#define STATE_InOCDMode 51 --#define STATE_INTENABLE 52 --#define STATE_DBREAKA0 53 --#define STATE_DBREAKC0 54 --#define STATE_DBREAKA1 55 --#define STATE_DBREAKC1 56 --#define STATE_IBREAKA0 57 --#define STATE_IBREAKA1 58 --#define STATE_IBREAKENABLE 59 --#define STATE_ICOUNTLEVEL 60 --#define STATE_DEBUGCAUSE 61 --#define STATE_DBNUM 62 --#define STATE_CCOMPARE0 63 --#define STATE_CCOMPARE1 64 --#define STATE_CCOMPARE2 65 --#define STATE_ASID3 66 --#define STATE_ASID2 67 --#define STATE_ASID1 68 --#define STATE_INSTPGSZID4 69 --#define STATE_DATAPGSZID4 70 --#define STATE_PTBASE 71 --#define STATE_CPENABLE 72 --#define STATE_SCOMPARE1 73 --#define STATE_RoundMode 74 --#define STATE_InvalidEnable 75 --#define STATE_DivZeroEnable 76 --#define STATE_OverflowEnable 77 --#define STATE_UnderflowEnable 78 --#define STATE_InexactEnable 79 --#define STATE_InvalidFlag 80 --#define STATE_DivZeroFlag 81 --#define STATE_OverflowFlag 82 --#define STATE_UnderflowFlag 83 --#define STATE_InexactFlag 84 --#define STATE_FPreserved20 85 --#define STATE_FPreserved20a 86 --#define STATE_FPreserved5 87 --#define STATE_FPreserved7 88 -+ { "CCOMPARE0", 32, 0 } -+}; -+ -+#define NUM_STATES 34 -+ -+enum xtensa_state_id { -+ STATE_PC, -+ STATE_ICOUNT, -+ STATE_DDR, -+ STATE_INTERRUPT, -+ STATE_CCOUNT, -+ STATE_XTSYNC, -+ STATE_VECBASE, -+ STATE_EPC1, -+ STATE_EPC2, -+ STATE_EPC3, -+ STATE_EXCSAVE1, -+ STATE_EXCSAVE2, -+ STATE_EXCSAVE3, -+ STATE_EPS2, -+ STATE_EPS3, -+ STATE_EXCCAUSE, -+ STATE_PSINTLEVEL, -+ STATE_PSUM, -+ STATE_PSEXCM, -+ STATE_DEPC, -+ STATE_EXCVADDR, -+ STATE_SAR, -+ STATE_LITBADDR, -+ STATE_LITBEN, -+ STATE_InOCDMode, -+ STATE_INTENABLE, -+ STATE_DBREAKA0, -+ STATE_DBREAKC0, -+ STATE_IBREAKA0, -+ STATE_IBREAKENABLE, -+ STATE_ICOUNTLEVEL, -+ STATE_DEBUGCAUSE, -+ STATE_DBNUM, -+ STATE_CCOMPARE0 -+}; - - - /* Field definitions. */ -@@ -316,71 +166,71 @@ - } - - static unsigned --Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -+Field_s_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - } - - static unsigned --Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -+Field_r_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_op2_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; - } - - static void --Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); - } - - static unsigned --Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_op1_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; - } - - static void --Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - } - - static unsigned --Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -+Field_op0_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -@@ -388,7 +238,7 @@ - } - - static void --Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -@@ -396,172 +246,166 @@ - } - - static unsigned --Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -+Field_m_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; - } - - static void --Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -+ tie_t = (val << 30) >> 30; -+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - } - - static unsigned --Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -+Field_n_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; - } - - static void --Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -+ tie_t = (val << 30) >> 30; -+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - } - - static unsigned --Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; - } - - static void --Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -+ tie_t = (val << 29) >> 29; -+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - } - - static unsigned --Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -+Field_sr_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 24) >> 28; -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); -+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; - } - - static void --Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 20) >> 20; -- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - } - - static unsigned --Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); -+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; - } - - static void --Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 24) >> 24; -- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - } - - static unsigned --Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); -+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; - } - - static void --Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 24) >> 24; -- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - } - - static unsigned --Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; - } - - static void --Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - } - - static unsigned --Field_s_Slot_inst_get (const xtensa_insnbuf insn) -+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; - } - - static void --Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - } - - static unsigned --Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned -@@ -581,7 +425,7 @@ - } - - static unsigned --Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -@@ -589,7 +433,7 @@ - } - - static void --Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -@@ -597,105 +441,105 @@ - } - - static unsigned --Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; - } - - static void --Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); - } - - static unsigned --Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; - } - - static void --Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ tie_t = (val << 27) >> 31; -+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); - } - - static unsigned --Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; - } - - static void --Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ tie_t = (val << 20) >> 20; -+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); - } - - static unsigned --Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; - } - - static void --Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -- tie_t = (val << 20) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - } - - static unsigned --Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 24) >> 24; -- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -- tie_t = (val << 20) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - } - - static unsigned --Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; - } - - static void --Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 20) >> 20; -- insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); -+ tie_t = (val << 24) >> 24; -+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -+ tie_t = (val << 20) >> 28; -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - } - - static unsigned -@@ -715,247 +559,258 @@ - } - - static unsigned --Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_offset_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); -+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; - } - - static void --Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 16) >> 16; -- insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); -+ tie_t = (val << 14) >> 14; -+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); - } - - static unsigned --Field_m_Slot_inst_get (const xtensa_insnbuf insn) -+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); -+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; - } - - static void --Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc) | (tie_t << 2); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); - } - - static unsigned --Field_n_Slot_inst_get (const xtensa_insnbuf insn) -+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; - } - - static void --Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); - } - - static unsigned --Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_sae_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); -+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 27) >> 31; -+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); - } - - static unsigned --Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -+Field_sal_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); -+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); -+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; - } - - static void --Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 14) >> 14; -- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ tie_t = (val << 27) >> 31; -+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); - } - - static unsigned --Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); -+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 14) >> 14; -- insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 27) >> 31; -+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); - } - - static unsigned --Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; - } - - static void --Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4); - } - - static unsigned --Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -+Field_sas_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); --} -- --static unsigned --Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -- --static void --Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 27) >> 31; -+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4); - } - - static unsigned --Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 24) >> 28; -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; - } - - static void --Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -+Field_st_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; - } - - static void --Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ tie_t = (val << 24) >> 28; -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - } - - static unsigned --Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; - } - - static void --Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ tie_t = (val << 24) >> 28; -+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - } - - static unsigned --Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; - } - - static void --Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - } - - static unsigned --Field_r_Slot_inst_get (const xtensa_insnbuf insn) -+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -@@ -963,7 +818,7 @@ - } - - static void --Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -@@ -971,7 +826,7 @@ - } - - static unsigned --Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -@@ -979,7 +834,7 @@ - } - - static void --Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -@@ -987,7 +842,7 @@ - } - - static unsigned --Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -@@ -995,7 +850,7 @@ - } - - static void --Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -@@ -1003,19832 +858,6491 @@ - } - - static unsigned --Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; - } - - static void --Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - } - - static unsigned --Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) -+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) -+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; - } - - static void --Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) -+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -+ tie_t = (val << 30) >> 30; -+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - } - - static unsigned --Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); -+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; - } - - static void --Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -+ tie_t = (val << 30) >> 30; -+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - } - - static unsigned --Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -+ tie_t = (val << 28) >> 28; -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - } - - static unsigned --Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; - } - - static void --Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -+ tie_t = (val << 29) >> 29; -+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - } - - static unsigned --Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; - } - - static void --Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -+ tie_t = (val << 29) >> 29; -+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - } - - static unsigned --Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); -+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; - } - - static void --Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 27) >> 27; -- insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); -+ tie_t = (val << 31) >> 31; -+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - } - - static unsigned --Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ tie_t = (val << 26) >> 30; -+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - } - - static unsigned --Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ tie_t = (val << 26) >> 30; -+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - } - - static unsigned --Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ tie_t = (val << 25) >> 29; -+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - } - - static unsigned --Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; - } - - static void --Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; - tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ tie_t = (val << 25) >> 29; -+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - } - - static unsigned --Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; - } - - static void --Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -+ tie_t = (val << 17) >> 17; -+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); - } - - static unsigned --Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) -+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) - { - unsigned tie_t = 0; -- tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); -+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; - } - - static void --Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) -+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) - { - uint32 tie_t; -- tie_t = (val << 27) >> 27; -- insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); --} -- --static unsigned --Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); -- return tie_t; -+ tie_t = (val << 14) >> 14; -+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); - } - - static void --Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) -+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, -+ uint32 val ATTRIBUTE_UNUSED) - { -- uint32 tie_t; -- tie_t = (val << 27) >> 27; -- insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); -+ /* Do nothing. */ - } - - static unsigned --Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); -- return tie_t; -+ return 0; - } - --static void --Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); --} -+enum xtensa_field_id { -+ FIELD_t, -+ FIELD_bbi4, -+ FIELD_bbi, -+ FIELD_imm12, -+ FIELD_imm8, -+ FIELD_s, -+ FIELD_imm12b, -+ FIELD_imm16, -+ FIELD_m, -+ FIELD_n, -+ FIELD_offset, -+ FIELD_op0, -+ FIELD_op1, -+ FIELD_op2, -+ FIELD_r, -+ FIELD_sa4, -+ FIELD_sae4, -+ FIELD_sae, -+ FIELD_sal, -+ FIELD_sargt, -+ FIELD_sas4, -+ FIELD_sas, -+ FIELD_sr, -+ FIELD_st, -+ FIELD_thi3, -+ FIELD_imm4, -+ FIELD_i, -+ FIELD_imm6lo, -+ FIELD_imm6hi, -+ FIELD_imm7lo, -+ FIELD_imm7hi, -+ FIELD_z, -+ FIELD_imm6, -+ FIELD_imm7, -+ FIELD_xt_wbr15_imm, -+ FIELD_xt_wbr18_imm, -+ FIELD__ar0 -+}; - --static unsigned --Field_sas_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- return tie_t; --} -+ -+/* Functional units. */ - --static void --Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static xtensa_funcUnit_internal funcUnits[] = { -+ -+}; -+ -+ -+/* Register files. */ -+ -+enum xtensa_regfile_id { -+ REGFILE_AR -+}; -+ -+static xtensa_regfile_internal regfiles[] = { -+ { "AR", "a", REGFILE_AR, 32, 16 } -+}; -+ -+ -+/* Interfaces. */ -+ -+static xtensa_interface_internal interfaces[] = { -+ -+}; -+ -+ -+/* Constant tables. */ -+ -+/* constant table ai4c */ -+static const unsigned CONST_TBL_ai4c_0[] = { -+ 0xffffffff, -+ 0x1, -+ 0x2, -+ 0x3, -+ 0x4, -+ 0x5, -+ 0x6, -+ 0x7, -+ 0x8, -+ 0x9, -+ 0xa, -+ 0xb, -+ 0xc, -+ 0xd, -+ 0xe, -+ 0xf, -+ 0 -+}; -+ -+/* constant table b4c */ -+static const unsigned CONST_TBL_b4c_0[] = { -+ 0xffffffff, -+ 0x1, -+ 0x2, -+ 0x3, -+ 0x4, -+ 0x5, -+ 0x6, -+ 0x7, -+ 0x8, -+ 0xa, -+ 0xc, -+ 0x10, -+ 0x20, -+ 0x40, -+ 0x80, -+ 0x100, -+ 0 -+}; -+ -+/* constant table b4cu */ -+static const unsigned CONST_TBL_b4cu_0[] = { -+ 0x8000, -+ 0x10000, -+ 0x2, -+ 0x3, -+ 0x4, -+ 0x5, -+ 0x6, -+ 0x7, -+ 0x8, -+ 0xa, -+ 0xc, -+ 0x10, -+ 0x20, -+ 0x40, -+ 0x80, -+ 0x100, -+ 0 -+}; -+ -+ -+/* Instruction operands. */ -+ -+static int -+Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -+ return 0; - } - --static unsigned --Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+static int -+Operand_art_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -- return tie_t; -+ int error; -+ error = (*valp & ~0xf) != 0; -+ return error; - } - --static void --Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -+ return 0; - } - --static unsigned --Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_ars_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- return tie_t; -+ int error; -+ error = (*valp & ~0xf) != 0; -+ return error; - } - --static void --Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ return 0; - } - --static unsigned --Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_arr_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- return tie_t; -+ int error; -+ error = (*valp & ~0xf) != 0; -+ return error; - } - --static void --Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ return 0; - } - --static unsigned --Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_ar0_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- return tie_t; -+ int error; -+ error = (*valp & ~0xf) != 0; -+ return error; - } - --static void --Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_soffsetx4_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned soffsetx4_0, offset_0; -+ offset_0 = *valp & 0x3ffff; -+ soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); -+ *valp = soffsetx4_0; -+ return 0; - } - --static unsigned --Field_st_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_soffsetx4_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -- return tie_t; -+ unsigned offset_0, soffsetx4_0; -+ soffsetx4_0 = *valp; -+ offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; -+ *valp = offset_0; -+ return 0; - } - --static void --Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_soffsetx4_ator (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ *valp -= (pc & ~0x3); -+ return 0; - } - --static unsigned --Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -- return tie_t; -+ *valp += (pc & ~0x3); -+ return 0; - } - --static void --Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_lsi4x4_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ unsigned lsi4x4_0, r_0; -+ r_0 = *valp & 0xf; -+ lsi4x4_0 = r_0 << 2; -+ *valp = lsi4x4_0; -+ return 0; - } - --static unsigned --Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_lsi4x4_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); -- return tie_t; -+ unsigned r_0, lsi4x4_0; -+ lsi4x4_0 = *valp; -+ r_0 = ((lsi4x4_0 >> 2) & 0xf); -+ *valp = r_0; -+ return 0; - } - --static void --Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_simm7_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -+ unsigned simm7_0, imm7_0; -+ imm7_0 = *valp & 0x7f; -+ simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; -+ *valp = simm7_0; -+ return 0; - } - --static unsigned --Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_simm7_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); -- return tie_t; -+ unsigned imm7_0, simm7_0; -+ simm7_0 = *valp; -+ imm7_0 = (simm7_0 & 0x7f); -+ *valp = imm7_0; -+ return 0; - } - --static void --Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm6_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -+ unsigned uimm6_0, imm6_0; -+ imm6_0 = *valp & 0x3f; -+ uimm6_0 = 0x4 + (((0) << 6) | imm6_0); -+ *valp = uimm6_0; -+ return 0; - } - --static unsigned --Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm6_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); -- return tie_t; -+ unsigned imm6_0, uimm6_0; -+ uimm6_0 = *valp; -+ imm6_0 = (uimm6_0 - 0x4) & 0x3f; -+ *valp = imm6_0; -+ return 0; - } - --static void --Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm6_ator (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -+ *valp -= pc; -+ return 0; - } - --static unsigned --Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm6_rtoa (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ *valp += pc; -+ return 0; - } - --static void --Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_ai4const_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned ai4const_0, t_0; -+ t_0 = *valp & 0xf; -+ ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; -+ *valp = ai4const_0; -+ return 0; - } - --static unsigned --Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_ai4const_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ unsigned t_0, ai4const_0; -+ ai4const_0 = *valp; -+ switch (ai4const_0) -+ { -+ case 0xffffffff: t_0 = 0; break; -+ case 0x1: t_0 = 0x1; break; -+ case 0x2: t_0 = 0x2; break; -+ case 0x3: t_0 = 0x3; break; -+ case 0x4: t_0 = 0x4; break; -+ case 0x5: t_0 = 0x5; break; -+ case 0x6: t_0 = 0x6; break; -+ case 0x7: t_0 = 0x7; break; -+ case 0x8: t_0 = 0x8; break; -+ case 0x9: t_0 = 0x9; break; -+ case 0xa: t_0 = 0xa; break; -+ case 0xb: t_0 = 0xb; break; -+ case 0xc: t_0 = 0xc; break; -+ case 0xd: t_0 = 0xd; break; -+ case 0xe: t_0 = 0xe; break; -+ default: t_0 = 0xf; break; -+ } -+ *valp = t_0; -+ return 0; - } - --static void --Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_b4const_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned b4const_0, r_0; -+ r_0 = *valp & 0xf; -+ b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; -+ *valp = b4const_0; -+ return 0; - } - --static unsigned --Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_b4const_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ unsigned r_0, b4const_0; -+ b4const_0 = *valp; -+ switch (b4const_0) -+ { -+ case 0xffffffff: r_0 = 0; break; -+ case 0x1: r_0 = 0x1; break; -+ case 0x2: r_0 = 0x2; break; -+ case 0x3: r_0 = 0x3; break; -+ case 0x4: r_0 = 0x4; break; -+ case 0x5: r_0 = 0x5; break; -+ case 0x6: r_0 = 0x6; break; -+ case 0x7: r_0 = 0x7; break; -+ case 0x8: r_0 = 0x8; break; -+ case 0xa: r_0 = 0x9; break; -+ case 0xc: r_0 = 0xa; break; -+ case 0x10: r_0 = 0xb; break; -+ case 0x20: r_0 = 0xc; break; -+ case 0x40: r_0 = 0xd; break; -+ case 0x80: r_0 = 0xe; break; -+ default: r_0 = 0xf; break; -+ } -+ *valp = r_0; -+ return 0; - } - --static void --Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_b4constu_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned b4constu_0, r_0; -+ r_0 = *valp & 0xf; -+ b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; -+ *valp = b4constu_0; -+ return 0; - } - --static unsigned --Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_b4constu_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); -- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -- return tie_t; -+ unsigned r_0, b4constu_0; -+ b4constu_0 = *valp; -+ switch (b4constu_0) -+ { -+ case 0x8000: r_0 = 0; break; -+ case 0x10000: r_0 = 0x1; break; -+ case 0x2: r_0 = 0x2; break; -+ case 0x3: r_0 = 0x3; break; -+ case 0x4: r_0 = 0x4; break; -+ case 0x5: r_0 = 0x5; break; -+ case 0x6: r_0 = 0x6; break; -+ case 0x7: r_0 = 0x7; break; -+ case 0x8: r_0 = 0x8; break; -+ case 0xa: r_0 = 0x9; break; -+ case 0xc: r_0 = 0xa; break; -+ case 0x10: r_0 = 0xb; break; -+ case 0x20: r_0 = 0xc; break; -+ case 0x40: r_0 = 0xd; break; -+ case 0x80: r_0 = 0xe; break; -+ default: r_0 = 0xf; break; -+ } -+ *valp = r_0; -+ return 0; - } - --static void --Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm8_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -- tie_t = (val << 28) >> 30; -- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -+ unsigned uimm8_0, imm8_0; -+ imm8_0 = *valp & 0xff; -+ uimm8_0 = imm8_0; -+ *valp = uimm8_0; -+ return 0; - } - --static unsigned --Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm8_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; -+ unsigned imm8_0, uimm8_0; -+ uimm8_0 = *valp; -+ imm8_0 = (uimm8_0 & 0xff); -+ *valp = imm8_0; -+ return 0; - } - --static void --Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm8x2_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -+ unsigned uimm8x2_0, imm8_0; -+ imm8_0 = *valp & 0xff; -+ uimm8x2_0 = imm8_0 << 1; -+ *valp = uimm8x2_0; -+ return 0; - } - --static unsigned --Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm8x2_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; -+ unsigned imm8_0, uimm8x2_0; -+ uimm8x2_0 = *valp; -+ imm8_0 = ((uimm8x2_0 >> 1) & 0xff); -+ *valp = imm8_0; -+ return 0; - } - --static void --Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm8x4_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -+ unsigned uimm8x4_0, imm8_0; -+ imm8_0 = *valp & 0xff; -+ uimm8x4_0 = imm8_0 << 2; -+ *valp = uimm8x4_0; -+ return 0; - } - --static unsigned --Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm8x4_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ unsigned imm8_0, uimm8x4_0; -+ uimm8x4_0 = *valp; -+ imm8_0 = ((uimm8x4_0 >> 2) & 0xff); -+ *valp = imm8_0; -+ return 0; - } - --static void --Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm4x16_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned uimm4x16_0, op2_0; -+ op2_0 = *valp & 0xf; -+ uimm4x16_0 = op2_0 << 4; -+ *valp = uimm4x16_0; -+ return 0; - } - --static unsigned --Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm4x16_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ unsigned op2_0, uimm4x16_0; -+ uimm4x16_0 = *valp; -+ op2_0 = ((uimm4x16_0 >> 4) & 0xf); -+ *valp = op2_0; -+ return 0; - } - --static void --Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_simm8_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned simm8_0, imm8_0; -+ imm8_0 = *valp & 0xff; -+ simm8_0 = ((int) imm8_0 << 24) >> 24; -+ *valp = simm8_0; -+ return 0; - } - --static unsigned --Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_simm8_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -- return tie_t; -+ unsigned imm8_0, simm8_0; -+ simm8_0 = *valp; -+ imm8_0 = (simm8_0 & 0xff); -+ *valp = imm8_0; -+ return 0; - } - --static void --Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_simm8x256_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -+ unsigned simm8x256_0, imm8_0; -+ imm8_0 = *valp & 0xff; -+ simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; -+ *valp = simm8x256_0; -+ return 0; - } - --static unsigned --Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_simm8x256_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -- return tie_t; -+ unsigned imm8_0, simm8x256_0; -+ simm8x256_0 = *valp; -+ imm8_0 = ((simm8x256_0 >> 8) & 0xff); -+ *valp = imm8_0; -+ return 0; - } - --static void --Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_simm12b_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -+ unsigned simm12b_0, imm12b_0; -+ imm12b_0 = *valp & 0xfff; -+ simm12b_0 = ((int) imm12b_0 << 20) >> 20; -+ *valp = simm12b_0; -+ return 0; - } - --static unsigned --Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_simm12b_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ unsigned imm12b_0, simm12b_0; -+ simm12b_0 = *valp; -+ imm12b_0 = (simm12b_0 & 0xfff); -+ *valp = imm12b_0; -+ return 0; - } - --static void --Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_msalp32_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned msalp32_0, sal_0; -+ sal_0 = *valp & 0x1f; -+ msalp32_0 = 0x20 - sal_0; -+ *valp = msalp32_0; -+ return 0; - } - --static unsigned --Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_msalp32_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ unsigned sal_0, msalp32_0; -+ msalp32_0 = *valp; -+ sal_0 = (0x20 - msalp32_0) & 0x1f; -+ *valp = sal_0; -+ return 0; - } - --static void --Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_op2p1_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -+ unsigned op2p1_0, op2_0; -+ op2_0 = *valp & 0xf; -+ op2p1_0 = op2_0 + 0x1; -+ *valp = op2p1_0; -+ return 0; - } - --static unsigned --Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_op2p1_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -- return tie_t; -+ unsigned op2_0, op2p1_0; -+ op2p1_0 = *valp; -+ op2_0 = (op2p1_0 - 0x1) & 0xf; -+ *valp = op2_0; -+ return 0; - } - --static void --Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_label8_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -+ unsigned label8_0, imm8_0; -+ imm8_0 = *valp & 0xff; -+ label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); -+ *valp = label8_0; -+ return 0; - } - --static unsigned --Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_label8_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -- return tie_t; -+ unsigned imm8_0, label8_0; -+ label8_0 = *valp; -+ imm8_0 = (label8_0 - 0x4) & 0xff; -+ *valp = imm8_0; -+ return 0; - } - --static void --Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_label8_ator (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -+ *valp -= pc; -+ return 0; - } - --static unsigned --Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_label8_rtoa (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); -- return tie_t; -+ *valp += pc; -+ return 0; - } - --static void --Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_label12_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -+ unsigned label12_0, imm12_0; -+ imm12_0 = *valp & 0xfff; -+ label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); -+ *valp = label12_0; -+ return 0; - } - --static unsigned --Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_label12_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); -- return tie_t; -+ unsigned imm12_0, label12_0; -+ label12_0 = *valp; -+ imm12_0 = (label12_0 - 0x4) & 0xfff; -+ *valp = imm12_0; -+ return 0; - } - --static void --Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_label12_ator (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -+ *valp -= pc; -+ return 0; - } - --static unsigned --Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_label12_rtoa (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ *valp += pc; -+ return 0; - } - --static void --Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_soffset_decode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -- tie_t = (val << 26) >> 30; -- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -+ unsigned soffset_0, offset_0; -+ offset_0 = *valp & 0x3ffff; -+ soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); -+ *valp = soffset_0; -+ return 0; - } - --static unsigned --Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -+static int -+Operand_soffset_encode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; -+ unsigned offset_0, soffset_0; -+ soffset_0 = *valp; -+ offset_0 = (soffset_0 - 0x4) & 0x3ffff; -+ *valp = offset_0; -+ return 0; - } - --static void --Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -- tie_t = (val << 26) >> 30; -- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); --} -- --static unsigned --Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; --} -- --static void --Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -- tie_t = (val << 25) >> 29; -- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); --} -- --static unsigned --Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; --} -- --static void --Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -- tie_t = (val << 25) >> 29; -- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); --} -- --static unsigned --Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); -- return tie_t; --} -- --static void --Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 25) >> 25; -- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); --} -- --static unsigned --Field_r3_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); -- return tie_t; --} -- --static void --Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); --} -- --static unsigned --Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); -- return tie_t; --} -- --static void --Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); --} -- --static unsigned --Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_soffset_ator (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); -- return tie_t; -+ *valp -= pc; -+ return 0; - } - --static void --Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_soffset_rtoa (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -+ *valp += pc; -+ return 0; - } - --static unsigned --Field_t3_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm16x4_decode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; -+ unsigned uimm16x4_0, imm16_0; -+ imm16_0 = *valp & 0xffff; -+ uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; -+ *valp = uimm16x4_0; -+ return 0; - } - --static void --Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm16x4_encode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -+ unsigned imm16_0, uimm16x4_0; -+ uimm16x4_0 = *valp; -+ imm16_0 = (uimm16x4_0 >> 2) & 0xffff; -+ *valp = imm16_0; -+ return 0; - } - --static unsigned --Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_uimm16x4_ator (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); -- return tie_t; -+ *valp -= ((pc + 3) & ~0x3); -+ return 0; - } - --static void --Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -+ *valp += ((pc + 3) & ~0x3); -+ return 0; - } - --static unsigned --Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_immt_decode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); -- return tie_t; -+ unsigned immt_0, t_0; -+ t_0 = *valp & 0xf; -+ immt_0 = t_0; -+ *valp = immt_0; -+ return 0; - } - --static void --Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_immt_encode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -+ unsigned t_0, immt_0; -+ immt_0 = *valp; -+ t_0 = immt_0 & 0xf; -+ *valp = t_0; -+ return 0; - } - --static unsigned --Field_w_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_imms_decode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); -- return tie_t; -+ unsigned imms_0, s_0; -+ s_0 = *valp & 0xf; -+ imms_0 = s_0; -+ *valp = imms_0; -+ return 0; - } - --static void --Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_imms_encode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -+ unsigned s_0, imms_0; -+ imms_0 = *valp; -+ s_0 = imms_0 & 0xf; -+ *valp = s_0; -+ return 0; - } - --static unsigned --Field_y_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_xt_wbr15_label_decode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); -- return tie_t; -+ unsigned xt_wbr15_label_0, xt_wbr15_imm_0; -+ xt_wbr15_imm_0 = *valp & 0x7fff; -+ xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); -+ *valp = xt_wbr15_label_0; -+ return 0; - } - --static void --Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_xt_wbr15_label_encode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -+ unsigned xt_wbr15_imm_0, xt_wbr15_label_0; -+ xt_wbr15_label_0 = *valp; -+ xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; -+ *valp = xt_wbr15_imm_0; -+ return 0; - } - --static unsigned --Field_x_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); -- return tie_t; -+ *valp -= pc; -+ return 0; - } - --static void --Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -+ *valp += pc; -+ return 0; - } - --static unsigned --Field_t2_Slot_inst_get (const xtensa_insnbuf insn) -+static int -+Operand_xt_wbr18_label_decode (uint32 *valp) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); -- return tie_t; -+ unsigned xt_wbr18_label_0, xt_wbr18_imm_0; -+ xt_wbr18_imm_0 = *valp & 0x3ffff; -+ xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); -+ *valp = xt_wbr18_label_0; -+ return 0; - } - --static void --Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_xt_wbr18_label_encode (uint32 *valp) - { -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -+ unsigned xt_wbr18_imm_0, xt_wbr18_label_0; -+ xt_wbr18_label_0 = *valp; -+ xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; -+ *valp = xt_wbr18_imm_0; -+ return 0; - } - --static unsigned --Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) -+static int -+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) - { -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); -- return tie_t; -+ *valp -= pc; -+ return 0; - } - --static void --Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -+static int -+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) - { -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -+ *valp += pc; -+ return 0; - } - --static unsigned --Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); -- return tie_t; --} -+static xtensa_operand_internal operands[] = { -+ { "art", FIELD_t, REGFILE_AR, 1, -+ XTENSA_OPERAND_IS_REGISTER, -+ Operand_art_encode, Operand_art_decode, -+ 0, 0 }, -+ { "ars", FIELD_s, REGFILE_AR, 1, -+ XTENSA_OPERAND_IS_REGISTER, -+ Operand_ars_encode, Operand_ars_decode, -+ 0, 0 }, -+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1, -+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -+ Operand_ars_encode, Operand_ars_decode, -+ 0, 0 }, -+ { "arr", FIELD_r, REGFILE_AR, 1, -+ XTENSA_OPERAND_IS_REGISTER, -+ Operand_arr_encode, Operand_arr_decode, -+ 0, 0 }, -+ { "ar0", FIELD__ar0, REGFILE_AR, 1, -+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -+ Operand_ar0_encode, Operand_ar0_decode, -+ 0, 0 }, -+ { "soffsetx4", FIELD_offset, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_soffsetx4_encode, Operand_soffsetx4_decode, -+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, -+ { "lsi4x4", FIELD_r, -1, 0, -+ 0, -+ Operand_lsi4x4_encode, Operand_lsi4x4_decode, -+ 0, 0 }, -+ { "simm7", FIELD_imm7, -1, 0, -+ 0, -+ Operand_simm7_encode, Operand_simm7_decode, -+ 0, 0 }, -+ { "uimm6", FIELD_imm6, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_uimm6_encode, Operand_uimm6_decode, -+ Operand_uimm6_ator, Operand_uimm6_rtoa }, -+ { "ai4const", FIELD_t, -1, 0, -+ 0, -+ Operand_ai4const_encode, Operand_ai4const_decode, -+ 0, 0 }, -+ { "b4const", FIELD_r, -1, 0, -+ 0, -+ Operand_b4const_encode, Operand_b4const_decode, -+ 0, 0 }, -+ { "b4constu", FIELD_r, -1, 0, -+ 0, -+ Operand_b4constu_encode, Operand_b4constu_decode, -+ 0, 0 }, -+ { "uimm8", FIELD_imm8, -1, 0, -+ 0, -+ Operand_uimm8_encode, Operand_uimm8_decode, -+ 0, 0 }, -+ { "uimm8x2", FIELD_imm8, -1, 0, -+ 0, -+ Operand_uimm8x2_encode, Operand_uimm8x2_decode, -+ 0, 0 }, -+ { "uimm8x4", FIELD_imm8, -1, 0, -+ 0, -+ Operand_uimm8x4_encode, Operand_uimm8x4_decode, -+ 0, 0 }, -+ { "uimm4x16", FIELD_op2, -1, 0, -+ 0, -+ Operand_uimm4x16_encode, Operand_uimm4x16_decode, -+ 0, 0 }, -+ { "simm8", FIELD_imm8, -1, 0, -+ 0, -+ Operand_simm8_encode, Operand_simm8_decode, -+ 0, 0 }, -+ { "simm8x256", FIELD_imm8, -1, 0, -+ 0, -+ Operand_simm8x256_encode, Operand_simm8x256_decode, -+ 0, 0 }, -+ { "simm12b", FIELD_imm12b, -1, 0, -+ 0, -+ Operand_simm12b_encode, Operand_simm12b_decode, -+ 0, 0 }, -+ { "msalp32", FIELD_sal, -1, 0, -+ 0, -+ Operand_msalp32_encode, Operand_msalp32_decode, -+ 0, 0 }, -+ { "op2p1", FIELD_op2, -1, 0, -+ 0, -+ Operand_op2p1_encode, Operand_op2p1_decode, -+ 0, 0 }, -+ { "label8", FIELD_imm8, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_label8_encode, Operand_label8_decode, -+ Operand_label8_ator, Operand_label8_rtoa }, -+ { "label12", FIELD_imm12, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_label12_encode, Operand_label12_decode, -+ Operand_label12_ator, Operand_label12_rtoa }, -+ { "soffset", FIELD_offset, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_soffset_encode, Operand_soffset_decode, -+ Operand_soffset_ator, Operand_soffset_rtoa }, -+ { "uimm16x4", FIELD_imm16, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_uimm16x4_encode, Operand_uimm16x4_decode, -+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, -+ { "immt", FIELD_t, -1, 0, -+ 0, -+ Operand_immt_encode, Operand_immt_decode, -+ 0, 0 }, -+ { "imms", FIELD_s, -1, 0, -+ 0, -+ Operand_imms_encode, Operand_imms_decode, -+ 0, 0 }, -+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, -+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, -+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, -+ XTENSA_OPERAND_IS_PCRELATIVE, -+ Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, -+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, -+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, -+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, -+ { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, -+ { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, -+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, -+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, -+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, -+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, -+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, -+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, -+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, -+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, -+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, -+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, -+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, -+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, -+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, -+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, -+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 } -+}; -+ -+enum xtensa_operand_id { -+ OPERAND_art, -+ OPERAND_ars, -+ OPERAND__ars_invisible, -+ OPERAND_arr, -+ OPERAND_ar0, -+ OPERAND_soffsetx4, -+ OPERAND_lsi4x4, -+ OPERAND_simm7, -+ OPERAND_uimm6, -+ OPERAND_ai4const, -+ OPERAND_b4const, -+ OPERAND_b4constu, -+ OPERAND_uimm8, -+ OPERAND_uimm8x2, -+ OPERAND_uimm8x4, -+ OPERAND_uimm4x16, -+ OPERAND_simm8, -+ OPERAND_simm8x256, -+ OPERAND_simm12b, -+ OPERAND_msalp32, -+ OPERAND_op2p1, -+ OPERAND_label8, -+ OPERAND_label12, -+ OPERAND_soffset, -+ OPERAND_uimm16x4, -+ OPERAND_immt, -+ OPERAND_imms, -+ OPERAND_xt_wbr15_label, -+ OPERAND_xt_wbr18_label, -+ OPERAND_t, -+ OPERAND_bbi4, -+ OPERAND_bbi, -+ OPERAND_imm12, -+ OPERAND_imm8, -+ OPERAND_s, -+ OPERAND_imm12b, -+ OPERAND_imm16, -+ OPERAND_m, -+ OPERAND_n, -+ OPERAND_offset, -+ OPERAND_op0, -+ OPERAND_op1, -+ OPERAND_op2, -+ OPERAND_r, -+ OPERAND_sa4, -+ OPERAND_sae4, -+ OPERAND_sae, -+ OPERAND_sal, -+ OPERAND_sargt, -+ OPERAND_sas4, -+ OPERAND_sas, -+ OPERAND_sr, -+ OPERAND_st, -+ OPERAND_thi3, -+ OPERAND_imm4, -+ OPERAND_i, -+ OPERAND_imm6lo, -+ OPERAND_imm6hi, -+ OPERAND_imm7lo, -+ OPERAND_imm7hi, -+ OPERAND_z, -+ OPERAND_imm6, -+ OPERAND_imm7, -+ OPERAND_xt_wbr15_imm, -+ OPERAND_xt_wbr18_imm -+}; - --static void --Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); --} -+ -+/* Iclass table. */ - --static unsigned --Field_s2_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { -+ { { STATE_PSEXCM }, 'o' }, -+ { { STATE_EPC1 }, 'i' } -+}; - --static void --Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); --} -+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { -+ { { STATE_DEPC }, 'i' } -+}; - --static unsigned --Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); --} -+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_ai4const }, 'i' } -+}; - --static unsigned --Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm6 }, 'i' } -+}; - --static void --Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); --} -+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_lsi4x4 }, 'i' } -+}; - --static unsigned --Field_r2_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' } -+}; - --static void --Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); --} -+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { -+ { { OPERAND_ars }, 'o' }, -+ { { OPERAND_simm7 }, 'i' } -+}; - --static unsigned --Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { -+ { { OPERAND__ars_invisible }, 'i' } -+}; - --static void --Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); --} -+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_lsi4x4 }, 'i' } -+}; - --static unsigned --Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_simm8 }, 'i' } -+}; - --static void --Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); --} -+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_simm8x256 }, 'i' } -+}; - --static unsigned --Field_t4_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); --} -+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_b4const }, 'i' }, -+ { { OPERAND_label8 }, 'i' } -+}; - --static void --Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); --} -+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_bbi }, 'i' }, -+ { { OPERAND_label8 }, 'i' } -+}; - --static unsigned --Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_b4constu }, 'i' }, -+ { { OPERAND_label8 }, 'i' } -+}; - --static void --Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); --} -+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_label8 }, 'i' } -+}; - --static unsigned --Field_s4_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_label12 }, 'i' } -+}; - --static void --Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); --} -+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { -+ { { OPERAND_soffsetx4 }, 'i' }, -+ { { OPERAND_ar0 }, 'o' } -+}; - --static unsigned --Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_ar0 }, 'o' } -+}; - --static void --Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); --} -+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_sae }, 'i' }, -+ { { OPERAND_op2p1 }, 'i' } -+}; - --static unsigned --Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { -+ { { OPERAND_soffset }, 'i' } -+}; - --static void --Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); --} -+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { -+ { { OPERAND_ars }, 'i' } -+}; - --static unsigned --Field_r4_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm8x2 }, 'i' } -+}; - --static void --Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); --} -+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm8x2 }, 'i' } -+}; - --static unsigned --Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm8x4 }, 'i' } -+}; - --static void --Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); --} -+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_uimm16x4 }, 'i' } -+}; - --static unsigned --Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { -+ { { STATE_LITBADDR }, 'i' }, -+ { { STATE_LITBEN }, 'i' } -+}; - --static void --Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); --} -+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm8 }, 'i' } -+}; - --static unsigned --Field_t8_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_simm12b }, 'i' } -+}; - --static void --Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); --} -+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { -+ { { OPERAND_arr }, 'm' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); --} -+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { -+ { { OPERAND__ars_invisible }, 'i' } -+}; - --static unsigned --Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm8x2 }, 'i' } -+}; - --static void --Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); --} -+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm8x4 }, 'i' } -+}; - --static unsigned --Field_s8_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_uimm8 }, 'i' } -+}; - --static void --Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); --} -+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { -+ { { OPERAND_ars }, 'i' } -+}; - --static unsigned --Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { -+ { { STATE_SAR }, 'o' } -+}; - --static void --Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); --} -+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { -+ { { OPERAND_sas }, 'i' } -+}; - --static unsigned --Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { -+ { { STATE_SAR }, 'o' } -+}; - --static void --Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); --} -+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' } -+}; - --static unsigned --Field_r8_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { -+ { { STATE_SAR }, 'i' } -+}; - --static void --Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); --} -+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { -+ { { STATE_SAR }, 'i' } -+}; - --static void --Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); --} -+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { -+ { { STATE_SAR }, 'i' } -+}; - --static void --Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); --} -+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_msalp32 }, 'i' } -+}; - --static unsigned --Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_sargt }, 'i' } -+}; - --static void --Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 17) >> 17; -- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); --} -+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_s }, 'i' } -+}; - --static unsigned --Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { -+ { { STATE_XTSYNC }, 'i' } -+}; - --static void --Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 14) >> 14; -- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_s }, 'i' } -+}; - --static unsigned --Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { -+ { { STATE_PSUM }, 'i' }, -+ { { STATE_PSEXCM }, 'i' }, -+ { { STATE_PSINTLEVEL }, 'm' } -+}; - --static void --Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 14) >> 14; -- insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); -- return tie_t; --} -- --static void --Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { -+ { { STATE_SAR }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { -+ { { STATE_SAR }, 'o' }, -+ { { STATE_XTSYNC }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { -+ { { STATE_SAR }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { -+ { { STATE_LITBADDR }, 'i' }, -+ { { STATE_LITBEN }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { -+ { { STATE_LITBADDR }, 'o' }, -+ { { STATE_LITBEN }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -- tie_t = (val << 24) >> 28; -- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { -+ { { STATE_LITBADDR }, 'm' }, -+ { { STATE_LITBEN }, 'm' } -+}; - --static unsigned --Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { -+ { { STATE_PSUM }, 'i' }, -+ { { STATE_PSEXCM }, 'i' }, -+ { { STATE_PSINTLEVEL }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { -+ { { STATE_PSUM }, 'o' }, -+ { { STATE_PSEXCM }, 'o' }, -+ { { STATE_PSINTLEVEL }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { -+ { { STATE_PSUM }, 'm' }, -+ { { STATE_PSEXCM }, 'm' }, -+ { { STATE_PSINTLEVEL }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 27) >> 27; -- insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { -+ { { STATE_EPC1 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 26) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { -+ { { STATE_EPC1 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -- tie_t = (val << 23) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { -+ { { STATE_EPC1 }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -- tie_t = (val << 23) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { -+ { { STATE_EXCSAVE1 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x60) | (tie_t << 5); -- tie_t = (val << 24) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { -+ { { STATE_EXCSAVE1 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -- tie_t = (val << 25) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { -+ { { STATE_EXCSAVE1 }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -- tie_t = (val << 24) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { -+ { { STATE_EPC2 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -- tie_t = (val << 24) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); -- tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { -+ { { STATE_EPC2 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x200) | (tie_t << 9); -- tie_t = (val << 25) >> 26; -- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { -+ { { STATE_EPC2 }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { -+ { { STATE_EXCSAVE2 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { -+ { { STATE_EXCSAVE2 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { -+ { { STATE_EXCSAVE2 }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); -- tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { -+ { { STATE_EPC3 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 26) >> 26; -- insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); -- tie_t = (val << 21) >> 27; -- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { -+ { { STATE_EPC3 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); -- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { -+ { { STATE_EPC3 }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -- tie_t = (val << 29) >> 30; -- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { -+ { { STATE_EXCSAVE3 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 27) >> 27; -- insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -- tie_t = (val << 26) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { -+ { { STATE_EXCSAVE3 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { -+ { { STATE_EXCSAVE3 }, 'm' } -+}; - --static void --Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { -+ { { STATE_EPS2 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { -+ { { STATE_EPS2 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -- tie_t = (val << 30) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { -+ { { STATE_EPS2 }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -- tie_t = (val << 30) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -- tie_t = (val << 29) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); -- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { -+ { { STATE_EPS3 }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -- tie_t = (val << 30) >> 31; -- insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -- tie_t = (val << 29) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { -+ { { STATE_EPS3 }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -- tie_t = (val << 28) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { -+ { { STATE_EPS3 }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -- tie_t = (val << 28) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { -+ { { STATE_EXCVADDR }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -- tie_t = (val << 29) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); -- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { -+ { { STATE_EXCVADDR }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -- tie_t = (val << 30) >> 31; -- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { -+ { { STATE_EXCVADDR }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x60) | (tie_t << 5); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { -+ { { STATE_DEPC }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); -- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { -+ { { STATE_DEPC }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 26) >> 30; -- insn[0] = (insn[0] & ~0x60) | (tie_t << 5); -- tie_t = (val << 22) >> 28; -- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); -- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { -+ { { STATE_DEPC }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -- tie_t = (val << 30) >> 31; -- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); -- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { -+ { { STATE_EXCCAUSE }, 'i' }, -+ { { STATE_XTSYNC }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 30) >> 30; -- insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -- tie_t = (val << 29) >> 31; -- insn[0] = (insn[0] & ~0x800) | (tie_t << 11); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { -+ { { STATE_EXCCAUSE }, 'o' } -+}; - --static void --Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 27) >> 27; -- insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { -+ { { STATE_EXCCAUSE }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 24) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 29) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { -+ { { STATE_VECBASE }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 24) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { -+ { { STATE_VECBASE }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 24) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { -+ { { STATE_VECBASE }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_mul16_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -- tie_t = (val << 27) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 24) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_mul32_args[] = { -+ { { OPERAND_arr }, 'o' }, -+ { { OPERAND_ars }, 'i' }, -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { -+ { { OPERAND_s }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { -+ { { STATE_PSUM }, 'o' }, -+ { { STATE_PSEXCM }, 'o' }, -+ { { STATE_PSINTLEVEL }, 'o' }, -+ { { STATE_EPC1 }, 'i' }, -+ { { STATE_EPC2 }, 'i' }, -+ { { STATE_EPC3 }, 'i' }, -+ { { STATE_EPS2 }, 'i' }, -+ { { STATE_EPS3 }, 'i' }, -+ { { STATE_InOCDMode }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { -+ { { OPERAND_s }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { -+ { { STATE_PSINTLEVEL }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { -+ { { STATE_INTERRUPT }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_INTERRUPT }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_INTERRUPT }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { -+ { { STATE_INTENABLE }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { -+ { { STATE_INTENABLE }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { -+ { { STATE_INTENABLE }, 'm' } -+}; - --static unsigned --Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { -+ { { OPERAND_imms }, 'i' }, -+ { { OPERAND_immt }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { -+ { { STATE_PSEXCM }, 'i' }, -+ { { STATE_PSINTLEVEL }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { -+ { { OPERAND_imms }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { -+ { { STATE_PSEXCM }, 'i' }, -+ { { STATE_PSINTLEVEL }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { -+ { { STATE_DBREAKA0 }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { -+ { { STATE_DBREAKA0 }, 'o' }, -+ { { STATE_XTSYNC }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { -+ { { STATE_DBREAKA0 }, 'm' }, -+ { { STATE_XTSYNC }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { -+ { { STATE_DBREAKC0 }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { -+ { { STATE_DBREAKC0 }, 'o' }, -+ { { STATE_XTSYNC }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { -+ { { STATE_DBREAKC0 }, 'm' }, -+ { { STATE_XTSYNC }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { -+ { { STATE_IBREAKA0 }, 'i' } -+}; - --static unsigned --Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static void --Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 31) >> 31; -- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -- tie_t = (val << 28) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { -+ { { STATE_IBREAKA0 }, 'o' } -+}; - --static unsigned --Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29); -- tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static void --Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 5) >> 5; -- insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0); -- tie_t = (val << 2) >> 29; -- insn[1] = (insn[1] & ~0x7) | (tie_t << 0); --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { -+ { { STATE_IBREAKA0 }, 'm' } -+}; - --static unsigned --Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn) --{ -- unsigned tie_t = 0; -- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); -- return tie_t; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static void --Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val) --{ -- uint32 tie_t; -- tie_t = (val << 28) >> 28; -- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { -+ { { STATE_IBREAKENABLE }, 'i' } -+}; - --static void --Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, -- uint32 val ATTRIBUTE_UNUSED) --{ -- /* Do nothing. */ --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { -+ { { STATE_IBREAKENABLE }, 'o' } -+}; - --static unsigned --Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 4; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 8; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { -+ { { STATE_IBREAKENABLE }, 'm' } -+}; - --static unsigned --Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 12; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { -+ { { STATE_DEBUGCAUSE }, 'i' }, -+ { { STATE_DBNUM }, 'i' } -+}; - --static unsigned --Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 1; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static unsigned --Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 2; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { -+ { { STATE_DEBUGCAUSE }, 'o' }, -+ { { STATE_DBNUM }, 'o' } -+}; - --static unsigned --Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 3; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static unsigned --Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { -+ { { STATE_DEBUGCAUSE }, 'm' }, -+ { { STATE_DBNUM }, 'm' } -+}; - --static unsigned --Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static unsigned --Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { -+ { { STATE_ICOUNT }, 'i' } -+}; - --static unsigned --Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - -- --/* Functional units. */ -+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_ICOUNT }, 'o' } -+}; - --static xtensa_funcUnit_internal funcUnits[] = { -+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - -+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_ICOUNT }, 'm' } - }; - -- --/* Register files. */ -+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static xtensa_regfile_internal regfiles[] = { -- { "AR", "a", 0, 32, 64 }, -- { "MR", "m", 1, 32, 4 }, -- { "BR", "b", 2, 1, 16 }, -- { "FR", "f", 3, 32, 16 }, -- { "BR2", "b", 2, 2, 8 }, -- { "BR4", "b", 2, 4, 4 }, -- { "BR8", "b", 2, 8, 2 }, -- { "BR16", "b", 2, 16, 1 } -+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { -+ { { STATE_ICOUNTLEVEL }, 'i' } - }; - -- --/* Interfaces. */ -+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static xtensa_interface_internal interfaces[] = { -+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { -+ { { STATE_ICOUNTLEVEL }, 'o' } -+}; - -+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { -+ { { OPERAND_art }, 'm' } - }; - -- --/* Constant tables. */ -+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { -+ { { STATE_ICOUNTLEVEL }, 'm' } -+}; - --/* constant table ai4c */ --static const unsigned CONST_TBL_ai4c_0[] = { -- 0xffffffff, -- 0x1, -- 0x2, -- 0x3, -- 0x4, -- 0x5, -- 0x6, -- 0x7, -- 0x8, -- 0x9, -- 0xa, -- 0xb, -- 0xc, -- 0xd, -- 0xe, -- 0xf, -- 0 -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { -+ { { OPERAND_art }, 'o' } - }; - --/* constant table b4c */ --static const unsigned CONST_TBL_b4c_0[] = { -- 0xffffffff, -- 0x1, -- 0x2, -- 0x3, -- 0x4, -- 0x5, -- 0x6, -- 0x7, -- 0x8, -- 0xa, -- 0xc, -- 0x10, -- 0x20, -- 0x40, -- 0x80, -- 0x100, -- 0 -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { -+ { { STATE_DDR }, 'i' } - }; - --/* constant table b4cu */ --static const unsigned CONST_TBL_b4cu_0[] = { -- 0x8000, -- 0x10000, -- 0x2, -- 0x3, -- 0x4, -- 0x5, -- 0x6, -- 0x7, -- 0x8, -- 0xa, -- 0xc, -- 0x10, -- 0x20, -- 0x40, -- 0x80, -- 0x100, -- 0 -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { -+ { { OPERAND_art }, 'i' } - }; - -- --/* Instruction operands. */ -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_DDR }, 'o' } -+}; - --static int --Operand_soffsetx4_decode (uint32 *valp) --{ -- unsigned soffsetx4_0, offset_0; -- offset_0 = *valp & 0x3ffff; -- soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); -- *valp = soffsetx4_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static int --Operand_soffsetx4_encode (uint32 *valp) --{ -- unsigned offset_0, soffsetx4_0; -- soffsetx4_0 = *valp; -- offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; -- *valp = offset_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_DDR }, 'm' } -+}; - --static int --Operand_soffsetx4_ator (uint32 *valp, uint32 pc) --{ -- *valp -= (pc & ~0x3); -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { -+ { { OPERAND_imms }, 'i' } -+}; - --static int --Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) --{ -- *valp += (pc & ~0x3); -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { -+ { { STATE_InOCDMode }, 'm' }, -+ { { STATE_EPC2 }, 'i' }, -+ { { STATE_PSUM }, 'o' }, -+ { { STATE_PSEXCM }, 'o' }, -+ { { STATE_PSINTLEVEL }, 'o' }, -+ { { STATE_EPS2 }, 'i' } -+}; - --static int --Operand_uimm12x8_decode (uint32 *valp) --{ -- unsigned uimm12x8_0, imm12_0; -- imm12_0 = *valp & 0xfff; -- uimm12x8_0 = imm12_0 << 3; -- *valp = uimm12x8_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { -+ { { STATE_InOCDMode }, 'm' } -+}; - --static int --Operand_uimm12x8_encode (uint32 *valp) --{ -- unsigned imm12_0, uimm12x8_0; -- uimm12x8_0 = *valp; -- imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); -- *valp = imm12_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static int --Operand_simm4_decode (uint32 *valp) --{ -- unsigned simm4_0, mn_0; -- mn_0 = *valp & 0xf; -- simm4_0 = ((int) mn_0 << 28) >> 28; -- *valp = simm4_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' } -+}; - --static int --Operand_simm4_encode (uint32 *valp) --{ -- unsigned mn_0, simm4_0; -- simm4_0 = *valp; -- mn_0 = (simm4_0 & 0xf); -- *valp = mn_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static int --Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { -+ { { STATE_CCOUNT }, 'i' } -+}; - --static int --Operand_arr_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0xf) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static int --Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_CCOUNT }, 'o' } -+}; - --static int --Operand_ars_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0xf) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static int --Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' }, -+ { { STATE_CCOUNT }, 'm' } -+}; - --static int --Operand_art_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0xf) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { -+ { { OPERAND_art }, 'o' } -+}; - --static int --Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { -+ { { STATE_CCOMPARE0 }, 'i' } -+}; - --static int --Operand_ar0_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0x3f) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { -+ { { OPERAND_art }, 'i' } -+}; - --static int --Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { -+ { { STATE_CCOMPARE0 }, 'o' }, -+ { { STATE_INTERRUPT }, 'm' } -+}; - --static int --Operand_ar4_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0x3f) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { -+ { { OPERAND_art }, 'm' } -+}; - --static int --Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { -+ { { STATE_CCOMPARE0 }, 'm' }, -+ { { STATE_INTERRUPT }, 'm' } -+}; - --static int --Operand_ar8_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0x3f) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { -+ { { OPERAND_ars }, 'i' } -+}; - --static int --Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' } -+}; - --static int --Operand_ar12_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0x3f) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' } -+}; - --static int --Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_ars }, 'i' } -+}; - --static int --Operand_ars_entry_encode (uint32 *valp) --{ -- int error; -- error = (*valp & ~0x3f) != 0; -- return error; --} -+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { -+ { { STATE_XTSYNC }, 'o' } -+}; - --static int --Operand_immrx4_decode (uint32 *valp) --{ -- unsigned immrx4_0, r_0; -- r_0 = *valp & 0xf; -- immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; -- *valp = immrx4_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { -+ { { OPERAND_ars }, 'i' } -+}; - --static int --Operand_immrx4_encode (uint32 *valp) --{ -- unsigned r_0, immrx4_0; -- immrx4_0 = *valp; -- r_0 = ((immrx4_0 >> 2) & 0xf); -- *valp = r_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' } -+}; - --static int --Operand_lsi4x4_decode (uint32 *valp) --{ -- unsigned lsi4x4_0, r_0; -- r_0 = *valp & 0xf; -- lsi4x4_0 = r_0 << 2; -- *valp = lsi4x4_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { -+ { { OPERAND_art }, 'i' }, -+ { { OPERAND_ars }, 'i' } -+}; - --static int --Operand_lsi4x4_encode (uint32 *valp) --{ -- unsigned r_0, lsi4x4_0; -- lsi4x4_0 = *valp; -- r_0 = ((lsi4x4_0 >> 2) & 0xf); -- *valp = r_0; -- return 0; --} -+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { -+ { { OPERAND_art }, 'o' }, -+ { { OPERAND_ars }, 'i' } -+}; - --static int --Operand_simm7_decode (uint32 *valp) --{ -- unsigned simm7_0, imm7_0; -- imm7_0 = *valp & 0x7f; -- simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; -- *valp = simm7_0; -- return 0; --} -+static xtensa_iclass_internal iclasses[] = { -+ { 0, 0 /* xt_iclass_excw */, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_rfe */, -+ 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, -+ { 0, 0 /* xt_iclass_rfde */, -+ 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, -+ { 0, 0 /* xt_iclass_syscall */, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_simcall */, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_add_n_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_addi_n_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_bz6_args, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_ill_n */, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_loadi4_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_mov_n_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_movi_n_args, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_nopn */, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_retn_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_storei4_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_addi_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_addmi_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_addsub_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_bit_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_bsi8_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_bsi8b_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_bsi8u_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_bst8_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_bsz12_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_call0_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_callx0_args, -+ 0, 0, 0, 0 }, -+ { 4, Iclass_xt_iclass_exti_args, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_ill */, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_jump_args, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_jumpx_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_l16ui_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_l16si_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_l32i_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_l32r_args, -+ 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, -+ { 3, Iclass_xt_iclass_l8i_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_movi_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_movz_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_neg_args, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_nop */, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_return_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_s16i_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_s32i_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_s8i_args, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_sar_args, -+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_sari_args, -+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, -+ { 2, Iclass_xt_iclass_shifts_args, -+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, -+ { 3, Iclass_xt_iclass_shiftst_args, -+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, -+ { 2, Iclass_xt_iclass_shiftt_args, -+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, -+ { 3, Iclass_xt_iclass_slli_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_srai_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_iclass_srli_args, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_memw */, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_extw */, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_isync */, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_sync */, -+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, -+ { 2, Iclass_xt_iclass_rsil_args, -+ 3, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_sar_args, -+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_sar_args, -+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_sar_args, -+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_litbase_args, -+ 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_litbase_args, -+ 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_litbase_args, -+ 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_176_args, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_176_args, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_208_args, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_ps_args, -+ 3, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_ps_args, -+ 3, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_ps_args, -+ 3, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_epc1_args, -+ 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_epc1_args, -+ 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_epc1_args, -+ 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_excsave1_args, -+ 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_excsave1_args, -+ 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_excsave1_args, -+ 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_epc2_args, -+ 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_epc2_args, -+ 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_epc2_args, -+ 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_excsave2_args, -+ 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_excsave2_args, -+ 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_excsave2_args, -+ 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_epc3_args, -+ 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_epc3_args, -+ 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_epc3_args, -+ 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_excsave3_args, -+ 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_excsave3_args, -+ 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_excsave3_args, -+ 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_eps2_args, -+ 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_eps2_args, -+ 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_eps2_args, -+ 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_eps3_args, -+ 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_eps3_args, -+ 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_eps3_args, -+ 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_excvaddr_args, -+ 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_excvaddr_args, -+ 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_excvaddr_args, -+ 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_depc_args, -+ 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_depc_args, -+ 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_depc_args, -+ 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_exccause_args, -+ 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_exccause_args, -+ 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_exccause_args, -+ 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_prid_args, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_vecbase_args, -+ 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_vecbase_args, -+ 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_vecbase_args, -+ 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, -+ { 3, Iclass_xt_mul16_args, -+ 0, 0, 0, 0 }, -+ { 3, Iclass_xt_mul32_args, -+ 0, 0, 0, 0 }, -+ { 1, Iclass_xt_iclass_rfi_args, -+ 9, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wait_args, -+ 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_interrupt_args, -+ 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_intset_args, -+ 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_intclear_args, -+ 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_intenable_args, -+ 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_intenable_args, -+ 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_intenable_args, -+ 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, -+ { 2, Iclass_xt_iclass_break_args, -+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_break_n_args, -+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args, -+ 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args, -+ 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args, -+ 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args, -+ 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args, -+ 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args, -+ 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args, -+ 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args, -+ 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args, -+ 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args, -+ 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args, -+ 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args, -+ 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_debugcause_args, -+ 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_debugcause_args, -+ 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_debugcause_args, -+ 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_icount_args, -+ 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_icount_args, -+ 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_icount_args, -+ 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_icountlevel_args, -+ 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_icountlevel_args, -+ 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_icountlevel_args, -+ 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_ddr_args, -+ 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_ddr_args, -+ 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_ddr_args, -+ 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rfdo_args, -+ 6, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, -+ { 0, 0 /* xt_iclass_rfdd */, -+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_mmid_args, -+ 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_ccount_args, -+ 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_ccount_args, -+ 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_ccount_args, -+ 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_rsr_ccompare0_args, -+ 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_wsr_ccompare0_args, -+ 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_xsr_ccompare0_args, -+ 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_idtlb_args, -+ 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, -+ { 2, Iclass_xt_iclass_rdtlb_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_wdtlb_args, -+ 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, -+ { 1, Iclass_xt_iclass_iitlb_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_ritlb_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_witlb_args, -+ 0, 0, 0, 0 }, -+ { 2, Iclass_xt_iclass_nsa_args, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_rer */, -+ 0, 0, 0, 0 }, -+ { 0, 0 /* xt_iclass_wer */, -+ 0, 0, 0, 0 } -+}; - --static int --Operand_simm7_encode (uint32 *valp) --{ -- unsigned imm7_0, simm7_0; -- simm7_0 = *valp; -- imm7_0 = (simm7_0 & 0x7f); -- *valp = imm7_0; -- return 0; --} -+enum xtensa_iclass_id { -+ ICLASS_xt_iclass_excw, -+ ICLASS_xt_iclass_rfe, -+ ICLASS_xt_iclass_rfde, -+ ICLASS_xt_iclass_syscall, -+ ICLASS_xt_iclass_simcall, -+ ICLASS_xt_iclass_add_n, -+ ICLASS_xt_iclass_addi_n, -+ ICLASS_xt_iclass_bz6, -+ ICLASS_xt_iclass_ill_n, -+ ICLASS_xt_iclass_loadi4, -+ ICLASS_xt_iclass_mov_n, -+ ICLASS_xt_iclass_movi_n, -+ ICLASS_xt_iclass_nopn, -+ ICLASS_xt_iclass_retn, -+ ICLASS_xt_iclass_storei4, -+ ICLASS_xt_iclass_addi, -+ ICLASS_xt_iclass_addmi, -+ ICLASS_xt_iclass_addsub, -+ ICLASS_xt_iclass_bit, -+ ICLASS_xt_iclass_bsi8, -+ ICLASS_xt_iclass_bsi8b, -+ ICLASS_xt_iclass_bsi8u, -+ ICLASS_xt_iclass_bst8, -+ ICLASS_xt_iclass_bsz12, -+ ICLASS_xt_iclass_call0, -+ ICLASS_xt_iclass_callx0, -+ ICLASS_xt_iclass_exti, -+ ICLASS_xt_iclass_ill, -+ ICLASS_xt_iclass_jump, -+ ICLASS_xt_iclass_jumpx, -+ ICLASS_xt_iclass_l16ui, -+ ICLASS_xt_iclass_l16si, -+ ICLASS_xt_iclass_l32i, -+ ICLASS_xt_iclass_l32r, -+ ICLASS_xt_iclass_l8i, -+ ICLASS_xt_iclass_movi, -+ ICLASS_xt_iclass_movz, -+ ICLASS_xt_iclass_neg, -+ ICLASS_xt_iclass_nop, -+ ICLASS_xt_iclass_return, -+ ICLASS_xt_iclass_s16i, -+ ICLASS_xt_iclass_s32i, -+ ICLASS_xt_iclass_s8i, -+ ICLASS_xt_iclass_sar, -+ ICLASS_xt_iclass_sari, -+ ICLASS_xt_iclass_shifts, -+ ICLASS_xt_iclass_shiftst, -+ ICLASS_xt_iclass_shiftt, -+ ICLASS_xt_iclass_slli, -+ ICLASS_xt_iclass_srai, -+ ICLASS_xt_iclass_srli, -+ ICLASS_xt_iclass_memw, -+ ICLASS_xt_iclass_extw, -+ ICLASS_xt_iclass_isync, -+ ICLASS_xt_iclass_sync, -+ ICLASS_xt_iclass_rsil, -+ ICLASS_xt_iclass_rsr_sar, -+ ICLASS_xt_iclass_wsr_sar, -+ ICLASS_xt_iclass_xsr_sar, -+ ICLASS_xt_iclass_rsr_litbase, -+ ICLASS_xt_iclass_wsr_litbase, -+ ICLASS_xt_iclass_xsr_litbase, -+ ICLASS_xt_iclass_rsr_176, -+ ICLASS_xt_iclass_wsr_176, -+ ICLASS_xt_iclass_rsr_208, -+ ICLASS_xt_iclass_rsr_ps, -+ ICLASS_xt_iclass_wsr_ps, -+ ICLASS_xt_iclass_xsr_ps, -+ ICLASS_xt_iclass_rsr_epc1, -+ ICLASS_xt_iclass_wsr_epc1, -+ ICLASS_xt_iclass_xsr_epc1, -+ ICLASS_xt_iclass_rsr_excsave1, -+ ICLASS_xt_iclass_wsr_excsave1, -+ ICLASS_xt_iclass_xsr_excsave1, -+ ICLASS_xt_iclass_rsr_epc2, -+ ICLASS_xt_iclass_wsr_epc2, -+ ICLASS_xt_iclass_xsr_epc2, -+ ICLASS_xt_iclass_rsr_excsave2, -+ ICLASS_xt_iclass_wsr_excsave2, -+ ICLASS_xt_iclass_xsr_excsave2, -+ ICLASS_xt_iclass_rsr_epc3, -+ ICLASS_xt_iclass_wsr_epc3, -+ ICLASS_xt_iclass_xsr_epc3, -+ ICLASS_xt_iclass_rsr_excsave3, -+ ICLASS_xt_iclass_wsr_excsave3, -+ ICLASS_xt_iclass_xsr_excsave3, -+ ICLASS_xt_iclass_rsr_eps2, -+ ICLASS_xt_iclass_wsr_eps2, -+ ICLASS_xt_iclass_xsr_eps2, -+ ICLASS_xt_iclass_rsr_eps3, -+ ICLASS_xt_iclass_wsr_eps3, -+ ICLASS_xt_iclass_xsr_eps3, -+ ICLASS_xt_iclass_rsr_excvaddr, -+ ICLASS_xt_iclass_wsr_excvaddr, -+ ICLASS_xt_iclass_xsr_excvaddr, -+ ICLASS_xt_iclass_rsr_depc, -+ ICLASS_xt_iclass_wsr_depc, -+ ICLASS_xt_iclass_xsr_depc, -+ ICLASS_xt_iclass_rsr_exccause, -+ ICLASS_xt_iclass_wsr_exccause, -+ ICLASS_xt_iclass_xsr_exccause, -+ ICLASS_xt_iclass_rsr_prid, -+ ICLASS_xt_iclass_rsr_vecbase, -+ ICLASS_xt_iclass_wsr_vecbase, -+ ICLASS_xt_iclass_xsr_vecbase, -+ ICLASS_xt_mul16, -+ ICLASS_xt_mul32, -+ ICLASS_xt_iclass_rfi, -+ ICLASS_xt_iclass_wait, -+ ICLASS_xt_iclass_rsr_interrupt, -+ ICLASS_xt_iclass_wsr_intset, -+ ICLASS_xt_iclass_wsr_intclear, -+ ICLASS_xt_iclass_rsr_intenable, -+ ICLASS_xt_iclass_wsr_intenable, -+ ICLASS_xt_iclass_xsr_intenable, -+ ICLASS_xt_iclass_break, -+ ICLASS_xt_iclass_break_n, -+ ICLASS_xt_iclass_rsr_dbreaka0, -+ ICLASS_xt_iclass_wsr_dbreaka0, -+ ICLASS_xt_iclass_xsr_dbreaka0, -+ ICLASS_xt_iclass_rsr_dbreakc0, -+ ICLASS_xt_iclass_wsr_dbreakc0, -+ ICLASS_xt_iclass_xsr_dbreakc0, -+ ICLASS_xt_iclass_rsr_ibreaka0, -+ ICLASS_xt_iclass_wsr_ibreaka0, -+ ICLASS_xt_iclass_xsr_ibreaka0, -+ ICLASS_xt_iclass_rsr_ibreakenable, -+ ICLASS_xt_iclass_wsr_ibreakenable, -+ ICLASS_xt_iclass_xsr_ibreakenable, -+ ICLASS_xt_iclass_rsr_debugcause, -+ ICLASS_xt_iclass_wsr_debugcause, -+ ICLASS_xt_iclass_xsr_debugcause, -+ ICLASS_xt_iclass_rsr_icount, -+ ICLASS_xt_iclass_wsr_icount, -+ ICLASS_xt_iclass_xsr_icount, -+ ICLASS_xt_iclass_rsr_icountlevel, -+ ICLASS_xt_iclass_wsr_icountlevel, -+ ICLASS_xt_iclass_xsr_icountlevel, -+ ICLASS_xt_iclass_rsr_ddr, -+ ICLASS_xt_iclass_wsr_ddr, -+ ICLASS_xt_iclass_xsr_ddr, -+ ICLASS_xt_iclass_rfdo, -+ ICLASS_xt_iclass_rfdd, -+ ICLASS_xt_iclass_wsr_mmid, -+ ICLASS_xt_iclass_rsr_ccount, -+ ICLASS_xt_iclass_wsr_ccount, -+ ICLASS_xt_iclass_xsr_ccount, -+ ICLASS_xt_iclass_rsr_ccompare0, -+ ICLASS_xt_iclass_wsr_ccompare0, -+ ICLASS_xt_iclass_xsr_ccompare0, -+ ICLASS_xt_iclass_idtlb, -+ ICLASS_xt_iclass_rdtlb, -+ ICLASS_xt_iclass_wdtlb, -+ ICLASS_xt_iclass_iitlb, -+ ICLASS_xt_iclass_ritlb, -+ ICLASS_xt_iclass_witlb, -+ ICLASS_xt_iclass_nsa, -+ ICLASS_xt_iclass_rer, -+ ICLASS_xt_iclass_wer -+}; - --static int --Operand_uimm6_decode (uint32 *valp) -+ -+/* Opcode encodings. */ -+ -+static void -+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned uimm6_0, imm6_0; -- imm6_0 = *valp & 0x3f; -- uimm6_0 = 0x4 + (((0) << 6) | imm6_0); -- *valp = uimm6_0; -- return 0; -+ slotbuf[0] = 0x2080; - } - --static int --Operand_uimm6_encode (uint32 *valp) -+static void -+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm6_0, uimm6_0; -- uimm6_0 = *valp; -- imm6_0 = (uimm6_0 - 0x4) & 0x3f; -- *valp = imm6_0; -- return 0; -+ slotbuf[0] = 0x3000; - } - --static int --Operand_uimm6_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= pc; -- return 0; -+ slotbuf[0] = 0x3200; - } - --static int --Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += pc; -- return 0; -+ slotbuf[0] = 0x5000; - } - --static int --Operand_ai4const_decode (uint32 *valp) -+static void -+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned ai4const_0, t_0; -- t_0 = *valp & 0xf; -- ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; -- *valp = ai4const_0; -- return 0; -+ slotbuf[0] = 0x5100; - } - --static int --Operand_ai4const_encode (uint32 *valp) -+static void -+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) - { -- unsigned t_0, ai4const_0; -- ai4const_0 = *valp; -- switch (ai4const_0) -- { -- case 0xffffffff: t_0 = 0; break; -- case 0x1: t_0 = 0x1; break; -- case 0x2: t_0 = 0x2; break; -- case 0x3: t_0 = 0x3; break; -- case 0x4: t_0 = 0x4; break; -- case 0x5: t_0 = 0x5; break; -- case 0x6: t_0 = 0x6; break; -- case 0x7: t_0 = 0x7; break; -- case 0x8: t_0 = 0x8; break; -- case 0x9: t_0 = 0x9; break; -- case 0xa: t_0 = 0xa; break; -- case 0xb: t_0 = 0xb; break; -- case 0xc: t_0 = 0xc; break; -- case 0xd: t_0 = 0xd; break; -- case 0xe: t_0 = 0xe; break; -- default: t_0 = 0xf; break; -- } -- *valp = t_0; -- return 0; -+ slotbuf[0] = 0xa; - } - --static int --Operand_b4const_decode (uint32 *valp) -+static void -+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) - { -- unsigned b4const_0, r_0; -- r_0 = *valp & 0xf; -- b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; -- *valp = b4const_0; -- return 0; -+ slotbuf[0] = 0xb; - } - --static int --Operand_b4const_encode (uint32 *valp) -+static void -+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) - { -- unsigned r_0, b4const_0; -- b4const_0 = *valp; -- switch (b4const_0) -- { -- case 0xffffffff: r_0 = 0; break; -- case 0x1: r_0 = 0x1; break; -- case 0x2: r_0 = 0x2; break; -- case 0x3: r_0 = 0x3; break; -- case 0x4: r_0 = 0x4; break; -- case 0x5: r_0 = 0x5; break; -- case 0x6: r_0 = 0x6; break; -- case 0x7: r_0 = 0x7; break; -- case 0x8: r_0 = 0x8; break; -- case 0xa: r_0 = 0x9; break; -- case 0xc: r_0 = 0xa; break; -- case 0x10: r_0 = 0xb; break; -- case 0x20: r_0 = 0xc; break; -- case 0x40: r_0 = 0xd; break; -- case 0x80: r_0 = 0xe; break; -- default: r_0 = 0xf; break; -- } -- *valp = r_0; -- return 0; -+ slotbuf[0] = 0x8c; - } - --static int --Operand_b4constu_decode (uint32 *valp) -+static void -+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) - { -- unsigned b4constu_0, r_0; -- r_0 = *valp & 0xf; -- b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; -- *valp = b4constu_0; -- return 0; -+ slotbuf[0] = 0xcc; - } - --static int --Operand_b4constu_encode (uint32 *valp) -+static void -+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) - { -- unsigned r_0, b4constu_0; -- b4constu_0 = *valp; -- switch (b4constu_0) -- { -- case 0x8000: r_0 = 0; break; -- case 0x10000: r_0 = 0x1; break; -- case 0x2: r_0 = 0x2; break; -- case 0x3: r_0 = 0x3; break; -- case 0x4: r_0 = 0x4; break; -- case 0x5: r_0 = 0x5; break; -- case 0x6: r_0 = 0x6; break; -- case 0x7: r_0 = 0x7; break; -- case 0x8: r_0 = 0x8; break; -- case 0xa: r_0 = 0x9; break; -- case 0xc: r_0 = 0xa; break; -- case 0x10: r_0 = 0xb; break; -- case 0x20: r_0 = 0xc; break; -- case 0x40: r_0 = 0xd; break; -- case 0x80: r_0 = 0xe; break; -- default: r_0 = 0xf; break; -- } -- *valp = r_0; -- return 0; -+ slotbuf[0] = 0xf06d; - } - --static int --Operand_uimm8_decode (uint32 *valp) -+static void -+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) - { -- unsigned uimm8_0, imm8_0; -- imm8_0 = *valp & 0xff; -- uimm8_0 = imm8_0; -- *valp = uimm8_0; -- return 0; -+ slotbuf[0] = 0x8; - } - --static int --Operand_uimm8_encode (uint32 *valp) -+static void -+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, uimm8_0; -- uimm8_0 = *valp; -- imm8_0 = (uimm8_0 & 0xff); -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0xd; - } - --static int --Operand_uimm8x2_decode (uint32 *valp) -+static void -+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) - { -- unsigned uimm8x2_0, imm8_0; -- imm8_0 = *valp & 0xff; -- uimm8x2_0 = imm8_0 << 1; -- *valp = uimm8x2_0; -- return 0; -+ slotbuf[0] = 0xc; - } - --static int --Operand_uimm8x2_encode (uint32 *valp) -+static void -+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, uimm8x2_0; -- uimm8x2_0 = *valp; -- imm8_0 = ((uimm8x2_0 >> 1) & 0xff); -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0xf03d; - } - --static int --Operand_uimm8x4_decode (uint32 *valp) -+static void -+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) - { -- unsigned uimm8x4_0, imm8_0; -- imm8_0 = *valp & 0xff; -- uimm8x4_0 = imm8_0 << 2; -- *valp = uimm8x4_0; -- return 0; -+ slotbuf[0] = 0xf00d; - } - --static int --Operand_uimm8x4_encode (uint32 *valp) -+static void -+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, uimm8x4_0; -- uimm8x4_0 = *valp; -- imm8_0 = ((uimm8x4_0 >> 2) & 0xff); -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0x9; - } - --static int --Operand_uimm4x16_decode (uint32 *valp) -+static void -+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned uimm4x16_0, op2_0; -- op2_0 = *valp & 0xf; -- uimm4x16_0 = op2_0 << 4; -- *valp = uimm4x16_0; -- return 0; -+ slotbuf[0] = 0xc002; - } - --static int --Operand_uimm4x16_encode (uint32 *valp) -+static void -+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned op2_0, uimm4x16_0; -- uimm4x16_0 = *valp; -- op2_0 = ((uimm4x16_0 >> 4) & 0xf); -- *valp = op2_0; -- return 0; -+ slotbuf[0] = 0xd002; - } - --static int --Operand_simm8_decode (uint32 *valp) -+static void -+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned simm8_0, imm8_0; -- imm8_0 = *valp & 0xff; -- simm8_0 = ((int) imm8_0 << 24) >> 24; -- *valp = simm8_0; -- return 0; -+ slotbuf[0] = 0x800000; - } - --static int --Operand_simm8_encode (uint32 *valp) -+static void -+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, simm8_0; -- simm8_0 = *valp; -- imm8_0 = (simm8_0 & 0xff); -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0xc00000; - } - --static int --Operand_simm8x256_decode (uint32 *valp) -+static void -+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned simm8x256_0, imm8_0; -- imm8_0 = *valp & 0xff; -- simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; -- *valp = simm8x256_0; -- return 0; -+ slotbuf[0] = 0x900000; - } - --static int --Operand_simm8x256_encode (uint32 *valp) -+static void -+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, simm8x256_0; -- simm8x256_0 = *valp; -- imm8_0 = ((simm8x256_0 >> 8) & 0xff); -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0xa00000; - } - --static int --Operand_simm12b_decode (uint32 *valp) -+static void -+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned simm12b_0, imm12b_0; -- imm12b_0 = *valp & 0xfff; -- simm12b_0 = ((int) imm12b_0 << 20) >> 20; -- *valp = simm12b_0; -- return 0; -+ slotbuf[0] = 0xb00000; - } - --static int --Operand_simm12b_encode (uint32 *valp) -+static void -+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm12b_0, simm12b_0; -- simm12b_0 = *valp; -- imm12b_0 = (simm12b_0 & 0xfff); -- *valp = imm12b_0; -- return 0; -+ slotbuf[0] = 0xd00000; - } - --static int --Operand_msalp32_decode (uint32 *valp) -+static void -+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned msalp32_0, sal_0; -- sal_0 = *valp & 0x1f; -- msalp32_0 = 0x20 - sal_0; -- *valp = msalp32_0; -- return 0; -+ slotbuf[0] = 0xe00000; - } - --static int --Operand_msalp32_encode (uint32 *valp) -+static void -+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned sal_0, msalp32_0; -- msalp32_0 = *valp; -- sal_0 = (0x20 - msalp32_0) & 0x1f; -- *valp = sal_0; -- return 0; -+ slotbuf[0] = 0xf00000; - } - --static int --Operand_op2p1_decode (uint32 *valp) -+static void -+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned op2p1_0, op2_0; -- op2_0 = *valp & 0xf; -- op2p1_0 = op2_0 + 0x1; -- *valp = op2p1_0; -- return 0; -+ slotbuf[0] = 0x100000; - } - --static int --Operand_op2p1_encode (uint32 *valp) -+static void -+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned op2_0, op2p1_0; -- op2p1_0 = *valp; -- op2_0 = (op2p1_0 - 0x1) & 0xf; -- *valp = op2_0; -- return 0; -+ slotbuf[0] = 0x200000; - } - --static int --Operand_label8_decode (uint32 *valp) -+static void -+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned label8_0, imm8_0; -- imm8_0 = *valp & 0xff; -- label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); -- *valp = label8_0; -- return 0; -+ slotbuf[0] = 0x300000; - } - --static int --Operand_label8_encode (uint32 *valp) -+static void -+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, label8_0; -- label8_0 = *valp; -- imm8_0 = (label8_0 - 0x4) & 0xff; -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0x26; - } - --static int --Operand_label8_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= pc; -- return 0; -+ slotbuf[0] = 0x66; - } - --static int --Operand_label8_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += pc; -- return 0; -+ slotbuf[0] = 0xe6; - } - --static int --Operand_ulabel8_decode (uint32 *valp) -+static void -+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned ulabel8_0, imm8_0; -- imm8_0 = *valp & 0xff; -- ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); -- *valp = ulabel8_0; -- return 0; -+ slotbuf[0] = 0xa6; - } - --static int --Operand_ulabel8_encode (uint32 *valp) -+static void -+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, ulabel8_0; -- ulabel8_0 = *valp; -- imm8_0 = (ulabel8_0 - 0x4) & 0xff; -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0x6007; - } - --static int --Operand_ulabel8_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= pc; -- return 0; -+ slotbuf[0] = 0xe007; - } - --static int --Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += pc; -- return 0; -+ slotbuf[0] = 0xf6; - } - --static int --Operand_label12_decode (uint32 *valp) -+static void -+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned label12_0, imm12_0; -- imm12_0 = *valp & 0xfff; -- label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); -- *valp = label12_0; -- return 0; -+ slotbuf[0] = 0xb6; - } - --static int --Operand_label12_encode (uint32 *valp) -+static void -+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm12_0, label12_0; -- label12_0 = *valp; -- imm12_0 = (label12_0 - 0x4) & 0xfff; -- *valp = imm12_0; -- return 0; -+ slotbuf[0] = 0x1007; - } - --static int --Operand_label12_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= pc; -- return 0; -+ slotbuf[0] = 0x9007; - } - --static int --Operand_label12_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += pc; -- return 0; -+ slotbuf[0] = 0xa007; - } - --static int --Operand_soffset_decode (uint32 *valp) -+static void -+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned soffset_0, offset_0; -- offset_0 = *valp & 0x3ffff; -- soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); -- *valp = soffset_0; -- return 0; -+ slotbuf[0] = 0x2007; - } - --static int --Operand_soffset_encode (uint32 *valp) -+static void -+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned offset_0, soffset_0; -- soffset_0 = *valp; -- offset_0 = (soffset_0 - 0x4) & 0x3ffff; -- *valp = offset_0; -- return 0; -+ slotbuf[0] = 0xb007; - } - --static int --Operand_soffset_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= pc; -- return 0; -+ slotbuf[0] = 0x3007; - } - --static int --Operand_soffset_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += pc; -- return 0; -+ slotbuf[0] = 0x8007; - } - --static int --Operand_uimm16x4_decode (uint32 *valp) -+static void -+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned uimm16x4_0, imm16_0; -- imm16_0 = *valp & 0xffff; -- uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; -- *valp = uimm16x4_0; -- return 0; -+ slotbuf[0] = 0x7; - } - --static int --Operand_uimm16x4_encode (uint32 *valp) -+static void -+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm16_0, uimm16x4_0; -- uimm16x4_0 = *valp; -- imm16_0 = (uimm16x4_0 >> 2) & 0xffff; -- *valp = imm16_0; -- return 0; -+ slotbuf[0] = 0x4007; - } - --static int --Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= ((pc + 3) & ~0x3); -- return 0; -+ slotbuf[0] = 0xc007; - } - --static int --Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += ((pc + 3) & ~0x3); -- return 0; -+ slotbuf[0] = 0x5007; - } - --static int --Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0xd007; - } - --static int --Operand_mx_encode (uint32 *valp) -+static void -+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0x3) != 0; -- return error; -+ slotbuf[0] = 0x16; - } - --static int --Operand_my_decode (uint32 *valp) -+static void -+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += 2; -- return 0; -+ slotbuf[0] = 0x56; - } - --static int --Operand_my_encode (uint32 *valp) -+static void -+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); -- *valp = *valp & 1; -- return error; -+ slotbuf[0] = 0xd6; - } - --static int --Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x96; - } - --static int --Operand_mw_encode (uint32 *valp) -+static void -+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0x3) != 0; -- return error; -+ slotbuf[0] = 0x5; - } - --static int --Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) --{ -- return 0; --} -- --static int --Operand_mr0_encode (uint32 *valp) -+static void -+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0x3) != 0; -- return error; -+ slotbuf[0] = 0xc0; - } - --static int --Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x40000; - } - --static int --Operand_mr1_encode (uint32 *valp) -+static void -+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0x3) != 0; -- return error; -+ slotbuf[0] = 0; - } - --static int --Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x6; - } - --static int --Operand_mr2_encode (uint32 *valp) -+static void -+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0x3) != 0; -- return error; -+ slotbuf[0] = 0xa0; - } - --static int --Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x1002; - } - --static int --Operand_mr3_encode (uint32 *valp) -+static void -+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0x3) != 0; -- return error; -+ slotbuf[0] = 0x9002; - } - --static int --Operand_immt_decode (uint32 *valp) -+static void -+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned immt_0, t_0; -- t_0 = *valp & 0xf; -- immt_0 = t_0; -- *valp = immt_0; -- return 0; -+ slotbuf[0] = 0x2002; - } - --static int --Operand_immt_encode (uint32 *valp) -+static void -+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned t_0, immt_0; -- immt_0 = *valp; -- t_0 = immt_0 & 0xf; -- *valp = t_0; -- return 0; -+ slotbuf[0] = 0x1; - } - --static int --Operand_imms_decode (uint32 *valp) -+static void -+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imms_0, s_0; -- s_0 = *valp & 0xf; -- imms_0 = s_0; -- *valp = imms_0; -- return 0; -+ slotbuf[0] = 0x2; - } - --static int --Operand_imms_encode (uint32 *valp) -+static void -+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned s_0, imms_0; -- imms_0 = *valp; -- s_0 = imms_0 & 0xf; -- *valp = s_0; -- return 0; -+ slotbuf[0] = 0xa002; - } - --static int --Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x830000; - } - --static int --Operand_bt_encode (uint32 *valp) -+static void -+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0xf) != 0; -- return error; -+ slotbuf[0] = 0x930000; - } - --static int --Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0xa30000; - } - --static int --Operand_bs_encode (uint32 *valp) -+static void -+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0xf) != 0; -- return error; -+ slotbuf[0] = 0xb30000; - } - --static int --Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x600000; - } - --static int --Operand_br_encode (uint32 *valp) -+static void -+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0xf) != 0; -- return error; -+ slotbuf[0] = 0x600100; - } - --static int --Operand_bt2_decode (uint32 *valp) -+static void -+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 1; -- return 0; -+ slotbuf[0] = 0x20f0; - } - --static int --Operand_bt2_encode (uint32 *valp) -+static void -+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x7 << 1)) != 0; -- *valp = *valp >> 1; -- return error; -+ slotbuf[0] = 0x80; - } - --static int --Operand_bs2_decode (uint32 *valp) -+static void -+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 1; -- return 0; -+ slotbuf[0] = 0x5002; - } - --static int --Operand_bs2_encode (uint32 *valp) -+static void -+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x7 << 1)) != 0; -- *valp = *valp >> 1; -- return error; -+ slotbuf[0] = 0x6002; - } - --static int --Operand_br2_decode (uint32 *valp) -+static void -+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 1; -- return 0; -+ slotbuf[0] = 0x4002; - } - --static int --Operand_br2_encode (uint32 *valp) -+static void -+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x7 << 1)) != 0; -- *valp = *valp >> 1; -- return error; -+ slotbuf[0] = 0x400000; - } - --static int --Operand_bt4_decode (uint32 *valp) -+static void -+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 2; -- return 0; -+ slotbuf[0] = 0x401000; - } - --static int --Operand_bt4_encode (uint32 *valp) -+static void -+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x3 << 2)) != 0; -- *valp = *valp >> 2; -- return error; -+ slotbuf[0] = 0x402000; - } - --static int --Operand_bs4_decode (uint32 *valp) -+static void -+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 2; -- return 0; -+ slotbuf[0] = 0x403000; - } - --static int --Operand_bs4_encode (uint32 *valp) -+static void -+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x3 << 2)) != 0; -- *valp = *valp >> 2; -- return error; -+ slotbuf[0] = 0x404000; - } - --static int --Operand_br4_decode (uint32 *valp) -+static void -+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 2; -- return 0; -+ slotbuf[0] = 0xa10000; - } - --static int --Operand_br4_encode (uint32 *valp) -+static void -+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x3 << 2)) != 0; -- *valp = *valp >> 2; -- return error; -+ slotbuf[0] = 0x810000; - } - --static int --Operand_bt8_decode (uint32 *valp) -+static void -+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 3; -- return 0; -+ slotbuf[0] = 0x910000; - } - --static int --Operand_bt8_encode (uint32 *valp) -+static void -+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x1 << 3)) != 0; -- *valp = *valp >> 3; -- return error; -+ slotbuf[0] = 0xb10000; - } - --static int --Operand_bs8_decode (uint32 *valp) -+static void -+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 3; -- return 0; -+ slotbuf[0] = 0x10000; - } - --static int --Operand_bs8_encode (uint32 *valp) -+static void -+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x1 << 3)) != 0; -- *valp = *valp >> 3; -- return error; -+ slotbuf[0] = 0x210000; - } - --static int --Operand_br8_decode (uint32 *valp) -+static void -+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 3; -- return 0; -+ slotbuf[0] = 0x410000; - } - --static int --Operand_br8_encode (uint32 *valp) -+static void -+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0x1 << 3)) != 0; -- *valp = *valp >> 3; -- return error; -+ slotbuf[0] = 0x20c0; - } - --static int --Operand_bt16_decode (uint32 *valp) -+static void -+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 4; -- return 0; -+ slotbuf[0] = 0x20d0; - } - --static int --Operand_bt16_encode (uint32 *valp) -+static void -+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0 << 4)) != 0; -- *valp = *valp >> 4; -- return error; -+ slotbuf[0] = 0x2000; - } - --static int --Operand_bs16_decode (uint32 *valp) -+static void -+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 4; -- return 0; -+ slotbuf[0] = 0x2010; - } - --static int --Operand_bs16_encode (uint32 *valp) -+static void -+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0 << 4)) != 0; -- *valp = *valp >> 4; -- return error; -+ slotbuf[0] = 0x2020; - } - --static int --Operand_br16_decode (uint32 *valp) -+static void -+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 4; -- return 0; -+ slotbuf[0] = 0x2030; - } - --static int --Operand_br16_encode (uint32 *valp) -+static void -+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0 << 4)) != 0; -- *valp = *valp >> 4; -- return error; -+ slotbuf[0] = 0x6000; - } - --static int --Operand_brall_decode (uint32 *valp) -+static void -+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp = *valp << 4; -- return 0; -+ slotbuf[0] = 0x30300; - } - --static int --Operand_brall_encode (uint32 *valp) -+static void -+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~(0 << 4)) != 0; -- *valp = *valp >> 4; -- return error; -+ slotbuf[0] = 0x130300; - } - --static int --Operand_tp7_decode (uint32 *valp) -+static void -+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned tp7_0, t_0; -- t_0 = *valp & 0xf; -- tp7_0 = t_0 + 0x7; -- *valp = tp7_0; -- return 0; -+ slotbuf[0] = 0x610300; - } - --static int --Operand_tp7_encode (uint32 *valp) -+static void -+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned t_0, tp7_0; -- tp7_0 = *valp; -- t_0 = (tp7_0 - 0x7) & 0xf; -- *valp = t_0; -- return 0; -+ slotbuf[0] = 0x30500; - } - --static int --Operand_xt_wbr15_label_decode (uint32 *valp) -+static void -+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned xt_wbr15_label_0, xt_wbr15_imm_0; -- xt_wbr15_imm_0 = *valp & 0x7fff; -- xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); -- *valp = xt_wbr15_label_0; -- return 0; -+ slotbuf[0] = 0x130500; - } - --static int --Operand_xt_wbr15_label_encode (uint32 *valp) -+static void -+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned xt_wbr15_imm_0, xt_wbr15_label_0; -- xt_wbr15_label_0 = *valp; -- xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; -- *valp = xt_wbr15_imm_0; -- return 0; -+ slotbuf[0] = 0x610500; - } - --static int --Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= pc; -- return 0; -+ slotbuf[0] = 0x3b000; - } - --static int --Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += pc; -- return 0; -+ slotbuf[0] = 0x13b000; - } - --static int --Operand_xt_wbr18_label_decode (uint32 *valp) -+static void -+Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned xt_wbr18_label_0, xt_wbr18_imm_0; -- xt_wbr18_imm_0 = *valp & 0x3ffff; -- xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); -- *valp = xt_wbr18_label_0; -- return 0; -+ slotbuf[0] = 0x3d000; - } - --static int --Operand_xt_wbr18_label_encode (uint32 *valp) -+static void -+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned xt_wbr18_imm_0, xt_wbr18_label_0; -- xt_wbr18_label_0 = *valp; -- xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; -- *valp = xt_wbr18_imm_0; -- return 0; -+ slotbuf[0] = 0x3e600; - } - --static int --Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -+static void -+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp -= pc; -- return 0; -+ slotbuf[0] = 0x13e600; - } - --static int --Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -+static void -+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- *valp += pc; -- return 0; -+ slotbuf[0] = 0x61e600; - } - --static int --Operand_cimm8x4_decode (uint32 *valp) -+static void -+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned cimm8x4_0, imm8_0; -- imm8_0 = *valp & 0xff; -- cimm8x4_0 = (imm8_0 << 2) | 0; -- *valp = cimm8x4_0; -- return 0; -+ slotbuf[0] = 0x3b100; - } - --static int --Operand_cimm8x4_encode (uint32 *valp) -+static void -+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- unsigned imm8_0, cimm8x4_0; -- cimm8x4_0 = *valp; -- imm8_0 = (cimm8x4_0 >> 2) & 0xff; -- *valp = imm8_0; -- return 0; -+ slotbuf[0] = 0x13b100; - } - --static int --Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x61b100; - } - --static int --Operand_frr_encode (uint32 *valp) -+static void -+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0xf) != 0; -- return error; -+ slotbuf[0] = 0x3d100; - } - --static int --Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x13d100; - } - --static int --Operand_frs_encode (uint32 *valp) -+static void -+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0xf) != 0; -- return error; -+ slotbuf[0] = 0x61d100; - } - --static int --Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED) -+static void -+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- return 0; -+ slotbuf[0] = 0x3b200; - } - --static int --Operand_frt_encode (uint32 *valp) -+static void -+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) - { -- int error; -- error = (*valp & ~0xf) != 0; -- return error; -+ slotbuf[0] = 0x13b200; - } - --static xtensa_operand_internal operands[] = { -- { "soffsetx4", 10, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_soffsetx4_encode, Operand_soffsetx4_decode, -- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, -- { "uimm12x8", 3, -1, 0, -- 0, -- Operand_uimm12x8_encode, Operand_uimm12x8_decode, -- 0, 0 }, -- { "simm4", 26, -1, 0, -- 0, -- Operand_simm4_encode, Operand_simm4_decode, -- 0, 0 }, -- { "arr", 14, 0, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_arr_encode, Operand_arr_decode, -- 0, 0 }, -- { "ars", 5, 0, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_ars_encode, Operand_ars_decode, -- 0, 0 }, -- { "*ars_invisible", 5, 0, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_ars_encode, Operand_ars_decode, -- 0, 0 }, -- { "art", 0, 0, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_art_encode, Operand_art_decode, -- 0, 0 }, -- { "ar0", 123, 0, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_ar0_encode, Operand_ar0_decode, -- 0, 0 }, -- { "ar4", 124, 0, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_ar4_encode, Operand_ar4_decode, -- 0, 0 }, -- { "ar8", 125, 0, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_ar8_encode, Operand_ar8_decode, -- 0, 0 }, -- { "ar12", 126, 0, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_ar12_encode, Operand_ar12_decode, -- 0, 0 }, -- { "ars_entry", 5, 0, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_ars_entry_encode, Operand_ars_entry_decode, -- 0, 0 }, -- { "immrx4", 14, -1, 0, -- 0, -- Operand_immrx4_encode, Operand_immrx4_decode, -- 0, 0 }, -- { "lsi4x4", 14, -1, 0, -- 0, -- Operand_lsi4x4_encode, Operand_lsi4x4_decode, -- 0, 0 }, -- { "simm7", 34, -1, 0, -- 0, -- Operand_simm7_encode, Operand_simm7_decode, -- 0, 0 }, -- { "uimm6", 33, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_uimm6_encode, Operand_uimm6_decode, -- Operand_uimm6_ator, Operand_uimm6_rtoa }, -- { "ai4const", 0, -1, 0, -- 0, -- Operand_ai4const_encode, Operand_ai4const_decode, -- 0, 0 }, -- { "b4const", 14, -1, 0, -- 0, -- Operand_b4const_encode, Operand_b4const_decode, -- 0, 0 }, -- { "b4constu", 14, -1, 0, -- 0, -- Operand_b4constu_encode, Operand_b4constu_decode, -- 0, 0 }, -- { "uimm8", 4, -1, 0, -- 0, -- Operand_uimm8_encode, Operand_uimm8_decode, -- 0, 0 }, -- { "uimm8x2", 4, -1, 0, -- 0, -- Operand_uimm8x2_encode, Operand_uimm8x2_decode, -- 0, 0 }, -- { "uimm8x4", 4, -1, 0, -- 0, -- Operand_uimm8x4_encode, Operand_uimm8x4_decode, -- 0, 0 }, -- { "uimm4x16", 13, -1, 0, -- 0, -- Operand_uimm4x16_encode, Operand_uimm4x16_decode, -- 0, 0 }, -- { "simm8", 4, -1, 0, -- 0, -- Operand_simm8_encode, Operand_simm8_decode, -- 0, 0 }, -- { "simm8x256", 4, -1, 0, -- 0, -- Operand_simm8x256_encode, Operand_simm8x256_decode, -- 0, 0 }, -- { "simm12b", 6, -1, 0, -- 0, -- Operand_simm12b_encode, Operand_simm12b_decode, -- 0, 0 }, -- { "msalp32", 18, -1, 0, -- 0, -- Operand_msalp32_encode, Operand_msalp32_decode, -- 0, 0 }, -- { "op2p1", 13, -1, 0, -- 0, -- Operand_op2p1_encode, Operand_op2p1_decode, -- 0, 0 }, -- { "label8", 4, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_label8_encode, Operand_label8_decode, -- Operand_label8_ator, Operand_label8_rtoa }, -- { "ulabel8", 4, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_ulabel8_encode, Operand_ulabel8_decode, -- Operand_ulabel8_ator, Operand_ulabel8_rtoa }, -- { "label12", 3, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_label12_encode, Operand_label12_decode, -- Operand_label12_ator, Operand_label12_rtoa }, -- { "soffset", 10, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_soffset_encode, Operand_soffset_decode, -- Operand_soffset_ator, Operand_soffset_rtoa }, -- { "uimm16x4", 7, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_uimm16x4_encode, Operand_uimm16x4_decode, -- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, -- { "mx", 43, 1, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, -- Operand_mx_encode, Operand_mx_decode, -- 0, 0 }, -- { "my", 42, 1, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, -- Operand_my_encode, Operand_my_decode, -- 0, 0 }, -- { "mw", 41, 1, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_mw_encode, Operand_mw_decode, -- 0, 0 }, -- { "mr0", 127, 1, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_mr0_encode, Operand_mr0_decode, -- 0, 0 }, -- { "mr1", 128, 1, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_mr1_encode, Operand_mr1_decode, -- 0, 0 }, -- { "mr2", 129, 1, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_mr2_encode, Operand_mr2_decode, -- 0, 0 }, -- { "mr3", 130, 1, 1, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_mr3_encode, Operand_mr3_decode, -- 0, 0 }, -- { "immt", 0, -1, 0, -- 0, -- Operand_immt_encode, Operand_immt_decode, -- 0, 0 }, -- { "imms", 5, -1, 0, -- 0, -- Operand_imms_encode, Operand_imms_decode, -- 0, 0 }, -- { "bt", 0, 2, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bt_encode, Operand_bt_decode, -- 0, 0 }, -- { "bs", 5, 2, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bs_encode, Operand_bs_decode, -- 0, 0 }, -- { "br", 14, 2, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_br_encode, Operand_br_decode, -- 0, 0 }, -- { "bt2", 44, 2, 2, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bt2_encode, Operand_bt2_decode, -- 0, 0 }, -- { "bs2", 45, 2, 2, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bs2_encode, Operand_bs2_decode, -- 0, 0 }, -- { "br2", 46, 2, 2, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_br2_encode, Operand_br2_decode, -- 0, 0 }, -- { "bt4", 47, 2, 4, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bt4_encode, Operand_bt4_decode, -- 0, 0 }, -- { "bs4", 48, 2, 4, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bs4_encode, Operand_bs4_decode, -- 0, 0 }, -- { "br4", 49, 2, 4, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_br4_encode, Operand_br4_decode, -- 0, 0 }, -- { "bt8", 50, 2, 8, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bt8_encode, Operand_bt8_decode, -- 0, 0 }, -- { "bs8", 51, 2, 8, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bs8_encode, Operand_bs8_decode, -- 0, 0 }, -- { "br8", 52, 2, 8, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_br8_encode, Operand_br8_decode, -- 0, 0 }, -- { "bt16", 131, 2, 16, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bt16_encode, Operand_bt16_decode, -- 0, 0 }, -- { "bs16", 132, 2, 16, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_bs16_encode, Operand_bs16_decode, -- 0, 0 }, -- { "br16", 133, 2, 16, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_br16_encode, Operand_br16_decode, -- 0, 0 }, -- { "brall", 134, 2, 16, -- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, -- Operand_brall_encode, Operand_brall_decode, -- 0, 0 }, -- { "tp7", 0, -1, 0, -- 0, -- Operand_tp7_encode, Operand_tp7_decode, -- 0, 0 }, -- { "xt_wbr15_label", 53, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, -- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, -- { "xt_wbr18_label", 54, -1, 0, -- XTENSA_OPERAND_IS_PCRELATIVE, -- Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, -- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, -- { "cimm8x4", 4, -1, 0, -- 0, -- Operand_cimm8x4_encode, Operand_cimm8x4_decode, -- 0, 0 }, -- { "frr", 14, 3, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_frr_encode, Operand_frr_decode, -- 0, 0 }, -- { "frs", 5, 3, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_frs_encode, Operand_frs_decode, -- 0, 0 }, -- { "frt", 0, 3, 1, -- XTENSA_OPERAND_IS_REGISTER, -- Operand_frt_encode, Operand_frt_decode, -- 0, 0 }, -- { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, -- { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, -- { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, -- { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, -- { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, -- { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, -- { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, -- { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, -- { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, -- { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, -- { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, -- { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, -- { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, -- { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, -- { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, -- { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, -- { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, -- { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, -- { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, -- { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, -- { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, -- { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, -- { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, -- { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, -- { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, -- { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, -- { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, -- { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, -- { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, -- { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, -- { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, -- { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, -- { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, -- { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, -- { "t2", 44, -1, 0, 0, 0, 0, 0, 0 }, -- { "s2", 45, -1, 0, 0, 0, 0, 0, 0 }, -- { "r2", 46, -1, 0, 0, 0, 0, 0, 0 }, -- { "t4", 47, -1, 0, 0, 0, 0, 0, 0 }, -- { "s4", 48, -1, 0, 0, 0, 0, 0, 0 }, -- { "r4", 49, -1, 0, 0, 0, 0, 0, 0 }, -- { "t8", 50, -1, 0, 0, 0, 0, 0, 0 }, -- { "s8", 51, -1, 0, 0, 0, 0, 0, 0 }, -- { "r8", 52, -1, 0, 0, 0, 0, 0, 0 }, -- { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 }, -- { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 }, -- { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 }, -- { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 }, -- { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 }, -- { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 }, -- { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 }, -- { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 } --}; -- -- --/* Iclass table. */ -+static void -+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61b200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { -- { { STATE_PSRING }, 'i' }, -- { { STATE_PSEXCM }, 'm' }, -- { { STATE_EPC1 }, 'i' } --}; -+static void -+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3d200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DEPC }, 'i' } --}; -+static void -+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13d200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { -- { { 0 /* soffsetx4 */ }, 'i' }, -- { { 10 /* ar12 */ }, 'o' } --}; -+static void -+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61d200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { -- { { STATE_PSCALLINC }, 'o' } --}; -+static void -+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3b300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { -- { { 0 /* soffsetx4 */ }, 'i' }, -- { { 9 /* ar8 */ }, 'o' } --}; -+static void -+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13b300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { -- { { STATE_PSCALLINC }, 'o' } --}; -+static void -+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61b300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { -- { { 0 /* soffsetx4 */ }, 'i' }, -- { { 8 /* ar4 */ }, 'o' } --}; -+static void -+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3d300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { -- { { STATE_PSCALLINC }, 'o' } --}; -+static void -+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13d300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 10 /* ar12 */ }, 'o' } --}; -+static void -+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61d300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { -- { { STATE_PSCALLINC }, 'o' } --}; -+static void -+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3c200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 9 /* ar8 */ }, 'o' } --}; -+static void -+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13c200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { -- { { STATE_PSCALLINC }, 'o' } --}; -+static void -+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61c200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 8 /* ar4 */ }, 'o' } --}; -+static void -+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3c300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { -- { { STATE_PSCALLINC }, 'o' } --}; -+static void -+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13c300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { -- { { 11 /* ars_entry */ }, 's' }, -- { { 4 /* ars */ }, 'i' }, -- { { 1 /* uimm12x8 */ }, 'i' } --}; -+static void -+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61c300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { -- { { STATE_PSCALLINC }, 'i' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSWOE }, 'i' }, -- { { STATE_WindowBase }, 'm' }, -- { { STATE_WindowStart }, 'm' } --}; -+static void -+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3ee00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -+static void -+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13ee00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { -- { { STATE_WindowBase }, 'i' }, -- { { STATE_WindowStart }, 'i' } --}; -+static void -+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61ee00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { -- { { 2 /* simm4 */ }, 'i' } --}; -+static void -+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3c000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowBase }, 'm' } --}; -+static void -+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13c000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { -- { { 5 /* *ars_invisible */ }, 'i' } --}; -+static void -+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61c000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { -- { { STATE_WindowBase }, 'm' }, -- { { STATE_WindowStart }, 'm' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSWOE }, 'i' } --}; -+static void -+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3e800; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { -- { { STATE_EPC1 }, 'i' }, -- { { STATE_PSEXCM }, 'm' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowBase }, 'm' }, -- { { STATE_WindowStart }, 'm' }, -- { { STATE_PSOWB }, 'i' } --}; -+static void -+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13e800; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 12 /* immrx4 */ }, 'i' } --}; -+static void -+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61e800; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -+static void -+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3eb00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 12 /* immrx4 */ }, 'i' } --}; -+static void -+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3e700; -+} - --static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -+static void -+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13e700; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { -- { { 6 /* art */ }, 'o' } --}; -+static void -+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61e700; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowBase }, 'i' } --}; -+static void -+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0xc10000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { -- { { 6 /* art */ }, 'i' } --}; -+static void -+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0xd10000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowBase }, 'o' } --}; -+static void -+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x820000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { -- { { 6 /* art */ }, 'm' } --}; -+static void -+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3010; -+} - --static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowBase }, 'm' } --}; -+static void -+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x7000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowStart }, 'i' } --}; -+static void -+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3e200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { -- { { 6 /* art */ }, 'i' } --}; -+static void -+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13e200; -+} - --static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowStart }, 'o' } --}; -+static void -+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13e300; -+} - --static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { -- { { 6 /* art */ }, 'm' } --}; -+static void -+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3e400; -+} - --static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_WindowStart }, 'm' } --}; -+static void -+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13e400; -+} - --static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -+static void -+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61e400; -+} - --static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 16 /* ai4const */ }, 'i' } --}; -+static void -+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x4000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 15 /* uimm6 */ }, 'i' } --}; -+static void -+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0xf02d; -+} - --static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 13 /* lsi4x4 */ }, 'i' } --}; -+static void -+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x39000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -+static void -+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x139000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { -- { { 4 /* ars */ }, 'o' }, -- { { 14 /* simm7 */ }, 'i' } --}; -+static void -+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x619000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { -- { { 5 /* *ars_invisible */ }, 'i' } --}; -+static void -+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3a000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 13 /* lsi4x4 */ }, 'i' } --}; -+static void -+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13a000; -+} - --static xtensa_arg_internal Iclass_rur_threadptr_args[] = { -- { { 3 /* arr */ }, 'o' } --}; -+static void -+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61a000; -+} - --static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { -- { { STATE_THREADPTR }, 'i' } --}; -+static void -+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x38000; -+} - --static xtensa_arg_internal Iclass_wur_threadptr_args[] = { -- { { 6 /* art */ }, 'i' } --}; -+static void -+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x138000; -+} - --static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { -- { { STATE_THREADPTR }, 'o' } --}; -+static void -+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x618000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 23 /* simm8 */ }, 'i' } --}; -+static void -+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x36000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 24 /* simm8x256 */ }, 'i' } --}; -+static void -+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x136000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -+static void -+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x616000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -+static void -+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3e900; -+} - --static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 17 /* b4const */ }, 'i' }, -- { { 28 /* label8 */ }, 'i' } --}; -+static void -+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13e900; -+} - --static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 67 /* bbi */ }, 'i' }, -- { { 28 /* label8 */ }, 'i' } --}; -+static void -+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61e900; -+} - --static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 18 /* b4constu */ }, 'i' }, -- { { 28 /* label8 */ }, 'i' } --}; -+static void -+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3ec00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' }, -- { { 28 /* label8 */ }, 'i' } --}; -+static void -+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13ec00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 30 /* label12 */ }, 'i' } --}; -+static void -+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61ec00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { -- { { 0 /* soffsetx4 */ }, 'i' }, -- { { 7 /* ar0 */ }, 'o' } --}; -+static void -+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3ed00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 7 /* ar0 */ }, 'o' } --}; -+static void -+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13ed00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 6 /* art */ }, 'i' }, -- { { 82 /* sae */ }, 'i' }, -- { { 27 /* op2p1 */ }, 'i' } --}; -+static void -+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61ed00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { -- { { 31 /* soffset */ }, 'i' } --}; -+static void -+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x36800; -+} - --static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { -- { { 4 /* ars */ }, 'i' } --}; -+static void -+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x136800; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 20 /* uimm8x2 */ }, 'i' } --}; -+static void -+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x616800; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 20 /* uimm8x2 */ }, 'i' } --}; -+static void -+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0xf1e000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -+static void -+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0xf1e010; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 32 /* uimm16x4 */ }, 'i' } --}; -+static void -+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x135900; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { -- { { STATE_LITBADDR }, 'i' }, -- { { STATE_LITBEN }, 'i' } --}; -+static void -+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3ea00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 19 /* uimm8 */ }, 'i' } --}; -+static void -+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13ea00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 29 /* ulabel8 */ }, 'i' } --}; -+static void -+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61ea00; -+} - --static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { -- { { STATE_LBEG }, 'o' }, -- { { STATE_LEND }, 'o' }, -- { { STATE_LCOUNT }, 'o' } --}; -+static void -+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x3f000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 29 /* ulabel8 */ }, 'i' } --}; -+static void -+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x13f000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { -- { { STATE_LBEG }, 'o' }, -- { { STATE_LEND }, 'o' }, -- { { STATE_LCOUNT }, 'o' } --}; -+static void -+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x61f000; -+} - --static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 25 /* simm12b */ }, 'i' } -+static void -+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x50c000; -+} -+ -+static void -+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x50d000; -+} -+ -+static void -+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x50b000; -+} -+ -+static void -+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x50f000; -+} -+ -+static void -+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x50e000; -+} -+ -+static void -+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x504000; -+} -+ -+static void -+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x505000; -+} -+ -+static void -+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x503000; -+} -+ -+static void -+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x507000; -+} -+ -+static void -+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x506000; -+} -+ -+static void -+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x40e000; -+} -+ -+static void -+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x40f000; -+} -+ -+static void -+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x406000; -+} -+ -+static void -+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = 0x407000; -+} -+ -+xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { -+ Opcode_excw_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { -- { { 3 /* arr */ }, 'm' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { -+ Opcode_rfe_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { -+ Opcode_rfde_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { -- { { 5 /* *ars_invisible */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { -+ Opcode_syscall_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 20 /* uimm8x2 */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { -+ Opcode_simcall_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { -+ 0, Opcode_add_n_Slot_inst16a_encode, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 19 /* uimm8 */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { -+ 0, Opcode_addi_n_Slot_inst16a_encode, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { -- { { 4 /* ars */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { -+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { -- { { STATE_SAR }, 'o' } -+xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { -+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { -- { { 86 /* sas */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { -+ 0, 0, Opcode_ill_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { -- { { STATE_SAR }, 'o' } -+xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { -+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { -+ 0, 0, Opcode_mov_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { -- { { STATE_SAR }, 'i' } -+xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { -+ 0, 0, Opcode_movi_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { -+ 0, 0, Opcode_nop_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { -- { { STATE_SAR }, 'i' } -+xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { -+ 0, 0, Opcode_ret_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { -+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { -- { { STATE_SAR }, 'i' } -+xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { -+ Opcode_addi_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 26 /* msalp32 */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { -+ Opcode_addmi_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 6 /* art */ }, 'i' }, -- { { 84 /* sargt */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { -+ Opcode_add_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 6 /* art */ }, 'i' }, -- { { 70 /* s */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { -+ Opcode_sub_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { -- { { STATE_XTSYNC }, 'i' } -+xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { -+ Opcode_addx2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 70 /* s */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { -+ Opcode_addx4_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { -- { { STATE_PSWOE }, 'i' }, -- { { STATE_PSCALLINC }, 'i' }, -- { { STATE_PSOWB }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_PSUM }, 'i' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSINTLEVEL }, 'm' } -+xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { -+ Opcode_addx8_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { -+ Opcode_subx2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { -- { { STATE_LEND }, 'i' } -+xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { -+ Opcode_subx4_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { -+ Opcode_subx8_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { -- { { STATE_LEND }, 'o' } -+xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { -+ Opcode_and_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { -+ Opcode_or_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { -- { { STATE_LEND }, 'm' } -+xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { -+ Opcode_xor_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { -+ Opcode_beqi_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { -- { { STATE_LCOUNT }, 'i' } -+xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { -+ Opcode_bnei_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { -+ Opcode_bgei_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_LCOUNT }, 'o' } -+xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { -+ Opcode_blti_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { -+ Opcode_bbci_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_LCOUNT }, 'm' } -+xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { -+ Opcode_bbsi_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { -+ Opcode_bgeui_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { -- { { STATE_LBEG }, 'i' } -+xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { -+ Opcode_bltui_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { -+ Opcode_beq_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { -- { { STATE_LBEG }, 'o' } -+xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { -+ Opcode_bne_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { -+ Opcode_bge_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { -- { { STATE_LBEG }, 'm' } -+xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { -+ Opcode_blt_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { -+ Opcode_bgeu_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { -- { { STATE_SAR }, 'i' } -+xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { -+ Opcode_bltu_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { -+ Opcode_bany_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { -- { { STATE_SAR }, 'o' }, -- { { STATE_XTSYNC }, 'o' } -+xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { -+ Opcode_bnone_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { -+ Opcode_ball_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { -- { { STATE_SAR }, 'm' } -+xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { -+ Opcode_bnall_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { -+ Opcode_bbc_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { -- { { STATE_LITBADDR }, 'i' }, -- { { STATE_LITBEN }, 'i' } -+xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { -+ Opcode_bbs_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { -+ Opcode_beqz_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { -- { { STATE_LITBADDR }, 'o' }, -- { { STATE_LITBEN }, 'o' } -+xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { -+ Opcode_bnez_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { -+ Opcode_bgez_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { -- { { STATE_LITBADDR }, 'm' }, -- { { STATE_LITBEN }, 'm' } -+xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { -+ Opcode_bltz_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { -+ Opcode_call0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } -+xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { -+ Opcode_callx0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { -+ Opcode_extui_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } -+xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { -+ Opcode_ill_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { -+ Opcode_j_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { -- { { STATE_PSWOE }, 'i' }, -- { { STATE_PSCALLINC }, 'i' }, -- { { STATE_PSOWB }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_PSUM }, 'i' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSINTLEVEL }, 'i' } -+xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { -+ Opcode_jx_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { -+ Opcode_l16ui_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { -- { { STATE_PSWOE }, 'o' }, -- { { STATE_PSCALLINC }, 'o' }, -- { { STATE_PSOWB }, 'o' }, -- { { STATE_PSRING }, 'm' }, -- { { STATE_PSUM }, 'o' }, -- { { STATE_PSEXCM }, 'm' }, -- { { STATE_PSINTLEVEL }, 'o' } -+xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { -+ Opcode_l16si_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { -+ Opcode_l32i_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { -- { { STATE_PSWOE }, 'm' }, -- { { STATE_PSCALLINC }, 'm' }, -- { { STATE_PSOWB }, 'm' }, -- { { STATE_PSRING }, 'm' }, -- { { STATE_PSUM }, 'm' }, -- { { STATE_PSEXCM }, 'm' }, -- { { STATE_PSINTLEVEL }, 'm' } -+xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { -+ Opcode_l32r_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { -+ Opcode_l8ui_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC1 }, 'i' } -+xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { -+ Opcode_movi_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { -+ Opcode_moveqz_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC1 }, 'o' } -+xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { -+ Opcode_movnez_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { -+ Opcode_movltz_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC1 }, 'm' } -+xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { -+ Opcode_movgez_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { -+ Opcode_neg_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE1 }, 'i' } -+xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { -+ Opcode_abs_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { -+ Opcode_nop_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE1 }, 'o' } -+xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { -+ Opcode_ret_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { -+ Opcode_s16i_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE1 }, 'm' } -+xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { -+ Opcode_s32i_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { -+ Opcode_s8i_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC2 }, 'i' } -+xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { -+ Opcode_ssr_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { -+ Opcode_ssl_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC2 }, 'o' } -+xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { -+ Opcode_ssa8l_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { -+ Opcode_ssa8b_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC2 }, 'm' } -+xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { -+ Opcode_ssai_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { -+ Opcode_sll_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE2 }, 'i' } -+xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { -+ Opcode_src_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { -+ Opcode_srl_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE2 }, 'o' } -+xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { -+ Opcode_sra_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { -+ Opcode_slli_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE2 }, 'm' } -+xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { -+ Opcode_srai_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { -+ Opcode_srli_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC3 }, 'i' } -+xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { -+ Opcode_memw_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { -+ Opcode_extw_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC3 }, 'o' } -+xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { -+ Opcode_isync_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { -+ Opcode_rsync_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC3 }, 'm' } -+xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { -+ Opcode_esync_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { -+ Opcode_dsync_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE3 }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { -+ Opcode_rsil_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { -+ Opcode_rsr_sar_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE3 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { -+ Opcode_wsr_sar_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { -+ Opcode_xsr_sar_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE3 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { -+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { -+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC4 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { -+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { -+ Opcode_rsr_176_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC4 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { -+ Opcode_wsr_176_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { -+ Opcode_rsr_208_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC4 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { -+ Opcode_rsr_ps_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { -+ Opcode_wsr_ps_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE4 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { -+ Opcode_xsr_ps_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { -+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE4 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { -+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { -+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE4 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { -+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { -+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC5 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { -+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { -+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC5 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { -+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { -+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC5 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { -+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { -+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE5 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { -+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { -+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE5 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { -+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { -+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE5 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { -+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { -+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC6 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { -+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { -+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC6 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { -+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { -+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC6 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { -+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { -+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE6 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { -+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { -+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE6 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { -+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { -+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE6 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { -+ Opcode_rsr_depc_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { -+ Opcode_wsr_depc_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC7 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { -+ Opcode_xsr_depc_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { -+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC7 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { -+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { -+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPC7 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { -+ Opcode_rsr_prid_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { -+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE7 }, 'i' } -+xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { -+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { -+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE7 }, 'o' } -+xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { -+ Opcode_mul16u_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { -+ Opcode_mul16s_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCSAVE7 }, 'm' } -+xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { -+ Opcode_mull_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { -+ Opcode_rfi_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS2 }, 'i' } -+xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { -+ Opcode_waiti_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { -+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS2 }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { -+ Opcode_wsr_intset_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { -+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS2 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { -+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { -+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS3 }, 'i' } -+xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { -+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { -+ Opcode_break_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS3 }, 'o' } -+xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { -+ 0, 0, Opcode_break_n_Slot_inst16b_encode - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { -+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS3 }, 'm' } -+xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { -+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { -+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS4 }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { -+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { -+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS4 }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { -+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { -+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS4 }, 'm' } -+xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { -+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { -+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS5 }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { -+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { -+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS5 }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { -+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { -+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS5 }, 'm' } -+xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { -+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { -+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS6 }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { -+ Opcode_rsr_icount_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { -+ Opcode_wsr_icount_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS6 }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { -+ Opcode_xsr_icount_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { -+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS6 }, 'm' } -+xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { -+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { -+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS7 }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { -+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { -+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS7 }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { -+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { -+ Opcode_rfdo_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EPS7 }, 'm' } -+xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { -+ Opcode_rfdd_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { -+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCVADDR }, 'i' } -+xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { -+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { -+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCVADDR }, 'o' } -+xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { -+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { -+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCVADDR }, 'm' } -+xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { -+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DEPC }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DEPC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DEPC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCCAUSE }, 'i' }, -- { { STATE_XTSYNC }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCCAUSE }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_EXCCAUSE }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC0 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC0 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC0 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC1 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC1 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC2 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC2 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC2 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC3 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC3 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_MISC3 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_VECBASE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_VECBASE }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_VECBASE }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { -- { { STATE_ACC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 34 /* my */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { -- { { STATE_ACC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { -- { { 33 /* mx */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { -- { { STATE_ACC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { -- { { 33 /* mx */ }, 'i' }, -- { { 34 /* my */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { -- { { STATE_ACC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { -- { { STATE_ACC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 34 /* my */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { -- { { STATE_ACC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { -- { { 33 /* mx */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { -- { { STATE_ACC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { -- { { 33 /* mx */ }, 'i' }, -- { { 34 /* my */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { -- { { STATE_ACC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { -- { { 35 /* mw */ }, 'o' }, -- { { 4 /* ars */ }, 'm' }, -- { { 33 /* mx */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { -- { { STATE_ACC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { -- { { 35 /* mw */ }, 'o' }, -- { { 4 /* ars */ }, 'm' }, -- { { 33 /* mx */ }, 'i' }, -- { { 34 /* my */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { -- { { STATE_ACC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { -- { { 35 /* mw */ }, 'o' }, -- { { 4 /* ars */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 36 /* mr0 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 36 /* mr0 */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { -- { { 6 /* art */ }, 'm' }, -- { { 36 /* mr0 */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 37 /* mr1 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 37 /* mr1 */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { -- { { 6 /* art */ }, 'm' }, -- { { 37 /* mr1 */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 38 /* mr2 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 38 /* mr2 */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { -- { { 6 /* art */ }, 'm' }, -- { { 38 /* mr2 */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 39 /* mr3 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 39 /* mr3 */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { -- { { 6 /* art */ }, 'm' }, -- { { 39 /* mr3 */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { -- { { STATE_ACC }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { -- { { STATE_ACC }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { -+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { -- { { STATE_ACC }, 'm' } -+xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { -+ Opcode_idtlb_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { -+ Opcode_pdtlb_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { -- { { STATE_ACC }, 'i' } -+xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { -+ Opcode_rdtlb0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { -+ Opcode_rdtlb1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { -- { { STATE_ACC }, 'm' } -+xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { -+ Opcode_wdtlb_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { -- { { 6 /* art */ }, 'm' } -+xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { -+ Opcode_iitlb_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { -- { { STATE_ACC }, 'm' } -+xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { -+ Opcode_pitlb_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { -- { { 70 /* s */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { -+ Opcode_ritlb0_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { -- { { STATE_PSWOE }, 'o' }, -- { { STATE_PSCALLINC }, 'o' }, -- { { STATE_PSOWB }, 'o' }, -- { { STATE_PSRING }, 'm' }, -- { { STATE_PSUM }, 'o' }, -- { { STATE_PSEXCM }, 'm' }, -- { { STATE_PSINTLEVEL }, 'o' }, -- { { STATE_EPC1 }, 'i' }, -- { { STATE_EPC2 }, 'i' }, -- { { STATE_EPC3 }, 'i' }, -- { { STATE_EPC4 }, 'i' }, -- { { STATE_EPC5 }, 'i' }, -- { { STATE_EPC6 }, 'i' }, -- { { STATE_EPC7 }, 'i' }, -- { { STATE_EPS2 }, 'i' }, -- { { STATE_EPS3 }, 'i' }, -- { { STATE_EPS4 }, 'i' }, -- { { STATE_EPS5 }, 'i' }, -- { { STATE_EPS6 }, 'i' }, -- { { STATE_EPS7 }, 'i' }, -- { { STATE_InOCDMode }, 'm' } -+xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { -+ Opcode_ritlb1_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { -- { { 70 /* s */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { -+ Opcode_witlb_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_PSINTLEVEL }, 'o' } -+xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { -+ Opcode_nsa_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { -- { { 6 /* art */ }, 'o' } -+xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { -+ Opcode_nsau_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_INTERRUPT }, 'i' } -+xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { -+ Opcode_rer_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { -- { { 6 /* art */ }, 'i' } -+xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { -+ Opcode_wer_Slot_inst_encode, 0, 0 - }; - --static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_INTERRUPT }, 'm' } --}; -+ -+/* Opcode table. */ - --static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_INTERRUPT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_INTENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_INTENABLE }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_INTENABLE }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { -- { { 41 /* imms */ }, 'i' }, -- { { 40 /* immt */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSINTLEVEL }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { -- { { 41 /* imms */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSINTLEVEL }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKA0 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKA0 }, 'o' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKA0 }, 'm' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKC0 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKC0 }, 'o' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKC0 }, 'm' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKA1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKA1 }, 'o' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKA1 }, 'm' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKC1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKC1 }, 'o' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DBREAKC1 }, 'm' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKA0 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKA0 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKA0 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKA1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKA1 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKA1 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKENABLE }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_IBREAKENABLE }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DEBUGCAUSE }, 'i' }, -- { { STATE_DBNUM }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DEBUGCAUSE }, 'o' }, -- { { STATE_DBNUM }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DEBUGCAUSE }, 'm' }, -- { { STATE_DBNUM }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_ICOUNT }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_ICOUNT }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_ICOUNT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_ICOUNTLEVEL }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_ICOUNTLEVEL }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_ICOUNTLEVEL }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DDR }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_DDR }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_DDR }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { -- { { 41 /* imms */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { -- { { STATE_InOCDMode }, 'm' }, -- { { STATE_EPC6 }, 'i' }, -- { { STATE_PSWOE }, 'o' }, -- { { STATE_PSCALLINC }, 'o' }, -- { { STATE_PSOWB }, 'o' }, -- { { STATE_PSRING }, 'o' }, -- { { STATE_PSUM }, 'o' }, -- { { STATE_PSEXCM }, 'o' }, -- { { STATE_PSINTLEVEL }, 'o' }, -- { { STATE_EPS6 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { -- { { STATE_InOCDMode }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { -- { { 44 /* br */ }, 'o' }, -- { { 43 /* bs */ }, 'i' }, -- { { 42 /* bt */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { -- { { 42 /* bt */ }, 'o' }, -- { { 49 /* bs4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { -- { { 42 /* bt */ }, 'o' }, -- { { 52 /* bs8 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { -- { { 43 /* bs */ }, 'i' }, -- { { 28 /* label8 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { -- { { 3 /* arr */ }, 'm' }, -- { { 4 /* ars */ }, 'i' }, -- { { 42 /* bt */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 57 /* brall */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 57 /* brall */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { -- { { 6 /* art */ }, 'm' }, -- { { 57 /* brall */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOUNT }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_CCOUNT }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_CCOUNT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE0 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE0 }, 'o' }, -- { { STATE_INTERRUPT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE0 }, 'm' }, -- { { STATE_INTERRUPT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE1 }, 'o' }, -- { { STATE_INTERRUPT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE1 }, 'm' }, -- { { STATE_INTERRUPT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE2 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE2 }, 'o' }, -- { { STATE_INTERRUPT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CCOMPARE2 }, 'm' }, -- { { STATE_INTERRUPT }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 22 /* uimm4x16 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 22 /* uimm4x16 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 22 /* uimm4x16 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_PTBASE }, 'o' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_PTBASE }, 'i' }, -- { { STATE_EXCVADDR }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_PTBASE }, 'm' }, -- { { STATE_EXCVADDR }, 'i' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_ASID3 }, 'i' }, -- { { STATE_ASID2 }, 'i' }, -- { { STATE_ASID1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_ASID3 }, 'o' }, -- { { STATE_ASID2 }, 'o' }, -- { { STATE_ASID1 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_ASID3 }, 'm' }, -- { { STATE_ASID2 }, 'm' }, -- { { STATE_ASID1 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_INSTPGSZID4 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_INSTPGSZID4 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_INSTPGSZID4 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DATAPGSZID4 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DATAPGSZID4 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { -- { { STATE_XTSYNC }, 'o' }, -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_DATAPGSZID4 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_XTSYNC }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { -- { { STATE_PTBASE }, 'i' }, -- { { STATE_EXCVADDR }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { -- { { STATE_EXCVADDR }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { -- { { STATE_EXCVADDR }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CPENABLE }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { -- { { STATE_PSEXCM }, 'i' }, -- { { STATE_PSRING }, 'i' }, -- { { STATE_CPENABLE }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 58 /* tp7 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 58 /* tp7 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { -- { { 6 /* art */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { -- { { 6 /* art */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { -- { { 6 /* art */ }, 'm' }, -- { { 4 /* ars */ }, 'i' }, -- { { 21 /* uimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { -- { { STATE_SCOMPARE1 }, 'i' }, -- { { STATE_SCOMPARE1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { -- { { 6 /* art */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { -- { { STATE_SCOMPARE1 }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { -- { { STATE_SCOMPARE1 }, 'o' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { -- { { 6 /* art */ }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { -- { { STATE_SCOMPARE1 }, 'm' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_mul32_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_rur_fcr_args[] = { -- { { 3 /* arr */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { -- { { STATE_RoundMode }, 'i' }, -- { { STATE_InvalidEnable }, 'i' }, -- { { STATE_DivZeroEnable }, 'i' }, -- { { STATE_OverflowEnable }, 'i' }, -- { { STATE_UnderflowEnable }, 'i' }, -- { { STATE_InexactEnable }, 'i' }, -- { { STATE_FPreserved20 }, 'i' }, -- { { STATE_FPreserved5 }, 'i' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_wur_fcr_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { -- { { STATE_RoundMode }, 'o' }, -- { { STATE_InvalidEnable }, 'o' }, -- { { STATE_DivZeroEnable }, 'o' }, -- { { STATE_OverflowEnable }, 'o' }, -- { { STATE_UnderflowEnable }, 'o' }, -- { { STATE_InexactEnable }, 'o' }, -- { { STATE_FPreserved20 }, 'o' }, -- { { STATE_FPreserved5 }, 'o' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_rur_fsr_args[] = { -- { { 3 /* arr */ }, 'o' } --}; -- --static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { -- { { STATE_InvalidFlag }, 'i' }, -- { { STATE_DivZeroFlag }, 'i' }, -- { { STATE_OverflowFlag }, 'i' }, -- { { STATE_UnderflowFlag }, 'i' }, -- { { STATE_InexactFlag }, 'i' }, -- { { STATE_FPreserved20a }, 'i' }, -- { { STATE_FPreserved7 }, 'i' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_wur_fsr_args[] = { -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { -- { { STATE_InvalidFlag }, 'o' }, -- { { STATE_DivZeroFlag }, 'o' }, -- { { STATE_OverflowFlag }, 'o' }, -- { { STATE_UnderflowFlag }, 'o' }, -- { { STATE_InexactFlag }, 'o' }, -- { { STATE_FPreserved20a }, 'o' }, -- { { STATE_FPreserved7 }, 'o' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_args[] = { -- { { 62 /* frr */ }, 'o' }, -- { { 63 /* frs */ }, 'i' }, -- { { 64 /* frt */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_stateArgs[] = { -- { { STATE_RoundMode }, 'i' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_mac_args[] = { -- { { 62 /* frr */ }, 'm' }, -- { { 63 /* frs */ }, 'i' }, -- { { 64 /* frt */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = { -- { { STATE_RoundMode }, 'i' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_cmov_args[] = { -- { { 62 /* frr */ }, 'm' }, -- { { 63 /* frs */ }, 'i' }, -- { { 42 /* bt */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_mov_args[] = { -- { { 62 /* frr */ }, 'm' }, -- { { 63 /* frs */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_mov2_args[] = { -- { { 62 /* frr */ }, 'o' }, -- { { 63 /* frs */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_cmp_args[] = { -- { { 44 /* br */ }, 'o' }, -- { { 63 /* frs */ }, 'i' }, -- { { 64 /* frt */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_float_args[] = { -- { { 62 /* frr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 65 /* t */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_float_stateArgs[] = { -- { { STATE_RoundMode }, 'i' }, -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_int_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 63 /* frs */ }, 'i' }, -- { { 65 /* t */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_int_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_rfr_args[] = { -- { { 3 /* arr */ }, 'o' }, -- { { 63 /* frs */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_wfr_args[] = { -- { { 62 /* frr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsi_args[] = { -- { { 64 /* frt */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 61 /* cimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsiu_args[] = { -- { { 64 /* frt */ }, 'o' }, -- { { 4 /* ars */ }, 'm' }, -- { { 61 /* cimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsx_args[] = { -- { { 62 /* frr */ }, 'o' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsxu_args[] = { -- { { 62 /* frr */ }, 'o' }, -- { { 4 /* ars */ }, 'm' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssi_args[] = { -- { { 64 /* frt */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 61 /* cimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssiu_args[] = { -- { { 64 /* frt */ }, 'i' }, -- { { 4 /* ars */ }, 'm' }, -- { { 61 /* cimm8x4 */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssx_args[] = { -- { { 62 /* frr */ }, 'i' }, -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssxu_args[] = { -- { { 62 /* frr */ }, 'i' }, -- { { 4 /* ars */ }, 'm' }, -- { { 6 /* art */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = { -- { { STATE_CPENABLE }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 60 /* xt_wbr18_label */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 17 /* b4const */ }, 'i' }, -- { { 60 /* xt_wbr18_label */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 18 /* b4constu */ }, 'i' }, -- { { 60 /* xt_wbr18_label */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 67 /* bbi */ }, 'i' }, -- { { 60 /* xt_wbr18_label */ }, 'i' } --}; -- --static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = { -- { { 4 /* ars */ }, 'i' }, -- { { 6 /* art */ }, 'i' }, -- { { 60 /* xt_wbr18_label */ }, 'i' } --}; -- --static xtensa_iclass_internal iclasses[] = { -- { 0, 0 /* xt_iclass_excw */, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_rfe */, -- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, -- { 0, 0 /* xt_iclass_rfde */, -- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, -- { 0, 0 /* xt_iclass_syscall */, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_simcall */, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_call12_args, -- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_call8_args, -- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_call4_args, -- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_callx12_args, -- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_callx8_args, -- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_callx4_args, -- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_entry_args, -- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_movsp_args, -- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rotw_args, -- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_retw_args, -- 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, -- { 0, 0 /* xt_iclass_rfwou */, -- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_l32e_args, -- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_s32e_args, -- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_windowbase_args, -- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_windowbase_args, -- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_windowbase_args, -- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_windowstart_args, -- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_windowstart_args, -- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_windowstart_args, -- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_add_n_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_addi_n_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_bz6_args, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_ill_n */, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_loadi4_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_mov_n_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_movi_n_args, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_nopn */, -- 0, 0, 0, 0 }, -- { 1, Iclass_xt_iclass_retn_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_storei4_args, -- 0, 0, 0, 0 }, -- { 1, Iclass_rur_threadptr_args, -- 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, -- { 1, Iclass_wur_threadptr_args, -- 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_addi_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_addmi_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_addsub_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_bit_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_bsi8_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_bsi8b_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_bsi8u_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_bst8_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_bsz12_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_call0_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_callx0_args, -- 0, 0, 0, 0 }, -- { 4, Iclass_xt_iclass_exti_args, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_ill */, -- 0, 0, 0, 0 }, -- { 1, Iclass_xt_iclass_jump_args, -- 0, 0, 0, 0 }, -- { 1, Iclass_xt_iclass_jumpx_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_l16ui_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_l16si_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_l32i_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_l32r_args, -- 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_l8i_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_loop_args, -- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_loopz_args, -- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_movi_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_movz_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_neg_args, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_nop */, -- 0, 0, 0, 0 }, -- { 1, Iclass_xt_iclass_return_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_s16i_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_s32i_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_s8i_args, -- 0, 0, 0, 0 }, -- { 1, Iclass_xt_iclass_sar_args, -- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_sari_args, -- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_shifts_args, -- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_shiftst_args, -- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_shiftt_args, -- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_slli_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_srai_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_srli_args, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_memw */, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_extw */, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_isync */, -- 0, 0, 0, 0 }, -- { 0, 0 /* xt_iclass_sync */, -- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_rsil_args, -- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_lend_args, -- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_lend_args, -- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_lend_args, -- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_lcount_args, -- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_lcount_args, -- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_lcount_args, -- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_lbeg_args, -- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_lbeg_args, -- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_lbeg_args, -- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_sar_args, -- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_sar_args, -- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_sar_args, -- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_litbase_args, -- 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_litbase_args, -- 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_litbase_args, -- 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_176_args, -- 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_208_args, -- 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ps_args, -- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ps_args, -- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ps_args, -- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_epc1_args, -- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_epc1_args, -- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_epc1_args, -- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excsave1_args, -- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excsave1_args, -- 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excsave1_args, -- 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_epc2_args, -- 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_epc2_args, -- 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_epc2_args, -- 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excsave2_args, -- 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excsave2_args, -- 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excsave2_args, -- 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_epc3_args, -- 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_epc3_args, -- 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_epc3_args, -- 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excsave3_args, -- 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excsave3_args, -- 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excsave3_args, -- 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_epc4_args, -- 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_epc4_args, -- 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_epc4_args, -- 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excsave4_args, -- 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excsave4_args, -- 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excsave4_args, -- 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_epc5_args, -- 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_epc5_args, -- 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_epc5_args, -- 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excsave5_args, -- 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excsave5_args, -- 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excsave5_args, -- 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_epc6_args, -- 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_epc6_args, -- 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_epc6_args, -- 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excsave6_args, -- 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excsave6_args, -- 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excsave6_args, -- 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_epc7_args, -- 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_epc7_args, -- 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_epc7_args, -- 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excsave7_args, -- 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excsave7_args, -- 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excsave7_args, -- 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_eps2_args, -- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_eps2_args, -- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_eps2_args, -- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_eps3_args, -- 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_eps3_args, -- 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_eps3_args, -- 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_eps4_args, -- 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_eps4_args, -- 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_eps4_args, -- 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_eps5_args, -- 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_eps5_args, -- 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_eps5_args, -- 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_eps6_args, -- 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_eps6_args, -- 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_eps6_args, -- 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_eps7_args, -- 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_eps7_args, -- 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_eps7_args, -- 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_excvaddr_args, -- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_excvaddr_args, -- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_excvaddr_args, -- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_depc_args, -- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_depc_args, -- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_depc_args, -- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_exccause_args, -- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_exccause_args, -- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_exccause_args, -- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_misc0_args, -- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_misc0_args, -- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_misc0_args, -- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_misc1_args, -- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_misc1_args, -- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_misc1_args, -- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_misc2_args, -- 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_misc2_args, -- 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_misc2_args, -- 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_misc3_args, -- 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_misc3_args, -- 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_misc3_args, -- 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_prid_args, -- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_vecbase_args, -- 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_vecbase_args, -- 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_vecbase_args, -- 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16_aa_args, -- 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16_ad_args, -- 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16_da_args, -- 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16_dd_args, -- 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16a_aa_args, -- 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16a_ad_args, -- 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16a_da_args, -- 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16a_dd_args, -- 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, -- { 4, Iclass_xt_iclass_mac16al_da_args, -- 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, -- { 4, Iclass_xt_iclass_mac16al_dd_args, -- 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_mac16_l_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_mul16_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_rsr_m0_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_wsr_m0_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_xsr_m0_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_rsr_m1_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_wsr_m1_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_xsr_m1_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_rsr_m2_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_wsr_m2_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_xsr_m2_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_rsr_m3_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_wsr_m3_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_xsr_m3_args, -- 0, 0, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_acclo_args, -- 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_acclo_args, -- 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_acclo_args, -- 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_acchi_args, -- 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_acchi_args, -- 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_acchi_args, -- 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rfi_args, -- 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wait_args, -- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_interrupt_args, -- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_intset_args, -- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_intclear_args, -- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_intenable_args, -- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_intenable_args, -- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_intenable_args, -- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_break_args, -- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_break_n_args, -- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_dbreaka0_args, -- 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_dbreaka0_args, -- 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_dbreaka0_args, -- 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_dbreakc0_args, -- 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_dbreakc0_args, -- 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_dbreakc0_args, -- 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_dbreaka1_args, -- 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_dbreaka1_args, -- 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_dbreaka1_args, -- 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_dbreakc1_args, -- 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_dbreakc1_args, -- 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_dbreakc1_args, -- 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ibreaka0_args, -- 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ibreaka0_args, -- 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ibreaka0_args, -- 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ibreaka1_args, -- 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ibreaka1_args, -- 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ibreaka1_args, -- 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ibreakenable_args, -- 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ibreakenable_args, -- 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ibreakenable_args, -- 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_debugcause_args, -- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_debugcause_args, -- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_debugcause_args, -- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_icount_args, -- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_icount_args, -- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_icount_args, -- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_icountlevel_args, -- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_icountlevel_args, -- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_icountlevel_args, -- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ddr_args, -- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ddr_args, -- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ddr_args, -- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rfdo_args, -- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, -- { 0, 0 /* xt_iclass_rfdd */, -- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_mmid_args, -- 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_bbool1_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_bbool4_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_bbool8_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_bbranch_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_bmove_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_RSR_BR_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_WSR_BR_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_XSR_BR_args, -- 0, 0, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ccount_args, -- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ccount_args, -- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ccount_args, -- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ccompare0_args, -- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ccompare0_args, -- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ccompare0_args, -- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ccompare1_args, -- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ccompare1_args, -- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ccompare1_args, -- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ccompare2_args, -- 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ccompare2_args, -- 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ccompare2_args, -- 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_icache_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_icache_lock_args, -- 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_icache_inv_args, -- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_licx_args, -- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_sicx_args, -- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_dcache_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_dcache_ind_args, -- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_dcache_inv_args, -- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_dpf_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_dcache_lock_args, -- 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_sdct_args, -- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_ldct_args, -- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_ptevaddr_args, -- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_ptevaddr_args, -- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_ptevaddr_args, -- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_rasid_args, -- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_rasid_args, -- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_rasid_args, -- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_itlbcfg_args, -- 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_itlbcfg_args, -- 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_itlbcfg_args, -- 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, -- 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, -- 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, -- 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_idtlb_args, -- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_rdtlb_args, -- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_wdtlb_args, -- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_iitlb_args, -- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_ritlb_args, -- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_witlb_args, -- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, -- { 0, 0 /* xt_iclass_ldpte */, -- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, -- { 0, 0 /* xt_iclass_hwwitlba */, -- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, -- { 0, 0 /* xt_iclass_hwwdtlba */, -- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_cpenable_args, -- 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_cpenable_args, -- 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_cpenable_args, -- 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_clamp_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_minmax_args, -- 0, 0, 0, 0 }, -- { 2, Iclass_xt_iclass_nsa_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_sx_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_l32ai_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_s32ri_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_s32c1i_args, -- 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_rsr_scompare1_args, -- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_wsr_scompare1_args, -- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, -- { 1, Iclass_xt_iclass_xsr_scompare1_args, -- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, -- { 3, Iclass_xt_iclass_div_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_mul32_args, -- 0, 0, 0, 0 }, -- { 1, Iclass_rur_fcr_args, -- 9, Iclass_rur_fcr_stateArgs, 0, 0 }, -- { 1, Iclass_wur_fcr_args, -- 9, Iclass_wur_fcr_stateArgs, 0, 0 }, -- { 1, Iclass_rur_fsr_args, -- 8, Iclass_rur_fsr_stateArgs, 0, 0 }, -- { 1, Iclass_wur_fsr_args, -- 8, Iclass_wur_fsr_stateArgs, 0, 0 }, -- { 3, Iclass_fp_args, -- 2, Iclass_fp_stateArgs, 0, 0 }, -- { 3, Iclass_fp_mac_args, -- 2, Iclass_fp_mac_stateArgs, 0, 0 }, -- { 3, Iclass_fp_cmov_args, -- 1, Iclass_fp_cmov_stateArgs, 0, 0 }, -- { 3, Iclass_fp_mov_args, -- 1, Iclass_fp_mov_stateArgs, 0, 0 }, -- { 2, Iclass_fp_mov2_args, -- 1, Iclass_fp_mov2_stateArgs, 0, 0 }, -- { 3, Iclass_fp_cmp_args, -- 1, Iclass_fp_cmp_stateArgs, 0, 0 }, -- { 3, Iclass_fp_float_args, -- 2, Iclass_fp_float_stateArgs, 0, 0 }, -- { 3, Iclass_fp_int_args, -- 1, Iclass_fp_int_stateArgs, 0, 0 }, -- { 2, Iclass_fp_rfr_args, -- 1, Iclass_fp_rfr_stateArgs, 0, 0 }, -- { 2, Iclass_fp_wfr_args, -- 1, Iclass_fp_wfr_stateArgs, 0, 0 }, -- { 3, Iclass_fp_lsi_args, -- 1, Iclass_fp_lsi_stateArgs, 0, 0 }, -- { 3, Iclass_fp_lsiu_args, -- 1, Iclass_fp_lsiu_stateArgs, 0, 0 }, -- { 3, Iclass_fp_lsx_args, -- 1, Iclass_fp_lsx_stateArgs, 0, 0 }, -- { 3, Iclass_fp_lsxu_args, -- 1, Iclass_fp_lsxu_stateArgs, 0, 0 }, -- { 3, Iclass_fp_ssi_args, -- 1, Iclass_fp_ssi_stateArgs, 0, 0 }, -- { 3, Iclass_fp_ssiu_args, -- 1, Iclass_fp_ssiu_stateArgs, 0, 0 }, -- { 3, Iclass_fp_ssx_args, -- 1, Iclass_fp_ssx_stateArgs, 0, 0 }, -- { 3, Iclass_fp_ssxu_args, -- 1, Iclass_fp_ssxu_stateArgs, 0, 0 }, -- { 2, Iclass_xt_iclass_wb18_0_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_wb18_1_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_wb18_2_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_wb18_3_args, -- 0, 0, 0, 0 }, -- { 3, Iclass_xt_iclass_wb18_4_args, -- 0, 0, 0, 0 } --}; -- -- --/* Opcode encodings. */ -- --static void --Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2080; --} -- --static void --Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3000; --} -- --static void --Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3200; --} -- --static void --Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5000; --} -- --static void --Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5100; --} -- --static void --Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x35; --} -- --static void --Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x25; --} -- --static void --Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x15; --} -- --static void --Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf0; --} -- --static void --Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe0; --} -- --static void --Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd0; --} -- --static void --Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x36; --} -- --static void --Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1000; --} -- --static void --Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x408000; --} -- --static void --Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x90; --} -- --static void --Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf01d; --} -- --static void --Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3400; --} -- --static void --Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3500; --} -- --static void --Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x90000; --} -- --static void --Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x490000; --} -- --static void --Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x34800; --} -- --static void --Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x134800; --} -- --static void --Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x614800; --} -- --static void --Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x34900; --} -- --static void --Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x134900; --} -- --static void --Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x614900; --} -- --static void --Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa; --} -- --static void --Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb; --} -- --static void --Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3000; --} -- --static void --Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8c; --} -- --static void --Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xcc; --} -- --static void --Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf06d; --} -- --static void --Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8; --} -- --static void --Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd; --} -- --static void --Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6000; --} -- --static void --Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa3000; --} -- --static void --Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc080; --} -- --static void --Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc; --} -- --static void --Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc000; --} -- --static void --Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf03d; --} -- --static void --Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf00d; --} -- --static void --Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9; --} -- --static void --Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe30e70; --} -- --static void --Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf3e700; --} -- --static void --Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc002; --} -- --static void --Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x60000; --} -- --static void --Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200c00; --} -- --static void --Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd002; --} -- --static void --Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x70000; --} -- --static void --Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200d00; --} -- --static void --Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x800000; --} -- --static void --Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x92000; --} -- --static void --Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2000; --} -- --static void --Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x80000; --} -- --static void --Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc00000; --} -- --static void --Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa8000; --} -- --static void --Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa000; --} -- --static void --Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc0000; --} -- --static void --Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x900000; --} -- --static void --Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x94000; --} -- --static void --Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4000; --} -- --static void --Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x90000; --} -- --static void --Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa00000; --} -- --static void --Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x98000; --} -- --static void --Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5000; --} -- --static void --Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa0000; --} -- --static void --Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb00000; --} -- --static void --Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x93000; --} -- --static void --Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb0000; --} -- --static void --Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd00000; --} -- --static void --Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd0000; --} -- --static void --Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe00000; --} -- --static void --Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe0000; --} -- --static void --Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf00000; --} -- --static void --Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf0000; --} -- --static void --Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x100000; --} -- --static void --Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x95000; --} -- --static void --Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6000; --} -- --static void --Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x10000; --} -- --static void --Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200000; --} -- --static void --Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9e000; --} -- --static void --Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7000; --} -- --static void --Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x20000; --} -- --static void --Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x300000; --} -- --static void --Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb0000; --} -- --static void --Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb000; --} -- --static void --Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30000; --} -- --static void --Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x26; --} -- --static void --Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x66; --} -- --static void --Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe6; --} -- --static void --Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa6; --} -- --static void --Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6007; --} -- --static void --Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe007; --} -- --static void --Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf6; --} -- --static void --Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb6; --} -- --static void --Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1007; --} -- --static void --Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9007; --} -- --static void --Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa007; --} -- --static void --Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2007; --} -- --static void --Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb007; --} -- --static void --Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3007; --} -- --static void --Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8007; --} -- --static void --Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7; --} -- --static void --Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4007; --} -- --static void --Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc007; --} -- --static void --Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5007; --} -- --static void --Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd007; --} -- --static void --Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x16; --} -- --static void --Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x56; --} -- --static void --Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd6; --} -- --static void --Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x96; --} -- --static void --Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5; --} -- --static void --Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc0; --} -- --static void --Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40000; --} -- --static void --Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40000; --} -- --static void --Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4000; --} -- --static void --Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0; --} -- --static void --Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6; --} -- --static void --Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc0000; --} -- --static void --Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa0; --} -- --static void --Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa3010; --} -- --static void --Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1002; --} -- --static void --Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200100; --} -- --static void --Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9002; --} -- --static void --Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200900; --} -- --static void --Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2002; --} -- --static void --Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200200; --} -- --static void --Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1; --} -- --static void --Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x100000; --} -- --static void --Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2; --} -- --static void --Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200000; --} -- --static void --Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8076; --} -- --static void --Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9076; --} -- --static void --Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa076; --} -- --static void --Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa002; --} -- --static void --Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x80000; --} -- --static void --Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200a00; --} -- --static void --Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x830000; --} -- --static void --Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x96000; --} -- --static void --Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x83000; --} -- --static void --Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x930000; --} -- --static void --Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9a000; --} -- --static void --Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x93000; --} -- --static void --Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa30000; --} -- --static void --Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x99000; --} -- --static void --Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa3000; --} -- --static void --Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb30000; --} -- --static void --Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x97000; --} -- --static void --Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb3000; --} -- --static void --Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x600000; --} -- --static void --Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa5000; --} -- --static void --Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd100; --} -- --static void --Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x60000; --} -- --static void --Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x600100; --} -- --static void --Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd000; --} -- --static void --Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x60010; --} -- --static void --Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x20f0; --} -- --static void --Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa3040; --} -- --static void --Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc090; --} -- --static void --Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc8000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x20f; --} -- --static void --Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x80; --} -- --static void --Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5002; --} -- --static void --Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200500; --} -- --static void --Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6002; --} -- --static void --Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200600; --} -- --static void --Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4002; --} -- --static void --Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x200400; --} -- --static void --Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x400000; --} -- --static void --Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40000; --} -- --static void --Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x401000; --} -- --static void --Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa3020; --} -- --static void --Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40100; --} -- --static void --Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x402000; --} -- --static void --Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40200; --} -- --static void --Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x403000; --} -- --static void --Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40300; --} -- --static void --Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x404000; --} -- --static void --Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40400; --} -- --static void --Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa10000; --} -- --static void --Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa6000; --} -- --static void --Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa1000; --} -- --static void --Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x810000; --} -- --static void --Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa2000; --} -- --static void --Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x81000; --} -- --static void --Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x910000; --} -- --static void --Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa5200; --} -- --static void --Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd400; --} -- --static void --Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x91000; --} -- --static void --Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb10000; --} -- --static void --Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa5100; --} -- --static void --Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd200; --} -- --static void --Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb1000; --} -- --static void --Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x10000; --} -- --static void --Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x90000; --} -- --static void --Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1000; --} -- --static void --Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x210000; --} -- --static void --Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa0000; --} -- --static void --Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe000; --} -- --static void --Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x21000; --} -- --static void --Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x410000; --} -- --static void --Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa4000; --} -- --static void --Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9000; --} -- --static void --Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x41000; --} -- --static void --Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x20c0; --} -- --static void --Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x20d0; --} -- --static void --Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2000; --} -- --static void --Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2010; --} -- --static void --Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2020; --} -- --static void --Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2030; --} -- --static void --Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6000; --} -- --static void --Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30100; --} -- --static void --Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x130100; --} -- --static void --Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x610100; --} -- --static void --Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30200; --} -- --static void --Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x130200; --} -- --static void --Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x610200; --} -- --static void --Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30000; --} -- --static void --Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x130000; --} -- --static void --Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x610000; --} -- --static void --Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30300; --} -- --static void --Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x130300; --} -- --static void --Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x610300; --} -- --static void --Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30500; --} -- --static void --Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x130500; --} -- --static void --Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x610500; --} -- --static void --Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b000; --} -- --static void --Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d000; --} -- --static void --Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e600; --} -- --static void --Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e600; --} -- --static void --Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61e600; --} -- --static void --Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b100; --} -- --static void --Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13b100; --} -- --static void --Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61b100; --} -- --static void --Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d100; --} -- --static void --Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13d100; --} -- --static void --Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61d100; --} -- --static void --Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b200; --} -- --static void --Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13b200; --} -- --static void --Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61b200; --} -- --static void --Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d200; --} -- --static void --Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13d200; --} -- --static void --Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61d200; --} -- --static void --Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b300; --} -- --static void --Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13b300; --} -- --static void --Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61b300; --} -- --static void --Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d300; --} -- --static void --Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13d300; --} -- --static void --Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61d300; --} -- --static void --Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b400; --} -- --static void --Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13b400; --} -- --static void --Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61b400; --} -- --static void --Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d400; --} -- --static void --Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13d400; --} -- --static void --Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61d400; --} -- --static void --Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b500; --} -- --static void --Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13b500; --} -- --static void --Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61b500; --} -- --static void --Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d500; --} -- --static void --Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13d500; --} -- --static void --Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61d500; --} -- --static void --Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b600; --} -- --static void --Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13b600; --} -- --static void --Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61b600; --} -- --static void --Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d600; --} -- --static void --Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13d600; --} -- --static void --Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61d600; --} -- --static void --Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b700; --} -- --static void --Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13b700; --} -- --static void --Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61b700; --} -- --static void --Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d700; --} -- --static void --Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13d700; --} -- --static void --Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61d700; --} -- --static void --Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c200; --} -- --static void --Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13c200; --} -- --static void --Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61c200; --} -- --static void --Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c300; --} -- --static void --Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13c300; --} -- --static void --Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61c300; --} -- --static void --Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c400; --} -- --static void --Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13c400; --} -- --static void --Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61c400; --} -- --static void --Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c500; --} -- --static void --Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13c500; --} -- --static void --Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61c500; --} -- --static void --Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c600; --} -- --static void --Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13c600; --} -- --static void --Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61c600; --} -- --static void --Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c700; --} -- --static void --Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13c700; --} -- --static void --Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61c700; --} -- --static void --Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3ee00; --} -- --static void --Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13ee00; --} -- --static void --Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61ee00; --} -- --static void --Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c000; --} -- --static void --Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13c000; --} -- --static void --Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61c000; --} -- --static void --Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e800; --} -- --static void --Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e800; --} -- --static void --Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61e800; --} -- --static void --Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f400; --} -- --static void --Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13f400; --} -- --static void --Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61f400; --} -- --static void --Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f500; --} -- --static void --Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13f500; --} -- --static void --Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61f500; --} -- --static void --Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f600; --} -- --static void --Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13f600; --} -- --static void --Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61f600; --} -- --static void --Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f700; --} -- --static void --Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13f700; --} -- --static void --Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61f700; --} -- --static void --Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3eb00; --} -- --static void --Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e700; --} -- --static void --Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e700; --} -- --static void --Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61e700; --} -- --static void --Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x740004; --} -- --static void --Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x750004; --} -- --static void --Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x760004; --} -- --static void --Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x770004; --} -- --static void --Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x700004; --} -- --static void --Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x710004; --} -- --static void --Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x720004; --} -- --static void --Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x730004; --} -- --static void --Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x340004; --} -- --static void --Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x350004; --} -- --static void --Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x360004; --} -- --static void --Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x370004; --} -- --static void --Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x640004; --} -- --static void --Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x650004; --} -- --static void --Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x660004; --} -- --static void --Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x670004; --} -- --static void --Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x240004; --} -- --static void --Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x250004; --} -- --static void --Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x260004; --} -- --static void --Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x270004; --} -- --static void --Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x780004; --} -- --static void --Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x790004; --} -- --static void --Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7a0004; --} -- --static void --Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7b0004; --} -- --static void --Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7c0004; --} -- --static void --Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7d0004; --} -- --static void --Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7e0004; --} -- --static void --Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7f0004; --} -- --static void --Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x380004; --} -- --static void --Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x390004; --} -- --static void --Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3a0004; --} -- --static void --Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b0004; --} -- --static void --Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3c0004; --} -- --static void --Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3d0004; --} -- --static void --Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e0004; --} -- --static void --Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f0004; --} -- --static void --Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x680004; --} -- --static void --Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x690004; --} -- --static void --Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6a0004; --} -- --static void --Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6b0004; --} -- --static void --Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6c0004; --} -- --static void --Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6d0004; --} -- --static void --Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6e0004; --} -- --static void --Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6f0004; --} -- --static void --Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x280004; --} -- --static void --Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x290004; --} -- --static void --Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2a0004; --} -- --static void --Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2b0004; --} -- --static void --Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2c0004; --} -- --static void --Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2d0004; --} -- --static void --Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2e0004; --} -- --static void --Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2f0004; --} -- --static void --Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x580004; --} -- --static void --Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x480004; --} -- --static void --Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x590004; --} -- --static void --Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x490004; --} -- --static void --Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5a0004; --} -- --static void --Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4a0004; --} -- --static void --Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5b0004; --} -- --static void --Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4b0004; --} -- --static void --Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x180004; --} -- --static void --Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x80004; --} -- --static void --Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x190004; --} -- --static void --Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x90004; --} -- --static void --Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1a0004; --} -- --static void --Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa0004; --} -- --static void --Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1b0004; --} -- --static void --Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb0004; --} -- --static void --Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x900004; --} -- --static void --Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x800004; --} -- --static void --Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc10000; --} -- --static void --Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9b000; --} -- --static void --Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc1000; --} -- --static void --Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd10000; --} -- --static void --Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9c000; --} -- --static void --Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd1000; --} -- --static void --Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x32000; --} -- --static void --Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x132000; --} -- --static void --Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x612000; --} -- --static void --Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x32100; --} -- --static void --Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x132100; --} -- --static void --Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x612100; --} -- --static void --Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x32200; --} -- --static void --Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x132200; --} -- --static void --Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x612200; --} -- --static void --Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x32300; --} -- --static void --Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x132300; --} -- --static void --Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x612300; --} -- --static void --Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x31000; --} -- --static void --Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x131000; --} -- --static void --Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x611000; --} -- --static void --Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x31100; --} -- --static void --Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x131100; --} -- --static void --Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x611100; --} -- --static void --Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3010; --} -- --static void --Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7000; --} -- --static void --Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e200; --} -- --static void --Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e200; --} -- --static void --Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e300; --} -- --static void --Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e400; --} -- --static void --Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e400; --} -- --static void --Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61e400; --} -- --static void --Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4000; --} -- --static void --Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf02d; --} -- --static void --Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x39000; --} -- --static void --Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x139000; --} -- --static void --Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x619000; --} -- --static void --Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3a000; --} -- --static void --Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13a000; --} -- --static void --Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61a000; --} -- --static void --Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x39100; --} -- --static void --Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x139100; --} -- --static void --Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x619100; --} -- --static void --Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3a100; --} -- --static void --Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13a100; --} -- --static void --Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61a100; --} -- --static void --Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x38000; --} -- --static void --Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x138000; --} -- --static void --Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x618000; --} -- --static void --Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x38100; --} -- --static void --Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x138100; --} -- --static void --Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x618100; --} -- --static void --Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x36000; --} -- --static void --Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x136000; --} -- --static void --Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x616000; --} -- --static void --Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e900; --} -- --static void --Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e900; --} -- --static void --Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61e900; --} -- --static void --Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3ec00; --} -- --static void --Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13ec00; --} -- --static void --Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61ec00; --} -- --static void --Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3ed00; --} -- --static void --Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13ed00; --} -- --static void --Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61ed00; --} -- --static void --Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x36800; --} -- --static void --Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x136800; --} -- --static void --Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x616800; --} -- --static void --Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf1e000; --} -- --static void --Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf1e010; --} -- --static void --Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x135900; --} -- --static void --Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x20000; --} -- --static void --Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x120000; --} -- --static void --Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x220000; --} -- --static void --Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x320000; --} -- --static void --Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x420000; --} -- --static void --Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8000; --} -- --static void --Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9000; --} -- --static void --Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa000; --} -- --static void --Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb000; --} -- --static void --Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x76; --} -- --static void --Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1076; --} -- --static void --Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc30000; --} -- --static void --Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd30000; --} -- --static void --Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30400; --} -- --static void --Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x130400; --} -- --static void --Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x610400; --} -- --static void --Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3ea00; --} -- --static void --Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13ea00; --} -- --static void --Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61ea00; --} -- --static void --Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f000; --} -- --static void --Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13f000; --} -- --static void --Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61f000; --} -- --static void --Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f100; --} -- --static void --Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13f100; --} -- --static void --Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61f100; --} -- --static void --Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3f200; --} -- --static void --Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13f200; --} -- --static void --Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61f200; --} -- --static void --Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x70c2; --} -- --static void --Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x70e2; --} -- --static void --Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x70d2; --} -- --static void --Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x270d2; --} -- --static void --Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x370d2; --} -- --static void --Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x70f2; --} -- --static void --Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf10000; --} -- --static void --Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf12000; --} -- --static void --Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf11000; --} -- --static void --Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf13000; --} -- --static void --Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7042; --} -- --static void --Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7052; --} -- --static void --Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x47082; --} -- --static void --Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x57082; --} -- --static void --Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7062; --} -- --static void --Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7072; --} -- --static void --Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7002; --} -- --static void --Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7012; --} -- --static void --Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7022; --} -- --static void --Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7032; --} -- --static void --Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7082; --} -- --static void --Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x27082; --} -- --static void --Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x37082; --} -- --static void --Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf19000; --} -- --static void --Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf18000; --} -- --static void --Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x135300; --} -- --static void --Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x35300; --} -- --static void --Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x615300; --} -- --static void --Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x35a00; --} -- --static void --Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x135a00; --} -- --static void --Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x615a00; --} -- --static void --Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x35b00; --} -- --static void --Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x135b00; --} -- --static void --Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x615b00; --} -- --static void --Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x35c00; --} -- --static void --Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x135c00; --} -- --static void --Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x615c00; --} -- --static void --Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x50c000; --} -- --static void --Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x50d000; --} -- --static void --Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x50b000; --} -- --static void --Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x50f000; --} -- --static void --Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x50e000; --} -- --static void --Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x504000; --} -- --static void --Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x505000; --} -- --static void --Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x503000; --} -- --static void --Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x507000; --} -- --static void --Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x506000; --} -- --static void --Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf1f000; --} -- --static void --Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x501000; --} -- --static void --Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x509000; --} -- --static void --Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3e000; --} -- --static void --Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x13e000; --} -- --static void --Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x61e000; --} -- --static void --Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x330000; --} -- --static void --Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x33000; --} -- --static void --Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x430000; --} -- --static void --Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x43000; --} -- --static void --Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x530000; --} -- --static void --Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x53000; --} -- --static void --Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x630000; --} -- --static void --Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x63000; --} -- --static void --Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x730000; --} -- --static void --Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x73000; --} -- --static void --Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40e000; --} -- --static void --Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40e00; --} -- --static void --Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40f000; --} -- --static void --Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40f00; --} -- --static void --Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x230000; --} -- --static void --Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9f000; --} -- --static void --Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8000; --} -- --static void --Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x23000; --} -- --static void --Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb002; --} -- --static void --Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf002; --} -- --static void --Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe002; --} -- --static void --Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30c00; --} -- --static void --Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x130c00; --} -- --static void --Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x610c00; --} -- --static void --Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc20000; --} -- --static void --Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xd20000; --} -- --static void --Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe20000; --} -- --static void --Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf20000; --} -- --static void --Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x820000; --} -- --static void --Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9d000; --} -- --static void --Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x82000; --} -- --static void --Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa20000; --} -- --static void --Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb20000; --} -- --static void --Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe30e80; --} -- --static void --Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf3e800; --} -- --static void --Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xe30e90; --} -- --static void --Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xf3e900; --} -- --static void --Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa0000; --} -- --static void --Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1a0000; --} -- --static void --Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2a0000; --} -- --static void --Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4a0000; --} -- --static void --Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5a0000; --} -- --static void --Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xcb0000; --} -- --static void --Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xdb0000; --} -- --static void --Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8b0000; --} -- --static void --Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9b0000; --} -- --static void --Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xab0000; --} -- --static void --Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xbb0000; --} -- --static void --Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xfa0010; --} -- --static void --Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xfa0000; --} -- --static void --Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xfa0060; --} -- --static void --Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x1b0000; --} -- --static void --Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x2b0000; --} -- --static void --Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3b0000; --} -- --static void --Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4b0000; --} -- --static void --Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x5b0000; --} -- --static void --Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x6b0000; --} -- --static void --Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x7b0000; --} -- --static void --Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xca0000; --} -- --static void --Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xda0000; --} -- --static void --Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8a0000; --} -- --static void --Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xba0000; --} -- --static void --Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xaa0000; --} -- --static void --Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x9a0000; --} -- --static void --Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xea0000; --} -- --static void --Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xfa0040; --} -- --static void --Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xfa0050; --} -- --static void --Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x3; --} -- --static void --Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8003; --} -- --static void --Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x80000; --} -- --static void --Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x180000; --} -- --static void --Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x4003; --} -- --static void --Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc003; --} -- --static void --Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x480000; --} -- --static void --Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x580000; --} -- --static void --Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa8000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xc0000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb0000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xb8000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x40000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x98000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x50000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x70000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x60000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x80000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x8000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x10000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x38000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x90000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x48000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x68000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x58000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x78000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x20000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0xa0000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x18000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x88000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x28000000; -- slotbuf[1] = 0; --} -- --static void --Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = 0x30000000; -- slotbuf[1] = 0; --} -- --xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { -- Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { -- Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { -- Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { -- Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { -- Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { -- Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { -- Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { -- Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { -- Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { -- Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { -- Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { -- Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { -- Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { -- Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { -- Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { -- 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { -- Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { -- Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { -- Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { -- Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { -- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { -- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { -- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { -- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { -- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { -- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { -- 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { -- 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { -- 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { -- 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { -- 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { -- 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { -- 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { -- 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { -- 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { -- 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { -- 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { -- Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { -- Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { -- Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { -- Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { -- Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { -- Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { -- Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { -- Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { -- Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { -- Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { -- Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { -- Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { -- Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { -- Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { -- Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { -- Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { -- Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { -- Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { -- Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { -- Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { -- Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { -- Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { -- Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { -- Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { -- Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { -- Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { -- Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { -- Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { -- Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { -- Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { -- Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { -- Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { -- Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { -- Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { -- Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { -- Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { -- Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { -- Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { -- Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { -- Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { -- Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { -- Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { -- Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { -- Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { -- Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { -- Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { -- Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { -- Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { -- Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { -- Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { -- Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { -- Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { -- Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { -- Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { -- Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { -- Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { -- Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { -- Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { -- Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { -- Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { -- Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { -- Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { -- Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { -- Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { -- Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { -- Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { -- Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { -- Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { -- Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { -- Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { -- Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { -- Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { -- Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { -- Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { -- Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { -- Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { -- Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { -- Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { -- Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { -- Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { -- Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { -- Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { -- Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { -- Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { -- Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { -- Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { -- Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { -- Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { -- Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { -- Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { -- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { -- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { -- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { -- Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { -- Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { -- Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { -- Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { -- Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { -- Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { -- Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { -- Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { -- Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { -- Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { -- Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { -- Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { -- Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { -- Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { -- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { -- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { -- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { -- Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { -- Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { -- Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { -- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { -- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { -- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { -- Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { -- Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { -- Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { -- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { -- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { -- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { -- Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { -- Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { -- Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { -- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { -- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { -- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { -- Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { -- Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { -- Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { -- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { -- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { -- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { -- Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { -- Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { -- Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { -- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { -- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { -- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { -- Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { -- Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { -- Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { -- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { -- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { -- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { -- Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { -- Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { -- Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { -- Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { -- Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { -- Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { -- Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { -- Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { -- Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { -- Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { -- Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { -- Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { -- Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { -- Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { -- Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { -- Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { -- Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { -- Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { -- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { -- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { -- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { -- Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { -- Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { -- Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { -- Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { -- Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { -- Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { -- Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { -- Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { -- Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { -- Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { -- Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { -- Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { -- Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { -- Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { -- Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { -- Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { -- Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { -- Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { -- Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { -- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { -- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { -- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { -- Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { -- Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { -- Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { -- Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { -- Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { -- Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { -- Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { -- Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { -- Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { -- Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { -- Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { -- Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { -- Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { -- Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { -- Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { -- Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { -- Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { -- Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { -- Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { -- Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { -- Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { -- Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { -- Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { -- Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { -- Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { -- Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { -- Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { -- Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { -- Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { -- Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { -- Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { -- Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { -- Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { -- Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { -- Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { -- Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { -- Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { -- Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { -- Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { -- Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { -- Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { -- Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { -- Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { -- Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { -- Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { -- Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { -- Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { -- Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { -- Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { -- Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { -- Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { -- Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { -- Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { -- Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { -- Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { -- Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { -- Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { -- Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { -- Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { -- Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { -- Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { -- Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { -- Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { -- Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { -- Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { -- Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { -- Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { -- Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { -- Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { -- Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { -- Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { -- Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { -- Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { -- Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { -- Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { -- Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { -- Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { -- Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { -- Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { -- Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { -- Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { -- Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { -- Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { -- Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { -- Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { -- Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { -- Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { -- Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { -- Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { -- Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { -- Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { -- Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { -- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { -- Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { -- Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { -- Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { -- Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { -- Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { -- Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { -- 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { -- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { -- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { -- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { -- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { -- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { -- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { -- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { -- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { -- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { -- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { -- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { -- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { -- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { -- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { -- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { -- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { -- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { -- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { -- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { -- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { -- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { -- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { -- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { -- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { -- Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { -- Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { -- Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { -- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { -- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { -- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { -- Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { -- Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { -- Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { -- Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { -- Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { -- Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { -- Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { -- Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { -- Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { -- Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { -- Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { -- Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { -- Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { -- Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { -- Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { -- Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { -- Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { -- Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { -- Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { -- Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { -- Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { -- Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { -- Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { -- Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { -- Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { -- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { -- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { -- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { -- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { -- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { -- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { -- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { -- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { -- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { -- Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { -- Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { -- Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { -- Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { -- Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { -- Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { -- Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { -- Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { -- Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { -- Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { -- Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { -- Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { -- Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { -- Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { -- Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { -- Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { -- Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { -- Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { -- Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { -- Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { -- Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { -- Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { -- Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { -- Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { -- Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { -- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { -- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { -- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { -- Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { -- Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { -- Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { -- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { -- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { -- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { -- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { -- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { -- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { -- Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { -- Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { -- Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { -- Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { -- Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { -- Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { -- Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { -- Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { -- Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { -- Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { -- Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { -- Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { -- Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { -- Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { -- Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { -- Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { -- Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { -- Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { -- Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { -- Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { -- Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { -- Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { -- Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { -- Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0 --}; -- --xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { -- Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { -- Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { -- Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { -- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { -- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { -- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { -- Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { -- Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { -- Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { -- Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { -- Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { -- Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { -- Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { -- Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { -- Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { -- Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { -- Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { -- Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { -- Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { -- Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { -- Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { -- Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { -- Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { -- Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { -- Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { -- Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { -- Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { -- Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { -- Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = { -- Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { -- Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { -- Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { -- Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { -- Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { -- Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { -- Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { -- Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { -- Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { -- Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { -- Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = { -- Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = { -- Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = { -- Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { -- Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { -- Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { -- Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { -- Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = { -- Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = { -- Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = { -- Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = { -- Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = { -- Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = { -- Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = { -- Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = { -- Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0 --}; -- --xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode --}; -- --xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = { -- 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode --}; -- -- --/* Opcode table. */ -- --static xtensa_opcode_internal opcodes[] = { -- { "excw", 0 /* xt_iclass_excw */, -- 0, -- Opcode_excw_encode_fns, 0, 0 }, -- { "rfe", 1 /* xt_iclass_rfe */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_rfe_encode_fns, 0, 0 }, -- { "rfde", 2 /* xt_iclass_rfde */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_rfde_encode_fns, 0, 0 }, -- { "syscall", 3 /* xt_iclass_syscall */, -- 0, -- Opcode_syscall_encode_fns, 0, 0 }, -- { "simcall", 4 /* xt_iclass_simcall */, -- 0, -- Opcode_simcall_encode_fns, 0, 0 }, -- { "call12", 5 /* xt_iclass_call12 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_call12_encode_fns, 0, 0 }, -- { "call8", 6 /* xt_iclass_call8 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_call8_encode_fns, 0, 0 }, -- { "call4", 7 /* xt_iclass_call4 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_call4_encode_fns, 0, 0 }, -- { "callx12", 8 /* xt_iclass_callx12 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_callx12_encode_fns, 0, 0 }, -- { "callx8", 9 /* xt_iclass_callx8 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_callx8_encode_fns, 0, 0 }, -- { "callx4", 10 /* xt_iclass_callx4 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_callx4_encode_fns, 0, 0 }, -- { "entry", 11 /* xt_iclass_entry */, -- 0, -- Opcode_entry_encode_fns, 0, 0 }, -- { "movsp", 12 /* xt_iclass_movsp */, -- 0, -- Opcode_movsp_encode_fns, 0, 0 }, -- { "rotw", 13 /* xt_iclass_rotw */, -- 0, -- Opcode_rotw_encode_fns, 0, 0 }, -- { "retw", 14 /* xt_iclass_retw */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_retw_encode_fns, 0, 0 }, -- { "retw.n", 14 /* xt_iclass_retw */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_retw_n_encode_fns, 0, 0 }, -- { "rfwo", 15 /* xt_iclass_rfwou */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_rfwo_encode_fns, 0, 0 }, -- { "rfwu", 15 /* xt_iclass_rfwou */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_rfwu_encode_fns, 0, 0 }, -- { "l32e", 16 /* xt_iclass_l32e */, -- 0, -- Opcode_l32e_encode_fns, 0, 0 }, -- { "s32e", 17 /* xt_iclass_s32e */, -- 0, -- Opcode_s32e_encode_fns, 0, 0 }, -- { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, -- 0, -- Opcode_rsr_windowbase_encode_fns, 0, 0 }, -- { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, -- 0, -- Opcode_wsr_windowbase_encode_fns, 0, 0 }, -- { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, -- 0, -- Opcode_xsr_windowbase_encode_fns, 0, 0 }, -- { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, -- 0, -- Opcode_rsr_windowstart_encode_fns, 0, 0 }, -- { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, -- 0, -- Opcode_wsr_windowstart_encode_fns, 0, 0 }, -- { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, -- 0, -- Opcode_xsr_windowstart_encode_fns, 0, 0 }, -- { "add.n", 24 /* xt_iclass_add.n */, -- 0, -- Opcode_add_n_encode_fns, 0, 0 }, -- { "addi.n", 25 /* xt_iclass_addi.n */, -- 0, -- Opcode_addi_n_encode_fns, 0, 0 }, -- { "beqz.n", 26 /* xt_iclass_bz6 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_beqz_n_encode_fns, 0, 0 }, -- { "bnez.n", 26 /* xt_iclass_bz6 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnez_n_encode_fns, 0, 0 }, -- { "ill.n", 27 /* xt_iclass_ill.n */, -- 0, -- Opcode_ill_n_encode_fns, 0, 0 }, -- { "l32i.n", 28 /* xt_iclass_loadi4 */, -- 0, -- Opcode_l32i_n_encode_fns, 0, 0 }, -- { "mov.n", 29 /* xt_iclass_mov.n */, -- 0, -- Opcode_mov_n_encode_fns, 0, 0 }, -- { "movi.n", 30 /* xt_iclass_movi.n */, -- 0, -- Opcode_movi_n_encode_fns, 0, 0 }, -- { "nop.n", 31 /* xt_iclass_nopn */, -- 0, -- Opcode_nop_n_encode_fns, 0, 0 }, -- { "ret.n", 32 /* xt_iclass_retn */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_ret_n_encode_fns, 0, 0 }, -- { "s32i.n", 33 /* xt_iclass_storei4 */, -- 0, -- Opcode_s32i_n_encode_fns, 0, 0 }, -- { "rur.threadptr", 34 /* rur_threadptr */, -- 0, -- Opcode_rur_threadptr_encode_fns, 0, 0 }, -- { "wur.threadptr", 35 /* wur_threadptr */, -- 0, -- Opcode_wur_threadptr_encode_fns, 0, 0 }, -- { "addi", 36 /* xt_iclass_addi */, -- 0, -- Opcode_addi_encode_fns, 0, 0 }, -- { "addmi", 37 /* xt_iclass_addmi */, -- 0, -- Opcode_addmi_encode_fns, 0, 0 }, -- { "add", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_add_encode_fns, 0, 0 }, -- { "sub", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_sub_encode_fns, 0, 0 }, -- { "addx2", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_addx2_encode_fns, 0, 0 }, -- { "addx4", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_addx4_encode_fns, 0, 0 }, -- { "addx8", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_addx8_encode_fns, 0, 0 }, -- { "subx2", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_subx2_encode_fns, 0, 0 }, -- { "subx4", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_subx4_encode_fns, 0, 0 }, -- { "subx8", 38 /* xt_iclass_addsub */, -- 0, -- Opcode_subx8_encode_fns, 0, 0 }, -- { "and", 39 /* xt_iclass_bit */, -- 0, -- Opcode_and_encode_fns, 0, 0 }, -- { "or", 39 /* xt_iclass_bit */, -- 0, -- Opcode_or_encode_fns, 0, 0 }, -- { "xor", 39 /* xt_iclass_bit */, -- 0, -- Opcode_xor_encode_fns, 0, 0 }, -- { "beqi", 40 /* xt_iclass_bsi8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_beqi_encode_fns, 0, 0 }, -- { "bnei", 40 /* xt_iclass_bsi8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnei_encode_fns, 0, 0 }, -- { "bgei", 40 /* xt_iclass_bsi8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgei_encode_fns, 0, 0 }, -- { "blti", 40 /* xt_iclass_bsi8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_blti_encode_fns, 0, 0 }, -- { "bbci", 41 /* xt_iclass_bsi8b */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbci_encode_fns, 0, 0 }, -- { "bbsi", 41 /* xt_iclass_bsi8b */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbsi_encode_fns, 0, 0 }, -- { "bgeui", 42 /* xt_iclass_bsi8u */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgeui_encode_fns, 0, 0 }, -- { "bltui", 42 /* xt_iclass_bsi8u */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bltui_encode_fns, 0, 0 }, -- { "beq", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_beq_encode_fns, 0, 0 }, -- { "bne", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bne_encode_fns, 0, 0 }, -- { "bge", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bge_encode_fns, 0, 0 }, -- { "blt", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_blt_encode_fns, 0, 0 }, -- { "bgeu", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgeu_encode_fns, 0, 0 }, -- { "bltu", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bltu_encode_fns, 0, 0 }, -- { "bany", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bany_encode_fns, 0, 0 }, -- { "bnone", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnone_encode_fns, 0, 0 }, -- { "ball", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_ball_encode_fns, 0, 0 }, -- { "bnall", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnall_encode_fns, 0, 0 }, -- { "bbc", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbc_encode_fns, 0, 0 }, -- { "bbs", 43 /* xt_iclass_bst8 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbs_encode_fns, 0, 0 }, -- { "beqz", 44 /* xt_iclass_bsz12 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_beqz_encode_fns, 0, 0 }, -- { "bnez", 44 /* xt_iclass_bsz12 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnez_encode_fns, 0, 0 }, -- { "bgez", 44 /* xt_iclass_bsz12 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgez_encode_fns, 0, 0 }, -- { "bltz", 44 /* xt_iclass_bsz12 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bltz_encode_fns, 0, 0 }, -- { "call0", 45 /* xt_iclass_call0 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_call0_encode_fns, 0, 0 }, -- { "callx0", 46 /* xt_iclass_callx0 */, -- XTENSA_OPCODE_IS_CALL, -- Opcode_callx0_encode_fns, 0, 0 }, -- { "extui", 47 /* xt_iclass_exti */, -- 0, -- Opcode_extui_encode_fns, 0, 0 }, -- { "ill", 48 /* xt_iclass_ill */, -- 0, -- Opcode_ill_encode_fns, 0, 0 }, -- { "j", 49 /* xt_iclass_jump */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_j_encode_fns, 0, 0 }, -- { "jx", 50 /* xt_iclass_jumpx */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_jx_encode_fns, 0, 0 }, -- { "l16ui", 51 /* xt_iclass_l16ui */, -- 0, -- Opcode_l16ui_encode_fns, 0, 0 }, -- { "l16si", 52 /* xt_iclass_l16si */, -- 0, -- Opcode_l16si_encode_fns, 0, 0 }, -- { "l32i", 53 /* xt_iclass_l32i */, -- 0, -- Opcode_l32i_encode_fns, 0, 0 }, -- { "l32r", 54 /* xt_iclass_l32r */, -- 0, -- Opcode_l32r_encode_fns, 0, 0 }, -- { "l8ui", 55 /* xt_iclass_l8i */, -- 0, -- Opcode_l8ui_encode_fns, 0, 0 }, -- { "loop", 56 /* xt_iclass_loop */, -- XTENSA_OPCODE_IS_LOOP, -- Opcode_loop_encode_fns, 0, 0 }, -- { "loopnez", 57 /* xt_iclass_loopz */, -- XTENSA_OPCODE_IS_LOOP, -- Opcode_loopnez_encode_fns, 0, 0 }, -- { "loopgtz", 57 /* xt_iclass_loopz */, -- XTENSA_OPCODE_IS_LOOP, -- Opcode_loopgtz_encode_fns, 0, 0 }, -- { "movi", 58 /* xt_iclass_movi */, -- 0, -- Opcode_movi_encode_fns, 0, 0 }, -- { "moveqz", 59 /* xt_iclass_movz */, -- 0, -- Opcode_moveqz_encode_fns, 0, 0 }, -- { "movnez", 59 /* xt_iclass_movz */, -- 0, -- Opcode_movnez_encode_fns, 0, 0 }, -- { "movltz", 59 /* xt_iclass_movz */, -- 0, -- Opcode_movltz_encode_fns, 0, 0 }, -- { "movgez", 59 /* xt_iclass_movz */, -- 0, -- Opcode_movgez_encode_fns, 0, 0 }, -- { "neg", 60 /* xt_iclass_neg */, -- 0, -- Opcode_neg_encode_fns, 0, 0 }, -- { "abs", 60 /* xt_iclass_neg */, -- 0, -- Opcode_abs_encode_fns, 0, 0 }, -- { "nop", 61 /* xt_iclass_nop */, -- 0, -- Opcode_nop_encode_fns, 0, 0 }, -- { "ret", 62 /* xt_iclass_return */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_ret_encode_fns, 0, 0 }, -- { "s16i", 63 /* xt_iclass_s16i */, -- 0, -- Opcode_s16i_encode_fns, 0, 0 }, -- { "s32i", 64 /* xt_iclass_s32i */, -- 0, -- Opcode_s32i_encode_fns, 0, 0 }, -- { "s8i", 65 /* xt_iclass_s8i */, -- 0, -- Opcode_s8i_encode_fns, 0, 0 }, -- { "ssr", 66 /* xt_iclass_sar */, -- 0, -- Opcode_ssr_encode_fns, 0, 0 }, -- { "ssl", 66 /* xt_iclass_sar */, -- 0, -- Opcode_ssl_encode_fns, 0, 0 }, -- { "ssa8l", 66 /* xt_iclass_sar */, -- 0, -- Opcode_ssa8l_encode_fns, 0, 0 }, -- { "ssa8b", 66 /* xt_iclass_sar */, -- 0, -- Opcode_ssa8b_encode_fns, 0, 0 }, -- { "ssai", 67 /* xt_iclass_sari */, -- 0, -- Opcode_ssai_encode_fns, 0, 0 }, -- { "sll", 68 /* xt_iclass_shifts */, -- 0, -- Opcode_sll_encode_fns, 0, 0 }, -- { "src", 69 /* xt_iclass_shiftst */, -- 0, -- Opcode_src_encode_fns, 0, 0 }, -- { "srl", 70 /* xt_iclass_shiftt */, -- 0, -- Opcode_srl_encode_fns, 0, 0 }, -- { "sra", 70 /* xt_iclass_shiftt */, -- 0, -- Opcode_sra_encode_fns, 0, 0 }, -- { "slli", 71 /* xt_iclass_slli */, -- 0, -- Opcode_slli_encode_fns, 0, 0 }, -- { "srai", 72 /* xt_iclass_srai */, -- 0, -- Opcode_srai_encode_fns, 0, 0 }, -- { "srli", 73 /* xt_iclass_srli */, -- 0, -- Opcode_srli_encode_fns, 0, 0 }, -- { "memw", 74 /* xt_iclass_memw */, -- 0, -- Opcode_memw_encode_fns, 0, 0 }, -- { "extw", 75 /* xt_iclass_extw */, -- 0, -- Opcode_extw_encode_fns, 0, 0 }, -- { "isync", 76 /* xt_iclass_isync */, -- 0, -- Opcode_isync_encode_fns, 0, 0 }, -- { "rsync", 77 /* xt_iclass_sync */, -- 0, -- Opcode_rsync_encode_fns, 0, 0 }, -- { "esync", 77 /* xt_iclass_sync */, -- 0, -- Opcode_esync_encode_fns, 0, 0 }, -- { "dsync", 77 /* xt_iclass_sync */, -- 0, -- Opcode_dsync_encode_fns, 0, 0 }, -- { "rsil", 78 /* xt_iclass_rsil */, -- 0, -- Opcode_rsil_encode_fns, 0, 0 }, -- { "rsr.lend", 79 /* xt_iclass_rsr.lend */, -- 0, -- Opcode_rsr_lend_encode_fns, 0, 0 }, -- { "wsr.lend", 80 /* xt_iclass_wsr.lend */, -- 0, -- Opcode_wsr_lend_encode_fns, 0, 0 }, -- { "xsr.lend", 81 /* xt_iclass_xsr.lend */, -- 0, -- Opcode_xsr_lend_encode_fns, 0, 0 }, -- { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, -- 0, -- Opcode_rsr_lcount_encode_fns, 0, 0 }, -- { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, -- 0, -- Opcode_wsr_lcount_encode_fns, 0, 0 }, -- { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, -- 0, -- Opcode_xsr_lcount_encode_fns, 0, 0 }, -- { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, -- 0, -- Opcode_rsr_lbeg_encode_fns, 0, 0 }, -- { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, -- 0, -- Opcode_wsr_lbeg_encode_fns, 0, 0 }, -- { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, -- 0, -- Opcode_xsr_lbeg_encode_fns, 0, 0 }, -- { "rsr.sar", 88 /* xt_iclass_rsr.sar */, -- 0, -- Opcode_rsr_sar_encode_fns, 0, 0 }, -- { "wsr.sar", 89 /* xt_iclass_wsr.sar */, -- 0, -- Opcode_wsr_sar_encode_fns, 0, 0 }, -- { "xsr.sar", 90 /* xt_iclass_xsr.sar */, -- 0, -- Opcode_xsr_sar_encode_fns, 0, 0 }, -- { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, -- 0, -- Opcode_rsr_litbase_encode_fns, 0, 0 }, -- { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, -- 0, -- Opcode_wsr_litbase_encode_fns, 0, 0 }, -- { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, -- 0, -- Opcode_xsr_litbase_encode_fns, 0, 0 }, -- { "rsr.176", 94 /* xt_iclass_rsr.176 */, -- 0, -- Opcode_rsr_176_encode_fns, 0, 0 }, -- { "rsr.208", 95 /* xt_iclass_rsr.208 */, -- 0, -- Opcode_rsr_208_encode_fns, 0, 0 }, -- { "rsr.ps", 96 /* xt_iclass_rsr.ps */, -- 0, -- Opcode_rsr_ps_encode_fns, 0, 0 }, -- { "wsr.ps", 97 /* xt_iclass_wsr.ps */, -- 0, -- Opcode_wsr_ps_encode_fns, 0, 0 }, -- { "xsr.ps", 98 /* xt_iclass_xsr.ps */, -- 0, -- Opcode_xsr_ps_encode_fns, 0, 0 }, -- { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, -- 0, -- Opcode_rsr_epc1_encode_fns, 0, 0 }, -- { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, -- 0, -- Opcode_wsr_epc1_encode_fns, 0, 0 }, -- { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, -- 0, -- Opcode_xsr_epc1_encode_fns, 0, 0 }, -- { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, -- 0, -- Opcode_rsr_excsave1_encode_fns, 0, 0 }, -- { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, -- 0, -- Opcode_wsr_excsave1_encode_fns, 0, 0 }, -- { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, -- 0, -- Opcode_xsr_excsave1_encode_fns, 0, 0 }, -- { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, -- 0, -- Opcode_rsr_epc2_encode_fns, 0, 0 }, -- { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, -- 0, -- Opcode_wsr_epc2_encode_fns, 0, 0 }, -- { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, -- 0, -- Opcode_xsr_epc2_encode_fns, 0, 0 }, -- { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, -- 0, -- Opcode_rsr_excsave2_encode_fns, 0, 0 }, -- { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, -- 0, -- Opcode_wsr_excsave2_encode_fns, 0, 0 }, -- { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, -- 0, -- Opcode_xsr_excsave2_encode_fns, 0, 0 }, -- { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, -- 0, -- Opcode_rsr_epc3_encode_fns, 0, 0 }, -- { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, -- 0, -- Opcode_wsr_epc3_encode_fns, 0, 0 }, -- { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, -- 0, -- Opcode_xsr_epc3_encode_fns, 0, 0 }, -- { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, -- 0, -- Opcode_rsr_excsave3_encode_fns, 0, 0 }, -- { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, -- 0, -- Opcode_wsr_excsave3_encode_fns, 0, 0 }, -- { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, -- 0, -- Opcode_xsr_excsave3_encode_fns, 0, 0 }, -- { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, -- 0, -- Opcode_rsr_epc4_encode_fns, 0, 0 }, -- { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, -- 0, -- Opcode_wsr_epc4_encode_fns, 0, 0 }, -- { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, -- 0, -- Opcode_xsr_epc4_encode_fns, 0, 0 }, -- { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, -- 0, -- Opcode_rsr_excsave4_encode_fns, 0, 0 }, -- { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, -- 0, -- Opcode_wsr_excsave4_encode_fns, 0, 0 }, -- { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, -- 0, -- Opcode_xsr_excsave4_encode_fns, 0, 0 }, -- { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, -- 0, -- Opcode_rsr_epc5_encode_fns, 0, 0 }, -- { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, -- 0, -- Opcode_wsr_epc5_encode_fns, 0, 0 }, -- { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, -- 0, -- Opcode_xsr_epc5_encode_fns, 0, 0 }, -- { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, -- 0, -- Opcode_rsr_excsave5_encode_fns, 0, 0 }, -- { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, -- 0, -- Opcode_wsr_excsave5_encode_fns, 0, 0 }, -- { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, -- 0, -- Opcode_xsr_excsave5_encode_fns, 0, 0 }, -- { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, -- 0, -- Opcode_rsr_epc6_encode_fns, 0, 0 }, -- { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, -- 0, -- Opcode_wsr_epc6_encode_fns, 0, 0 }, -- { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, -- 0, -- Opcode_xsr_epc6_encode_fns, 0, 0 }, -- { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, -- 0, -- Opcode_rsr_excsave6_encode_fns, 0, 0 }, -- { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, -- 0, -- Opcode_wsr_excsave6_encode_fns, 0, 0 }, -- { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, -- 0, -- Opcode_xsr_excsave6_encode_fns, 0, 0 }, -- { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, -- 0, -- Opcode_rsr_epc7_encode_fns, 0, 0 }, -- { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, -- 0, -- Opcode_wsr_epc7_encode_fns, 0, 0 }, -- { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, -- 0, -- Opcode_xsr_epc7_encode_fns, 0, 0 }, -- { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, -- 0, -- Opcode_rsr_excsave7_encode_fns, 0, 0 }, -- { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, -- 0, -- Opcode_wsr_excsave7_encode_fns, 0, 0 }, -- { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, -- 0, -- Opcode_xsr_excsave7_encode_fns, 0, 0 }, -- { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, -- 0, -- Opcode_rsr_eps2_encode_fns, 0, 0 }, -- { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, -- 0, -- Opcode_wsr_eps2_encode_fns, 0, 0 }, -- { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, -- 0, -- Opcode_xsr_eps2_encode_fns, 0, 0 }, -- { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, -- 0, -- Opcode_rsr_eps3_encode_fns, 0, 0 }, -- { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, -- 0, -- Opcode_wsr_eps3_encode_fns, 0, 0 }, -- { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, -- 0, -- Opcode_xsr_eps3_encode_fns, 0, 0 }, -- { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, -- 0, -- Opcode_rsr_eps4_encode_fns, 0, 0 }, -- { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, -- 0, -- Opcode_wsr_eps4_encode_fns, 0, 0 }, -- { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, -- 0, -- Opcode_xsr_eps4_encode_fns, 0, 0 }, -- { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, -- 0, -- Opcode_rsr_eps5_encode_fns, 0, 0 }, -- { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, -- 0, -- Opcode_wsr_eps5_encode_fns, 0, 0 }, -- { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, -- 0, -- Opcode_xsr_eps5_encode_fns, 0, 0 }, -- { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, -- 0, -- Opcode_rsr_eps6_encode_fns, 0, 0 }, -- { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, -- 0, -- Opcode_wsr_eps6_encode_fns, 0, 0 }, -- { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, -- 0, -- Opcode_xsr_eps6_encode_fns, 0, 0 }, -- { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, -- 0, -- Opcode_rsr_eps7_encode_fns, 0, 0 }, -- { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, -- 0, -- Opcode_wsr_eps7_encode_fns, 0, 0 }, -- { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, -- 0, -- Opcode_xsr_eps7_encode_fns, 0, 0 }, -- { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, -- 0, -- Opcode_rsr_excvaddr_encode_fns, 0, 0 }, -- { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, -- 0, -- Opcode_wsr_excvaddr_encode_fns, 0, 0 }, -- { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, -- 0, -- Opcode_xsr_excvaddr_encode_fns, 0, 0 }, -- { "rsr.depc", 162 /* xt_iclass_rsr.depc */, -- 0, -- Opcode_rsr_depc_encode_fns, 0, 0 }, -- { "wsr.depc", 163 /* xt_iclass_wsr.depc */, -- 0, -- Opcode_wsr_depc_encode_fns, 0, 0 }, -- { "xsr.depc", 164 /* xt_iclass_xsr.depc */, -- 0, -- Opcode_xsr_depc_encode_fns, 0, 0 }, -- { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, -- 0, -- Opcode_rsr_exccause_encode_fns, 0, 0 }, -- { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, -- 0, -- Opcode_wsr_exccause_encode_fns, 0, 0 }, -- { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, -- 0, -- Opcode_xsr_exccause_encode_fns, 0, 0 }, -- { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, -- 0, -- Opcode_rsr_misc0_encode_fns, 0, 0 }, -- { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, -- 0, -- Opcode_wsr_misc0_encode_fns, 0, 0 }, -- { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, -- 0, -- Opcode_xsr_misc0_encode_fns, 0, 0 }, -- { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, -- 0, -- Opcode_rsr_misc1_encode_fns, 0, 0 }, -- { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, -- 0, -- Opcode_wsr_misc1_encode_fns, 0, 0 }, -- { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, -- 0, -- Opcode_xsr_misc1_encode_fns, 0, 0 }, -- { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */, -- 0, -- Opcode_rsr_misc2_encode_fns, 0, 0 }, -- { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */, -- 0, -- Opcode_wsr_misc2_encode_fns, 0, 0 }, -- { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */, -- 0, -- Opcode_xsr_misc2_encode_fns, 0, 0 }, -- { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */, -- 0, -- Opcode_rsr_misc3_encode_fns, 0, 0 }, -- { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */, -- 0, -- Opcode_wsr_misc3_encode_fns, 0, 0 }, -- { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */, -- 0, -- Opcode_xsr_misc3_encode_fns, 0, 0 }, -- { "rsr.prid", 180 /* xt_iclass_rsr.prid */, -- 0, -- Opcode_rsr_prid_encode_fns, 0, 0 }, -- { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */, -- 0, -- Opcode_rsr_vecbase_encode_fns, 0, 0 }, -- { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */, -- 0, -- Opcode_wsr_vecbase_encode_fns, 0, 0 }, -- { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */, -- 0, -- Opcode_xsr_vecbase_encode_fns, 0, 0 }, -- { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_mul_aa_ll_encode_fns, 0, 0 }, -- { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_mul_aa_hl_encode_fns, 0, 0 }, -- { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_mul_aa_lh_encode_fns, 0, 0 }, -- { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_mul_aa_hh_encode_fns, 0, 0 }, -- { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_umul_aa_ll_encode_fns, 0, 0 }, -- { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_umul_aa_hl_encode_fns, 0, 0 }, -- { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_umul_aa_lh_encode_fns, 0, 0 }, -- { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */, -- 0, -- Opcode_umul_aa_hh_encode_fns, 0, 0 }, -- { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */, -- 0, -- Opcode_mul_ad_ll_encode_fns, 0, 0 }, -- { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */, -- 0, -- Opcode_mul_ad_hl_encode_fns, 0, 0 }, -- { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */, -- 0, -- Opcode_mul_ad_lh_encode_fns, 0, 0 }, -- { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */, -- 0, -- Opcode_mul_ad_hh_encode_fns, 0, 0 }, -- { "mul.da.ll", 186 /* xt_iclass_mac16_da */, -- 0, -- Opcode_mul_da_ll_encode_fns, 0, 0 }, -- { "mul.da.hl", 186 /* xt_iclass_mac16_da */, -- 0, -- Opcode_mul_da_hl_encode_fns, 0, 0 }, -- { "mul.da.lh", 186 /* xt_iclass_mac16_da */, -- 0, -- Opcode_mul_da_lh_encode_fns, 0, 0 }, -- { "mul.da.hh", 186 /* xt_iclass_mac16_da */, -- 0, -- Opcode_mul_da_hh_encode_fns, 0, 0 }, -- { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */, -- 0, -- Opcode_mul_dd_ll_encode_fns, 0, 0 }, -- { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */, -- 0, -- Opcode_mul_dd_hl_encode_fns, 0, 0 }, -- { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */, -- 0, -- Opcode_mul_dd_lh_encode_fns, 0, 0 }, -- { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */, -- 0, -- Opcode_mul_dd_hh_encode_fns, 0, 0 }, -- { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_mula_aa_ll_encode_fns, 0, 0 }, -- { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_mula_aa_hl_encode_fns, 0, 0 }, -- { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_mula_aa_lh_encode_fns, 0, 0 }, -- { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_mula_aa_hh_encode_fns, 0, 0 }, -- { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_muls_aa_ll_encode_fns, 0, 0 }, -- { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_muls_aa_hl_encode_fns, 0, 0 }, -- { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_muls_aa_lh_encode_fns, 0, 0 }, -- { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */, -- 0, -- Opcode_muls_aa_hh_encode_fns, 0, 0 }, -- { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_mula_ad_ll_encode_fns, 0, 0 }, -- { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_mula_ad_hl_encode_fns, 0, 0 }, -- { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_mula_ad_lh_encode_fns, 0, 0 }, -- { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_mula_ad_hh_encode_fns, 0, 0 }, -- { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_muls_ad_ll_encode_fns, 0, 0 }, -- { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_muls_ad_hl_encode_fns, 0, 0 }, -- { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_muls_ad_lh_encode_fns, 0, 0 }, -- { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */, -- 0, -- Opcode_muls_ad_hh_encode_fns, 0, 0 }, -- { "mula.da.ll", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_mula_da_ll_encode_fns, 0, 0 }, -- { "mula.da.hl", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_mula_da_hl_encode_fns, 0, 0 }, -- { "mula.da.lh", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_mula_da_lh_encode_fns, 0, 0 }, -- { "mula.da.hh", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_mula_da_hh_encode_fns, 0, 0 }, -- { "muls.da.ll", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_muls_da_ll_encode_fns, 0, 0 }, -- { "muls.da.hl", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_muls_da_hl_encode_fns, 0, 0 }, -- { "muls.da.lh", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_muls_da_lh_encode_fns, 0, 0 }, -- { "muls.da.hh", 190 /* xt_iclass_mac16a_da */, -- 0, -- Opcode_muls_da_hh_encode_fns, 0, 0 }, -- { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_mula_dd_ll_encode_fns, 0, 0 }, -- { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_mula_dd_hl_encode_fns, 0, 0 }, -- { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_mula_dd_lh_encode_fns, 0, 0 }, -- { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_mula_dd_hh_encode_fns, 0, 0 }, -- { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_muls_dd_ll_encode_fns, 0, 0 }, -- { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_muls_dd_hl_encode_fns, 0, 0 }, -- { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_muls_dd_lh_encode_fns, 0, 0 }, -- { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */, -- 0, -- Opcode_muls_dd_hh_encode_fns, 0, 0 }, -- { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, -- { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, -- { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, -- { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, -- { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, -- { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, -- { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, -- { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */, -- 0, -- Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, -- { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, -- { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, -- { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, -- { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, -- { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, -- { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, -- { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, -- { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */, -- 0, -- Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, -- { "lddec", 194 /* xt_iclass_mac16_l */, -- 0, -- Opcode_lddec_encode_fns, 0, 0 }, -- { "ldinc", 194 /* xt_iclass_mac16_l */, -- 0, -- Opcode_ldinc_encode_fns, 0, 0 }, -- { "mul16u", 195 /* xt_iclass_mul16 */, -- 0, -- Opcode_mul16u_encode_fns, 0, 0 }, -- { "mul16s", 195 /* xt_iclass_mul16 */, -- 0, -- Opcode_mul16s_encode_fns, 0, 0 }, -- { "rsr.m0", 196 /* xt_iclass_rsr.m0 */, -- 0, -- Opcode_rsr_m0_encode_fns, 0, 0 }, -- { "wsr.m0", 197 /* xt_iclass_wsr.m0 */, -- 0, -- Opcode_wsr_m0_encode_fns, 0, 0 }, -- { "xsr.m0", 198 /* xt_iclass_xsr.m0 */, -- 0, -- Opcode_xsr_m0_encode_fns, 0, 0 }, -- { "rsr.m1", 199 /* xt_iclass_rsr.m1 */, -- 0, -- Opcode_rsr_m1_encode_fns, 0, 0 }, -- { "wsr.m1", 200 /* xt_iclass_wsr.m1 */, -- 0, -- Opcode_wsr_m1_encode_fns, 0, 0 }, -- { "xsr.m1", 201 /* xt_iclass_xsr.m1 */, -- 0, -- Opcode_xsr_m1_encode_fns, 0, 0 }, -- { "rsr.m2", 202 /* xt_iclass_rsr.m2 */, -- 0, -- Opcode_rsr_m2_encode_fns, 0, 0 }, -- { "wsr.m2", 203 /* xt_iclass_wsr.m2 */, -- 0, -- Opcode_wsr_m2_encode_fns, 0, 0 }, -- { "xsr.m2", 204 /* xt_iclass_xsr.m2 */, -- 0, -- Opcode_xsr_m2_encode_fns, 0, 0 }, -- { "rsr.m3", 205 /* xt_iclass_rsr.m3 */, -- 0, -- Opcode_rsr_m3_encode_fns, 0, 0 }, -- { "wsr.m3", 206 /* xt_iclass_wsr.m3 */, -- 0, -- Opcode_wsr_m3_encode_fns, 0, 0 }, -- { "xsr.m3", 207 /* xt_iclass_xsr.m3 */, -- 0, -- Opcode_xsr_m3_encode_fns, 0, 0 }, -- { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */, -- 0, -- Opcode_rsr_acclo_encode_fns, 0, 0 }, -- { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */, -- 0, -- Opcode_wsr_acclo_encode_fns, 0, 0 }, -- { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */, -- 0, -- Opcode_xsr_acclo_encode_fns, 0, 0 }, -- { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */, -- 0, -- Opcode_rsr_acchi_encode_fns, 0, 0 }, -- { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */, -- 0, -- Opcode_wsr_acchi_encode_fns, 0, 0 }, -- { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */, -- 0, -- Opcode_xsr_acchi_encode_fns, 0, 0 }, -- { "rfi", 214 /* xt_iclass_rfi */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_rfi_encode_fns, 0, 0 }, -- { "waiti", 215 /* xt_iclass_wait */, -- 0, -- Opcode_waiti_encode_fns, 0, 0 }, -- { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */, -- 0, -- Opcode_rsr_interrupt_encode_fns, 0, 0 }, -- { "wsr.intset", 217 /* xt_iclass_wsr.intset */, -- 0, -- Opcode_wsr_intset_encode_fns, 0, 0 }, -- { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */, -- 0, -- Opcode_wsr_intclear_encode_fns, 0, 0 }, -- { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */, -- 0, -- Opcode_rsr_intenable_encode_fns, 0, 0 }, -- { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */, -- 0, -- Opcode_wsr_intenable_encode_fns, 0, 0 }, -- { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */, -- 0, -- Opcode_xsr_intenable_encode_fns, 0, 0 }, -- { "break", 222 /* xt_iclass_break */, -- 0, -- Opcode_break_encode_fns, 0, 0 }, -- { "break.n", 223 /* xt_iclass_break.n */, -- 0, -- Opcode_break_n_encode_fns, 0, 0 }, -- { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */, -- 0, -- Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, -- { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */, -- 0, -- Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, -- { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */, -- 0, -- Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, -- { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */, -- 0, -- Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, -- { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */, -- 0, -- Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, -- { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */, -- 0, -- Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, -- { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */, -- 0, -- Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, -- { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */, -- 0, -- Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, -- { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */, -- 0, -- Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, -- { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */, -- 0, -- Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, -- { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */, -- 0, -- Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, -- { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */, -- 0, -- Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, -- { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */, -- 0, -- Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, -- { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */, -- 0, -- Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, -- { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */, -- 0, -- Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, -- { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */, -- 0, -- Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, -- { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */, -- 0, -- Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, -- { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */, -- 0, -- Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, -- { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */, -- 0, -- Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, -- { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */, -- 0, -- Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, -- { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */, -- 0, -- Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, -- { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */, -- 0, -- Opcode_rsr_debugcause_encode_fns, 0, 0 }, -- { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */, -- 0, -- Opcode_wsr_debugcause_encode_fns, 0, 0 }, -- { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */, -- 0, -- Opcode_xsr_debugcause_encode_fns, 0, 0 }, -- { "rsr.icount", 248 /* xt_iclass_rsr.icount */, -- 0, -- Opcode_rsr_icount_encode_fns, 0, 0 }, -- { "wsr.icount", 249 /* xt_iclass_wsr.icount */, -- 0, -- Opcode_wsr_icount_encode_fns, 0, 0 }, -- { "xsr.icount", 250 /* xt_iclass_xsr.icount */, -- 0, -- Opcode_xsr_icount_encode_fns, 0, 0 }, -- { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */, -- 0, -- Opcode_rsr_icountlevel_encode_fns, 0, 0 }, -- { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */, -- 0, -- Opcode_wsr_icountlevel_encode_fns, 0, 0 }, -- { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */, -- 0, -- Opcode_xsr_icountlevel_encode_fns, 0, 0 }, -- { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */, -- 0, -- Opcode_rsr_ddr_encode_fns, 0, 0 }, -- { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */, -- 0, -- Opcode_wsr_ddr_encode_fns, 0, 0 }, -- { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */, -- 0, -- Opcode_xsr_ddr_encode_fns, 0, 0 }, -- { "rfdo", 257 /* xt_iclass_rfdo */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_rfdo_encode_fns, 0, 0 }, -- { "rfdd", 258 /* xt_iclass_rfdd */, -- XTENSA_OPCODE_IS_JUMP, -- Opcode_rfdd_encode_fns, 0, 0 }, -- { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */, -- 0, -- Opcode_wsr_mmid_encode_fns, 0, 0 }, -- { "andb", 260 /* xt_iclass_bbool1 */, -- 0, -- Opcode_andb_encode_fns, 0, 0 }, -- { "andbc", 260 /* xt_iclass_bbool1 */, -- 0, -- Opcode_andbc_encode_fns, 0, 0 }, -- { "orb", 260 /* xt_iclass_bbool1 */, -- 0, -- Opcode_orb_encode_fns, 0, 0 }, -- { "orbc", 260 /* xt_iclass_bbool1 */, -- 0, -- Opcode_orbc_encode_fns, 0, 0 }, -- { "xorb", 260 /* xt_iclass_bbool1 */, -- 0, -- Opcode_xorb_encode_fns, 0, 0 }, -- { "any4", 261 /* xt_iclass_bbool4 */, -- 0, -- Opcode_any4_encode_fns, 0, 0 }, -- { "all4", 261 /* xt_iclass_bbool4 */, -- 0, -- Opcode_all4_encode_fns, 0, 0 }, -- { "any8", 262 /* xt_iclass_bbool8 */, -- 0, -- Opcode_any8_encode_fns, 0, 0 }, -- { "all8", 262 /* xt_iclass_bbool8 */, -- 0, -- Opcode_all8_encode_fns, 0, 0 }, -- { "bf", 263 /* xt_iclass_bbranch */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bf_encode_fns, 0, 0 }, -- { "bt", 263 /* xt_iclass_bbranch */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bt_encode_fns, 0, 0 }, -- { "movf", 264 /* xt_iclass_bmove */, -- 0, -- Opcode_movf_encode_fns, 0, 0 }, -- { "movt", 264 /* xt_iclass_bmove */, -- 0, -- Opcode_movt_encode_fns, 0, 0 }, -- { "rsr.br", 265 /* xt_iclass_RSR.BR */, -- 0, -- Opcode_rsr_br_encode_fns, 0, 0 }, -- { "wsr.br", 266 /* xt_iclass_WSR.BR */, -- 0, -- Opcode_wsr_br_encode_fns, 0, 0 }, -- { "xsr.br", 267 /* xt_iclass_XSR.BR */, -- 0, -- Opcode_xsr_br_encode_fns, 0, 0 }, -- { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */, -- 0, -- Opcode_rsr_ccount_encode_fns, 0, 0 }, -- { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */, -- 0, -- Opcode_wsr_ccount_encode_fns, 0, 0 }, -- { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */, -- 0, -- Opcode_xsr_ccount_encode_fns, 0, 0 }, -- { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */, -- 0, -- Opcode_rsr_ccompare0_encode_fns, 0, 0 }, -- { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */, -- 0, -- Opcode_wsr_ccompare0_encode_fns, 0, 0 }, -- { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */, -- 0, -- Opcode_xsr_ccompare0_encode_fns, 0, 0 }, -- { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */, -- 0, -- Opcode_rsr_ccompare1_encode_fns, 0, 0 }, -- { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */, -- 0, -- Opcode_wsr_ccompare1_encode_fns, 0, 0 }, -- { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */, -- 0, -- Opcode_xsr_ccompare1_encode_fns, 0, 0 }, -- { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */, -- 0, -- Opcode_rsr_ccompare2_encode_fns, 0, 0 }, -- { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */, -- 0, -- Opcode_wsr_ccompare2_encode_fns, 0, 0 }, -- { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */, -- 0, -- Opcode_xsr_ccompare2_encode_fns, 0, 0 }, -- { "ipf", 280 /* xt_iclass_icache */, -- 0, -- Opcode_ipf_encode_fns, 0, 0 }, -- { "ihi", 280 /* xt_iclass_icache */, -- 0, -- Opcode_ihi_encode_fns, 0, 0 }, -- { "ipfl", 281 /* xt_iclass_icache_lock */, -- 0, -- Opcode_ipfl_encode_fns, 0, 0 }, -- { "ihu", 281 /* xt_iclass_icache_lock */, -- 0, -- Opcode_ihu_encode_fns, 0, 0 }, -- { "iiu", 281 /* xt_iclass_icache_lock */, -- 0, -- Opcode_iiu_encode_fns, 0, 0 }, -- { "iii", 282 /* xt_iclass_icache_inv */, -- 0, -- Opcode_iii_encode_fns, 0, 0 }, -- { "lict", 283 /* xt_iclass_licx */, -- 0, -- Opcode_lict_encode_fns, 0, 0 }, -- { "licw", 283 /* xt_iclass_licx */, -- 0, -- Opcode_licw_encode_fns, 0, 0 }, -- { "sict", 284 /* xt_iclass_sicx */, -- 0, -- Opcode_sict_encode_fns, 0, 0 }, -- { "sicw", 284 /* xt_iclass_sicx */, -- 0, -- Opcode_sicw_encode_fns, 0, 0 }, -- { "dhwb", 285 /* xt_iclass_dcache */, -- 0, -- Opcode_dhwb_encode_fns, 0, 0 }, -- { "dhwbi", 285 /* xt_iclass_dcache */, -- 0, -- Opcode_dhwbi_encode_fns, 0, 0 }, -- { "diwb", 286 /* xt_iclass_dcache_ind */, -- 0, -- Opcode_diwb_encode_fns, 0, 0 }, -- { "diwbi", 286 /* xt_iclass_dcache_ind */, -- 0, -- Opcode_diwbi_encode_fns, 0, 0 }, -- { "dhi", 287 /* xt_iclass_dcache_inv */, -- 0, -- Opcode_dhi_encode_fns, 0, 0 }, -- { "dii", 287 /* xt_iclass_dcache_inv */, -- 0, -- Opcode_dii_encode_fns, 0, 0 }, -- { "dpfr", 288 /* xt_iclass_dpf */, -- 0, -- Opcode_dpfr_encode_fns, 0, 0 }, -- { "dpfw", 288 /* xt_iclass_dpf */, -- 0, -- Opcode_dpfw_encode_fns, 0, 0 }, -- { "dpfro", 288 /* xt_iclass_dpf */, -- 0, -- Opcode_dpfro_encode_fns, 0, 0 }, -- { "dpfwo", 288 /* xt_iclass_dpf */, -- 0, -- Opcode_dpfwo_encode_fns, 0, 0 }, -- { "dpfl", 289 /* xt_iclass_dcache_lock */, -- 0, -- Opcode_dpfl_encode_fns, 0, 0 }, -- { "dhu", 289 /* xt_iclass_dcache_lock */, -- 0, -- Opcode_dhu_encode_fns, 0, 0 }, -- { "diu", 289 /* xt_iclass_dcache_lock */, -- 0, -- Opcode_diu_encode_fns, 0, 0 }, -- { "sdct", 290 /* xt_iclass_sdct */, -- 0, -- Opcode_sdct_encode_fns, 0, 0 }, -- { "ldct", 291 /* xt_iclass_ldct */, -- 0, -- Opcode_ldct_encode_fns, 0, 0 }, -- { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */, -- 0, -- Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, -- { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */, -- 0, -- Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, -- { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */, -- 0, -- Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, -- { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */, -- 0, -- Opcode_rsr_rasid_encode_fns, 0, 0 }, -- { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */, -- 0, -- Opcode_wsr_rasid_encode_fns, 0, 0 }, -- { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */, -- 0, -- Opcode_xsr_rasid_encode_fns, 0, 0 }, -- { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */, -- 0, -- Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, -- { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */, -- 0, -- Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, -- { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */, -- 0, -- Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, -- { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */, -- 0, -- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, -- { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */, -- 0, -- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, -- { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */, -- 0, -- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, -- { "idtlb", 304 /* xt_iclass_idtlb */, -- 0, -- Opcode_idtlb_encode_fns, 0, 0 }, -- { "pdtlb", 305 /* xt_iclass_rdtlb */, -- 0, -- Opcode_pdtlb_encode_fns, 0, 0 }, -- { "rdtlb0", 305 /* xt_iclass_rdtlb */, -- 0, -- Opcode_rdtlb0_encode_fns, 0, 0 }, -- { "rdtlb1", 305 /* xt_iclass_rdtlb */, -- 0, -- Opcode_rdtlb1_encode_fns, 0, 0 }, -- { "wdtlb", 306 /* xt_iclass_wdtlb */, -- 0, -- Opcode_wdtlb_encode_fns, 0, 0 }, -- { "iitlb", 307 /* xt_iclass_iitlb */, -- 0, -- Opcode_iitlb_encode_fns, 0, 0 }, -- { "pitlb", 308 /* xt_iclass_ritlb */, -- 0, -- Opcode_pitlb_encode_fns, 0, 0 }, -- { "ritlb0", 308 /* xt_iclass_ritlb */, -- 0, -- Opcode_ritlb0_encode_fns, 0, 0 }, -- { "ritlb1", 308 /* xt_iclass_ritlb */, -- 0, -- Opcode_ritlb1_encode_fns, 0, 0 }, -- { "witlb", 309 /* xt_iclass_witlb */, -- 0, -- Opcode_witlb_encode_fns, 0, 0 }, -- { "ldpte", 310 /* xt_iclass_ldpte */, -- 0, -- Opcode_ldpte_encode_fns, 0, 0 }, -- { "hwwitlba", 311 /* xt_iclass_hwwitlba */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_hwwitlba_encode_fns, 0, 0 }, -- { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */, -- 0, -- Opcode_hwwdtlba_encode_fns, 0, 0 }, -- { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */, -- 0, -- Opcode_rsr_cpenable_encode_fns, 0, 0 }, -- { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */, -- 0, -- Opcode_wsr_cpenable_encode_fns, 0, 0 }, -- { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */, -- 0, -- Opcode_xsr_cpenable_encode_fns, 0, 0 }, -- { "clamps", 316 /* xt_iclass_clamp */, -- 0, -- Opcode_clamps_encode_fns, 0, 0 }, -- { "min", 317 /* xt_iclass_minmax */, -- 0, -- Opcode_min_encode_fns, 0, 0 }, -- { "max", 317 /* xt_iclass_minmax */, -- 0, -- Opcode_max_encode_fns, 0, 0 }, -- { "minu", 317 /* xt_iclass_minmax */, -- 0, -- Opcode_minu_encode_fns, 0, 0 }, -- { "maxu", 317 /* xt_iclass_minmax */, -- 0, -- Opcode_maxu_encode_fns, 0, 0 }, -- { "nsa", 318 /* xt_iclass_nsa */, -- 0, -- Opcode_nsa_encode_fns, 0, 0 }, -- { "nsau", 318 /* xt_iclass_nsa */, -- 0, -- Opcode_nsau_encode_fns, 0, 0 }, -- { "sext", 319 /* xt_iclass_sx */, -- 0, -- Opcode_sext_encode_fns, 0, 0 }, -- { "l32ai", 320 /* xt_iclass_l32ai */, -- 0, -- Opcode_l32ai_encode_fns, 0, 0 }, -- { "s32ri", 321 /* xt_iclass_s32ri */, -- 0, -- Opcode_s32ri_encode_fns, 0, 0 }, -- { "s32c1i", 322 /* xt_iclass_s32c1i */, -- 0, -- Opcode_s32c1i_encode_fns, 0, 0 }, -- { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */, -- 0, -- Opcode_rsr_scompare1_encode_fns, 0, 0 }, -- { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */, -- 0, -- Opcode_wsr_scompare1_encode_fns, 0, 0 }, -- { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */, -- 0, -- Opcode_xsr_scompare1_encode_fns, 0, 0 }, -- { "quou", 326 /* xt_iclass_div */, -- 0, -- Opcode_quou_encode_fns, 0, 0 }, -- { "quos", 326 /* xt_iclass_div */, -- 0, -- Opcode_quos_encode_fns, 0, 0 }, -- { "remu", 326 /* xt_iclass_div */, -- 0, -- Opcode_remu_encode_fns, 0, 0 }, -- { "rems", 326 /* xt_iclass_div */, -- 0, -- Opcode_rems_encode_fns, 0, 0 }, -- { "mull", 327 /* xt_mul32 */, -- 0, -- Opcode_mull_encode_fns, 0, 0 }, -- { "muluh", 327 /* xt_mul32 */, -- 0, -- Opcode_muluh_encode_fns, 0, 0 }, -- { "mulsh", 327 /* xt_mul32 */, -- 0, -- Opcode_mulsh_encode_fns, 0, 0 }, -- { "rur.fcr", 328 /* rur_fcr */, -- 0, -- Opcode_rur_fcr_encode_fns, 0, 0 }, -- { "wur.fcr", 329 /* wur_fcr */, -- 0, -- Opcode_wur_fcr_encode_fns, 0, 0 }, -- { "rur.fsr", 330 /* rur_fsr */, -- 0, -- Opcode_rur_fsr_encode_fns, 0, 0 }, -- { "wur.fsr", 331 /* wur_fsr */, -- 0, -- Opcode_wur_fsr_encode_fns, 0, 0 }, -- { "add.s", 332 /* fp */, -- 0, -- Opcode_add_s_encode_fns, 0, 0 }, -- { "sub.s", 332 /* fp */, -- 0, -- Opcode_sub_s_encode_fns, 0, 0 }, -- { "mul.s", 332 /* fp */, -- 0, -- Opcode_mul_s_encode_fns, 0, 0 }, -- { "madd.s", 333 /* fp_mac */, -- 0, -- Opcode_madd_s_encode_fns, 0, 0 }, -- { "msub.s", 333 /* fp_mac */, -- 0, -- Opcode_msub_s_encode_fns, 0, 0 }, -- { "movf.s", 334 /* fp_cmov */, -- 0, -- Opcode_movf_s_encode_fns, 0, 0 }, -- { "movt.s", 334 /* fp_cmov */, -- 0, -- Opcode_movt_s_encode_fns, 0, 0 }, -- { "moveqz.s", 335 /* fp_mov */, -- 0, -- Opcode_moveqz_s_encode_fns, 0, 0 }, -- { "movnez.s", 335 /* fp_mov */, -- 0, -- Opcode_movnez_s_encode_fns, 0, 0 }, -- { "movltz.s", 335 /* fp_mov */, -- 0, -- Opcode_movltz_s_encode_fns, 0, 0 }, -- { "movgez.s", 335 /* fp_mov */, -- 0, -- Opcode_movgez_s_encode_fns, 0, 0 }, -- { "abs.s", 336 /* fp_mov2 */, -- 0, -- Opcode_abs_s_encode_fns, 0, 0 }, -- { "mov.s", 336 /* fp_mov2 */, -- 0, -- Opcode_mov_s_encode_fns, 0, 0 }, -- { "neg.s", 336 /* fp_mov2 */, -- 0, -- Opcode_neg_s_encode_fns, 0, 0 }, -- { "un.s", 337 /* fp_cmp */, -- 0, -- Opcode_un_s_encode_fns, 0, 0 }, -- { "oeq.s", 337 /* fp_cmp */, -- 0, -- Opcode_oeq_s_encode_fns, 0, 0 }, -- { "ueq.s", 337 /* fp_cmp */, -- 0, -- Opcode_ueq_s_encode_fns, 0, 0 }, -- { "olt.s", 337 /* fp_cmp */, -- 0, -- Opcode_olt_s_encode_fns, 0, 0 }, -- { "ult.s", 337 /* fp_cmp */, -- 0, -- Opcode_ult_s_encode_fns, 0, 0 }, -- { "ole.s", 337 /* fp_cmp */, -- 0, -- Opcode_ole_s_encode_fns, 0, 0 }, -- { "ule.s", 337 /* fp_cmp */, -- 0, -- Opcode_ule_s_encode_fns, 0, 0 }, -- { "float.s", 338 /* fp_float */, -- 0, -- Opcode_float_s_encode_fns, 0, 0 }, -- { "ufloat.s", 338 /* fp_float */, -- 0, -- Opcode_ufloat_s_encode_fns, 0, 0 }, -- { "round.s", 339 /* fp_int */, -- 0, -- Opcode_round_s_encode_fns, 0, 0 }, -- { "ceil.s", 339 /* fp_int */, -- 0, -- Opcode_ceil_s_encode_fns, 0, 0 }, -- { "floor.s", 339 /* fp_int */, -- 0, -- Opcode_floor_s_encode_fns, 0, 0 }, -- { "trunc.s", 339 /* fp_int */, -- 0, -- Opcode_trunc_s_encode_fns, 0, 0 }, -- { "utrunc.s", 339 /* fp_int */, -- 0, -- Opcode_utrunc_s_encode_fns, 0, 0 }, -- { "rfr", 340 /* fp_rfr */, -- 0, -- Opcode_rfr_encode_fns, 0, 0 }, -- { "wfr", 341 /* fp_wfr */, -- 0, -- Opcode_wfr_encode_fns, 0, 0 }, -- { "lsi", 342 /* fp_lsi */, -- 0, -- Opcode_lsi_encode_fns, 0, 0 }, -- { "lsiu", 343 /* fp_lsiu */, -- 0, -- Opcode_lsiu_encode_fns, 0, 0 }, -- { "lsx", 344 /* fp_lsx */, -- 0, -- Opcode_lsx_encode_fns, 0, 0 }, -- { "lsxu", 345 /* fp_lsxu */, -- 0, -- Opcode_lsxu_encode_fns, 0, 0 }, -- { "ssi", 346 /* fp_ssi */, -- 0, -- Opcode_ssi_encode_fns, 0, 0 }, -- { "ssiu", 347 /* fp_ssiu */, -- 0, -- Opcode_ssiu_encode_fns, 0, 0 }, -- { "ssx", 348 /* fp_ssx */, -- 0, -- Opcode_ssx_encode_fns, 0, 0 }, -- { "ssxu", 349 /* fp_ssxu */, -- 0, -- Opcode_ssxu_encode_fns, 0, 0 }, -- { "beqz.w18", 350 /* xt_iclass_wb18_0 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_beqz_w18_encode_fns, 0, 0 }, -- { "bnez.w18", 350 /* xt_iclass_wb18_0 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnez_w18_encode_fns, 0, 0 }, -- { "bgez.w18", 350 /* xt_iclass_wb18_0 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgez_w18_encode_fns, 0, 0 }, -- { "bltz.w18", 350 /* xt_iclass_wb18_0 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bltz_w18_encode_fns, 0, 0 }, -- { "beqi.w18", 351 /* xt_iclass_wb18_1 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_beqi_w18_encode_fns, 0, 0 }, -- { "bnei.w18", 351 /* xt_iclass_wb18_1 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnei_w18_encode_fns, 0, 0 }, -- { "bgei.w18", 351 /* xt_iclass_wb18_1 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgei_w18_encode_fns, 0, 0 }, -- { "blti.w18", 351 /* xt_iclass_wb18_1 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_blti_w18_encode_fns, 0, 0 }, -- { "bgeui.w18", 352 /* xt_iclass_wb18_2 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgeui_w18_encode_fns, 0, 0 }, -- { "bltui.w18", 352 /* xt_iclass_wb18_2 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bltui_w18_encode_fns, 0, 0 }, -- { "bbci.w18", 353 /* xt_iclass_wb18_3 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbci_w18_encode_fns, 0, 0 }, -- { "bbsi.w18", 353 /* xt_iclass_wb18_3 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbsi_w18_encode_fns, 0, 0 }, -- { "beq.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_beq_w18_encode_fns, 0, 0 }, -- { "bne.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bne_w18_encode_fns, 0, 0 }, -- { "bge.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bge_w18_encode_fns, 0, 0 }, -- { "blt.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_blt_w18_encode_fns, 0, 0 }, -- { "bgeu.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bgeu_w18_encode_fns, 0, 0 }, -- { "bltu.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bltu_w18_encode_fns, 0, 0 }, -- { "bany.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bany_w18_encode_fns, 0, 0 }, -- { "bnone.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnone_w18_encode_fns, 0, 0 }, -- { "ball.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_ball_w18_encode_fns, 0, 0 }, -- { "bnall.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bnall_w18_encode_fns, 0, 0 }, -- { "bbc.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbc_w18_encode_fns, 0, 0 }, -- { "bbs.w18", 354 /* xt_iclass_wb18_4 */, -- XTENSA_OPCODE_IS_BRANCH, -- Opcode_bbs_w18_encode_fns, 0, 0 } --}; -- -- --/* Slot-specific opcode decode functions. */ -- --static int --Slot_inst_decode (const xtensa_insnbuf insn) --{ -- switch (Field_op0_Slot_inst_get (insn)) -- { -- case 0: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 0: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 0: -- switch (Field_m_Slot_inst_get (insn)) -- { -- case 0: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_n_Slot_inst_get (insn) == 0) -- return 79; /* ill */ -- break; -- case 2: -- switch (Field_n_Slot_inst_get (insn)) -- { -- case 0: -- return 98; /* ret */ -- case 1: -- return 14; /* retw */ -- case 2: -- return 81; /* jx */ -- } -- break; -- case 3: -- switch (Field_n_Slot_inst_get (insn)) -- { -- case 0: -- return 77; /* callx0 */ -- case 1: -- return 10; /* callx4 */ -- case 2: -- return 9; /* callx8 */ -- case 3: -- return 8; /* callx12 */ -- } -- break; -- } -- break; -- case 1: -- return 12; /* movsp */ -- case 2: -- if (Field_s_Slot_inst_get (insn) == 0) -- { -- switch (Field_t_Slot_inst_get (insn)) -- { -- case 0: -- return 116; /* isync */ -- case 1: -- return 117; /* rsync */ -- case 2: -- return 118; /* esync */ -- case 3: -- return 119; /* dsync */ -- case 8: -- return 0; /* excw */ -- case 12: -- return 114; /* memw */ -- case 13: -- return 115; /* extw */ -- case 15: -- return 97; /* nop */ -- } -- } -- break; -- case 3: -- switch (Field_t_Slot_inst_get (insn)) -- { -- case 0: -- switch (Field_s_Slot_inst_get (insn)) -- { -- case 0: -- return 1; /* rfe */ -- case 2: -- return 2; /* rfde */ -- case 4: -- return 16; /* rfwo */ -- case 5: -- return 17; /* rfwu */ -- } -- break; -- case 1: -- return 316; /* rfi */ -- } -- break; -- case 4: -- return 324; /* break */ -- case 5: -- switch (Field_s_Slot_inst_get (insn)) -- { -- case 0: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 3; /* syscall */ -- break; -- case 1: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 4; /* simcall */ -- break; -- } -- break; -- case 6: -- return 120; /* rsil */ -- case 7: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 317; /* waiti */ -- break; -- case 8: -- return 367; /* any4 */ -- case 9: -- return 368; /* all4 */ -- case 10: -- return 369; /* any8 */ -- case 11: -- return 370; /* all8 */ -- } -- break; -- case 1: -- return 49; /* and */ -- case 2: -- return 50; /* or */ -- case 3: -- return 51; /* xor */ -- case 4: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 0: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 102; /* ssr */ -- break; -- case 1: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 103; /* ssl */ -- break; -- case 2: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 104; /* ssa8l */ -- break; -- case 3: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 105; /* ssa8b */ -- break; -- case 4: -- if (Field_thi3_Slot_inst_get (insn) == 0) -- return 106; /* ssai */ -- break; -- case 8: -- if (Field_s_Slot_inst_get (insn) == 0) -- return 13; /* rotw */ -- break; -- case 14: -- return 448; /* nsa */ -- case 15: -- return 449; /* nsau */ -- } -- break; -- case 5: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 1: -- return 438; /* hwwitlba */ -- case 3: -- return 434; /* ritlb0 */ -- case 4: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 432; /* iitlb */ -- break; -- case 5: -- return 433; /* pitlb */ -- case 6: -- return 436; /* witlb */ -- case 7: -- return 435; /* ritlb1 */ -- case 9: -- return 439; /* hwwdtlba */ -- case 11: -- return 429; /* rdtlb0 */ -- case 12: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 427; /* idtlb */ -- break; -- case 13: -- return 428; /* pdtlb */ -- case 14: -- return 431; /* wdtlb */ -- case 15: -- return 430; /* rdtlb1 */ -- } -- break; -- case 6: -- switch (Field_s_Slot_inst_get (insn)) -- { -- case 0: -- return 95; /* neg */ -- case 1: -- return 96; /* abs */ -- } -- break; -- case 8: -- return 41; /* add */ -- case 9: -- return 43; /* addx2 */ -- case 10: -- return 44; /* addx4 */ -- case 11: -- return 45; /* addx8 */ -- case 12: -- return 42; /* sub */ -- case 13: -- return 46; /* subx2 */ -- case 14: -- return 47; /* subx4 */ -- case 15: -- return 48; /* subx8 */ -- } -- break; -- case 1: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- case 1: -- return 111; /* slli */ -- case 2: -- case 3: -- return 112; /* srai */ -- case 4: -- return 113; /* srli */ -- case 6: -- switch (Field_sr_Slot_inst_get (insn)) -- { -- case 0: -- return 129; /* xsr.lbeg */ -- case 1: -- return 123; /* xsr.lend */ -- case 2: -- return 126; /* xsr.lcount */ -- case 3: -- return 132; /* xsr.sar */ -- case 4: -- return 377; /* xsr.br */ -- case 5: -- return 135; /* xsr.litbase */ -- case 12: -- return 456; /* xsr.scompare1 */ -- case 16: -- return 312; /* xsr.acclo */ -- case 17: -- return 315; /* xsr.acchi */ -- case 32: -- return 300; /* xsr.m0 */ -- case 33: -- return 303; /* xsr.m1 */ -- case 34: -- return 306; /* xsr.m2 */ -- case 35: -- return 309; /* xsr.m3 */ -- case 72: -- return 22; /* xsr.windowbase */ -- case 73: -- return 25; /* xsr.windowstart */ -- case 83: -- return 417; /* xsr.ptevaddr */ -- case 90: -- return 420; /* xsr.rasid */ -- case 91: -- return 423; /* xsr.itlbcfg */ -- case 92: -- return 426; /* xsr.dtlbcfg */ -- case 96: -- return 346; /* xsr.ibreakenable */ -- case 104: -- return 358; /* xsr.ddr */ -- case 128: -- return 340; /* xsr.ibreaka0 */ -- case 129: -- return 343; /* xsr.ibreaka1 */ -- case 144: -- return 328; /* xsr.dbreaka0 */ -- case 145: -- return 334; /* xsr.dbreaka1 */ -- case 160: -- return 331; /* xsr.dbreakc0 */ -- case 161: -- return 337; /* xsr.dbreakc1 */ -- case 177: -- return 143; /* xsr.epc1 */ -- case 178: -- return 149; /* xsr.epc2 */ -- case 179: -- return 155; /* xsr.epc3 */ -- case 180: -- return 161; /* xsr.epc4 */ -- case 181: -- return 167; /* xsr.epc5 */ -- case 182: -- return 173; /* xsr.epc6 */ -- case 183: -- return 179; /* xsr.epc7 */ -- case 192: -- return 206; /* xsr.depc */ -- case 194: -- return 185; /* xsr.eps2 */ -- case 195: -- return 188; /* xsr.eps3 */ -- case 196: -- return 191; /* xsr.eps4 */ -- case 197: -- return 194; /* xsr.eps5 */ -- case 198: -- return 197; /* xsr.eps6 */ -- case 199: -- return 200; /* xsr.eps7 */ -- case 209: -- return 146; /* xsr.excsave1 */ -- case 210: -- return 152; /* xsr.excsave2 */ -- case 211: -- return 158; /* xsr.excsave3 */ -- case 212: -- return 164; /* xsr.excsave4 */ -- case 213: -- return 170; /* xsr.excsave5 */ -- case 214: -- return 176; /* xsr.excsave6 */ -- case 215: -- return 182; /* xsr.excsave7 */ -- case 224: -- return 442; /* xsr.cpenable */ -- case 228: -- return 323; /* xsr.intenable */ -- case 230: -- return 140; /* xsr.ps */ -- case 231: -- return 225; /* xsr.vecbase */ -- case 232: -- return 209; /* xsr.exccause */ -- case 233: -- return 349; /* xsr.debugcause */ -- case 234: -- return 380; /* xsr.ccount */ -- case 236: -- return 352; /* xsr.icount */ -- case 237: -- return 355; /* xsr.icountlevel */ -- case 238: -- return 203; /* xsr.excvaddr */ -- case 240: -- return 383; /* xsr.ccompare0 */ -- case 241: -- return 386; /* xsr.ccompare1 */ -- case 242: -- return 389; /* xsr.ccompare2 */ -- case 244: -- return 212; /* xsr.misc0 */ -- case 245: -- return 215; /* xsr.misc1 */ -- case 246: -- return 218; /* xsr.misc2 */ -- case 247: -- return 221; /* xsr.misc3 */ -- } -- break; -- case 8: -- return 108; /* src */ -- case 9: -- if (Field_s_Slot_inst_get (insn) == 0) -- return 109; /* srl */ -- break; -- case 10: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 107; /* sll */ -- break; -- case 11: -- if (Field_s_Slot_inst_get (insn) == 0) -- return 110; /* sra */ -- break; -- case 12: -- return 296; /* mul16u */ -- case 13: -- return 297; /* mul16s */ -- case 15: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 0: -- return 396; /* lict */ -- case 1: -- return 398; /* sict */ -- case 2: -- return 397; /* licw */ -- case 3: -- return 399; /* sicw */ -- case 8: -- return 414; /* ldct */ -- case 9: -- return 413; /* sdct */ -- case 14: -- if (Field_t_Slot_inst_get (insn) == 0) -- return 359; /* rfdo */ -- if (Field_t_Slot_inst_get (insn) == 1) -- return 360; /* rfdd */ -- break; -- case 15: -- return 437; /* ldpte */ -- } -- break; -- } -- break; -- case 2: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- return 362; /* andb */ -- case 1: -- return 363; /* andbc */ -- case 2: -- return 364; /* orb */ -- case 3: -- return 365; /* orbc */ -- case 4: -- return 366; /* xorb */ -- case 8: -- return 461; /* mull */ -- case 10: -- return 462; /* muluh */ -- case 11: -- return 463; /* mulsh */ -- case 12: -- return 457; /* quou */ -- case 13: -- return 458; /* quos */ -- case 14: -- return 459; /* remu */ -- case 15: -- return 460; /* rems */ -- } -- break; -- case 3: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- switch (Field_sr_Slot_inst_get (insn)) -- { -- case 0: -- return 127; /* rsr.lbeg */ -- case 1: -- return 121; /* rsr.lend */ -- case 2: -- return 124; /* rsr.lcount */ -- case 3: -- return 130; /* rsr.sar */ -- case 4: -- return 375; /* rsr.br */ -- case 5: -- return 133; /* rsr.litbase */ -- case 12: -- return 454; /* rsr.scompare1 */ -- case 16: -- return 310; /* rsr.acclo */ -- case 17: -- return 313; /* rsr.acchi */ -- case 32: -- return 298; /* rsr.m0 */ -- case 33: -- return 301; /* rsr.m1 */ -- case 34: -- return 304; /* rsr.m2 */ -- case 35: -- return 307; /* rsr.m3 */ -- case 72: -- return 20; /* rsr.windowbase */ -- case 73: -- return 23; /* rsr.windowstart */ -- case 83: -- return 416; /* rsr.ptevaddr */ -- case 90: -- return 418; /* rsr.rasid */ -- case 91: -- return 421; /* rsr.itlbcfg */ -- case 92: -- return 424; /* rsr.dtlbcfg */ -- case 96: -- return 344; /* rsr.ibreakenable */ -- case 104: -- return 356; /* rsr.ddr */ -- case 128: -- return 338; /* rsr.ibreaka0 */ -- case 129: -- return 341; /* rsr.ibreaka1 */ -- case 144: -- return 326; /* rsr.dbreaka0 */ -- case 145: -- return 332; /* rsr.dbreaka1 */ -- case 160: -- return 329; /* rsr.dbreakc0 */ -- case 161: -- return 335; /* rsr.dbreakc1 */ -- case 176: -- return 136; /* rsr.176 */ -- case 177: -- return 141; /* rsr.epc1 */ -- case 178: -- return 147; /* rsr.epc2 */ -- case 179: -- return 153; /* rsr.epc3 */ -- case 180: -- return 159; /* rsr.epc4 */ -- case 181: -- return 165; /* rsr.epc5 */ -- case 182: -- return 171; /* rsr.epc6 */ -- case 183: -- return 177; /* rsr.epc7 */ -- case 192: -- return 204; /* rsr.depc */ -- case 194: -- return 183; /* rsr.eps2 */ -- case 195: -- return 186; /* rsr.eps3 */ -- case 196: -- return 189; /* rsr.eps4 */ -- case 197: -- return 192; /* rsr.eps5 */ -- case 198: -- return 195; /* rsr.eps6 */ -- case 199: -- return 198; /* rsr.eps7 */ -- case 208: -- return 137; /* rsr.208 */ -- case 209: -- return 144; /* rsr.excsave1 */ -- case 210: -- return 150; /* rsr.excsave2 */ -- case 211: -- return 156; /* rsr.excsave3 */ -- case 212: -- return 162; /* rsr.excsave4 */ -- case 213: -- return 168; /* rsr.excsave5 */ -- case 214: -- return 174; /* rsr.excsave6 */ -- case 215: -- return 180; /* rsr.excsave7 */ -- case 224: -- return 440; /* rsr.cpenable */ -- case 226: -- return 318; /* rsr.interrupt */ -- case 228: -- return 321; /* rsr.intenable */ -- case 230: -- return 138; /* rsr.ps */ -- case 231: -- return 223; /* rsr.vecbase */ -- case 232: -- return 207; /* rsr.exccause */ -- case 233: -- return 347; /* rsr.debugcause */ -- case 234: -- return 378; /* rsr.ccount */ -- case 235: -- return 222; /* rsr.prid */ -- case 236: -- return 350; /* rsr.icount */ -- case 237: -- return 353; /* rsr.icountlevel */ -- case 238: -- return 201; /* rsr.excvaddr */ -- case 240: -- return 381; /* rsr.ccompare0 */ -- case 241: -- return 384; /* rsr.ccompare1 */ -- case 242: -- return 387; /* rsr.ccompare2 */ -- case 244: -- return 210; /* rsr.misc0 */ -- case 245: -- return 213; /* rsr.misc1 */ -- case 246: -- return 216; /* rsr.misc2 */ -- case 247: -- return 219; /* rsr.misc3 */ -- } -- break; -- case 1: -- switch (Field_sr_Slot_inst_get (insn)) -- { -- case 0: -- return 128; /* wsr.lbeg */ -- case 1: -- return 122; /* wsr.lend */ -- case 2: -- return 125; /* wsr.lcount */ -- case 3: -- return 131; /* wsr.sar */ -- case 4: -- return 376; /* wsr.br */ -- case 5: -- return 134; /* wsr.litbase */ -- case 12: -- return 455; /* wsr.scompare1 */ -- case 16: -- return 311; /* wsr.acclo */ -- case 17: -- return 314; /* wsr.acchi */ -- case 32: -- return 299; /* wsr.m0 */ -- case 33: -- return 302; /* wsr.m1 */ -- case 34: -- return 305; /* wsr.m2 */ -- case 35: -- return 308; /* wsr.m3 */ -- case 72: -- return 21; /* wsr.windowbase */ -- case 73: -- return 24; /* wsr.windowstart */ -- case 83: -- return 415; /* wsr.ptevaddr */ -- case 89: -- return 361; /* wsr.mmid */ -- case 90: -- return 419; /* wsr.rasid */ -- case 91: -- return 422; /* wsr.itlbcfg */ -- case 92: -- return 425; /* wsr.dtlbcfg */ -- case 96: -- return 345; /* wsr.ibreakenable */ -- case 104: -- return 357; /* wsr.ddr */ -- case 128: -- return 339; /* wsr.ibreaka0 */ -- case 129: -- return 342; /* wsr.ibreaka1 */ -- case 144: -- return 327; /* wsr.dbreaka0 */ -- case 145: -- return 333; /* wsr.dbreaka1 */ -- case 160: -- return 330; /* wsr.dbreakc0 */ -- case 161: -- return 336; /* wsr.dbreakc1 */ -- case 177: -- return 142; /* wsr.epc1 */ -- case 178: -- return 148; /* wsr.epc2 */ -- case 179: -- return 154; /* wsr.epc3 */ -- case 180: -- return 160; /* wsr.epc4 */ -- case 181: -- return 166; /* wsr.epc5 */ -- case 182: -- return 172; /* wsr.epc6 */ -- case 183: -- return 178; /* wsr.epc7 */ -- case 192: -- return 205; /* wsr.depc */ -- case 194: -- return 184; /* wsr.eps2 */ -- case 195: -- return 187; /* wsr.eps3 */ -- case 196: -- return 190; /* wsr.eps4 */ -- case 197: -- return 193; /* wsr.eps5 */ -- case 198: -- return 196; /* wsr.eps6 */ -- case 199: -- return 199; /* wsr.eps7 */ -- case 209: -- return 145; /* wsr.excsave1 */ -- case 210: -- return 151; /* wsr.excsave2 */ -- case 211: -- return 157; /* wsr.excsave3 */ -- case 212: -- return 163; /* wsr.excsave4 */ -- case 213: -- return 169; /* wsr.excsave5 */ -- case 214: -- return 175; /* wsr.excsave6 */ -- case 215: -- return 181; /* wsr.excsave7 */ -- case 224: -- return 441; /* wsr.cpenable */ -- case 226: -- return 319; /* wsr.intset */ -- case 227: -- return 320; /* wsr.intclear */ -- case 228: -- return 322; /* wsr.intenable */ -- case 230: -- return 139; /* wsr.ps */ -- case 231: -- return 224; /* wsr.vecbase */ -- case 232: -- return 208; /* wsr.exccause */ -- case 233: -- return 348; /* wsr.debugcause */ -- case 234: -- return 379; /* wsr.ccount */ -- case 236: -- return 351; /* wsr.icount */ -- case 237: -- return 354; /* wsr.icountlevel */ -- case 238: -- return 202; /* wsr.excvaddr */ -- case 240: -- return 382; /* wsr.ccompare0 */ -- case 241: -- return 385; /* wsr.ccompare1 */ -- case 242: -- return 388; /* wsr.ccompare2 */ -- case 244: -- return 211; /* wsr.misc0 */ -- case 245: -- return 214; /* wsr.misc1 */ -- case 246: -- return 217; /* wsr.misc2 */ -- case 247: -- return 220; /* wsr.misc3 */ -- } -- break; -- case 2: -- return 450; /* sext */ -- case 3: -- return 443; /* clamps */ -- case 4: -- return 444; /* min */ -- case 5: -- return 445; /* max */ -- case 6: -- return 446; /* minu */ -- case 7: -- return 447; /* maxu */ -- case 8: -- return 91; /* moveqz */ -- case 9: -- return 92; /* movnez */ -- case 10: -- return 93; /* movltz */ -- case 11: -- return 94; /* movgez */ -- case 12: -- return 373; /* movf */ -- case 13: -- return 374; /* movt */ -- case 14: -- switch (Field_st_Slot_inst_get (insn)) -- { -- case 231: -- return 37; /* rur.threadptr */ -- case 232: -- return 464; /* rur.fcr */ -- case 233: -- return 466; /* rur.fsr */ -- } -- break; -- case 15: -- switch (Field_sr_Slot_inst_get (insn)) -- { -- case 231: -- return 38; /* wur.threadptr */ -- case 232: -- return 465; /* wur.fcr */ -- case 233: -- return 467; /* wur.fsr */ -- } -- break; -- } -- break; -- case 4: -- case 5: -- return 78; /* extui */ -- case 8: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- return 500; /* lsx */ -- case 1: -- return 501; /* lsxu */ -- case 4: -- return 504; /* ssx */ -- case 5: -- return 505; /* ssxu */ -- } -- break; -- case 9: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- return 18; /* l32e */ -- case 4: -- return 19; /* s32e */ -- } -- break; -- case 10: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- return 468; /* add.s */ -- case 1: -- return 469; /* sub.s */ -- case 2: -- return 470; /* mul.s */ -- case 4: -- return 471; /* madd.s */ -- case 5: -- return 472; /* msub.s */ -- case 8: -- return 491; /* round.s */ -- case 9: -- return 494; /* trunc.s */ -- case 10: -- return 493; /* floor.s */ -- case 11: -- return 492; /* ceil.s */ -- case 12: -- return 489; /* float.s */ -- case 13: -- return 490; /* ufloat.s */ -- case 14: -- return 495; /* utrunc.s */ -- case 15: -- switch (Field_t_Slot_inst_get (insn)) -- { -- case 0: -- return 480; /* mov.s */ -- case 1: -- return 479; /* abs.s */ -- case 4: -- return 496; /* rfr */ -- case 5: -- return 497; /* wfr */ -- case 6: -- return 481; /* neg.s */ -- } -- break; -- } -- break; -- case 11: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 1: -- return 482; /* un.s */ -- case 2: -- return 483; /* oeq.s */ -- case 3: -- return 484; /* ueq.s */ -- case 4: -- return 485; /* olt.s */ -- case 5: -- return 486; /* ult.s */ -- case 6: -- return 487; /* ole.s */ -- case 7: -- return 488; /* ule.s */ -- case 8: -- return 475; /* moveqz.s */ -- case 9: -- return 476; /* movnez.s */ -- case 10: -- return 477; /* movltz.s */ -- case 11: -- return 478; /* movgez.s */ -- case 12: -- return 473; /* movf.s */ -- case 13: -- return 474; /* movt.s */ -- } -- break; -- } -- break; -- case 1: -- return 85; /* l32r */ -- case 2: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 0: -- return 86; /* l8ui */ -- case 1: -- return 82; /* l16ui */ -- case 2: -- return 84; /* l32i */ -- case 4: -- return 101; /* s8i */ -- case 5: -- return 99; /* s16i */ -- case 6: -- return 100; /* s32i */ -- case 7: -- switch (Field_t_Slot_inst_get (insn)) -- { -- case 0: -- return 406; /* dpfr */ -- case 1: -- return 407; /* dpfw */ -- case 2: -- return 408; /* dpfro */ -- case 3: -- return 409; /* dpfwo */ -- case 4: -- return 400; /* dhwb */ -- case 5: -- return 401; /* dhwbi */ -- case 6: -- return 404; /* dhi */ -- case 7: -- return 405; /* dii */ -- case 8: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 0: -- return 410; /* dpfl */ -- case 2: -- return 411; /* dhu */ -- case 3: -- return 412; /* diu */ -- case 4: -- return 402; /* diwb */ -- case 5: -- return 403; /* diwbi */ -- } -- break; -- case 12: -- return 390; /* ipf */ -- case 13: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 0: -- return 392; /* ipfl */ -- case 2: -- return 393; /* ihu */ -- case 3: -- return 394; /* iiu */ -- } -- break; -- case 14: -- return 391; /* ihi */ -- case 15: -- return 395; /* iii */ -- } -- break; -- case 9: -- return 83; /* l16si */ -- case 10: -- return 90; /* movi */ -- case 11: -- return 451; /* l32ai */ -- case 12: -- return 39; /* addi */ -- case 13: -- return 40; /* addmi */ -- case 14: -- return 453; /* s32c1i */ -- case 15: -- return 452; /* s32ri */ -- } -- break; -- case 3: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 0: -- return 498; /* lsi */ -- case 4: -- return 502; /* ssi */ -- case 8: -- return 499; /* lsiu */ -- case 12: -- return 503; /* ssiu */ -- } -- break; -- case 4: -- switch (Field_op2_Slot_inst_get (insn)) -- { -- case 0: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 8: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 287; /* mula.dd.ll.ldinc */ -- break; -- case 9: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 289; /* mula.dd.hl.ldinc */ -- break; -- case 10: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 291; /* mula.dd.lh.ldinc */ -- break; -- case 11: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 293; /* mula.dd.hh.ldinc */ -- break; -- } -- break; -- case 1: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 8: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 286; /* mula.dd.ll.lddec */ -- break; -- case 9: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 288; /* mula.dd.hl.lddec */ -- break; -- case 10: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 290; /* mula.dd.lh.lddec */ -- break; -- case 11: -- if (Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 292; /* mula.dd.hh.lddec */ -- break; -- } -- break; -- case 2: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 4: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 242; /* mul.dd.ll */ -- break; -- case 5: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 243; /* mul.dd.hl */ -- break; -- case 6: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 244; /* mul.dd.lh */ -- break; -- case 7: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 245; /* mul.dd.hh */ -- break; -- case 8: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 270; /* mula.dd.ll */ -- break; -- case 9: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 271; /* mula.dd.hl */ -- break; -- case 10: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 272; /* mula.dd.lh */ -- break; -- case 11: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 273; /* mula.dd.hh */ -- break; -- case 12: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 274; /* muls.dd.ll */ -- break; -- case 13: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 275; /* muls.dd.hl */ -- break; -- case 14: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 276; /* muls.dd.lh */ -- break; -- case 15: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 277; /* muls.dd.hh */ -- break; -- } -- break; -- case 3: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 4: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 234; /* mul.ad.ll */ -- break; -- case 5: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 235; /* mul.ad.hl */ -- break; -- case 6: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 236; /* mul.ad.lh */ -- break; -- case 7: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 237; /* mul.ad.hh */ -- break; -- case 8: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 254; /* mula.ad.ll */ -- break; -- case 9: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 255; /* mula.ad.hl */ -- break; -- case 10: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 256; /* mula.ad.lh */ -- break; -- case 11: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 257; /* mula.ad.hh */ -- break; -- case 12: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 258; /* muls.ad.ll */ -- break; -- case 13: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 259; /* muls.ad.hl */ -- break; -- case 14: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 260; /* muls.ad.lh */ -- break; -- case 15: -- if (Field_r_Slot_inst_get (insn) == 0 && -- Field_t3_Slot_inst_get (insn) == 0 && -- Field_tlo_Slot_inst_get (insn) == 0) -- return 261; /* muls.ad.hh */ -- break; -- } -- break; -- case 4: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 8: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 279; /* mula.da.ll.ldinc */ -- break; -- case 9: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 281; /* mula.da.hl.ldinc */ -- break; -- case 10: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 283; /* mula.da.lh.ldinc */ -- break; -- case 11: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 285; /* mula.da.hh.ldinc */ -- break; -- } -- break; -- case 5: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 8: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 278; /* mula.da.ll.lddec */ -- break; -- case 9: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 280; /* mula.da.hl.lddec */ -- break; -- case 10: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 282; /* mula.da.lh.lddec */ -- break; -- case 11: -- if (Field_r3_Slot_inst_get (insn) == 0) -- return 284; /* mula.da.hh.lddec */ -- break; -- } -- break; -- case 6: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 4: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 238; /* mul.da.ll */ -- break; -- case 5: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 239; /* mul.da.hl */ -- break; -- case 6: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 240; /* mul.da.lh */ -- break; -- case 7: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 241; /* mul.da.hh */ -- break; -- case 8: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 262; /* mula.da.ll */ -- break; -- case 9: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 263; /* mula.da.hl */ -- break; -- case 10: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 264; /* mula.da.lh */ -- break; -- case 11: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 265; /* mula.da.hh */ -- break; -- case 12: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 266; /* muls.da.ll */ -- break; -- case 13: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 267; /* muls.da.hl */ -- break; -- case 14: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 268; /* muls.da.lh */ -- break; -- case 15: -- if (Field_s_Slot_inst_get (insn) == 0 && -- Field_w_Slot_inst_get (insn) == 0 && -- Field_r3_Slot_inst_get (insn) == 0) -- return 269; /* muls.da.hh */ -- break; -- } -- break; -- case 7: -- switch (Field_op1_Slot_inst_get (insn)) -- { -- case 0: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 230; /* umul.aa.ll */ -- break; -- case 1: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 231; /* umul.aa.hl */ -- break; -- case 2: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 232; /* umul.aa.lh */ -- break; -- case 3: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 233; /* umul.aa.hh */ -- break; -- case 4: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 226; /* mul.aa.ll */ -- break; -- case 5: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 227; /* mul.aa.hl */ -- break; -- case 6: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 228; /* mul.aa.lh */ -- break; -- case 7: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 229; /* mul.aa.hh */ -- break; -- case 8: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 246; /* mula.aa.ll */ -- break; -- case 9: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 247; /* mula.aa.hl */ -- break; -- case 10: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 248; /* mula.aa.lh */ -- break; -- case 11: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 249; /* mula.aa.hh */ -- break; -- case 12: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 250; /* muls.aa.ll */ -- break; -- case 13: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 251; /* muls.aa.hl */ -- break; -- case 14: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 252; /* muls.aa.lh */ -- break; -- case 15: -- if (Field_r_Slot_inst_get (insn) == 0) -- return 253; /* muls.aa.hh */ -- break; -- } -- break; -- case 8: -- if (Field_op1_Slot_inst_get (insn) == 0 && -- Field_t_Slot_inst_get (insn) == 0 && -- Field_rhi_Slot_inst_get (insn) == 0) -- return 295; /* ldinc */ -- break; -- case 9: -- if (Field_op1_Slot_inst_get (insn) == 0 && -- Field_t_Slot_inst_get (insn) == 0 && -- Field_rhi_Slot_inst_get (insn) == 0) -- return 294; /* lddec */ -- break; -- } -- break; -- case 5: -- switch (Field_n_Slot_inst_get (insn)) -- { -- case 0: -- return 76; /* call0 */ -- case 1: -- return 7; /* call4 */ -- case 2: -- return 6; /* call8 */ -- case 3: -- return 5; /* call12 */ -- } -- break; -- case 6: -- switch (Field_n_Slot_inst_get (insn)) -- { -- case 0: -- return 80; /* j */ -- case 1: -- switch (Field_m_Slot_inst_get (insn)) -- { -- case 0: -- return 72; /* beqz */ -- case 1: -- return 73; /* bnez */ -- case 2: -- return 75; /* bltz */ -- case 3: -- return 74; /* bgez */ -- } -- break; -- case 2: -- switch (Field_m_Slot_inst_get (insn)) -- { -- case 0: -- return 52; /* beqi */ -- case 1: -- return 53; /* bnei */ -- case 2: -- return 55; /* blti */ -- case 3: -- return 54; /* bgei */ -- } -- break; -- case 3: -- switch (Field_m_Slot_inst_get (insn)) -- { -- case 0: -- return 11; /* entry */ -- case 1: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 0: -- return 371; /* bf */ -- case 1: -- return 372; /* bt */ -- case 8: -- return 87; /* loop */ -- case 9: -- return 88; /* loopnez */ -- case 10: -- return 89; /* loopgtz */ -- } -- break; -- case 2: -- return 59; /* bltui */ -- case 3: -- return 58; /* bgeui */ -- } -- break; -- } -- break; -- case 7: -- switch (Field_r_Slot_inst_get (insn)) -- { -- case 0: -- return 67; /* bnone */ -- case 1: -- return 60; /* beq */ -- case 2: -- return 63; /* blt */ -- case 3: -- return 65; /* bltu */ -- case 4: -- return 68; /* ball */ -- case 5: -- return 70; /* bbc */ -- case 6: -- case 7: -- return 56; /* bbci */ -- case 8: -- return 66; /* bany */ -- case 9: -- return 61; /* bne */ -- case 10: -- return 62; /* bge */ -- case 11: -- return 64; /* bgeu */ -- case 12: -- return 69; /* bnall */ -- case 13: -- return 71; /* bbs */ -- case 14: -- case 15: -- return 57; /* bbsi */ -- } -- break; -- } -- return 0; --} -- --static int --Slot_inst16b_decode (const xtensa_insnbuf insn) --{ -- switch (Field_op0_Slot_inst16b_get (insn)) -- { -- case 12: -- switch (Field_i_Slot_inst16b_get (insn)) -- { -- case 0: -- return 33; /* movi.n */ -- case 1: -- switch (Field_z_Slot_inst16b_get (insn)) -- { -- case 0: -- return 28; /* beqz.n */ -- case 1: -- return 29; /* bnez.n */ -- } -- break; -- } -- break; -- case 13: -- switch (Field_r_Slot_inst16b_get (insn)) -- { -- case 0: -- return 32; /* mov.n */ -- case 15: -- switch (Field_t_Slot_inst16b_get (insn)) -- { -- case 0: -- return 35; /* ret.n */ -- case 1: -- return 15; /* retw.n */ -- case 2: -- return 325; /* break.n */ -- case 3: -- if (Field_s_Slot_inst16b_get (insn) == 0) -- return 34; /* nop.n */ -- break; -- case 6: -- if (Field_s_Slot_inst16b_get (insn) == 0) -- return 30; /* ill.n */ -- break; -- } -- break; -- } -- break; -- } -- return 0; --} -- --static int --Slot_inst16a_decode (const xtensa_insnbuf insn) --{ -- switch (Field_op0_Slot_inst16a_get (insn)) -- { -- case 8: -- return 31; /* l32i.n */ -- case 9: -- return 36; /* s32i.n */ -- case 10: -- return 26; /* add.n */ -- case 11: -- return 27; /* addi.n */ -- } -- return 0; --} -- --static int --Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn) --{ -- switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn)) -- { -- case 0: -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1) -- return 41; /* add */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5) -- return 42; /* sub */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2) -- return 43; /* addx2 */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3) -- return 49; /* and */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4) -- return 450; /* sext */ -- break; -- case 1: -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1) -- return 27; /* addi.n */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2) -- return 44; /* addx4 */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3) -- return 50; /* or */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5) -- return 51; /* xor */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4) -- return 113; /* srli */ -- break; -- } -- if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 && -- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6) -- return 33; /* movi.n */ -- if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 && -- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && -- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) -- return 32; /* mov.n */ -- if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 && -- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && -- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) -- return 97; /* nop */ -- if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 && -- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && -- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) -- return 96; /* abs */ -- if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 && -- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && -- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) -- return 95; /* neg */ -- if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 && -- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && -- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) -- return 110; /* sra */ -- if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 && -- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 && -- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0) -- return 109; /* srl */ -- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7) -- return 112; /* srai */ -- return 0; --} -- --static int --Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn) --{ -- switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn)) -- { -- case 0: -- if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2) -- return 78; /* extui */ -- switch (Field_op1_Slot_xt_flix64_slot0_get (insn)) -- { -- case 0: -- switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) -- { -- case 0: -- if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2) -- { -- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) -- { -- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15) -- return 97; /* nop */ -- } -- } -- break; -- case 1: -- return 49; /* and */ -- case 2: -- return 50; /* or */ -- case 3: -- return 51; /* xor */ -- case 4: -- switch (Field_r_Slot_xt_flix64_slot0_get (insn)) -- { -- case 0: -- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) -- return 102; /* ssr */ -- break; -- case 1: -- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) -- return 103; /* ssl */ -- break; -- case 2: -- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) -- return 104; /* ssa8l */ -- break; -- case 3: -- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) -- return 105; /* ssa8b */ -- break; -- case 4: -- if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0) -- return 106; /* ssai */ -- break; -- case 14: -- return 448; /* nsa */ -- case 15: -- return 449; /* nsau */ -- } -- break; -- case 6: -- switch (Field_s_Slot_xt_flix64_slot0_get (insn)) -- { -- case 0: -- return 95; /* neg */ -- case 1: -- return 96; /* abs */ -- } -- break; -- case 8: -- return 41; /* add */ -- case 9: -- return 43; /* addx2 */ -- case 10: -- return 44; /* addx4 */ -- case 11: -- return 45; /* addx8 */ -- case 12: -- return 42; /* sub */ -- case 13: -- return 46; /* subx2 */ -- case 14: -- return 47; /* subx4 */ -- case 15: -- return 48; /* subx8 */ -- } -- break; -- case 1: -- if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1) -- return 112; /* srai */ -- if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0) -- return 111; /* slli */ -- switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) -- { -- case 4: -- return 113; /* srli */ -- case 8: -- return 108; /* src */ -- case 9: -- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) -- return 109; /* srl */ -- break; -- case 10: -- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0) -- return 107; /* sll */ -- break; -- case 11: -- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0) -- return 110; /* sra */ -- break; -- case 12: -- return 296; /* mul16u */ -- case 13: -- return 297; /* mul16s */ -- } -- break; -- case 2: -- if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8) -- return 461; /* mull */ -- break; -- case 3: -- switch (Field_op2_Slot_xt_flix64_slot0_get (insn)) -- { -- case 2: -- return 450; /* sext */ -- case 3: -- return 443; /* clamps */ -- case 4: -- return 444; /* min */ -- case 5: -- return 445; /* max */ -- case 6: -- return 446; /* minu */ -- case 7: -- return 447; /* maxu */ -- case 8: -- return 91; /* moveqz */ -- case 9: -- return 92; /* movnez */ -- case 10: -- return 93; /* movltz */ -- case 11: -- return 94; /* movgez */ -- } -- break; -- } -- break; -- case 2: -- switch (Field_r_Slot_xt_flix64_slot0_get (insn)) -- { -- case 0: -- return 86; /* l8ui */ -- case 1: -- return 82; /* l16ui */ -- case 2: -- return 84; /* l32i */ -- case 4: -- return 101; /* s8i */ -- case 5: -- return 99; /* s16i */ -- case 6: -- return 100; /* s32i */ -- case 9: -- return 83; /* l16si */ -- case 10: -- return 90; /* movi */ -- case 12: -- return 39; /* addi */ -- case 13: -- return 40; /* addmi */ -- } -- break; -- } -- if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1) -- return 85; /* l32r */ -- if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 && -- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 && -- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 && -- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0) -- return 32; /* mov.n */ -- return 0; --} -- --static int --Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn) --{ -- if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) -- return 78; /* extui */ -- switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) -- { -- case 0: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 90; /* movi */ -- break; -- case 2: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) -- return 39; /* addi */ -- break; -- case 3: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1) -- return 40; /* addmi */ -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0) -- return 51; /* xor */ -- break; -- } -- switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) -- { -- case 8: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 111; /* slli */ -- break; -- case 16: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 112; /* srai */ -- break; -- case 19: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 107; /* sll */ -- break; -- } -- switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn)) -- { -- case 18: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 41; /* add */ -- break; -- case 19: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 45; /* addx8 */ -- break; -- case 20: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 43; /* addx2 */ -- break; -- case 21: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 49; /* and */ -- break; -- case 22: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 91; /* moveqz */ -- break; -- case 23: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 94; /* movgez */ -- break; -- case 24: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 44; /* addx4 */ -- break; -- case 25: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 93; /* movltz */ -- break; -- case 26: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 92; /* movnez */ -- break; -- case 27: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 296; /* mul16u */ -- break; -- case 28: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 297; /* mul16s */ -- break; -- case 29: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 461; /* mull */ -- break; -- case 30: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 50; /* or */ -- break; -- case 31: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 450; /* sext */ -- break; -- case 34: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 108; /* src */ -- break; -- case 36: -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2) -- return 113; /* srli */ -- break; -- } -- if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 32; /* mov.n */ -- if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 81; /* jx */ -- if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 103; /* ssl */ -- if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 97; /* nop */ -- if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 95; /* neg */ -- if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 110; /* sra */ -- if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 109; /* srl */ -- if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 && -- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 && -- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0) -- return 42; /* sub */ -- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3) -- return 80; /* j */ -- return 0; --} -- --static int --Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn) --{ -- switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn)) -- { -- case 1: -- if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0) -- return 516; /* bbci.w18 */ -- break; -- case 2: -- if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0) -- return 517; /* bbsi.w18 */ -- break; -- case 3: -- if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 526; /* ball.w18 */ -- break; -- case 4: -- if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 524; /* bany.w18 */ -- break; -- case 5: -- if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 528; /* bbc.w18 */ -- break; -- case 6: -- if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 529; /* bbs.w18 */ -- break; -- case 7: -- if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 518; /* beq.w18 */ -- break; -- case 8: -- if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 510; /* beqi.w18 */ -- break; -- case 9: -- if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 520; /* bge.w18 */ -- break; -- case 10: -- if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 512; /* bgei.w18 */ -- break; -- case 11: -- if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 522; /* bgeu.w18 */ -- break; -- case 12: -- if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 514; /* bgeui.w18 */ -- break; -- case 13: -- if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 521; /* blt.w18 */ -- break; -- case 14: -- if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 513; /* blti.w18 */ -- break; -- case 15: -- if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 523; /* bltu.w18 */ -- break; -- case 16: -- if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 515; /* bltui.w18 */ -- break; -- case 17: -- if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 527; /* bnall.w18 */ -- break; -- case 18: -- if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 519; /* bne.w18 */ -- break; -- case 19: -- if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 511; /* bnei.w18 */ -- break; -- case 20: -- if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 525; /* bnone.w18 */ -- break; -- case 21: -- if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 506; /* beqz.w18 */ -- break; -- case 22: -- if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 508; /* bgez.w18 */ -- break; -- case 23: -- if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 509; /* bltz.w18 */ -- break; -- case 24: -- if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 507; /* bnez.w18 */ -- break; -- case 25: -- if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0) -- return 97; /* nop */ -- break; -- } -- return 0; --} -- -- --/* Instruction slots. */ -- --static void --Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[1] = 0; -- slotbuf[0] = (insn[0] & 0xffffff); --} -- --static void --Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); --} -- --static void --Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[1] = 0; -- slotbuf[0] = (insn[0] & 0xffff); --} -- --static void --Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); --} -- --static void --Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[1] = 0; -- slotbuf[0] = (insn[0] & 0xffff); --} -- --static void --Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); --} -- --static void --Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[1] = 0; -- slotbuf[0] = ((insn[0] & 0xffffff0) >> 4); --} -- --static void --Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4); --} -- --static void --Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[1] = 0; -- slotbuf[0] = ((insn[0] & 0xffffff0) >> 4); --} -- --static void --Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4); --} -- --static void --Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[1] = 0; -- slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); -- slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4); --} -- --static void --Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); -- insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4); --} -- --static void --Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[1] = 0; -- slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); --} -- --static void --Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); --} -- --static void --Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn, -- xtensa_insnbuf slotbuf) --{ -- slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); -- slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4); -- slotbuf[1] = ((insn[1] & 0x70000000) >> 28); --} -- --static void --Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn, -- const xtensa_insnbuf slotbuf) --{ -- insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); -- insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4); -- insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28); --} -- --static xtensa_get_field_fn --Slot_inst_get_field_fns[] = { -- Field_t_Slot_inst_get, -- Field_bbi4_Slot_inst_get, -- Field_bbi_Slot_inst_get, -- Field_imm12_Slot_inst_get, -- Field_imm8_Slot_inst_get, -- Field_s_Slot_inst_get, -- Field_imm12b_Slot_inst_get, -- Field_imm16_Slot_inst_get, -- Field_m_Slot_inst_get, -- Field_n_Slot_inst_get, -- Field_offset_Slot_inst_get, -- Field_op0_Slot_inst_get, -- Field_op1_Slot_inst_get, -- Field_op2_Slot_inst_get, -- Field_r_Slot_inst_get, -- Field_sa4_Slot_inst_get, -- Field_sae4_Slot_inst_get, -- Field_sae_Slot_inst_get, -- Field_sal_Slot_inst_get, -- Field_sargt_Slot_inst_get, -- Field_sas4_Slot_inst_get, -- Field_sas_Slot_inst_get, -- Field_sr_Slot_inst_get, -- Field_st_Slot_inst_get, -- Field_thi3_Slot_inst_get, -- Field_imm4_Slot_inst_get, -- Field_mn_Slot_inst_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_r3_Slot_inst_get, -- Field_rbit2_Slot_inst_get, -- Field_rhi_Slot_inst_get, -- Field_t3_Slot_inst_get, -- Field_tbit2_Slot_inst_get, -- Field_tlo_Slot_inst_get, -- Field_w_Slot_inst_get, -- Field_y_Slot_inst_get, -- Field_x_Slot_inst_get, -- Field_t2_Slot_inst_get, -- Field_s2_Slot_inst_get, -- Field_r2_Slot_inst_get, -- Field_t4_Slot_inst_get, -- Field_s4_Slot_inst_get, -- Field_r4_Slot_inst_get, -- Field_t8_Slot_inst_get, -- Field_s8_Slot_inst_get, -- Field_r8_Slot_inst_get, -- Field_xt_wbr15_imm_Slot_inst_get, -- Field_xt_wbr18_imm_Slot_inst_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_ar0_get, -- Implicit_Field_ar4_get, -- Implicit_Field_ar8_get, -- Implicit_Field_ar12_get, -- Implicit_Field_mr0_get, -- Implicit_Field_mr1_get, -- Implicit_Field_mr2_get, -- Implicit_Field_mr3_get, -- Implicit_Field_bt16_get, -- Implicit_Field_bs16_get, -- Implicit_Field_br16_get, -- Implicit_Field_brall_get --}; -- --static xtensa_set_field_fn --Slot_inst_set_field_fns[] = { -- Field_t_Slot_inst_set, -- Field_bbi4_Slot_inst_set, -- Field_bbi_Slot_inst_set, -- Field_imm12_Slot_inst_set, -- Field_imm8_Slot_inst_set, -- Field_s_Slot_inst_set, -- Field_imm12b_Slot_inst_set, -- Field_imm16_Slot_inst_set, -- Field_m_Slot_inst_set, -- Field_n_Slot_inst_set, -- Field_offset_Slot_inst_set, -- Field_op0_Slot_inst_set, -- Field_op1_Slot_inst_set, -- Field_op2_Slot_inst_set, -- Field_r_Slot_inst_set, -- Field_sa4_Slot_inst_set, -- Field_sae4_Slot_inst_set, -- Field_sae_Slot_inst_set, -- Field_sal_Slot_inst_set, -- Field_sargt_Slot_inst_set, -- Field_sas4_Slot_inst_set, -- Field_sas_Slot_inst_set, -- Field_sr_Slot_inst_set, -- Field_st_Slot_inst_set, -- Field_thi3_Slot_inst_set, -- Field_imm4_Slot_inst_set, -- Field_mn_Slot_inst_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_r3_Slot_inst_set, -- Field_rbit2_Slot_inst_set, -- Field_rhi_Slot_inst_set, -- Field_t3_Slot_inst_set, -- Field_tbit2_Slot_inst_set, -- Field_tlo_Slot_inst_set, -- Field_w_Slot_inst_set, -- Field_y_Slot_inst_set, -- Field_x_Slot_inst_set, -- Field_t2_Slot_inst_set, -- Field_s2_Slot_inst_set, -- Field_r2_Slot_inst_set, -- Field_t4_Slot_inst_set, -- Field_s4_Slot_inst_set, -- Field_r4_Slot_inst_set, -- Field_t8_Slot_inst_set, -- Field_s8_Slot_inst_set, -- Field_r8_Slot_inst_set, -- Field_xt_wbr15_imm_Slot_inst_set, -- Field_xt_wbr18_imm_Slot_inst_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set --}; -- --static xtensa_get_field_fn --Slot_inst16a_get_field_fns[] = { -- Field_t_Slot_inst16a_get, -- 0, -- 0, -- 0, -- 0, -- Field_s_Slot_inst16a_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_Slot_inst16a_get, -- 0, -- 0, -- Field_r_Slot_inst16a_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_sr_Slot_inst16a_get, -- Field_st_Slot_inst16a_get, -- 0, -- Field_imm4_Slot_inst16a_get, -- 0, -- Field_i_Slot_inst16a_get, -- Field_imm6lo_Slot_inst16a_get, -- Field_imm6hi_Slot_inst16a_get, -- Field_imm7lo_Slot_inst16a_get, -- Field_imm7hi_Slot_inst16a_get, -- Field_z_Slot_inst16a_get, -- Field_imm6_Slot_inst16a_get, -- Field_imm7_Slot_inst16a_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_t2_Slot_inst16a_get, -- Field_s2_Slot_inst16a_get, -- Field_r2_Slot_inst16a_get, -- Field_t4_Slot_inst16a_get, -- Field_s4_Slot_inst16a_get, -- Field_r4_Slot_inst16a_get, -- Field_t8_Slot_inst16a_get, -- Field_s8_Slot_inst16a_get, -- Field_r8_Slot_inst16a_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_ar0_get, -- Implicit_Field_ar4_get, -- Implicit_Field_ar8_get, -- Implicit_Field_ar12_get, -- Implicit_Field_mr0_get, -- Implicit_Field_mr1_get, -- Implicit_Field_mr2_get, -- Implicit_Field_mr3_get, -- Implicit_Field_bt16_get, -- Implicit_Field_bs16_get, -- Implicit_Field_br16_get, -- Implicit_Field_brall_get --}; -- --static xtensa_set_field_fn --Slot_inst16a_set_field_fns[] = { -- Field_t_Slot_inst16a_set, -- 0, -- 0, -- 0, -- 0, -- Field_s_Slot_inst16a_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_Slot_inst16a_set, -- 0, -- 0, -- Field_r_Slot_inst16a_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_sr_Slot_inst16a_set, -- Field_st_Slot_inst16a_set, -- 0, -- Field_imm4_Slot_inst16a_set, -- 0, -- Field_i_Slot_inst16a_set, -- Field_imm6lo_Slot_inst16a_set, -- Field_imm6hi_Slot_inst16a_set, -- Field_imm7lo_Slot_inst16a_set, -- Field_imm7hi_Slot_inst16a_set, -- Field_z_Slot_inst16a_set, -- Field_imm6_Slot_inst16a_set, -- Field_imm7_Slot_inst16a_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_t2_Slot_inst16a_set, -- Field_s2_Slot_inst16a_set, -- Field_r2_Slot_inst16a_set, -- Field_t4_Slot_inst16a_set, -- Field_s4_Slot_inst16a_set, -- Field_r4_Slot_inst16a_set, -- Field_t8_Slot_inst16a_set, -- Field_s8_Slot_inst16a_set, -- Field_r8_Slot_inst16a_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set --}; -- --static xtensa_get_field_fn --Slot_inst16b_get_field_fns[] = { -- Field_t_Slot_inst16b_get, -- 0, -- 0, -- 0, -- 0, -- Field_s_Slot_inst16b_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_Slot_inst16b_get, -- 0, -- 0, -- Field_r_Slot_inst16b_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_sr_Slot_inst16b_get, -- Field_st_Slot_inst16b_get, -- 0, -- Field_imm4_Slot_inst16b_get, -- 0, -- Field_i_Slot_inst16b_get, -- Field_imm6lo_Slot_inst16b_get, -- Field_imm6hi_Slot_inst16b_get, -- Field_imm7lo_Slot_inst16b_get, -- Field_imm7hi_Slot_inst16b_get, -- Field_z_Slot_inst16b_get, -- Field_imm6_Slot_inst16b_get, -- Field_imm7_Slot_inst16b_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_t2_Slot_inst16b_get, -- Field_s2_Slot_inst16b_get, -- Field_r2_Slot_inst16b_get, -- Field_t4_Slot_inst16b_get, -- Field_s4_Slot_inst16b_get, -- Field_r4_Slot_inst16b_get, -- Field_t8_Slot_inst16b_get, -- Field_s8_Slot_inst16b_get, -- Field_r8_Slot_inst16b_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_ar0_get, -- Implicit_Field_ar4_get, -- Implicit_Field_ar8_get, -- Implicit_Field_ar12_get, -- Implicit_Field_mr0_get, -- Implicit_Field_mr1_get, -- Implicit_Field_mr2_get, -- Implicit_Field_mr3_get, -- Implicit_Field_bt16_get, -- Implicit_Field_bs16_get, -- Implicit_Field_br16_get, -- Implicit_Field_brall_get --}; -- --static xtensa_set_field_fn --Slot_inst16b_set_field_fns[] = { -- Field_t_Slot_inst16b_set, -- 0, -- 0, -- 0, -- 0, -- Field_s_Slot_inst16b_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_Slot_inst16b_set, -- 0, -- 0, -- Field_r_Slot_inst16b_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_sr_Slot_inst16b_set, -- Field_st_Slot_inst16b_set, -- 0, -- Field_imm4_Slot_inst16b_set, -- 0, -- Field_i_Slot_inst16b_set, -- Field_imm6lo_Slot_inst16b_set, -- Field_imm6hi_Slot_inst16b_set, -- Field_imm7lo_Slot_inst16b_set, -- Field_imm7hi_Slot_inst16b_set, -- Field_z_Slot_inst16b_set, -- Field_imm6_Slot_inst16b_set, -- Field_imm7_Slot_inst16b_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_t2_Slot_inst16b_set, -- Field_s2_Slot_inst16b_set, -- Field_r2_Slot_inst16b_set, -- Field_t4_Slot_inst16b_set, -- Field_s4_Slot_inst16b_set, -- Field_r4_Slot_inst16b_set, -- Field_t8_Slot_inst16b_set, -- Field_s8_Slot_inst16b_set, -- Field_r8_Slot_inst16b_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set --}; -- --static xtensa_get_field_fn --Slot_xt_flix64_slot0_get_field_fns[] = { -- Field_t_Slot_xt_flix64_slot0_get, -- 0, -- 0, -- 0, -- Field_imm8_Slot_xt_flix64_slot0_get, -- Field_s_Slot_xt_flix64_slot0_get, -- Field_imm12b_Slot_xt_flix64_slot0_get, -- Field_imm16_Slot_xt_flix64_slot0_get, -- Field_m_Slot_xt_flix64_slot0_get, -- Field_n_Slot_xt_flix64_slot0_get, -- 0, -- 0, -- Field_op1_Slot_xt_flix64_slot0_get, -- Field_op2_Slot_xt_flix64_slot0_get, -- Field_r_Slot_xt_flix64_slot0_get, -- 0, -- Field_sae4_Slot_xt_flix64_slot0_get, -- Field_sae_Slot_xt_flix64_slot0_get, -- Field_sal_Slot_xt_flix64_slot0_get, -- Field_sargt_Slot_xt_flix64_slot0_get, -- 0, -- Field_sas_Slot_xt_flix64_slot0_get, -- 0, -- 0, -- Field_thi3_Slot_xt_flix64_slot0_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get, -- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get, -- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get, -- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get, -- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get, -- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get, -- Implicit_Field_ar0_get, -- Implicit_Field_ar4_get, -- Implicit_Field_ar8_get, -- Implicit_Field_ar12_get, -- Implicit_Field_mr0_get, -- Implicit_Field_mr1_get, -- Implicit_Field_mr2_get, -- Implicit_Field_mr3_get, -- Implicit_Field_bt16_get, -- Implicit_Field_bs16_get, -- Implicit_Field_br16_get, -- Implicit_Field_brall_get -+static xtensa_opcode_internal opcodes[] = { -+ { "excw", ICLASS_xt_iclass_excw, -+ 0, -+ Opcode_excw_encode_fns, 0, 0 }, -+ { "rfe", ICLASS_xt_iclass_rfe, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_rfe_encode_fns, 0, 0 }, -+ { "rfde", ICLASS_xt_iclass_rfde, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_rfde_encode_fns, 0, 0 }, -+ { "syscall", ICLASS_xt_iclass_syscall, -+ 0, -+ Opcode_syscall_encode_fns, 0, 0 }, -+ { "simcall", ICLASS_xt_iclass_simcall, -+ 0, -+ Opcode_simcall_encode_fns, 0, 0 }, -+ { "add.n", ICLASS_xt_iclass_add_n, -+ 0, -+ Opcode_add_n_encode_fns, 0, 0 }, -+ { "addi.n", ICLASS_xt_iclass_addi_n, -+ 0, -+ Opcode_addi_n_encode_fns, 0, 0 }, -+ { "beqz.n", ICLASS_xt_iclass_bz6, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_beqz_n_encode_fns, 0, 0 }, -+ { "bnez.n", ICLASS_xt_iclass_bz6, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bnez_n_encode_fns, 0, 0 }, -+ { "ill.n", ICLASS_xt_iclass_ill_n, -+ 0, -+ Opcode_ill_n_encode_fns, 0, 0 }, -+ { "l32i.n", ICLASS_xt_iclass_loadi4, -+ 0, -+ Opcode_l32i_n_encode_fns, 0, 0 }, -+ { "mov.n", ICLASS_xt_iclass_mov_n, -+ 0, -+ Opcode_mov_n_encode_fns, 0, 0 }, -+ { "movi.n", ICLASS_xt_iclass_movi_n, -+ 0, -+ Opcode_movi_n_encode_fns, 0, 0 }, -+ { "nop.n", ICLASS_xt_iclass_nopn, -+ 0, -+ Opcode_nop_n_encode_fns, 0, 0 }, -+ { "ret.n", ICLASS_xt_iclass_retn, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_ret_n_encode_fns, 0, 0 }, -+ { "s32i.n", ICLASS_xt_iclass_storei4, -+ 0, -+ Opcode_s32i_n_encode_fns, 0, 0 }, -+ { "addi", ICLASS_xt_iclass_addi, -+ 0, -+ Opcode_addi_encode_fns, 0, 0 }, -+ { "addmi", ICLASS_xt_iclass_addmi, -+ 0, -+ Opcode_addmi_encode_fns, 0, 0 }, -+ { "add", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_add_encode_fns, 0, 0 }, -+ { "sub", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_sub_encode_fns, 0, 0 }, -+ { "addx2", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_addx2_encode_fns, 0, 0 }, -+ { "addx4", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_addx4_encode_fns, 0, 0 }, -+ { "addx8", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_addx8_encode_fns, 0, 0 }, -+ { "subx2", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_subx2_encode_fns, 0, 0 }, -+ { "subx4", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_subx4_encode_fns, 0, 0 }, -+ { "subx8", ICLASS_xt_iclass_addsub, -+ 0, -+ Opcode_subx8_encode_fns, 0, 0 }, -+ { "and", ICLASS_xt_iclass_bit, -+ 0, -+ Opcode_and_encode_fns, 0, 0 }, -+ { "or", ICLASS_xt_iclass_bit, -+ 0, -+ Opcode_or_encode_fns, 0, 0 }, -+ { "xor", ICLASS_xt_iclass_bit, -+ 0, -+ Opcode_xor_encode_fns, 0, 0 }, -+ { "beqi", ICLASS_xt_iclass_bsi8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_beqi_encode_fns, 0, 0 }, -+ { "bnei", ICLASS_xt_iclass_bsi8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bnei_encode_fns, 0, 0 }, -+ { "bgei", ICLASS_xt_iclass_bsi8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bgei_encode_fns, 0, 0 }, -+ { "blti", ICLASS_xt_iclass_bsi8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_blti_encode_fns, 0, 0 }, -+ { "bbci", ICLASS_xt_iclass_bsi8b, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bbci_encode_fns, 0, 0 }, -+ { "bbsi", ICLASS_xt_iclass_bsi8b, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bbsi_encode_fns, 0, 0 }, -+ { "bgeui", ICLASS_xt_iclass_bsi8u, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bgeui_encode_fns, 0, 0 }, -+ { "bltui", ICLASS_xt_iclass_bsi8u, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bltui_encode_fns, 0, 0 }, -+ { "beq", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_beq_encode_fns, 0, 0 }, -+ { "bne", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bne_encode_fns, 0, 0 }, -+ { "bge", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bge_encode_fns, 0, 0 }, -+ { "blt", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_blt_encode_fns, 0, 0 }, -+ { "bgeu", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bgeu_encode_fns, 0, 0 }, -+ { "bltu", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bltu_encode_fns, 0, 0 }, -+ { "bany", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bany_encode_fns, 0, 0 }, -+ { "bnone", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bnone_encode_fns, 0, 0 }, -+ { "ball", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_ball_encode_fns, 0, 0 }, -+ { "bnall", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bnall_encode_fns, 0, 0 }, -+ { "bbc", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bbc_encode_fns, 0, 0 }, -+ { "bbs", ICLASS_xt_iclass_bst8, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bbs_encode_fns, 0, 0 }, -+ { "beqz", ICLASS_xt_iclass_bsz12, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_beqz_encode_fns, 0, 0 }, -+ { "bnez", ICLASS_xt_iclass_bsz12, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bnez_encode_fns, 0, 0 }, -+ { "bgez", ICLASS_xt_iclass_bsz12, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bgez_encode_fns, 0, 0 }, -+ { "bltz", ICLASS_xt_iclass_bsz12, -+ XTENSA_OPCODE_IS_BRANCH, -+ Opcode_bltz_encode_fns, 0, 0 }, -+ { "call0", ICLASS_xt_iclass_call0, -+ XTENSA_OPCODE_IS_CALL, -+ Opcode_call0_encode_fns, 0, 0 }, -+ { "callx0", ICLASS_xt_iclass_callx0, -+ XTENSA_OPCODE_IS_CALL, -+ Opcode_callx0_encode_fns, 0, 0 }, -+ { "extui", ICLASS_xt_iclass_exti, -+ 0, -+ Opcode_extui_encode_fns, 0, 0 }, -+ { "ill", ICLASS_xt_iclass_ill, -+ 0, -+ Opcode_ill_encode_fns, 0, 0 }, -+ { "j", ICLASS_xt_iclass_jump, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_j_encode_fns, 0, 0 }, -+ { "jx", ICLASS_xt_iclass_jumpx, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_jx_encode_fns, 0, 0 }, -+ { "l16ui", ICLASS_xt_iclass_l16ui, -+ 0, -+ Opcode_l16ui_encode_fns, 0, 0 }, -+ { "l16si", ICLASS_xt_iclass_l16si, -+ 0, -+ Opcode_l16si_encode_fns, 0, 0 }, -+ { "l32i", ICLASS_xt_iclass_l32i, -+ 0, -+ Opcode_l32i_encode_fns, 0, 0 }, -+ { "l32r", ICLASS_xt_iclass_l32r, -+ 0, -+ Opcode_l32r_encode_fns, 0, 0 }, -+ { "l8ui", ICLASS_xt_iclass_l8i, -+ 0, -+ Opcode_l8ui_encode_fns, 0, 0 }, -+ { "movi", ICLASS_xt_iclass_movi, -+ 0, -+ Opcode_movi_encode_fns, 0, 0 }, -+ { "moveqz", ICLASS_xt_iclass_movz, -+ 0, -+ Opcode_moveqz_encode_fns, 0, 0 }, -+ { "movnez", ICLASS_xt_iclass_movz, -+ 0, -+ Opcode_movnez_encode_fns, 0, 0 }, -+ { "movltz", ICLASS_xt_iclass_movz, -+ 0, -+ Opcode_movltz_encode_fns, 0, 0 }, -+ { "movgez", ICLASS_xt_iclass_movz, -+ 0, -+ Opcode_movgez_encode_fns, 0, 0 }, -+ { "neg", ICLASS_xt_iclass_neg, -+ 0, -+ Opcode_neg_encode_fns, 0, 0 }, -+ { "abs", ICLASS_xt_iclass_neg, -+ 0, -+ Opcode_abs_encode_fns, 0, 0 }, -+ { "nop", ICLASS_xt_iclass_nop, -+ 0, -+ Opcode_nop_encode_fns, 0, 0 }, -+ { "ret", ICLASS_xt_iclass_return, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_ret_encode_fns, 0, 0 }, -+ { "s16i", ICLASS_xt_iclass_s16i, -+ 0, -+ Opcode_s16i_encode_fns, 0, 0 }, -+ { "s32i", ICLASS_xt_iclass_s32i, -+ 0, -+ Opcode_s32i_encode_fns, 0, 0 }, -+ { "s8i", ICLASS_xt_iclass_s8i, -+ 0, -+ Opcode_s8i_encode_fns, 0, 0 }, -+ { "ssr", ICLASS_xt_iclass_sar, -+ 0, -+ Opcode_ssr_encode_fns, 0, 0 }, -+ { "ssl", ICLASS_xt_iclass_sar, -+ 0, -+ Opcode_ssl_encode_fns, 0, 0 }, -+ { "ssa8l", ICLASS_xt_iclass_sar, -+ 0, -+ Opcode_ssa8l_encode_fns, 0, 0 }, -+ { "ssa8b", ICLASS_xt_iclass_sar, -+ 0, -+ Opcode_ssa8b_encode_fns, 0, 0 }, -+ { "ssai", ICLASS_xt_iclass_sari, -+ 0, -+ Opcode_ssai_encode_fns, 0, 0 }, -+ { "sll", ICLASS_xt_iclass_shifts, -+ 0, -+ Opcode_sll_encode_fns, 0, 0 }, -+ { "src", ICLASS_xt_iclass_shiftst, -+ 0, -+ Opcode_src_encode_fns, 0, 0 }, -+ { "srl", ICLASS_xt_iclass_shiftt, -+ 0, -+ Opcode_srl_encode_fns, 0, 0 }, -+ { "sra", ICLASS_xt_iclass_shiftt, -+ 0, -+ Opcode_sra_encode_fns, 0, 0 }, -+ { "slli", ICLASS_xt_iclass_slli, -+ 0, -+ Opcode_slli_encode_fns, 0, 0 }, -+ { "srai", ICLASS_xt_iclass_srai, -+ 0, -+ Opcode_srai_encode_fns, 0, 0 }, -+ { "srli", ICLASS_xt_iclass_srli, -+ 0, -+ Opcode_srli_encode_fns, 0, 0 }, -+ { "memw", ICLASS_xt_iclass_memw, -+ 0, -+ Opcode_memw_encode_fns, 0, 0 }, -+ { "extw", ICLASS_xt_iclass_extw, -+ 0, -+ Opcode_extw_encode_fns, 0, 0 }, -+ { "isync", ICLASS_xt_iclass_isync, -+ 0, -+ Opcode_isync_encode_fns, 0, 0 }, -+ { "rsync", ICLASS_xt_iclass_sync, -+ 0, -+ Opcode_rsync_encode_fns, 0, 0 }, -+ { "esync", ICLASS_xt_iclass_sync, -+ 0, -+ Opcode_esync_encode_fns, 0, 0 }, -+ { "dsync", ICLASS_xt_iclass_sync, -+ 0, -+ Opcode_dsync_encode_fns, 0, 0 }, -+ { "rsil", ICLASS_xt_iclass_rsil, -+ 0, -+ Opcode_rsil_encode_fns, 0, 0 }, -+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar, -+ 0, -+ Opcode_rsr_sar_encode_fns, 0, 0 }, -+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar, -+ 0, -+ Opcode_wsr_sar_encode_fns, 0, 0 }, -+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar, -+ 0, -+ Opcode_xsr_sar_encode_fns, 0, 0 }, -+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, -+ 0, -+ Opcode_rsr_litbase_encode_fns, 0, 0 }, -+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, -+ 0, -+ Opcode_wsr_litbase_encode_fns, 0, 0 }, -+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, -+ 0, -+ Opcode_xsr_litbase_encode_fns, 0, 0 }, -+ { "rsr.176", ICLASS_xt_iclass_rsr_176, -+ 0, -+ Opcode_rsr_176_encode_fns, 0, 0 }, -+ { "wsr.176", ICLASS_xt_iclass_wsr_176, -+ 0, -+ Opcode_wsr_176_encode_fns, 0, 0 }, -+ { "rsr.208", ICLASS_xt_iclass_rsr_208, -+ 0, -+ Opcode_rsr_208_encode_fns, 0, 0 }, -+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps, -+ 0, -+ Opcode_rsr_ps_encode_fns, 0, 0 }, -+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps, -+ 0, -+ Opcode_wsr_ps_encode_fns, 0, 0 }, -+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps, -+ 0, -+ Opcode_xsr_ps_encode_fns, 0, 0 }, -+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, -+ 0, -+ Opcode_rsr_epc1_encode_fns, 0, 0 }, -+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, -+ 0, -+ Opcode_wsr_epc1_encode_fns, 0, 0 }, -+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, -+ 0, -+ Opcode_xsr_epc1_encode_fns, 0, 0 }, -+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, -+ 0, -+ Opcode_rsr_excsave1_encode_fns, 0, 0 }, -+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, -+ 0, -+ Opcode_wsr_excsave1_encode_fns, 0, 0 }, -+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, -+ 0, -+ Opcode_xsr_excsave1_encode_fns, 0, 0 }, -+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, -+ 0, -+ Opcode_rsr_epc2_encode_fns, 0, 0 }, -+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, -+ 0, -+ Opcode_wsr_epc2_encode_fns, 0, 0 }, -+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, -+ 0, -+ Opcode_xsr_epc2_encode_fns, 0, 0 }, -+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, -+ 0, -+ Opcode_rsr_excsave2_encode_fns, 0, 0 }, -+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, -+ 0, -+ Opcode_wsr_excsave2_encode_fns, 0, 0 }, -+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, -+ 0, -+ Opcode_xsr_excsave2_encode_fns, 0, 0 }, -+ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, -+ 0, -+ Opcode_rsr_epc3_encode_fns, 0, 0 }, -+ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, -+ 0, -+ Opcode_wsr_epc3_encode_fns, 0, 0 }, -+ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, -+ 0, -+ Opcode_xsr_epc3_encode_fns, 0, 0 }, -+ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, -+ 0, -+ Opcode_rsr_excsave3_encode_fns, 0, 0 }, -+ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, -+ 0, -+ Opcode_wsr_excsave3_encode_fns, 0, 0 }, -+ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, -+ 0, -+ Opcode_xsr_excsave3_encode_fns, 0, 0 }, -+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, -+ 0, -+ Opcode_rsr_eps2_encode_fns, 0, 0 }, -+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, -+ 0, -+ Opcode_wsr_eps2_encode_fns, 0, 0 }, -+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, -+ 0, -+ Opcode_xsr_eps2_encode_fns, 0, 0 }, -+ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, -+ 0, -+ Opcode_rsr_eps3_encode_fns, 0, 0 }, -+ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, -+ 0, -+ Opcode_wsr_eps3_encode_fns, 0, 0 }, -+ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, -+ 0, -+ Opcode_xsr_eps3_encode_fns, 0, 0 }, -+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, -+ 0, -+ Opcode_rsr_excvaddr_encode_fns, 0, 0 }, -+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, -+ 0, -+ Opcode_wsr_excvaddr_encode_fns, 0, 0 }, -+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, -+ 0, -+ Opcode_xsr_excvaddr_encode_fns, 0, 0 }, -+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc, -+ 0, -+ Opcode_rsr_depc_encode_fns, 0, 0 }, -+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc, -+ 0, -+ Opcode_wsr_depc_encode_fns, 0, 0 }, -+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc, -+ 0, -+ Opcode_xsr_depc_encode_fns, 0, 0 }, -+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, -+ 0, -+ Opcode_rsr_exccause_encode_fns, 0, 0 }, -+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, -+ 0, -+ Opcode_wsr_exccause_encode_fns, 0, 0 }, -+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, -+ 0, -+ Opcode_xsr_exccause_encode_fns, 0, 0 }, -+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid, -+ 0, -+ Opcode_rsr_prid_encode_fns, 0, 0 }, -+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, -+ 0, -+ Opcode_rsr_vecbase_encode_fns, 0, 0 }, -+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, -+ 0, -+ Opcode_wsr_vecbase_encode_fns, 0, 0 }, -+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, -+ 0, -+ Opcode_xsr_vecbase_encode_fns, 0, 0 }, -+ { "mul16u", ICLASS_xt_mul16, -+ 0, -+ Opcode_mul16u_encode_fns, 0, 0 }, -+ { "mul16s", ICLASS_xt_mul16, -+ 0, -+ Opcode_mul16s_encode_fns, 0, 0 }, -+ { "mull", ICLASS_xt_mul32, -+ 0, -+ Opcode_mull_encode_fns, 0, 0 }, -+ { "rfi", ICLASS_xt_iclass_rfi, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_rfi_encode_fns, 0, 0 }, -+ { "waiti", ICLASS_xt_iclass_wait, -+ 0, -+ Opcode_waiti_encode_fns, 0, 0 }, -+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, -+ 0, -+ Opcode_rsr_interrupt_encode_fns, 0, 0 }, -+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset, -+ 0, -+ Opcode_wsr_intset_encode_fns, 0, 0 }, -+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, -+ 0, -+ Opcode_wsr_intclear_encode_fns, 0, 0 }, -+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, -+ 0, -+ Opcode_rsr_intenable_encode_fns, 0, 0 }, -+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, -+ 0, -+ Opcode_wsr_intenable_encode_fns, 0, 0 }, -+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, -+ 0, -+ Opcode_xsr_intenable_encode_fns, 0, 0 }, -+ { "break", ICLASS_xt_iclass_break, -+ 0, -+ Opcode_break_encode_fns, 0, 0 }, -+ { "break.n", ICLASS_xt_iclass_break_n, -+ 0, -+ Opcode_break_n_encode_fns, 0, 0 }, -+ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, -+ 0, -+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, -+ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, -+ 0, -+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, -+ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, -+ 0, -+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, -+ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, -+ 0, -+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, -+ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, -+ 0, -+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, -+ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, -+ 0, -+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, -+ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, -+ 0, -+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, -+ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, -+ 0, -+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, -+ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, -+ 0, -+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, -+ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, -+ 0, -+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, -+ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, -+ 0, -+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, -+ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, -+ 0, -+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, -+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, -+ 0, -+ Opcode_rsr_debugcause_encode_fns, 0, 0 }, -+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, -+ 0, -+ Opcode_wsr_debugcause_encode_fns, 0, 0 }, -+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, -+ 0, -+ Opcode_xsr_debugcause_encode_fns, 0, 0 }, -+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount, -+ 0, -+ Opcode_rsr_icount_encode_fns, 0, 0 }, -+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount, -+ 0, -+ Opcode_wsr_icount_encode_fns, 0, 0 }, -+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount, -+ 0, -+ Opcode_xsr_icount_encode_fns, 0, 0 }, -+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, -+ 0, -+ Opcode_rsr_icountlevel_encode_fns, 0, 0 }, -+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, -+ 0, -+ Opcode_wsr_icountlevel_encode_fns, 0, 0 }, -+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, -+ 0, -+ Opcode_xsr_icountlevel_encode_fns, 0, 0 }, -+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, -+ 0, -+ Opcode_rsr_ddr_encode_fns, 0, 0 }, -+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, -+ 0, -+ Opcode_wsr_ddr_encode_fns, 0, 0 }, -+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, -+ 0, -+ Opcode_xsr_ddr_encode_fns, 0, 0 }, -+ { "rfdo", ICLASS_xt_iclass_rfdo, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_rfdo_encode_fns, 0, 0 }, -+ { "rfdd", ICLASS_xt_iclass_rfdd, -+ XTENSA_OPCODE_IS_JUMP, -+ Opcode_rfdd_encode_fns, 0, 0 }, -+ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, -+ 0, -+ Opcode_wsr_mmid_encode_fns, 0, 0 }, -+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, -+ 0, -+ Opcode_rsr_ccount_encode_fns, 0, 0 }, -+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, -+ 0, -+ Opcode_wsr_ccount_encode_fns, 0, 0 }, -+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, -+ 0, -+ Opcode_xsr_ccount_encode_fns, 0, 0 }, -+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, -+ 0, -+ Opcode_rsr_ccompare0_encode_fns, 0, 0 }, -+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, -+ 0, -+ Opcode_wsr_ccompare0_encode_fns, 0, 0 }, -+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, -+ 0, -+ Opcode_xsr_ccompare0_encode_fns, 0, 0 }, -+ { "idtlb", ICLASS_xt_iclass_idtlb, -+ 0, -+ Opcode_idtlb_encode_fns, 0, 0 }, -+ { "pdtlb", ICLASS_xt_iclass_rdtlb, -+ 0, -+ Opcode_pdtlb_encode_fns, 0, 0 }, -+ { "rdtlb0", ICLASS_xt_iclass_rdtlb, -+ 0, -+ Opcode_rdtlb0_encode_fns, 0, 0 }, -+ { "rdtlb1", ICLASS_xt_iclass_rdtlb, -+ 0, -+ Opcode_rdtlb1_encode_fns, 0, 0 }, -+ { "wdtlb", ICLASS_xt_iclass_wdtlb, -+ 0, -+ Opcode_wdtlb_encode_fns, 0, 0 }, -+ { "iitlb", ICLASS_xt_iclass_iitlb, -+ 0, -+ Opcode_iitlb_encode_fns, 0, 0 }, -+ { "pitlb", ICLASS_xt_iclass_ritlb, -+ 0, -+ Opcode_pitlb_encode_fns, 0, 0 }, -+ { "ritlb0", ICLASS_xt_iclass_ritlb, -+ 0, -+ Opcode_ritlb0_encode_fns, 0, 0 }, -+ { "ritlb1", ICLASS_xt_iclass_ritlb, -+ 0, -+ Opcode_ritlb1_encode_fns, 0, 0 }, -+ { "witlb", ICLASS_xt_iclass_witlb, -+ 0, -+ Opcode_witlb_encode_fns, 0, 0 }, -+ { "nsa", ICLASS_xt_iclass_nsa, -+ 0, -+ Opcode_nsa_encode_fns, 0, 0 }, -+ { "nsau", ICLASS_xt_iclass_nsa, -+ 0, -+ Opcode_nsau_encode_fns, 0, 0 }, -+ { "rer", ICLASS_xt_iclass_rer, -+ 0, -+ Opcode_rer_encode_fns, 0, 0 }, -+ { "wer", ICLASS_xt_iclass_wer, -+ 0, -+ Opcode_wer_encode_fns, 0, 0 } - }; - --static xtensa_set_field_fn --Slot_xt_flix64_slot0_set_field_fns[] = { -- Field_t_Slot_xt_flix64_slot0_set, -- 0, -- 0, -- 0, -- Field_imm8_Slot_xt_flix64_slot0_set, -- Field_s_Slot_xt_flix64_slot0_set, -- Field_imm12b_Slot_xt_flix64_slot0_set, -- Field_imm16_Slot_xt_flix64_slot0_set, -- Field_m_Slot_xt_flix64_slot0_set, -- Field_n_Slot_xt_flix64_slot0_set, -- 0, -- 0, -- Field_op1_Slot_xt_flix64_slot0_set, -- Field_op2_Slot_xt_flix64_slot0_set, -- Field_r_Slot_xt_flix64_slot0_set, -- 0, -- Field_sae4_Slot_xt_flix64_slot0_set, -- Field_sae_Slot_xt_flix64_slot0_set, -- Field_sal_Slot_xt_flix64_slot0_set, -- Field_sargt_Slot_xt_flix64_slot0_set, -- 0, -- Field_sas_Slot_xt_flix64_slot0_set, -- 0, -- 0, -- Field_thi3_Slot_xt_flix64_slot0_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set, -- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set, -- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set, -- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set, -- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set, -- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set -+enum xtensa_opcode_id { -+ OPCODE_EXCW, -+ OPCODE_RFE, -+ OPCODE_RFDE, -+ OPCODE_SYSCALL, -+ OPCODE_SIMCALL, -+ OPCODE_ADD_N, -+ OPCODE_ADDI_N, -+ OPCODE_BEQZ_N, -+ OPCODE_BNEZ_N, -+ OPCODE_ILL_N, -+ OPCODE_L32I_N, -+ OPCODE_MOV_N, -+ OPCODE_MOVI_N, -+ OPCODE_NOP_N, -+ OPCODE_RET_N, -+ OPCODE_S32I_N, -+ OPCODE_ADDI, -+ OPCODE_ADDMI, -+ OPCODE_ADD, -+ OPCODE_SUB, -+ OPCODE_ADDX2, -+ OPCODE_ADDX4, -+ OPCODE_ADDX8, -+ OPCODE_SUBX2, -+ OPCODE_SUBX4, -+ OPCODE_SUBX8, -+ OPCODE_AND, -+ OPCODE_OR, -+ OPCODE_XOR, -+ OPCODE_BEQI, -+ OPCODE_BNEI, -+ OPCODE_BGEI, -+ OPCODE_BLTI, -+ OPCODE_BBCI, -+ OPCODE_BBSI, -+ OPCODE_BGEUI, -+ OPCODE_BLTUI, -+ OPCODE_BEQ, -+ OPCODE_BNE, -+ OPCODE_BGE, -+ OPCODE_BLT, -+ OPCODE_BGEU, -+ OPCODE_BLTU, -+ OPCODE_BANY, -+ OPCODE_BNONE, -+ OPCODE_BALL, -+ OPCODE_BNALL, -+ OPCODE_BBC, -+ OPCODE_BBS, -+ OPCODE_BEQZ, -+ OPCODE_BNEZ, -+ OPCODE_BGEZ, -+ OPCODE_BLTZ, -+ OPCODE_CALL0, -+ OPCODE_CALLX0, -+ OPCODE_EXTUI, -+ OPCODE_ILL, -+ OPCODE_J, -+ OPCODE_JX, -+ OPCODE_L16UI, -+ OPCODE_L16SI, -+ OPCODE_L32I, -+ OPCODE_L32R, -+ OPCODE_L8UI, -+ OPCODE_MOVI, -+ OPCODE_MOVEQZ, -+ OPCODE_MOVNEZ, -+ OPCODE_MOVLTZ, -+ OPCODE_MOVGEZ, -+ OPCODE_NEG, -+ OPCODE_ABS, -+ OPCODE_NOP, -+ OPCODE_RET, -+ OPCODE_S16I, -+ OPCODE_S32I, -+ OPCODE_S8I, -+ OPCODE_SSR, -+ OPCODE_SSL, -+ OPCODE_SSA8L, -+ OPCODE_SSA8B, -+ OPCODE_SSAI, -+ OPCODE_SLL, -+ OPCODE_SRC, -+ OPCODE_SRL, -+ OPCODE_SRA, -+ OPCODE_SLLI, -+ OPCODE_SRAI, -+ OPCODE_SRLI, -+ OPCODE_MEMW, -+ OPCODE_EXTW, -+ OPCODE_ISYNC, -+ OPCODE_RSYNC, -+ OPCODE_ESYNC, -+ OPCODE_DSYNC, -+ OPCODE_RSIL, -+ OPCODE_RSR_SAR, -+ OPCODE_WSR_SAR, -+ OPCODE_XSR_SAR, -+ OPCODE_RSR_LITBASE, -+ OPCODE_WSR_LITBASE, -+ OPCODE_XSR_LITBASE, -+ OPCODE_RSR_176, -+ OPCODE_WSR_176, -+ OPCODE_RSR_208, -+ OPCODE_RSR_PS, -+ OPCODE_WSR_PS, -+ OPCODE_XSR_PS, -+ OPCODE_RSR_EPC1, -+ OPCODE_WSR_EPC1, -+ OPCODE_XSR_EPC1, -+ OPCODE_RSR_EXCSAVE1, -+ OPCODE_WSR_EXCSAVE1, -+ OPCODE_XSR_EXCSAVE1, -+ OPCODE_RSR_EPC2, -+ OPCODE_WSR_EPC2, -+ OPCODE_XSR_EPC2, -+ OPCODE_RSR_EXCSAVE2, -+ OPCODE_WSR_EXCSAVE2, -+ OPCODE_XSR_EXCSAVE2, -+ OPCODE_RSR_EPC3, -+ OPCODE_WSR_EPC3, -+ OPCODE_XSR_EPC3, -+ OPCODE_RSR_EXCSAVE3, -+ OPCODE_WSR_EXCSAVE3, -+ OPCODE_XSR_EXCSAVE3, -+ OPCODE_RSR_EPS2, -+ OPCODE_WSR_EPS2, -+ OPCODE_XSR_EPS2, -+ OPCODE_RSR_EPS3, -+ OPCODE_WSR_EPS3, -+ OPCODE_XSR_EPS3, -+ OPCODE_RSR_EXCVADDR, -+ OPCODE_WSR_EXCVADDR, -+ OPCODE_XSR_EXCVADDR, -+ OPCODE_RSR_DEPC, -+ OPCODE_WSR_DEPC, -+ OPCODE_XSR_DEPC, -+ OPCODE_RSR_EXCCAUSE, -+ OPCODE_WSR_EXCCAUSE, -+ OPCODE_XSR_EXCCAUSE, -+ OPCODE_RSR_PRID, -+ OPCODE_RSR_VECBASE, -+ OPCODE_WSR_VECBASE, -+ OPCODE_XSR_VECBASE, -+ OPCODE_MUL16U, -+ OPCODE_MUL16S, -+ OPCODE_MULL, -+ OPCODE_RFI, -+ OPCODE_WAITI, -+ OPCODE_RSR_INTERRUPT, -+ OPCODE_WSR_INTSET, -+ OPCODE_WSR_INTCLEAR, -+ OPCODE_RSR_INTENABLE, -+ OPCODE_WSR_INTENABLE, -+ OPCODE_XSR_INTENABLE, -+ OPCODE_BREAK, -+ OPCODE_BREAK_N, -+ OPCODE_RSR_DBREAKA0, -+ OPCODE_WSR_DBREAKA0, -+ OPCODE_XSR_DBREAKA0, -+ OPCODE_RSR_DBREAKC0, -+ OPCODE_WSR_DBREAKC0, -+ OPCODE_XSR_DBREAKC0, -+ OPCODE_RSR_IBREAKA0, -+ OPCODE_WSR_IBREAKA0, -+ OPCODE_XSR_IBREAKA0, -+ OPCODE_RSR_IBREAKENABLE, -+ OPCODE_WSR_IBREAKENABLE, -+ OPCODE_XSR_IBREAKENABLE, -+ OPCODE_RSR_DEBUGCAUSE, -+ OPCODE_WSR_DEBUGCAUSE, -+ OPCODE_XSR_DEBUGCAUSE, -+ OPCODE_RSR_ICOUNT, -+ OPCODE_WSR_ICOUNT, -+ OPCODE_XSR_ICOUNT, -+ OPCODE_RSR_ICOUNTLEVEL, -+ OPCODE_WSR_ICOUNTLEVEL, -+ OPCODE_XSR_ICOUNTLEVEL, -+ OPCODE_RSR_DDR, -+ OPCODE_WSR_DDR, -+ OPCODE_XSR_DDR, -+ OPCODE_RFDO, -+ OPCODE_RFDD, -+ OPCODE_WSR_MMID, -+ OPCODE_RSR_CCOUNT, -+ OPCODE_WSR_CCOUNT, -+ OPCODE_XSR_CCOUNT, -+ OPCODE_RSR_CCOMPARE0, -+ OPCODE_WSR_CCOMPARE0, -+ OPCODE_XSR_CCOMPARE0, -+ OPCODE_IDTLB, -+ OPCODE_PDTLB, -+ OPCODE_RDTLB0, -+ OPCODE_RDTLB1, -+ OPCODE_WDTLB, -+ OPCODE_IITLB, -+ OPCODE_PITLB, -+ OPCODE_RITLB0, -+ OPCODE_RITLB1, -+ OPCODE_WITLB, -+ OPCODE_NSA, -+ OPCODE_NSAU, -+ OPCODE_RER, -+ OPCODE_WER - }; - --static xtensa_get_field_fn --Slot_xt_flix64_slot1_get_field_fns[] = { -- Field_t_Slot_xt_flix64_slot1_get, -- 0, -- 0, -- 0, -- Field_imm8_Slot_xt_flix64_slot1_get, -- Field_s_Slot_xt_flix64_slot1_get, -- Field_imm12b_Slot_xt_flix64_slot1_get, -- 0, -- 0, -- 0, -- Field_offset_Slot_xt_flix64_slot1_get, -- 0, -- 0, -- Field_op2_Slot_xt_flix64_slot1_get, -- Field_r_Slot_xt_flix64_slot1_get, -- 0, -- 0, -- Field_sae_Slot_xt_flix64_slot1_get, -- Field_sal_Slot_xt_flix64_slot1_get, -- Field_sargt_Slot_xt_flix64_slot1_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_s4_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_ar0_get, -- Implicit_Field_ar4_get, -- Implicit_Field_ar8_get, -- Implicit_Field_ar12_get, -- Implicit_Field_mr0_get, -- Implicit_Field_mr1_get, -- Implicit_Field_mr2_get, -- Implicit_Field_mr3_get, -- Implicit_Field_bt16_get, -- Implicit_Field_bs16_get, -- Implicit_Field_br16_get, -- Implicit_Field_brall_get --}; -+ -+/* Slot-specific opcode decode functions. */ -+ -+static int -+Slot_inst_decode (const xtensa_insnbuf insn) -+{ -+ switch (Field_op0_Slot_inst_get (insn)) -+ { -+ case 0: -+ switch (Field_op1_Slot_inst_get (insn)) -+ { -+ case 0: -+ switch (Field_op2_Slot_inst_get (insn)) -+ { -+ case 0: -+ switch (Field_r_Slot_inst_get (insn)) -+ { -+ case 0: -+ switch (Field_m_Slot_inst_get (insn)) -+ { -+ case 0: -+ if (Field_s_Slot_inst_get (insn) == 0 && -+ Field_n_Slot_inst_get (insn) == 0) -+ return OPCODE_ILL; -+ break; -+ case 2: -+ switch (Field_n_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_RET; -+ case 2: -+ return OPCODE_JX; -+ } -+ break; -+ case 3: -+ if (Field_n_Slot_inst_get (insn) == 0) -+ return OPCODE_CALLX0; -+ break; -+ } -+ break; -+ case 2: -+ if (Field_s_Slot_inst_get (insn) == 0) -+ { -+ switch (Field_t_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_ISYNC; -+ case 1: -+ return OPCODE_RSYNC; -+ case 2: -+ return OPCODE_ESYNC; -+ case 3: -+ return OPCODE_DSYNC; -+ case 8: -+ return OPCODE_EXCW; -+ case 12: -+ return OPCODE_MEMW; -+ case 13: -+ return OPCODE_EXTW; -+ case 15: -+ return OPCODE_NOP; -+ } -+ } -+ break; -+ case 3: -+ switch (Field_t_Slot_inst_get (insn)) -+ { -+ case 0: -+ switch (Field_s_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_RFE; -+ case 2: -+ return OPCODE_RFDE; -+ } -+ break; -+ case 1: -+ return OPCODE_RFI; -+ } -+ break; -+ case 4: -+ return OPCODE_BREAK; -+ case 5: -+ switch (Field_s_Slot_inst_get (insn)) -+ { -+ case 0: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_SYSCALL; -+ break; -+ case 1: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_SIMCALL; -+ break; -+ } -+ break; -+ case 6: -+ return OPCODE_RSIL; -+ case 7: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_WAITI; -+ break; -+ } -+ break; -+ case 1: -+ return OPCODE_AND; -+ case 2: -+ return OPCODE_OR; -+ case 3: -+ return OPCODE_XOR; -+ case 4: -+ switch (Field_r_Slot_inst_get (insn)) -+ { -+ case 0: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_SSR; -+ break; -+ case 1: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_SSL; -+ break; -+ case 2: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_SSA8L; -+ break; -+ case 3: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_SSA8B; -+ break; -+ case 4: -+ if (Field_thi3_Slot_inst_get (insn) == 0) -+ return OPCODE_SSAI; -+ break; -+ case 6: -+ return OPCODE_RER; -+ case 7: -+ return OPCODE_WER; -+ case 14: -+ return OPCODE_NSA; -+ case 15: -+ return OPCODE_NSAU; -+ } -+ break; -+ case 5: -+ switch (Field_r_Slot_inst_get (insn)) -+ { -+ case 3: -+ return OPCODE_RITLB0; -+ case 4: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_IITLB; -+ break; -+ case 5: -+ return OPCODE_PITLB; -+ case 6: -+ return OPCODE_WITLB; -+ case 7: -+ return OPCODE_RITLB1; -+ case 11: -+ return OPCODE_RDTLB0; -+ case 12: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_IDTLB; -+ break; -+ case 13: -+ return OPCODE_PDTLB; -+ case 14: -+ return OPCODE_WDTLB; -+ case 15: -+ return OPCODE_RDTLB1; -+ } -+ break; -+ case 6: -+ switch (Field_s_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_NEG; -+ case 1: -+ return OPCODE_ABS; -+ } -+ break; -+ case 8: -+ return OPCODE_ADD; -+ case 9: -+ return OPCODE_ADDX2; -+ case 10: -+ return OPCODE_ADDX4; -+ case 11: -+ return OPCODE_ADDX8; -+ case 12: -+ return OPCODE_SUB; -+ case 13: -+ return OPCODE_SUBX2; -+ case 14: -+ return OPCODE_SUBX4; -+ case 15: -+ return OPCODE_SUBX8; -+ } -+ break; -+ case 1: -+ switch (Field_op2_Slot_inst_get (insn)) -+ { -+ case 0: -+ case 1: -+ return OPCODE_SLLI; -+ case 2: -+ case 3: -+ return OPCODE_SRAI; -+ case 4: -+ return OPCODE_SRLI; -+ case 6: -+ switch (Field_sr_Slot_inst_get (insn)) -+ { -+ case 3: -+ return OPCODE_XSR_SAR; -+ case 5: -+ return OPCODE_XSR_LITBASE; -+ case 96: -+ return OPCODE_XSR_IBREAKENABLE; -+ case 104: -+ return OPCODE_XSR_DDR; -+ case 128: -+ return OPCODE_XSR_IBREAKA0; -+ case 144: -+ return OPCODE_XSR_DBREAKA0; -+ case 160: -+ return OPCODE_XSR_DBREAKC0; -+ case 177: -+ return OPCODE_XSR_EPC1; -+ case 178: -+ return OPCODE_XSR_EPC2; -+ case 179: -+ return OPCODE_XSR_EPC3; -+ case 192: -+ return OPCODE_XSR_DEPC; -+ case 194: -+ return OPCODE_XSR_EPS2; -+ case 195: -+ return OPCODE_XSR_EPS3; -+ case 209: -+ return OPCODE_XSR_EXCSAVE1; -+ case 210: -+ return OPCODE_XSR_EXCSAVE2; -+ case 211: -+ return OPCODE_XSR_EXCSAVE3; -+ case 228: -+ return OPCODE_XSR_INTENABLE; -+ case 230: -+ return OPCODE_XSR_PS; -+ case 231: -+ return OPCODE_XSR_VECBASE; -+ case 232: -+ return OPCODE_XSR_EXCCAUSE; -+ case 233: -+ return OPCODE_XSR_DEBUGCAUSE; -+ case 234: -+ return OPCODE_XSR_CCOUNT; -+ case 236: -+ return OPCODE_XSR_ICOUNT; -+ case 237: -+ return OPCODE_XSR_ICOUNTLEVEL; -+ case 238: -+ return OPCODE_XSR_EXCVADDR; -+ case 240: -+ return OPCODE_XSR_CCOMPARE0; -+ } -+ break; -+ case 8: -+ return OPCODE_SRC; -+ case 9: -+ if (Field_s_Slot_inst_get (insn) == 0) -+ return OPCODE_SRL; -+ break; -+ case 10: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_SLL; -+ break; -+ case 11: -+ if (Field_s_Slot_inst_get (insn) == 0) -+ return OPCODE_SRA; -+ break; -+ case 12: -+ return OPCODE_MUL16U; -+ case 13: -+ return OPCODE_MUL16S; -+ case 15: -+ switch (Field_r_Slot_inst_get (insn)) -+ { -+ case 14: -+ if (Field_t_Slot_inst_get (insn) == 0) -+ return OPCODE_RFDO; -+ if (Field_t_Slot_inst_get (insn) == 1) -+ return OPCODE_RFDD; -+ break; -+ } -+ break; -+ } -+ break; -+ case 2: -+ if (Field_op2_Slot_inst_get (insn) == 8) -+ return OPCODE_MULL; -+ break; -+ case 3: -+ switch (Field_op2_Slot_inst_get (insn)) -+ { -+ case 0: -+ switch (Field_sr_Slot_inst_get (insn)) -+ { -+ case 3: -+ return OPCODE_RSR_SAR; -+ case 5: -+ return OPCODE_RSR_LITBASE; -+ case 96: -+ return OPCODE_RSR_IBREAKENABLE; -+ case 104: -+ return OPCODE_RSR_DDR; -+ case 128: -+ return OPCODE_RSR_IBREAKA0; -+ case 144: -+ return OPCODE_RSR_DBREAKA0; -+ case 160: -+ return OPCODE_RSR_DBREAKC0; -+ case 176: -+ return OPCODE_RSR_176; -+ case 177: -+ return OPCODE_RSR_EPC1; -+ case 178: -+ return OPCODE_RSR_EPC2; -+ case 179: -+ return OPCODE_RSR_EPC3; -+ case 192: -+ return OPCODE_RSR_DEPC; -+ case 194: -+ return OPCODE_RSR_EPS2; -+ case 195: -+ return OPCODE_RSR_EPS3; -+ case 208: -+ return OPCODE_RSR_208; -+ case 209: -+ return OPCODE_RSR_EXCSAVE1; -+ case 210: -+ return OPCODE_RSR_EXCSAVE2; -+ case 211: -+ return OPCODE_RSR_EXCSAVE3; -+ case 226: -+ return OPCODE_RSR_INTERRUPT; -+ case 228: -+ return OPCODE_RSR_INTENABLE; -+ case 230: -+ return OPCODE_RSR_PS; -+ case 231: -+ return OPCODE_RSR_VECBASE; -+ case 232: -+ return OPCODE_RSR_EXCCAUSE; -+ case 233: -+ return OPCODE_RSR_DEBUGCAUSE; -+ case 234: -+ return OPCODE_RSR_CCOUNT; -+ case 235: -+ return OPCODE_RSR_PRID; -+ case 236: -+ return OPCODE_RSR_ICOUNT; -+ case 237: -+ return OPCODE_RSR_ICOUNTLEVEL; -+ case 238: -+ return OPCODE_RSR_EXCVADDR; -+ case 240: -+ return OPCODE_RSR_CCOMPARE0; -+ } -+ break; -+ case 1: -+ switch (Field_sr_Slot_inst_get (insn)) -+ { -+ case 3: -+ return OPCODE_WSR_SAR; -+ case 5: -+ return OPCODE_WSR_LITBASE; -+ case 89: -+ return OPCODE_WSR_MMID; -+ case 96: -+ return OPCODE_WSR_IBREAKENABLE; -+ case 104: -+ return OPCODE_WSR_DDR; -+ case 128: -+ return OPCODE_WSR_IBREAKA0; -+ case 144: -+ return OPCODE_WSR_DBREAKA0; -+ case 160: -+ return OPCODE_WSR_DBREAKC0; -+ case 176: -+ return OPCODE_WSR_176; -+ case 177: -+ return OPCODE_WSR_EPC1; -+ case 178: -+ return OPCODE_WSR_EPC2; -+ case 179: -+ return OPCODE_WSR_EPC3; -+ case 192: -+ return OPCODE_WSR_DEPC; -+ case 194: -+ return OPCODE_WSR_EPS2; -+ case 195: -+ return OPCODE_WSR_EPS3; -+ case 209: -+ return OPCODE_WSR_EXCSAVE1; -+ case 210: -+ return OPCODE_WSR_EXCSAVE2; -+ case 211: -+ return OPCODE_WSR_EXCSAVE3; -+ case 226: -+ return OPCODE_WSR_INTSET; -+ case 227: -+ return OPCODE_WSR_INTCLEAR; -+ case 228: -+ return OPCODE_WSR_INTENABLE; -+ case 230: -+ return OPCODE_WSR_PS; -+ case 231: -+ return OPCODE_WSR_VECBASE; -+ case 232: -+ return OPCODE_WSR_EXCCAUSE; -+ case 233: -+ return OPCODE_WSR_DEBUGCAUSE; -+ case 234: -+ return OPCODE_WSR_CCOUNT; -+ case 236: -+ return OPCODE_WSR_ICOUNT; -+ case 237: -+ return OPCODE_WSR_ICOUNTLEVEL; -+ case 238: -+ return OPCODE_WSR_EXCVADDR; -+ case 240: -+ return OPCODE_WSR_CCOMPARE0; -+ } -+ break; -+ case 8: -+ return OPCODE_MOVEQZ; -+ case 9: -+ return OPCODE_MOVNEZ; -+ case 10: -+ return OPCODE_MOVLTZ; -+ case 11: -+ return OPCODE_MOVGEZ; -+ } -+ break; -+ case 4: -+ case 5: -+ return OPCODE_EXTUI; -+ } -+ break; -+ case 1: -+ return OPCODE_L32R; -+ case 2: -+ switch (Field_r_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_L8UI; -+ case 1: -+ return OPCODE_L16UI; -+ case 2: -+ return OPCODE_L32I; -+ case 4: -+ return OPCODE_S8I; -+ case 5: -+ return OPCODE_S16I; -+ case 6: -+ return OPCODE_S32I; -+ case 9: -+ return OPCODE_L16SI; -+ case 10: -+ return OPCODE_MOVI; -+ case 12: -+ return OPCODE_ADDI; -+ case 13: -+ return OPCODE_ADDMI; -+ } -+ break; -+ case 5: -+ if (Field_n_Slot_inst_get (insn) == 0) -+ return OPCODE_CALL0; -+ break; -+ case 6: -+ switch (Field_n_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_J; -+ case 1: -+ switch (Field_m_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_BEQZ; -+ case 1: -+ return OPCODE_BNEZ; -+ case 2: -+ return OPCODE_BLTZ; -+ case 3: -+ return OPCODE_BGEZ; -+ } -+ break; -+ case 2: -+ switch (Field_m_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_BEQI; -+ case 1: -+ return OPCODE_BNEI; -+ case 2: -+ return OPCODE_BLTI; -+ case 3: -+ return OPCODE_BGEI; -+ } -+ break; -+ case 3: -+ switch (Field_m_Slot_inst_get (insn)) -+ { -+ case 2: -+ return OPCODE_BLTUI; -+ case 3: -+ return OPCODE_BGEUI; -+ } -+ break; -+ } -+ break; -+ case 7: -+ switch (Field_r_Slot_inst_get (insn)) -+ { -+ case 0: -+ return OPCODE_BNONE; -+ case 1: -+ return OPCODE_BEQ; -+ case 2: -+ return OPCODE_BLT; -+ case 3: -+ return OPCODE_BLTU; -+ case 4: -+ return OPCODE_BALL; -+ case 5: -+ return OPCODE_BBC; -+ case 6: -+ case 7: -+ return OPCODE_BBCI; -+ case 8: -+ return OPCODE_BANY; -+ case 9: -+ return OPCODE_BNE; -+ case 10: -+ return OPCODE_BGE; -+ case 11: -+ return OPCODE_BGEU; -+ case 12: -+ return OPCODE_BNALL; -+ case 13: -+ return OPCODE_BBS; -+ case 14: -+ case 15: -+ return OPCODE_BBSI; -+ } -+ break; -+ } -+ return 0; -+} -+ -+static int -+Slot_inst16a_decode (const xtensa_insnbuf insn) -+{ -+ switch (Field_op0_Slot_inst16a_get (insn)) -+ { -+ case 8: -+ return OPCODE_L32I_N; -+ case 9: -+ return OPCODE_S32I_N; -+ case 10: -+ return OPCODE_ADD_N; -+ case 11: -+ return OPCODE_ADDI_N; -+ } -+ return 0; -+} - --static xtensa_set_field_fn --Slot_xt_flix64_slot1_set_field_fns[] = { -- Field_t_Slot_xt_flix64_slot1_set, -- 0, -- 0, -- 0, -- Field_imm8_Slot_xt_flix64_slot1_set, -- Field_s_Slot_xt_flix64_slot1_set, -- Field_imm12b_Slot_xt_flix64_slot1_set, -- 0, -- 0, -- 0, -- Field_offset_Slot_xt_flix64_slot1_set, -- 0, -- 0, -- Field_op2_Slot_xt_flix64_slot1_set, -- Field_r_Slot_xt_flix64_slot1_set, -- 0, -- 0, -- Field_sae_Slot_xt_flix64_slot1_set, -- Field_sal_Slot_xt_flix64_slot1_set, -- Field_sargt_Slot_xt_flix64_slot1_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_s4_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set --}; -+static int -+Slot_inst16b_decode (const xtensa_insnbuf insn) -+{ -+ switch (Field_op0_Slot_inst16b_get (insn)) -+ { -+ case 12: -+ switch (Field_i_Slot_inst16b_get (insn)) -+ { -+ case 0: -+ return OPCODE_MOVI_N; -+ case 1: -+ switch (Field_z_Slot_inst16b_get (insn)) -+ { -+ case 0: -+ return OPCODE_BEQZ_N; -+ case 1: -+ return OPCODE_BNEZ_N; -+ } -+ break; -+ } -+ break; -+ case 13: -+ switch (Field_r_Slot_inst16b_get (insn)) -+ { -+ case 0: -+ return OPCODE_MOV_N; -+ case 15: -+ switch (Field_t_Slot_inst16b_get (insn)) -+ { -+ case 0: -+ return OPCODE_RET_N; -+ case 2: -+ return OPCODE_BREAK_N; -+ case 3: -+ if (Field_s_Slot_inst16b_get (insn) == 0) -+ return OPCODE_NOP_N; -+ break; -+ case 6: -+ if (Field_s_Slot_inst16b_get (insn) == 0) -+ return OPCODE_ILL_N; -+ break; -+ } -+ break; -+ } -+ break; -+ } -+ return 0; -+} - --static xtensa_get_field_fn --Slot_xt_flix64_slot2_get_field_fns[] = { -- Field_t_Slot_xt_flix64_slot2_get, -- 0, -- 0, -- 0, -- 0, -- Field_s_Slot_xt_flix64_slot2_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_r_Slot_xt_flix64_slot2_get, -- 0, -- 0, -- 0, -- 0, -- Field_sargt_Slot_xt_flix64_slot2_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_imm7_Slot_xt_flix64_slot2_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_s5_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Implicit_Field_ar0_get, -- Implicit_Field_ar4_get, -- Implicit_Field_ar8_get, -- Implicit_Field_ar12_get, -- Implicit_Field_mr0_get, -- Implicit_Field_mr1_get, -- Implicit_Field_mr2_get, -- Implicit_Field_mr3_get, -- Implicit_Field_bt16_get, -- Implicit_Field_bs16_get, -- Implicit_Field_br16_get, -- Implicit_Field_brall_get --}; -+ -+/* Instruction slots. */ - --static xtensa_set_field_fn --Slot_xt_flix64_slot2_set_field_fns[] = { -- Field_t_Slot_xt_flix64_slot2_set, -- 0, -- 0, -- 0, -- 0, -- Field_s_Slot_xt_flix64_slot2_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_r_Slot_xt_flix64_slot2_set, -- 0, -- 0, -- 0, -- 0, -- Field_sargt_Slot_xt_flix64_slot2_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_imm7_Slot_xt_flix64_slot2_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_op0_s5_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -+static void -+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, -+ xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = (insn[0] & 0xffffff); -+} -+ -+static void -+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, -+ const xtensa_insnbuf slotbuf) -+{ -+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -+} -+ -+static void -+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, -+ xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = (insn[0] & 0xffff); -+} -+ -+static void -+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, -+ const xtensa_insnbuf slotbuf) -+{ -+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -+} -+ -+static void -+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, -+ xtensa_insnbuf slotbuf) -+{ -+ slotbuf[0] = (insn[0] & 0xffff); -+} -+ -+static void -+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, -+ const xtensa_insnbuf slotbuf) -+{ -+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -+} -+ -+static xtensa_get_field_fn -+Slot_inst_get_field_fns[] = { -+ Field_t_Slot_inst_get, -+ Field_bbi4_Slot_inst_get, -+ Field_bbi_Slot_inst_get, -+ Field_imm12_Slot_inst_get, -+ Field_imm8_Slot_inst_get, -+ Field_s_Slot_inst_get, -+ Field_imm12b_Slot_inst_get, -+ Field_imm16_Slot_inst_get, -+ Field_m_Slot_inst_get, -+ Field_n_Slot_inst_get, -+ Field_offset_Slot_inst_get, -+ Field_op0_Slot_inst_get, -+ Field_op1_Slot_inst_get, -+ Field_op2_Slot_inst_get, -+ Field_r_Slot_inst_get, -+ Field_sa4_Slot_inst_get, -+ Field_sae4_Slot_inst_get, -+ Field_sae_Slot_inst_get, -+ Field_sal_Slot_inst_get, -+ Field_sargt_Slot_inst_get, -+ Field_sas4_Slot_inst_get, -+ Field_sas_Slot_inst_get, -+ Field_sr_Slot_inst_get, -+ Field_st_Slot_inst_get, -+ Field_thi3_Slot_inst_get, -+ Field_imm4_Slot_inst_get, - 0, - 0, - 0, -@@ -20837,6 +7351,39 @@ - 0, - 0, - 0, -+ Field_xt_wbr15_imm_Slot_inst_get, -+ Field_xt_wbr18_imm_Slot_inst_get, -+ Implicit_Field_ar0_get -+}; -+ -+static xtensa_set_field_fn -+Slot_inst_set_field_fns[] = { -+ Field_t_Slot_inst_set, -+ Field_bbi4_Slot_inst_set, -+ Field_bbi_Slot_inst_set, -+ Field_imm12_Slot_inst_set, -+ Field_imm8_Slot_inst_set, -+ Field_s_Slot_inst_set, -+ Field_imm12b_Slot_inst_set, -+ Field_imm16_Slot_inst_set, -+ Field_m_Slot_inst_set, -+ Field_n_Slot_inst_set, -+ Field_offset_Slot_inst_set, -+ Field_op0_Slot_inst_set, -+ Field_op1_Slot_inst_set, -+ Field_op2_Slot_inst_set, -+ Field_r_Slot_inst_set, -+ Field_sa4_Slot_inst_set, -+ Field_sae4_Slot_inst_set, -+ Field_sae_Slot_inst_set, -+ Field_sal_Slot_inst_set, -+ Field_sargt_Slot_inst_set, -+ Field_sas4_Slot_inst_set, -+ Field_sas_Slot_inst_set, -+ Field_sr_Slot_inst_set, -+ Field_st_Slot_inst_set, -+ Field_thi3_Slot_inst_set, -+ Field_imm4_Slot_inst_set, - 0, - 0, - 0, -@@ -20845,110 +7392,28 @@ - 0, - 0, - 0, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -+ Field_xt_wbr15_imm_Slot_inst_set, -+ Field_xt_wbr18_imm_Slot_inst_set, - Implicit_Field_set - }; - - static xtensa_get_field_fn --Slot_xt_flix64_slot3_get_field_fns[] = { -- Field_t_Slot_xt_flix64_slot3_get, -- 0, -- Field_bbi_Slot_xt_flix64_slot3_get, -- 0, -- 0, -- Field_s_Slot_xt_flix64_slot3_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_r_Slot_xt_flix64_slot3_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -+Slot_inst16a_get_field_fns[] = { -+ Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, -+ Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, -+ Field_op0_Slot_inst16a_get, - 0, - 0, -+ Field_r_Slot_inst16a_get, - 0, - 0, - 0, -@@ -20956,95 +7421,40 @@ - 0, - 0, - 0, -+ Field_sr_Slot_inst16a_get, -+ Field_st_Slot_inst16a_get, - 0, -+ Field_imm4_Slot_inst16a_get, -+ Field_i_Slot_inst16a_get, -+ Field_imm6lo_Slot_inst16a_get, -+ Field_imm6hi_Slot_inst16a_get, -+ Field_imm7lo_Slot_inst16a_get, -+ Field_imm7hi_Slot_inst16a_get, -+ Field_z_Slot_inst16a_get, -+ Field_imm6_Slot_inst16a_get, -+ Field_imm7_Slot_inst16a_get, - 0, -- Field_op0_s6_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get, -- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get, - 0, -- Implicit_Field_ar0_get, -- Implicit_Field_ar4_get, -- Implicit_Field_ar8_get, -- Implicit_Field_ar12_get, -- Implicit_Field_mr0_get, -- Implicit_Field_mr1_get, -- Implicit_Field_mr2_get, -- Implicit_Field_mr3_get, -- Implicit_Field_bt16_get, -- Implicit_Field_bs16_get, -- Implicit_Field_br16_get, -- Implicit_Field_brall_get -+ Implicit_Field_ar0_get - }; - - static xtensa_set_field_fn --Slot_xt_flix64_slot3_set_field_fns[] = { -- Field_t_Slot_xt_flix64_slot3_set, -- 0, -- Field_bbi_Slot_xt_flix64_slot3_set, -- 0, -- 0, -- Field_s_Slot_xt_flix64_slot3_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- Field_r_Slot_xt_flix64_slot3_set, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -- 0, -+Slot_inst16a_set_field_fns[] = { -+ Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, -+ Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, -+ Field_op0_Slot_inst16a_set, - 0, - 0, -+ Field_r_Slot_inst16a_set, - 0, - 0, - 0, -@@ -21052,21 +7462,40 @@ - 0, - 0, - 0, -+ Field_sr_Slot_inst16a_set, -+ Field_st_Slot_inst16a_set, - 0, -+ Field_imm4_Slot_inst16a_set, -+ Field_i_Slot_inst16a_set, -+ Field_imm6lo_Slot_inst16a_set, -+ Field_imm6hi_Slot_inst16a_set, -+ Field_imm7lo_Slot_inst16a_set, -+ Field_imm7hi_Slot_inst16a_set, -+ Field_z_Slot_inst16a_set, -+ Field_imm6_Slot_inst16a_set, -+ Field_imm7_Slot_inst16a_set, - 0, -- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set, - 0, -+ Implicit_Field_set -+}; -+ -+static xtensa_get_field_fn -+Slot_inst16b_get_field_fns[] = { -+ Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, -+ Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, -+ Field_op0_Slot_inst16b_get, - 0, - 0, -+ Field_r_Slot_inst16b_get, - 0, - 0, - 0, -@@ -21074,20 +7503,40 @@ - 0, - 0, - 0, -+ Field_sr_Slot_inst16b_get, -+ Field_st_Slot_inst16b_get, - 0, -+ Field_imm4_Slot_inst16b_get, -+ Field_i_Slot_inst16b_get, -+ Field_imm6lo_Slot_inst16b_get, -+ Field_imm6hi_Slot_inst16b_get, -+ Field_imm7lo_Slot_inst16b_get, -+ Field_imm7hi_Slot_inst16b_get, -+ Field_z_Slot_inst16b_get, -+ Field_imm6_Slot_inst16b_get, -+ Field_imm7_Slot_inst16b_get, - 0, - 0, -+ Implicit_Field_ar0_get -+}; -+ -+static xtensa_set_field_fn -+Slot_inst16b_set_field_fns[] = { -+ Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, -+ Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, -+ Field_op0_Slot_inst16b_set, - 0, - 0, -+ Field_r_Slot_inst16b_set, - 0, - 0, - 0, -@@ -21095,45 +7544,20 @@ - 0, - 0, - 0, -+ Field_sr_Slot_inst16b_set, -+ Field_st_Slot_inst16b_set, - 0, -+ Field_imm4_Slot_inst16b_set, -+ Field_i_Slot_inst16b_set, -+ Field_imm6lo_Slot_inst16b_set, -+ Field_imm6hi_Slot_inst16b_set, -+ Field_imm7lo_Slot_inst16b_set, -+ Field_imm7hi_Slot_inst16b_set, -+ Field_z_Slot_inst16b_set, -+ Field_imm6_Slot_inst16b_set, -+ Field_imm7_Slot_inst16b_set, - 0, -- Field_op0_s6_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set, -- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set, - 0, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, -- Implicit_Field_set, - Implicit_Field_set - }; - -@@ -21149,27 +7573,7 @@ - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, -- Slot_inst16b_decode, "nop.n" }, -- { "xt_flix64_slot0", "xt_format1", 0, -- Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set, -- Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns, -- Slot_xt_flix64_slot0_decode, "nop" }, -- { "xt_flix64_slot0", "xt_format2", 0, -- Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set, -- Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns, -- Slot_xt_flix64_slot0_decode, "nop" }, -- { "xt_flix64_slot1", "xt_format1", 1, -- Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set, -- Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns, -- Slot_xt_flix64_slot1_decode, "nop" }, -- { "xt_flix64_slot2", "xt_format1", 2, -- Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set, -- Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns, -- Slot_xt_flix64_slot2_decode, "nop" }, -- { "xt_flix64_slot3", "xt_format2", 1, -- Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set, -- Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns, -- Slot_xt_flix64_slot3_decode, "nop" } -+ Slot_inst16b_decode, "nop.n" } - }; - - -@@ -21179,35 +7583,18 @@ - Format_x24_encode (xtensa_insnbuf insn) - { - insn[0] = 0; -- insn[1] = 0; - } - - static void - Format_x16a_encode (xtensa_insnbuf insn) - { - insn[0] = 0x8; -- insn[1] = 0; - } - - static void - Format_x16b_encode (xtensa_insnbuf insn) - { - insn[0] = 0xc; -- insn[1] = 0; --} -- --static void --Format_xt_format1_encode (xtensa_insnbuf insn) --{ -- insn[0] = 0xe; -- insn[1] = 0; --} -- --static void --Format_xt_format2_encode (xtensa_insnbuf insn) --{ -- insn[0] = 0xf; -- insn[1] = 0; - } - - static int Format_x24_slots[] = { 0 }; -@@ -21216,32 +7603,22 @@ - - static int Format_x16b_slots[] = { 2 }; - --static int Format_xt_format1_slots[] = { 3, 5, 6 }; -- --static int Format_xt_format2_slots[] = { 4, 7 }; -- - static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, -- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, -- { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots }, -- { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots } -+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } - }; - - - static int - format_decoder (const xtensa_insnbuf insn) - { -- if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) -+ if ((insn[0] & 0x8) == 0) - return 0; /* x24 */ -- if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) -+ if ((insn[0] & 0xc) == 0x8) - return 1; /* x16a */ -- if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) -+ if ((insn[0] & 0xe) == 0xc) - return 2; /* x16b */ -- if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0) -- return 3; /* xt_format1 */ -- if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0) -- return 4; /* xt_format2 */ - return -1; - } - -@@ -21260,8 +7637,8 @@ - 2, - 2, - 2, -- 8, -- 8 -+ -1, -+ -1 - }; - - static int -@@ -21276,14 +7653,14 @@ - - xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, -- 8 /* insn_size */, 0, -- 5, formats, format_decoder, length_decoder, -- 8, slots, -- 135 /* num_fields */, -- 188, operands, -- 355, iclasses, -- 530, opcodes, 0, -- 8, regfiles, -+ 3 /* insn_size */, 0, -+ 3, formats, format_decoder, length_decoder, -+ 3, slots, -+ 37 /* num_fields */, -+ 65, operands, -+ 159, iclasses, -+ 204, opcodes, 0, -+ 1, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, -diff -urN gdb-7.5.1-orig/config.guess gdb-7.5.1/config.guess ---- gdb-7.5.1-orig/config.guess 2011-06-06 03:36:06.000000000 -0700 -+++ gdb-7.5.1/config.guess 2015-08-04 11:34:36.037584800 -0700 -@@ -1,14 +1,12 @@ - #! /bin/sh - # Attempt to guess a canonical system name. --# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, --# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, --# 2011 Free Software Foundation, Inc. -+# Copyright 1992-2014 Free Software Foundation, Inc. - --timestamp='2011-06-03' -+timestamp='2014-03-23' - - # This file is free software; you can redistribute it and/or modify it - # under the terms of the GNU General Public License as published by --# the Free Software Foundation; either version 2 of the License, or -+# the Free Software Foundation; either version 3 of the License, or - # (at your option) any later version. - # - # This program is distributed in the hope that it will be useful, but -@@ -17,26 +15,22 @@ - # General Public License for more details. - # - # You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA --# 02110-1301, USA. -+# along with this program; if not, see . - # - # As a special exception to the GNU General Public License, if you - # distribute this file as part of a program that contains a - # configuration script generated by Autoconf, you may include it under --# the same distribution terms that you use for the rest of that program. -- -- --# Originally written by Per Bothner. Please send patches (context --# diff format) to and include a ChangeLog --# entry. -+# the same distribution terms that you use for the rest of that -+# program. This Exception is an additional permission under section 7 -+# of the GNU General Public License, version 3 ("GPLv3"). - # --# This script attempts to guess a canonical system name similar to --# config.sub. If it succeeds, it prints the system name on stdout, and --# exits with 0. Otherwise, it exits with 1. -+# Originally written by Per Bothner. - # - # You can get the latest version of this script from: - # http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD -+# -+# Please send patches with a ChangeLog entry to config-patches@gnu.org. -+ - - me=`echo "$0" | sed -e 's,.*/,,'` - -@@ -56,9 +50,7 @@ - GNU config.guess ($timestamp) - - Originally written by Per Bothner. --Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, --2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free --Software Foundation, Inc. -+Copyright 1992-2014 Free Software Foundation, Inc. - - This is free software; see the source for copying conditions. There is NO - warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." -@@ -140,12 +132,33 @@ - UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown - UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown - -+case "${UNAME_SYSTEM}" in -+Linux|GNU|GNU/*) -+ # If the system lacks a compiler, then just pick glibc. -+ # We could probably try harder. -+ LIBC=gnu -+ -+ eval $set_cc_for_build -+ cat <<-EOF > $dummy.c -+ #include -+ #if defined(__UCLIBC__) -+ LIBC=uclibc -+ #elif defined(__dietlibc__) -+ LIBC=dietlibc -+ #else -+ LIBC=gnu -+ #endif -+ EOF -+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'` -+ ;; -+esac -+ - # Note: order is significant - the case branches are not exclusive. - - case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in - *:NetBSD:*:*) - # NetBSD (nbsd) targets should (where applicable) match one or -- # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, -+ # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, - # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently - # switched to ELF, *-*-netbsd* would select the old - # object file format. This provides both forward -@@ -202,6 +215,10 @@ - # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. - echo "${machine}-${os}${release}" - exit ;; -+ *:Bitrig:*:*) -+ UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'` -+ echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE} -+ exit ;; - *:OpenBSD:*:*) - UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` - echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} -@@ -304,7 +321,7 @@ - arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) - echo arm-acorn-riscix${UNAME_RELEASE} - exit ;; -- arm:riscos:*:*|arm:RISCOS:*:*) -+ arm*:riscos:*:*|arm*:RISCOS:*:*) - echo arm-unknown-riscos - exit ;; - SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) -@@ -792,21 +809,26 @@ - echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} - exit ;; - *:FreeBSD:*:*) -- case ${UNAME_MACHINE} in -- pc98) -- echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; -+ UNAME_PROCESSOR=`/usr/bin/uname -p` -+ case ${UNAME_PROCESSOR} in - amd64) - echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - *) -- echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; -+ echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - esac - exit ;; - i*:CYGWIN*:*) - echo ${UNAME_MACHINE}-pc-cygwin - exit ;; -+ *:MINGW64*:*) -+ echo ${UNAME_MACHINE}-pc-mingw64 -+ exit ;; - *:MINGW*:*) - echo ${UNAME_MACHINE}-pc-mingw32 - exit ;; -+ *:MSYS*:*) -+ echo ${UNAME_MACHINE}-pc-msys -+ exit ;; - i*:windows32*:*) - # uname -m includes "-pc" on this system. - echo ${UNAME_MACHINE}-mingw32 -@@ -852,15 +874,22 @@ - exit ;; - *:GNU:*:*) - # the GNU system -- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` -+ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` - exit ;; - *:GNU/*:*:*) - # other systems with GNU libc and userland -- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu -+ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} - exit ;; - i*86:Minix:*:*) - echo ${UNAME_MACHINE}-pc-minix - exit ;; -+ aarch64:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ aarch64_be:Linux:*:*) -+ UNAME_MACHINE=aarch64_be -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; - alpha:Linux:*:*) - case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in - EV5) UNAME_MACHINE=alphaev5 ;; -@@ -872,56 +901,54 @@ - EV68*) UNAME_MACHINE=alphaev68 ;; - esac - objdump --private-headers /bin/sh | grep -q ld.so.1 -- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi -- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} -+ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ arc:Linux:*:* | arceb:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - arm*:Linux:*:*) - eval $set_cc_for_build - if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ - | grep -q __ARM_EABI__ - then -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - else - if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ - | grep -q __ARM_PCS_VFP - then -- echo ${UNAME_MACHINE}-unknown-linux-gnueabi -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi - else -- echo ${UNAME_MACHINE}-unknown-linux-gnueabihf -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf - fi - fi - exit ;; - avr32*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - cris:Linux:*:*) -- echo cris-axis-linux-gnu -+ echo ${UNAME_MACHINE}-axis-linux-${LIBC} - exit ;; - crisv32:Linux:*:*) -- echo crisv32-axis-linux-gnu -+ echo ${UNAME_MACHINE}-axis-linux-${LIBC} - exit ;; - frv:Linux:*:*) -- echo frv-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ hexagon:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - i*86:Linux:*:*) -- LIBC=gnu -- eval $set_cc_for_build -- sed 's/^ //' << EOF >$dummy.c -- #ifdef __dietlibc__ -- LIBC=dietlibc -- #endif --EOF -- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` -- echo "${UNAME_MACHINE}-pc-linux-${LIBC}" -+ echo ${UNAME_MACHINE}-pc-linux-${LIBC} - exit ;; - ia64:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - m32r*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - m68*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - mips:Linux:*:* | mips64:Linux:*:*) - eval $set_cc_for_build -@@ -940,54 +967,63 @@ - #endif - EOF - eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` -- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } -+ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } - ;; -- or32:Linux:*:*) -- echo or32-unknown-linux-gnu -+ openrisc*:Linux:*:*) -+ echo or1k-unknown-linux-${LIBC} -+ exit ;; -+ or32:Linux:*:* | or1k*:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - padre:Linux:*:*) -- echo sparc-unknown-linux-gnu -+ echo sparc-unknown-linux-${LIBC} - exit ;; - parisc64:Linux:*:* | hppa64:Linux:*:*) -- echo hppa64-unknown-linux-gnu -+ echo hppa64-unknown-linux-${LIBC} - exit ;; - parisc:Linux:*:* | hppa:Linux:*:*) - # Look for CPU level - case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in -- PA7*) echo hppa1.1-unknown-linux-gnu ;; -- PA8*) echo hppa2.0-unknown-linux-gnu ;; -- *) echo hppa-unknown-linux-gnu ;; -+ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; -+ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; -+ *) echo hppa-unknown-linux-${LIBC} ;; - esac - exit ;; - ppc64:Linux:*:*) -- echo powerpc64-unknown-linux-gnu -+ echo powerpc64-unknown-linux-${LIBC} - exit ;; - ppc:Linux:*:*) -- echo powerpc-unknown-linux-gnu -+ echo powerpc-unknown-linux-${LIBC} -+ exit ;; -+ ppc64le:Linux:*:*) -+ echo powerpc64le-unknown-linux-${LIBC} -+ exit ;; -+ ppcle:Linux:*:*) -+ echo powerpcle-unknown-linux-${LIBC} - exit ;; - s390:Linux:*:* | s390x:Linux:*:*) -- echo ${UNAME_MACHINE}-ibm-linux -+ echo ${UNAME_MACHINE}-ibm-linux-${LIBC} - exit ;; - sh64*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - sh*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - sparc:Linux:*:* | sparc64:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - tile*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - vax:Linux:*:*) -- echo ${UNAME_MACHINE}-dec-linux-gnu -+ echo ${UNAME_MACHINE}-dec-linux-${LIBC} - exit ;; - x86_64:Linux:*:*) -- echo x86_64-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - xtensa*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - i*86:DYNIX/ptx:4*:*) - # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. -@@ -1191,6 +1227,9 @@ - BePC:Haiku:*:*) # Haiku running on Intel PC compatible. - echo i586-pc-haiku - exit ;; -+ x86_64:Haiku:*:*) -+ echo x86_64-unknown-haiku -+ exit ;; - SX-4:SUPER-UX:*:*) - echo sx4-nec-superux${UNAME_RELEASE} - exit ;; -@@ -1217,19 +1256,31 @@ - exit ;; - *:Darwin:*:*) - UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown -- case $UNAME_PROCESSOR in -- i386) -- eval $set_cc_for_build -- if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then -- if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ -- (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ -- grep IS_64BIT_ARCH >/dev/null -- then -- UNAME_PROCESSOR="x86_64" -- fi -- fi ;; -- unknown) UNAME_PROCESSOR=powerpc ;; -- esac -+ eval $set_cc_for_build -+ if test "$UNAME_PROCESSOR" = unknown ; then -+ UNAME_PROCESSOR=powerpc -+ fi -+ if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then -+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then -+ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ -+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ -+ grep IS_64BIT_ARCH >/dev/null -+ then -+ case $UNAME_PROCESSOR in -+ i386) UNAME_PROCESSOR=x86_64 ;; -+ powerpc) UNAME_PROCESSOR=powerpc64 ;; -+ esac -+ fi -+ fi -+ elif test "$UNAME_PROCESSOR" = i386 ; then -+ # Avoid executing cc on OS X 10.9, as it ships with a stub -+ # that puts up a graphical alert prompting to install -+ # developer tools. Any system running Mac OS X 10.7 or -+ # later (Darwin 11 and later) is required to have a 64-bit -+ # processor. This is not true of the ARM version of Darwin -+ # that Apple uses in portable devices. -+ UNAME_PROCESSOR=x86_64 -+ fi - echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} - exit ;; - *:procnto*:*:* | *:QNX:[0123456789]*:*) -@@ -1246,7 +1297,7 @@ - NEO-?:NONSTOP_KERNEL:*:*) - echo neo-tandem-nsk${UNAME_RELEASE} - exit ;; -- NSE-?:NONSTOP_KERNEL:*:*) -+ NSE-*:NONSTOP_KERNEL:*:*) - echo nse-tandem-nsk${UNAME_RELEASE} - exit ;; - NSR-?:NONSTOP_KERNEL:*:*) -@@ -1315,158 +1366,10 @@ - i*86:AROS:*:*) - echo ${UNAME_MACHINE}-pc-aros - exit ;; --esac -- --#echo '(No uname command or uname output not recognized.)' 1>&2 --#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 -- --eval $set_cc_for_build --cat >$dummy.c < --# include --#endif --main () --{ --#if defined (sony) --#if defined (MIPSEB) -- /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, -- I don't know.... */ -- printf ("mips-sony-bsd\n"); exit (0); --#else --#include -- printf ("m68k-sony-newsos%s\n", --#ifdef NEWSOS4 -- "4" --#else -- "" --#endif -- ); exit (0); --#endif --#endif -- --#if defined (__arm) && defined (__acorn) && defined (__unix) -- printf ("arm-acorn-riscix\n"); exit (0); --#endif -- --#if defined (hp300) && !defined (hpux) -- printf ("m68k-hp-bsd\n"); exit (0); --#endif -- --#if defined (NeXT) --#if !defined (__ARCHITECTURE__) --#define __ARCHITECTURE__ "m68k" --#endif -- int version; -- version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; -- if (version < 4) -- printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); -- else -- printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); -- exit (0); --#endif -- --#if defined (MULTIMAX) || defined (n16) --#if defined (UMAXV) -- printf ("ns32k-encore-sysv\n"); exit (0); --#else --#if defined (CMU) -- printf ("ns32k-encore-mach\n"); exit (0); --#else -- printf ("ns32k-encore-bsd\n"); exit (0); --#endif --#endif --#endif -- --#if defined (__386BSD__) -- printf ("i386-pc-bsd\n"); exit (0); --#endif -- --#if defined (sequent) --#if defined (i386) -- printf ("i386-sequent-dynix\n"); exit (0); --#endif --#if defined (ns32000) -- printf ("ns32k-sequent-dynix\n"); exit (0); --#endif --#endif -- --#if defined (_SEQUENT_) -- struct utsname un; -- -- uname(&un); -- -- if (strncmp(un.version, "V2", 2) == 0) { -- printf ("i386-sequent-ptx2\n"); exit (0); -- } -- if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ -- printf ("i386-sequent-ptx1\n"); exit (0); -- } -- printf ("i386-sequent-ptx\n"); exit (0); -- --#endif -- --#if defined (vax) --# if !defined (ultrix) --# include --# if defined (BSD) --# if BSD == 43 -- printf ("vax-dec-bsd4.3\n"); exit (0); --# else --# if BSD == 199006 -- printf ("vax-dec-bsd4.3reno\n"); exit (0); --# else -- printf ("vax-dec-bsd\n"); exit (0); --# endif --# endif --# else -- printf ("vax-dec-bsd\n"); exit (0); --# endif --# else -- printf ("vax-dec-ultrix\n"); exit (0); --# endif --#endif -- --#if defined (alliant) && defined (i860) -- printf ("i860-alliant-bsd\n"); exit (0); --#endif -- -- exit (1); --} --EOF -- --$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && -- { echo "$SYSTEM_NAME"; exit; } -- --# Apollos put the system type in the environment. -- --test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } -- --# Convex versions that predate uname can use getsysinfo(1) -- --if [ -x /usr/convex/getsysinfo ] --then -- case `getsysinfo -f cpu_type` in -- c1*) -- echo c1-convex-bsd -+ x86_64:VMkernel:*:*) -+ echo ${UNAME_MACHINE}-unknown-esx - exit ;; -- c2*) -- if getsysinfo -f scalar_acc -- then echo c32-convex-bsd -- else echo c2-convex-bsd -- fi -- exit ;; -- c34*) -- echo c34-convex-bsd -- exit ;; -- c38*) -- echo c38-convex-bsd -- exit ;; -- c4*) -- echo c4-convex-bsd -- exit ;; -- esac --fi -+esac - - cat >&2 <. -@@ -26,11 +20,12 @@ - # As a special exception to the GNU General Public License, if you - # distribute this file as part of a program that contains a - # configuration script generated by Autoconf, you may include it under --# the same distribution terms that you use for the rest of that program. -+# the same distribution terms that you use for the rest of that -+# program. This Exception is an additional permission under section 7 -+# of the GNU General Public License, version 3 ("GPLv3"). - - --# Please send patches to . Submit a context --# diff and a properly formatted GNU ChangeLog entry. -+# Please send patches with a ChangeLog entry to config-patches@gnu.org. - # - # Configuration subroutine to validate and canonicalize a configuration type. - # Supply the specified configuration type as an argument. -@@ -73,9 +68,7 @@ - version="\ - GNU config.sub ($timestamp) - --Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, --2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 --Free Software Foundation, Inc. -+Copyright 1992-2014 Free Software Foundation, Inc. - - This is free software; see the source for copying conditions. There is NO - warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." -@@ -123,7 +116,7 @@ - maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` - case $maybe_os in - nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ -- linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ -+ linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ - knetbsd*-gnu* | netbsd*-gnu* | \ - kopensolaris*-gnu* | \ - storm-chaos* | os2-emx* | rtmk-nova*) -@@ -156,7 +149,7 @@ - -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ - -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ - -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ -- -apple | -axis | -knuth | -cray | -microblaze) -+ -apple | -axis | -knuth | -cray | -microblaze*) - os= - basic_machine=$1 - ;; -@@ -259,10 +252,12 @@ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -- | be32 | be64 \ -+ | arc | arceb \ -+ | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \ -+ | avr | avr32 \ -+ | be32 | be64 \ - | bfin \ -- | c4x | clipper \ -+ | c4x | c8051 | clipper \ - | d10v | d30v | dlx | dsp16xx \ - | epiphany \ - | fido | fr30 | frv \ -@@ -270,10 +265,11 @@ - | hexagon \ - | i370 | i860 | i960 | ia64 \ - | ip2k | iq2000 \ -+ | k1om \ - | le32 | le64 \ - | lm32 \ - | m32c | m32r | m32rle | m68000 | m68k | m88k \ -- | maxq | mb | microblaze | mcore | mep | metag \ -+ | maxq | mb | microblaze | microblazeel | mcore | mep | metag \ - | mips | mipsbe | mipseb | mipsel | mipsle \ - | mips16 \ - | mips64 | mips64el \ -@@ -287,20 +283,22 @@ - | mips64vr5900 | mips64vr5900el \ - | mipsisa32 | mipsisa32el \ - | mipsisa32r2 | mipsisa32r2el \ -+ | mipsisa32r6 | mipsisa32r6el \ - | mipsisa64 | mipsisa64el \ - | mipsisa64r2 | mipsisa64r2el \ -+ | mipsisa64r6 | mipsisa64r6el \ - | mipsisa64sb1 | mipsisa64sb1el \ - | mipsisa64sr71k | mipsisa64sr71kel \ -+ | mipsr5900 | mipsr5900el \ - | mipstx39 | mipstx39el \ - | mn10200 | mn10300 \ - | moxie \ - | mt \ - | msp430 \ - | nds32 | nds32le | nds32be \ -- | nios | nios2 \ -+ | nios | nios2 | nios2eb | nios2el \ - | ns16k | ns32k \ -- | open8 \ -- | or32 \ -+ | open8 | or1k | or1knd | or32 \ - | pdp10 | pdp11 | pj | pjl \ - | powerpc | powerpc64 | powerpc64le | powerpcle \ - | pyramid \ -@@ -328,7 +326,7 @@ - c6x) - basic_machine=tic6x-unknown - ;; -- m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | picochip) -+ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip) - basic_machine=$basic_machine-unknown - os=-none - ;; -@@ -370,13 +368,13 @@ - | aarch64-* | aarch64_be-* \ - | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ - | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ -- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ -+ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \ - | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ - | avr-* | avr32-* \ - | be32-* | be64-* \ - | bfin-* | bs2000-* \ - | c[123]* | c30-* | [cjt]90-* | c4x-* \ -- | clipper-* | craynv-* | cydra-* \ -+ | c8051-* | clipper-* | craynv-* | cydra-* \ - | d10v-* | d30v-* | dlx-* \ - | elxsi-* \ - | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ -@@ -385,11 +383,13 @@ - | hexagon-* \ - | i*86-* | i860-* | i960-* | ia64-* \ - | ip2k-* | iq2000-* \ -+ | k1om-* \ - | le32-* | le64-* \ - | lm32-* \ - | m32c-* | m32r-* | m32rle-* \ - | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ -- | m88110-* | m88k-* | maxq-* | mcore-* | metag-* | microblaze-* \ -+ | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \ -+ | microblaze-* | microblazeel-* \ - | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ - | mips16-* \ - | mips64-* | mips64el-* \ -@@ -403,18 +403,22 @@ - | mips64vr5900-* | mips64vr5900el-* \ - | mipsisa32-* | mipsisa32el-* \ - | mipsisa32r2-* | mipsisa32r2el-* \ -+ | mipsisa32r6-* | mipsisa32r6el-* \ - | mipsisa64-* | mipsisa64el-* \ - | mipsisa64r2-* | mipsisa64r2el-* \ -+ | mipsisa64r6-* | mipsisa64r6el-* \ - | mipsisa64sb1-* | mipsisa64sb1el-* \ - | mipsisa64sr71k-* | mipsisa64sr71kel-* \ -+ | mipsr5900-* | mipsr5900el-* \ - | mipstx39-* | mipstx39el-* \ - | mmix-* \ - | mt-* \ - | msp430-* \ - | nds32-* | nds32le-* | nds32be-* \ -- | nios-* | nios2-* \ -+ | nios-* | nios2-* | nios2eb-* | nios2el-* \ - | none-* | np1-* | ns16k-* | ns32k-* \ - | open8-* \ -+ | or1k*-* \ - | orion-* \ - | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ - | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ -@@ -788,11 +792,15 @@ - basic_machine=ns32k-utek - os=-sysv - ;; -- microblaze) -+ microblaze*) - basic_machine=microblaze-xilinx - ;; -+ mingw64) -+ basic_machine=x86_64-pc -+ os=-mingw64 -+ ;; - mingw32) -- basic_machine=i386-pc -+ basic_machine=i686-pc - os=-mingw32 - ;; - mingw32ce) -@@ -828,7 +836,7 @@ - basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` - ;; - msys) -- basic_machine=i386-pc -+ basic_machine=i686-pc - os=-msys - ;; - mvs) -@@ -1019,7 +1027,11 @@ - basic_machine=i586-unknown - os=-pw32 - ;; -- rdos) -+ rdos | rdos64) -+ basic_machine=x86_64-pc -+ os=-rdos -+ ;; -+ rdos32) - basic_machine=i386-pc - os=-rdos - ;; -@@ -1346,21 +1358,21 @@ - -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ - | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\ - | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \ -- | -sym* | -kopensolaris* \ -+ | -sym* | -kopensolaris* | -plan9* \ - | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ - | -aos* | -aros* \ - | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ - | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ - | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ -- | -openbsd* | -solidbsd* \ -+ | -bitrig* | -openbsd* | -solidbsd* \ - | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ - | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ - | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ - | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ - | -chorusos* | -chorusrdb* | -cegcc* \ - | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ -- | -mingw32* | -linux-gnu* | -linux-android* \ -- | -linux-newlib* | -linux-uclibc* \ -+ | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ -+ | -linux-newlib* | -linux-musl* | -linux-uclibc* \ - | -uxpv* | -beos* | -mpeix* | -udk* \ - | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ - | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ -@@ -1368,7 +1380,7 @@ - | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ - | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ - | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ -- | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es*) -+ | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*) - # Remember, each alternative MUST END IN *, to match a version number. - ;; - -qnx*) -@@ -1492,9 +1504,6 @@ - -aros*) - os=-aros - ;; -- -kaos*) -- os=-kaos -- ;; - -zvmoe) - os=-zvmoe - ;; -@@ -1543,6 +1552,12 @@ - c4x-* | tic4x-*) - os=-coff - ;; -+ c8051-*) -+ os=-elf -+ ;; -+ hexagon-*) -+ os=-elf -+ ;; - tic54x-*) - os=-coff - ;; -diff -urN gdb-7.5.1-orig/gdb/configure gdb-7.5.1/gdb/configure ---- gdb-7.5.1-orig/gdb/configure 2012-07-17 20:43:41.000000000 -0700 -+++ gdb-7.5.1/gdb/configure 2015-08-18 17:02:34.366940800 -0700 -@@ -4443,6 +4443,8 @@ - - am_cv_CC_dependencies_compiler_type=none - if test "$am_compiler_list" = ""; then -+ echo $am_depcomp -+ echo xxxxxxxxxxxxxxxxx - am_compiler_list=`sed -n 's/^\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` - fi - for depmode in $am_compiler_list; do -diff -urN gdb-7.5.1-orig/gdb/dwarf2-frame.c gdb-7.5.1/gdb/dwarf2-frame.c ---- gdb-7.5.1-orig/gdb/dwarf2-frame.c 2012-08-06 12:21:51.000000000 -0700 -+++ gdb-7.5.1/gdb/dwarf2-frame.c 2015-08-23 18:57:53.906408800 -0700 -@@ -1493,22 +1493,30 @@ - the DWARF unwinder. This is used to implement - DW_OP_call_frame_cfa. */ - -+ - CORE_ADDR - dwarf2_frame_cfa (struct frame_info *this_frame) - { -+ CORE_ADDR cfa; - while (get_frame_type (this_frame) == INLINE_FRAME) - this_frame = get_prev_frame (this_frame); - /* This restriction could be lifted if other unwinders are known to - compute the frame base in a way compatible with the DWARF - unwinder. */ -+#if 0 - if (!frame_unwinder_is (this_frame, &dwarf2_frame_unwind) - && !frame_unwinder_is (this_frame, &dwarf2_tailcall_frame_unwind)) - error (_("can't compute CFA for this frame")); -+#endif -+ - if (get_frame_unwind_stop_reason (this_frame) == UNWIND_UNAVAILABLE) - throw_error (NOT_AVAILABLE_ERROR, - _("can't compute CFA for this frame: " - "required registers or memory are unavailable")); -- return get_frame_base (this_frame); -+ cfa = get_frame_base (this_frame); -+ if (!cfa) -+ error("Cannot determine frame base. Please call the current function from a function compiled with frame pointer to allow viewing local variables."); -+ return cfa; - } - - const struct objfile_data *dwarf2_frame_objfile_data; -diff -urN gdb-7.5.1-orig/gdb/gdbserver/xtensa-xtregs.c gdb-7.5.1/gdb/gdbserver/xtensa-xtregs.c ---- gdb-7.5.1-orig/gdb/gdbserver/xtensa-xtregs.c 2012-01-04 00:17:24.000000000 -0800 -+++ gdb-7.5.1/gdb/gdbserver/xtensa-xtregs.c 2015-08-04 11:34:10.500831300 -0700 -@@ -1,37 +1,42 @@ --/* Table mapping between kernel xtregset and GDB register cache. -- Copyright 2007-2012 Free Software Foundation, Inc. -- -- This file is part of GDB. -- -- This program is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License as -- published by the Free Software Foundation; either version 3 of the -- License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . */ -- -- --typedef struct { -- int gdb_regnum; -- int gdb_offset; -- int ptrace_cp_offset; -- int ptrace_offset; -- int size; -- int coproc; -- int dbnum; -- char* name --;} xtensa_regtable_t; -- --#define XTENSA_ELF_XTREG_SIZE 4 -- --const xtensa_regtable_t xtensa_regmap_table[] = { -- /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ -- { 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" }, -- { 0 } --}; -+/* Customized table mapping between kernel xtregset and GDB register cache. -+ -+ Copyright (c) 2007-2010 Tensilica Inc. -+ -+ Permission is hereby granted, free of charge, to any person obtaining -+ a copy of this software and associated documentation files (the -+ "Software"), to deal in the Software without restriction, including -+ without limitation the rights to use, copy, modify, merge, publish, -+ distribute, sublicense, and/or sell copies of the Software, and to -+ permit persons to whom the Software is furnished to do so, subject to -+ the following conditions: -+ -+ The above copyright notice and this permission notice shall be included -+ in all copies or substantial portions of the Software. -+ -+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -+ -+ -+typedef struct { -+ int gdb_regnum; -+ int gdb_offset; -+ int ptrace_cp_offset; -+ int ptrace_offset; -+ int size; -+ int coproc; -+ int dbnum; -+ char* name -+;} xtensa_regtable_t; -+ -+#define XTENSA_ELF_XTREG_SIZE 0 -+ -+const xtensa_regtable_t xtensa_regmap_table[] = { -+ /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ -+ { 0 } -+}; -+ -diff -urN gdb-7.5.1-orig/gdb/regformats/reg-xtensa.dat gdb-7.5.1/gdb/regformats/reg-xtensa.dat ---- gdb-7.5.1-orig/gdb/regformats/reg-xtensa.dat 2008-11-19 10:29:47.000000000 -0800 -+++ gdb-7.5.1/gdb/regformats/reg-xtensa.dat 2015-08-04 11:34:12.301911300 -0700 -@@ -1,47 +1,24 @@ --name:xtensa --expedite:pc,windowbase,windowstart --32:pc --32:ar0 --32:ar1 --32:ar2 --32:ar3 --32:ar4 --32:ar5 --32:ar6 --32:ar7 --32:ar8 --32:ar9 --32:ar10 --32:ar11 --32:ar12 --32:ar13 --32:ar14 --32:ar15 --32:ar16 --32:ar17 --32:ar18 --32:ar19 --32:ar20 --32:ar21 --32:ar22 --32:ar23 --32:ar24 --32:ar25 --32:ar26 --32:ar27 --32:ar28 --32:ar29 --32:ar30 --32:ar31 --32:lbeg --32:lend --32:lcount --32:sar --32:litbase --32:windowbase --32:windowstart --32:sr176 --32:sr208 --32:ps --32:threadptr --32:scompare1 -+name:xtensa -+expedite:pc,windowbase,windowstart -+32:a0 -+32:a1 -+32:a2 -+32:a3 -+32:a4 -+32:a5 -+32:a6 -+32:a7 -+32:a8 -+32:a9 -+32:a10 -+32:a11 -+32:a12 -+32:a13 -+32:a14 -+32:a15 -+32:pc -+32:sar -+32:litbase -+32:sr176 -+32:sr208 -+32:ps -diff -urN gdb-7.5.1-orig/gdb/xtensa-config.c gdb-7.5.1/gdb/xtensa-config.c ---- gdb-7.5.1-orig/gdb/xtensa-config.c 2012-01-04 00:27:58.000000000 -0800 -+++ gdb-7.5.1/gdb/xtensa-config.c 2015-08-18 17:06:01.571940800 -0700 -@@ -1,219 +1,118 @@ --/* Configuration for the Xtensa architecture for GDB, the GNU debugger. -- -- Copyright (C) 2003, 2005-2012 Free Software Foundation, Inc. -- -- This file is part of GDB. -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . */ -- --#define XTENSA_CONFIG_VERSION 0x60 -- --#include "xtensa-config.h" --#include "xtensa-tdep.h" -- -- -- --/* Masked registers. */ --xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } }; --const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; --xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } }; --const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; --xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } }; --const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; --xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } }; --const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; --xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } }; --const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; --xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } }; --const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; --xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } }; --const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; --xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } }; --const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; --xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } }; --const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; --xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } }; --const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; --xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } }; --const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; --xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } }; --const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; --xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } }; --const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; --xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } }; --const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; --xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } }; --const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; --xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } }; --const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; -- -- --/* Register map. */ --xtensa_register_t rmap[] = --{ -- /* idx ofs bi sz al targno flags cp typ group name */ -- XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) -- XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) -- XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) -- XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) -- XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) -- XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) -- XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) -- XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) -- XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) -- XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) -- XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) -- XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) -- XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) -- XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) -- XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) -- XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) -- XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) -- XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) -- XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) -- XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) -- XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) -- XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) -- XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) -- XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) -- XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) -- XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) -- XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) -- XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) -- XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) -- XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) -- XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) -- XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) -- XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) -- XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) -- XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) -- XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) -- XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) -- XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0) -- XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) -- XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) -- XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0) -- XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0) -- XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) -- XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) -- XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) -- XTREG( 45,180,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0) -- XTREG( 46,184,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) -- XTREG( 47,188,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0) -- XTREG( 48,192,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0) -- XTREG( 49,196,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0) -- XTREG( 50,200, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) -- XTREG( 51,204,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) -- XTREG( 52,208,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) -- XTREG( 53,212,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) -- XTREG( 54,216,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) -- XTREG( 55,220,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) -- XTREG( 56,224,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) -- XTREG( 57,228,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) -- XTREG( 58,232,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) -- XTREG( 59,236,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) -- XTREG( 60,240,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) -- XTREG( 61,244,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) -- XTREG( 62,248,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) -- XTREG( 63,252,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) -- XTREG( 64,256,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) -- XTREG( 65,260,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) -- XTREG( 66,264,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) -- XTREG( 67,268,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) -- XTREG( 68,272,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) -- XTREG( 69,276,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) -- XTREG( 70,280,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) -- XTREG( 71,284,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) -- XTREG( 72,288,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) -- XTREG( 73,292,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) -- XTREG( 74,296,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) -- XTREG( 75,300,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) -- XTREG( 76,304,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) -- XTREG( 77,308,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) -- XTREG( 78,312,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) -- XTREG( 79,316, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) -- XTREG( 80,320,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) -- XTREG( 81,324,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) -- XTREG( 82,328,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) -- XTREG( 83,332,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) -- XTREG( 84,336,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) -- XTREG( 85,340, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) -- XTREG( 86,344,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) -- XTREG( 87,348,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) -- XTREG( 88,352,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) -- XTREG( 89,356,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) -- XTREG( 90,360, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) -- XTREG( 91,364,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) -- XTREG( 92,368,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) -- XTREG( 93,372,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) -- XTREG( 94,376,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) -- XTREG( 95,380,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) -- XTREG( 96,384,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) -- XTREG( 97,388,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) -- XTREG( 98,392,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) -- XTREG( 99,396,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) -- XTREG(100,400,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) -- XTREG(101,404,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) -- XTREG(102,408,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) -- XTREG(103,412,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) -- XTREG(104,416,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) -- XTREG(105,420,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) -- XTREG(106,424,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) -- XTREG(107,428,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) -- XTREG(108,432,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) -- XTREG(109,436,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) -- XTREG(110,440,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) -- XTREG(111,444,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) -- XTREG(112,448,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) -- XTREG(113,452, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, -- 0,0,&xtensa_mask0,0,0,0) -- XTREG(114,456, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, -- 0,0,&xtensa_mask1,0,0,0) -- XTREG(115,460, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, -- 0,0,&xtensa_mask2,0,0,0) -- XTREG(116,464, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, -- 0,0,&xtensa_mask3,0,0,0) -- XTREG(117,468, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, -- 0,0,&xtensa_mask4,0,0,0) -- XTREG(118,472, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, -- 0,0,&xtensa_mask5,0,0,0) -- XTREG(119,476, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, -- 0,0,&xtensa_mask6,0,0,0) -- XTREG(120,480,20, 4, 4,0x200f,0x0006,-2, 6,0x1010,litbaddr, -- 0,0,&xtensa_mask7,0,0,0) -- XTREG(121,484, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,litben, -- 0,0,&xtensa_mask8,0,0,0) -- XTREG(122,488, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum, -- 0,0,&xtensa_mask9,0,0,0) -- XTREG(123,492, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3, -- 0,0,&xtensa_mask10,0,0,0) -- XTREG(124,496, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2, -- 0,0,&xtensa_mask11,0,0,0) -- XTREG(125,500, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1, -- 0,0,&xtensa_mask12,0,0,0) -- XTREG(126,504, 2, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid4, -- 0,0,&xtensa_mask13,0,0,0) -- XTREG(127,508, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,datapgszid4, -- 0,0,&xtensa_mask14,0,0,0) -- XTREG(128,512,10, 4, 4,0x201b,0x0006,-2, 6,0x1010,ptbase, -- 0,0,&xtensa_mask15,0,0,0) -- XTREG_END --}; -- -- -- --#ifdef XTENSA_CONFIG_INSTANTIATE --XTENSA_CONFIG_INSTANTIATE(rmap,0) --#endif -- -+/* Configuration for the Xtensa architecture for GDB, the GNU debugger. -+ -+ Copyright (c) 2003-2010 Tensilica Inc. -+ -+ Permission is hereby granted, free of charge, to any person obtaining -+ a copy of this software and associated documentation files (the -+ "Software"), to deal in the Software without restriction, including -+ without limitation the rights to use, copy, modify, merge, publish, -+ distribute, sublicense, and/or sell copies of the Software, and to -+ permit persons to whom the Software is furnished to do so, subject to -+ the following conditions: -+ -+ The above copyright notice and this permission notice shall be included -+ in all copies or substantial portions of the Software. -+ -+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -+ -+#define XTENSA_CONFIG_VERSION 0x60 -+ -+#include "xtensa-config.h" -+#include "xtensa-tdep.h" -+ -+ -+ -+/* Masked registers. */ -+xtensa_reg_mask_t xtensa_submask0[] = { { 21, 0, 4 } }; -+const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; -+xtensa_reg_mask_t xtensa_submask1[] = { { 21, 5, 1 } }; -+const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; -+xtensa_reg_mask_t xtensa_submask2[] = { { 21, 4, 1 } }; -+const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; -+xtensa_reg_mask_t xtensa_submask3[] = { { 18, 12, 20 } }; -+const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; -+xtensa_reg_mask_t xtensa_submask4[] = { { 18, 0, 1 } }; -+const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; -+xtensa_reg_mask_t xtensa_submask5[] = { { 43, 8, 4 } }; -+const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; -+ -+ -+/* Register map. */ -+xtensa_register_t rmap[] = -+{ -+ /* idx ofs bi sz al targno flags cp typ group name */ -+ XTREG( 0, 0,32, 4, 4,0x0000,0x0006 & ~1,-2, 8,0x0100,a0, 0,0,0,0,0,0) -+ XTREG( 1, 4,32, 4, 4,0x0001,0x0006 & ~1,-2, 8,0x0100,a1, 0,0,0,0,0,0) -+ XTREG( 2, 8,32, 4, 4,0x0002,0x0006 & ~1,-2, 8,0x0100,a2, 0,0,0,0,0,0) -+ XTREG( 3, 12,32, 4, 4,0x0003,0x0006 & ~1,-2, 8,0x0100,a3, 0,0,0,0,0,0) -+ XTREG( 4, 16,32, 4, 4,0x0004,0x0006 & ~1,-2, 8,0x0100,a4, 0,0,0,0,0,0) -+ XTREG( 5, 20,32, 4, 4,0x0005,0x0006 & ~1,-2, 8,0x0100,a5, 0,0,0,0,0,0) -+ XTREG( 6, 24,32, 4, 4,0x0006,0x0006 & ~1,-2, 8,0x0100,a6, 0,0,0,0,0,0) -+ XTREG( 7, 28,32, 4, 4,0x0007,0x0006 & ~1,-2, 8,0x0100,a7, 0,0,0,0,0,0) -+ XTREG( 8, 32,32, 4, 4,0x0008,0x0006 & ~1,-2, 8,0x0100,a8, 0,0,0,0,0,0) -+ XTREG( 9, 36,32, 4, 4,0x0009,0x0006 & ~1,-2, 8,0x0100,a9, 0,0,0,0,0,0) -+ XTREG( 10, 40,32, 4, 4,0x000a,0x0006 & ~1,-2, 8,0x0100,a10, 0,0,0,0,0,0) -+ XTREG( 11, 44,32, 4, 4,0x000b,0x0006 & ~1,-2, 8,0x0100,a11, 0,0,0,0,0,0) -+ XTREG( 12, 48,32, 4, 4,0x000c,0x0006 & ~1,-2, 8,0x0100,a12, 0,0,0,0,0,0) -+ XTREG( 13, 52,32, 4, 4,0x000d,0x0006 & ~1,-2, 8,0x0100,a13, 0,0,0,0,0,0) -+ XTREG( 14, 56,32, 4, 4,0x000e,0x0006 & ~1,-2, 8,0x0100,a14, 0,0,0,0,0,0) -+ XTREG( 15, 60,32, 4, 4,0x000f,0x0006 & ~1,-2, 8,0x0100,a15, 0,0,0,0,0,0) -+ XTREG( 16, 64,32, 4, 4,0x0020,0x0006 & ~1,-2, 9,0x0100,pc, 0,0,0,0,0,0) -+ XTREG( 17, 68, 6, 4, 4,0x0203,0x0006 & ~1,-2, 2,0x1100,sar, 0,0,0,0,0,0) -+ XTREG( 18, 72,32, 4, 4,0x0205,0x0006 & ~1,-2, 2,0x1100,litbase, 0,0,0,0,0,0) -+ XTREG( 19, 76,32, 4, 4,0x02b0,0x0002 & ~1,-2, 2,0x1000,sr176, 0,0,0,0,0,0) -+ XTREG( 20, 80,32, 4, 4,0x02d0,0x0002 & ~1,-2, 2,0x1000,sr208, 0,0,0,0,0,0) -+ XTREG( 21, 84, 6, 4, 4,0x02e6,0x0006 & ~1,-2, 2,0x1100,ps, 0,0,0,0,0,0) -+ XTREG( 22, 88,32, 4, 4,0x0259,0x000d & ~1,-2, 2,0x1000,mmid, 0,0,0,0,0,0) -+ XTREG( 23, 92, 1, 4, 4,0x0260,0x0007 & ~1,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) -+ XTREG( 24, 96,32, 4, 4,0x0268,0x0007 & ~1,-2, 2,0x1000,ddr, 0,0,0,0,0,0) -+ XTREG( 25,100,32, 4, 4,0x0280,0x0007 & ~1,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) -+ XTREG( 26,104,32, 4, 4,0x0290,0x0007 & ~1,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) -+ XTREG( 27,108,32, 4, 4,0x02a0,0x0007 & ~1,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) -+ XTREG( 28,112,32, 4, 4,0x02b1,0x0007 & ~1,-2, 2,0x1000,epc1, 0,0,0,0,0,0) -+ XTREG( 29,116,32, 4, 4,0x02b2,0x0007 & ~1,-2, 2,0x1000,epc2, 0,0,0,0,0,0) -+ XTREG( 30,120,32, 4, 4,0x02b3,0x0007 & ~1,-2, 2,0x1000,epc3, 0,0,0,0,0,0) -+ XTREG( 31,124,32, 4, 4,0x02c0,0x0007 & ~1,-2, 2,0x1000,depc, 0,0,0,0,0,0) -+ XTREG( 32,128, 6, 4, 4,0x02c2,0x0007 & ~1,-2, 2,0x1000,eps2, 0,0,0,0,0,0) -+ XTREG( 33,132, 6, 4, 4,0x02c3,0x0007 & ~1,-2, 2,0x1000,eps3, 0,0,0,0,0,0) -+ XTREG( 34,136,32, 4, 4,0x02d1,0x0007 & ~1,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) -+ XTREG( 35,140,32, 4, 4,0x02d2,0x0007 & ~1,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) -+ XTREG( 36,144,32, 4, 4,0x02d3,0x0007 & ~1,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) -+ XTREG( 37,148,15, 4, 4,0x02e2,0x000b & ~1,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) -+ XTREG( 38,152,15, 4, 4,0x02e2,0x000d & ~1,-2, 2,0x1000,intset, 0,0,0,0,0,0) -+ XTREG( 39,156,15, 4, 4,0x02e3,0x000d & ~1,-2, 2,0x1000,intclear, 0,0,0,0,0,0) -+ XTREG( 40,160,15, 4, 4,0x02e4,0x0007 & ~1,-2, 2,0x1000,intenable, 0,0,0,0,0,0) -+ XTREG( 41,164,32, 4, 4,0x02e7,0x0007 & ~1,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) -+ XTREG( 42,168, 6, 4, 4,0x02e8,0x0007 & ~1,-2, 2,0x1000,exccause, 0,0,0,0,0,0) -+ XTREG( 43,172,12, 4, 4,0x02e9,0x0003 & ~1,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) -+ XTREG( 44,176,32, 4, 4,0x02ea,0x000f & ~1,-2, 2,0x1000,ccount, 0,0,0,0,0,0) -+ XTREG( 45,180,32, 4, 4,0x02eb,0x0003 & ~1,-2, 2,0x1000,prid, 0,0,0,0,0,0) -+ XTREG( 46,184,32, 4, 4,0x02ec,0x000f & ~1,-2, 2,0x1000,icount, 0,0,0,0,0,0) -+ XTREG( 47,188, 4, 4, 4,0x02ed,0x0007 & ~1,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) -+ XTREG( 48,192,32, 4, 4,0x02ee,0x0007 & ~1,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) -+ XTREG( 49,196,32, 4, 4,0x02f0,0x000f & ~1,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) -+ XTREG( 50,200, 4, 4, 4,0x2002,0x0006,-2, 6,0x1010,psintlevel, -+ 0,0,&xtensa_mask0,0,0,0) -+ XTREG( 51,204, 1, 4, 4,0x2003,0x0006,-2, 6,0x1010,psum, -+ 0,0,&xtensa_mask1,0,0,0) -+ XTREG( 52,208, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psexcm, -+ 0,0,&xtensa_mask2,0,0,0) -+ XTREG( 53,212,20, 4, 4,0x2005,0x0006,-2, 6,0x1010,litbaddr, -+ 0,0,&xtensa_mask3,0,0,0) -+ XTREG( 54,216, 1, 4, 4,0x2006,0x0006,-2, 6,0x1010,litben, -+ 0,0,&xtensa_mask4,0,0,0) -+ XTREG_END -+}; -+ -+ -+ -+#ifdef XTENSA_CONFIG_INSTANTIATE -+XTENSA_CONFIG_INSTANTIATE(rmap,0) -+#endif -+ -diff -urN gdb-7.5.1-orig/gdb/xtensa-tdep.c gdb-7.5.1/gdb/xtensa-tdep.c ---- gdb-7.5.1-orig/gdb/xtensa-tdep.c 2012-05-18 14:02:51.000000000 -0700 -+++ gdb-7.5.1/gdb/xtensa-tdep.c 2015-08-18 17:50:12.374935700 -0700 -@@ -555,10 +555,6 @@ - DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", - regnum, xtensa_register_name (gdbarch, regnum)); - -- if (regnum == gdbarch_num_regs (gdbarch) -- + gdbarch_num_pseudo_regs (gdbarch) - 1) -- regnum = gdbarch_tdep (gdbarch)->a0_base + 1; -- - /* Read aliases a0..a15, if this is a Windowed ABI. */ - if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers - && (regnum >= gdbarch_tdep (gdbarch)->a0_base) -@@ -655,10 +651,6 @@ - DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", - regnum, xtensa_register_name (gdbarch, regnum)); - -- if (regnum == gdbarch_num_regs (gdbarch) -- + gdbarch_num_pseudo_regs (gdbarch) -1) -- regnum = gdbarch_tdep (gdbarch)->a0_base + 1; -- - /* Renumber register, if aliase a0..a15 on Windowed ABI. */ - if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers - && (regnum >= gdbarch_tdep (gdbarch)->a0_base) -@@ -2040,6 +2032,8 @@ - const char *opcname; - int found_ret = 0; - -+ if (!xtensa_default_isa) -+ xtensa_default_isa = xtensa_isa_init(0, 0); - isa = xtensa_default_isa; - gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); - ins = xtensa_insnbuf_alloc (isa); -@@ -2425,7 +2419,7 @@ - /* Find out, if we have an information about the prologue from DWARF. */ - prologue_sal = find_pc_line (start, 0); - if (prologue_sal.line != 0) /* Found debug info. */ -- body_pc = prologue_sal.end; -+ body_pc = prologue_sal.end + 40; - - /* If we are going to analyze the prologue in general without knowing about - the current PC, make the best assumtion for the end of the prologue. */ -@@ -2819,6 +2813,8 @@ - /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */ - int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140; - -+ if (!xtensa_default_isa) -+ xtensa_default_isa = xtensa_isa_init(0, 0); - isa = xtensa_default_isa; - gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); - ins = xtensa_insnbuf_alloc (isa); -@@ -3190,6 +3186,9 @@ - tdep->num_regs = n; - } - -+ if (tdep->ar_base == -1) -+ tdep->ar_base = tdep->a0_base; -+ - /* Number of pseudo registers. */ - tdep->num_pseudo_regs = n - tdep->num_regs; - -diff -urN gdb-7.5.1-orig/gdb/xtensa-tdep.h gdb-7.5.1/gdb/xtensa-tdep.h ---- gdb-7.5.1-orig/gdb/xtensa-tdep.h 2012-01-04 00:27:58.000000000 -0800 -+++ gdb-7.5.1/gdb/xtensa-tdep.h 2015-08-18 17:06:02.796940800 -0700 -@@ -244,7 +244,8 @@ - .spill_location = -1, \ - .spill_size = (spillsz), \ - .unused = 0, \ -- .call_abi = 0, \ -+ .call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0) ? \ -+ CallAbiCall0Only : CallAbiDefault, \ - .debug_interrupt_level = XCHAL_DEBUGLEVEL, \ - .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \ - .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ -diff -urN gdb-7.5.1-orig/include/xtensa-config.h gdb-7.5.1/include/xtensa-config.h ---- gdb-7.5.1-orig/include/xtensa-config.h 2011-01-03 13:05:50.000000000 -0800 -+++ gdb-7.5.1/include/xtensa-config.h 2015-08-04 11:34:09.056465200 -0700 -@@ -1,177 +1,171 @@ --/* Xtensa configuration settings. -- Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 -- Free Software Foundation, Inc. -- Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2, or (at your option) -- any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -- --#ifndef XTENSA_CONFIG_H --#define XTENSA_CONFIG_H -- --/* The macros defined here match those with the same names in the Xtensa -- compile-time HAL (Hardware Abstraction Layer). Please refer to the -- Xtensa System Software Reference Manual for documentation of these -- macros. */ -- --#undef XCHAL_HAVE_BE --#define XCHAL_HAVE_BE 1 -- --#undef XCHAL_HAVE_DENSITY --#define XCHAL_HAVE_DENSITY 1 -- --#undef XCHAL_HAVE_CONST16 --#define XCHAL_HAVE_CONST16 0 -- --#undef XCHAL_HAVE_ABS --#define XCHAL_HAVE_ABS 1 -- --#undef XCHAL_HAVE_ADDX --#define XCHAL_HAVE_ADDX 1 -- --#undef XCHAL_HAVE_L32R --#define XCHAL_HAVE_L32R 1 -- --#undef XSHAL_USE_ABSOLUTE_LITERALS --#define XSHAL_USE_ABSOLUTE_LITERALS 0 -- --#undef XSHAL_HAVE_TEXT_SECTION_LITERALS --#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ -- --#undef XCHAL_HAVE_MAC16 --#define XCHAL_HAVE_MAC16 0 -- --#undef XCHAL_HAVE_MUL16 --#define XCHAL_HAVE_MUL16 1 -- --#undef XCHAL_HAVE_MUL32 --#define XCHAL_HAVE_MUL32 1 -- --#undef XCHAL_HAVE_MUL32_HIGH --#define XCHAL_HAVE_MUL32_HIGH 0 -- --#undef XCHAL_HAVE_DIV32 --#define XCHAL_HAVE_DIV32 1 -- --#undef XCHAL_HAVE_NSA --#define XCHAL_HAVE_NSA 1 -- --#undef XCHAL_HAVE_MINMAX --#define XCHAL_HAVE_MINMAX 1 -- --#undef XCHAL_HAVE_SEXT --#define XCHAL_HAVE_SEXT 1 -- --#undef XCHAL_HAVE_LOOPS --#define XCHAL_HAVE_LOOPS 1 -- --#undef XCHAL_HAVE_THREADPTR --#define XCHAL_HAVE_THREADPTR 1 -- --#undef XCHAL_HAVE_RELEASE_SYNC --#define XCHAL_HAVE_RELEASE_SYNC 1 -- --#undef XCHAL_HAVE_S32C1I --#define XCHAL_HAVE_S32C1I 1 -- --#undef XCHAL_HAVE_BOOLEANS --#define XCHAL_HAVE_BOOLEANS 0 -- --#undef XCHAL_HAVE_FP --#define XCHAL_HAVE_FP 0 -- --#undef XCHAL_HAVE_FP_DIV --#define XCHAL_HAVE_FP_DIV 0 -- --#undef XCHAL_HAVE_FP_RECIP --#define XCHAL_HAVE_FP_RECIP 0 -- --#undef XCHAL_HAVE_FP_SQRT --#define XCHAL_HAVE_FP_SQRT 0 -- --#undef XCHAL_HAVE_FP_RSQRT --#define XCHAL_HAVE_FP_RSQRT 0 -- --#undef XCHAL_HAVE_DFP_accel --#define XCHAL_HAVE_DFP_accel 0 --#undef XCHAL_HAVE_WINDOWED --#define XCHAL_HAVE_WINDOWED 1 -- --#undef XCHAL_NUM_AREGS --#define XCHAL_NUM_AREGS 32 -- --#undef XCHAL_HAVE_WIDE_BRANCHES --#define XCHAL_HAVE_WIDE_BRANCHES 0 -- --#undef XCHAL_HAVE_PREDICTED_BRANCHES --#define XCHAL_HAVE_PREDICTED_BRANCHES 0 -- -- --#undef XCHAL_ICACHE_SIZE --#define XCHAL_ICACHE_SIZE 16384 -- --#undef XCHAL_DCACHE_SIZE --#define XCHAL_DCACHE_SIZE 16384 -- --#undef XCHAL_ICACHE_LINESIZE --#define XCHAL_ICACHE_LINESIZE 32 -- --#undef XCHAL_DCACHE_LINESIZE --#define XCHAL_DCACHE_LINESIZE 32 -- --#undef XCHAL_ICACHE_LINEWIDTH --#define XCHAL_ICACHE_LINEWIDTH 5 -- --#undef XCHAL_DCACHE_LINEWIDTH --#define XCHAL_DCACHE_LINEWIDTH 5 -- --#undef XCHAL_DCACHE_IS_WRITEBACK --#define XCHAL_DCACHE_IS_WRITEBACK 1 -- -- --#undef XCHAL_HAVE_MMU --#define XCHAL_HAVE_MMU 1 -- --#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE --#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 -- -- --#undef XCHAL_HAVE_DEBUG --#define XCHAL_HAVE_DEBUG 1 -- --#undef XCHAL_NUM_IBREAK --#define XCHAL_NUM_IBREAK 2 -- --#undef XCHAL_NUM_DBREAK --#define XCHAL_NUM_DBREAK 2 -- --#undef XCHAL_DEBUGLEVEL --#define XCHAL_DEBUGLEVEL 6 -- -- --#undef XCHAL_MAX_INSTRUCTION_SIZE --#define XCHAL_MAX_INSTRUCTION_SIZE 3 -- --#undef XCHAL_INST_FETCH_WIDTH --#define XCHAL_INST_FETCH_WIDTH 4 -- -- --#undef XSHAL_ABI --#undef XTHAL_ABI_WINDOWED --#undef XTHAL_ABI_CALL0 --#define XSHAL_ABI XTHAL_ABI_WINDOWED --#define XTHAL_ABI_WINDOWED 0 --#define XTHAL_ABI_CALL0 1 -- --#endif /* !XTENSA_CONFIG_H */ -+/* Xtensa configuration settings. -+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 -+ Free Software Foundation, Inc. -+ Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2, or (at your option) -+ any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -+ -+#ifndef XTENSA_CONFIG_H -+#define XTENSA_CONFIG_H -+ -+/* The macros defined here match those with the same names in the Xtensa -+ compile-time HAL (Hardware Abstraction Layer). Please refer to the -+ Xtensa System Software Reference Manual for documentation of these -+ macros. */ -+ -+#undef XCHAL_HAVE_BE -+#define XCHAL_HAVE_BE 0 -+ -+#undef XCHAL_HAVE_DENSITY -+#define XCHAL_HAVE_DENSITY 1 -+ -+#undef XCHAL_HAVE_CONST16 -+#define XCHAL_HAVE_CONST16 0 -+ -+#undef XCHAL_HAVE_ABS -+#define XCHAL_HAVE_ABS 1 -+ -+#undef XCHAL_HAVE_ADDX -+#define XCHAL_HAVE_ADDX 1 -+ -+#undef XCHAL_HAVE_L32R -+#define XCHAL_HAVE_L32R 1 -+ -+#undef XSHAL_USE_ABSOLUTE_LITERALS -+#define XSHAL_USE_ABSOLUTE_LITERALS 0 -+ -+#undef XCHAL_HAVE_MAC16 -+#define XCHAL_HAVE_MAC16 0 -+ -+#undef XCHAL_HAVE_MUL16 -+#define XCHAL_HAVE_MUL16 1 -+ -+#undef XCHAL_HAVE_MUL32 -+#define XCHAL_HAVE_MUL32 1 -+ -+#undef XCHAL_HAVE_MUL32_HIGH -+#define XCHAL_HAVE_MUL32_HIGH 0 -+ -+#undef XCHAL_HAVE_DIV32 -+#define XCHAL_HAVE_DIV32 0 -+ -+#undef XCHAL_HAVE_NSA -+#define XCHAL_HAVE_NSA 1 -+ -+#undef XCHAL_HAVE_MINMAX -+#define XCHAL_HAVE_MINMAX 0 -+ -+#undef XCHAL_HAVE_SEXT -+#define XCHAL_HAVE_SEXT 0 -+ -+#undef XCHAL_HAVE_LOOPS -+#define XCHAL_HAVE_LOOPS 0 -+ -+#undef XCHAL_HAVE_THREADPTR -+#define XCHAL_HAVE_THREADPTR 0 -+ -+#undef XCHAL_HAVE_RELEASE_SYNC -+#define XCHAL_HAVE_RELEASE_SYNC 0 -+ -+#undef XCHAL_HAVE_S32C1I -+#define XCHAL_HAVE_S32C1I 0 -+ -+#undef XCHAL_HAVE_BOOLEANS -+#define XCHAL_HAVE_BOOLEANS 0 -+ -+#undef XCHAL_HAVE_FP -+#define XCHAL_HAVE_FP 0 -+ -+#undef XCHAL_HAVE_FP_DIV -+#define XCHAL_HAVE_FP_DIV 0 -+ -+#undef XCHAL_HAVE_FP_RECIP -+#define XCHAL_HAVE_FP_RECIP 0 -+ -+#undef XCHAL_HAVE_FP_SQRT -+#define XCHAL_HAVE_FP_SQRT 0 -+ -+#undef XCHAL_HAVE_FP_RSQRT -+#define XCHAL_HAVE_FP_RSQRT 0 -+ -+#undef XCHAL_HAVE_DFP_accel -+#define XCHAL_HAVE_DFP_accel 0 -+#undef XCHAL_HAVE_WINDOWED -+#define XCHAL_HAVE_WINDOWED 0 -+ -+#undef XCHAL_NUM_AREGS -+#define XCHAL_NUM_AREGS 16 -+ -+#undef XCHAL_HAVE_WIDE_BRANCHES -+#define XCHAL_HAVE_WIDE_BRANCHES 0 -+ -+#undef XCHAL_HAVE_PREDICTED_BRANCHES -+#define XCHAL_HAVE_PREDICTED_BRANCHES 0 -+ -+ -+#undef XCHAL_ICACHE_SIZE -+#define XCHAL_ICACHE_SIZE 0 -+ -+#undef XCHAL_DCACHE_SIZE -+#define XCHAL_DCACHE_SIZE 0 -+ -+#undef XCHAL_ICACHE_LINESIZE -+#define XCHAL_ICACHE_LINESIZE 16 -+ -+#undef XCHAL_DCACHE_LINESIZE -+#define XCHAL_DCACHE_LINESIZE 16 -+ -+#undef XCHAL_ICACHE_LINEWIDTH -+#define XCHAL_ICACHE_LINEWIDTH 4 -+ -+#undef XCHAL_DCACHE_LINEWIDTH -+#define XCHAL_DCACHE_LINEWIDTH 4 -+ -+#undef XCHAL_DCACHE_IS_WRITEBACK -+#define XCHAL_DCACHE_IS_WRITEBACK 0 -+ -+ -+#undef XCHAL_HAVE_MMU -+#define XCHAL_HAVE_MMU 0 -+ -+ -+#undef XCHAL_HAVE_DEBUG -+#define XCHAL_HAVE_DEBUG 1 -+ -+#undef XCHAL_NUM_IBREAK -+#define XCHAL_NUM_IBREAK 1 -+ -+#undef XCHAL_NUM_DBREAK -+#define XCHAL_NUM_DBREAK 1 -+ -+#undef XCHAL_DEBUGLEVEL -+#define XCHAL_DEBUGLEVEL 2 -+ -+ -+#undef XCHAL_MAX_INSTRUCTION_SIZE -+#define XCHAL_MAX_INSTRUCTION_SIZE 3 -+ -+#undef XCHAL_INST_FETCH_WIDTH -+#define XCHAL_INST_FETCH_WIDTH 4 -+ -+ -+#undef XSHAL_ABI -+#undef XTHAL_ABI_WINDOWED -+#undef XTHAL_ABI_CALL0 -+#define XSHAL_ABI XTHAL_ABI_CALL0 -+#define XTHAL_ABI_WINDOWED 0 -+#define XTHAL_ABI_CALL0 1 -+ -+#endif /* !XTENSA_CONFIG_H */ -diff -urN gdb-7.5.1-orig/readline/support/config.guess gdb-7.5.1/readline/support/config.guess ---- gdb-7.5.1-orig/readline/support/config.guess 2011-05-11 16:38:44.000000000 -0700 -+++ gdb-7.5.1/readline/support/config.guess 2015-08-04 11:34:36.368217000 -0700 -@@ -1,14 +1,12 @@ - #! /bin/sh - # Attempt to guess a canonical system name. --# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, --# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 --# Free Software Foundation, Inc. -+# Copyright 1992-2014 Free Software Foundation, Inc. - --timestamp='2008-03-12' -+timestamp='2014-03-23' - - # This file is free software; you can redistribute it and/or modify it - # under the terms of the GNU General Public License as published by --# the Free Software Foundation; either version 2 of the License, or -+# the Free Software Foundation; either version 3 of the License, or - # (at your option) any later version. - # - # This program is distributed in the hope that it will be useful, but -@@ -17,26 +15,22 @@ - # General Public License for more details. - # - # You should have received a copy of the GNU General Public License --# along with this program; if not, write to the Free Software --# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA --# 02110-1301, USA. -+# along with this program; if not, see . - # - # As a special exception to the GNU General Public License, if you - # distribute this file as part of a program that contains a - # configuration script generated by Autoconf, you may include it under --# the same distribution terms that you use for the rest of that program. -- -- --# Originally written by Per Bothner . --# Please send patches to . Submit a context --# diff and a properly formatted ChangeLog entry. -+# the same distribution terms that you use for the rest of that -+# program. This Exception is an additional permission under section 7 -+# of the GNU General Public License, version 3 ("GPLv3"). -+# -+# Originally written by Per Bothner. - # --# This script attempts to guess a canonical system name similar to --# config.sub. If it succeeds, it prints the system name on stdout, and --# exits with 0. Otherwise, it exits with 1. -+# You can get the latest version of this script from: -+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD - # --# The plan is that this can be called by configure scripts if you --# don't specify an explicit build system type. -+# Please send patches with a ChangeLog entry to config-patches@gnu.org. -+ - - me=`echo "$0" | sed -e 's,.*/,,'` - -@@ -56,8 +50,7 @@ - GNU config.guess ($timestamp) - - Originally written by Per Bothner. --Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, --2002, 2003, 2004, 2005, 2006, 2007, 2008,2009 Free Software Foundation, Inc. -+Copyright 1992-2014 Free Software Foundation, Inc. - - This is free software; see the source for copying conditions. There is NO - warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." -@@ -139,12 +132,33 @@ - UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown - UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown - -+case "${UNAME_SYSTEM}" in -+Linux|GNU|GNU/*) -+ # If the system lacks a compiler, then just pick glibc. -+ # We could probably try harder. -+ LIBC=gnu -+ -+ eval $set_cc_for_build -+ cat <<-EOF > $dummy.c -+ #include -+ #if defined(__UCLIBC__) -+ LIBC=uclibc -+ #elif defined(__dietlibc__) -+ LIBC=dietlibc -+ #else -+ LIBC=gnu -+ #endif -+ EOF -+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'` -+ ;; -+esac -+ - # Note: order is significant - the case branches are not exclusive. - - case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in - *:NetBSD:*:*) - # NetBSD (nbsd) targets should (where applicable) match one or -- # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, -+ # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, - # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently - # switched to ELF, *-*-netbsd* would select the old - # object file format. This provides both forward -@@ -170,7 +184,7 @@ - arm*|i386|m68k|ns32k|sh3*|sparc|vax) - eval $set_cc_for_build - if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ -- | grep __ELF__ >/dev/null -+ | grep -q __ELF__ - then - # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). - # Return netbsd for either. FIX? -@@ -180,7 +194,7 @@ - fi - ;; - *) -- os=netbsd -+ os=netbsd - ;; - esac - # The OS release -@@ -201,6 +215,10 @@ - # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. - echo "${machine}-${os}${release}" - exit ;; -+ *:Bitrig:*:*) -+ UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'` -+ echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE} -+ exit ;; - *:OpenBSD:*:*) - UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` - echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} -@@ -223,7 +241,7 @@ - UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` - ;; - *5.*) -- UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` -+ UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` - ;; - esac - # According to Compaq, /usr/sbin/psrinfo has been available on -@@ -269,7 +287,10 @@ - # A Xn.n version is an unreleased experimental baselevel. - # 1.2 uses "1.2" for uname -r. - echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` -- exit ;; -+ # Reset EXIT trap before exiting to avoid spurious non-zero exit code. -+ exitcode=$? -+ trap '' 0 -+ exit $exitcode ;; - Alpha\ *:Windows_NT*:*) - # How do we know it's Interix rather than the generic POSIX subsystem? - # Should we change UNAME_MACHINE based on the output of uname instead -@@ -295,12 +316,12 @@ - echo s390-ibm-zvmoe - exit ;; - *:OS400:*:*) -- echo powerpc-ibm-os400 -+ echo powerpc-ibm-os400 - exit ;; - arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) - echo arm-acorn-riscix${UNAME_RELEASE} - exit ;; -- arm:riscos:*:*|arm:RISCOS:*:*) -+ arm*:riscos:*:*|arm*:RISCOS:*:*) - echo arm-unknown-riscos - exit ;; - SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) -@@ -324,14 +345,33 @@ - case `/usr/bin/uname -p` in - sparc) echo sparc-icl-nx7; exit ;; - esac ;; -+ s390x:SunOS:*:*) -+ echo ${UNAME_MACHINE}-ibm-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` -+ exit ;; - sun4H:SunOS:5.*:*) - echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit ;; - sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) - echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit ;; -+ i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*) -+ echo i386-pc-auroraux${UNAME_RELEASE} -+ exit ;; - i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) -- echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` -+ eval $set_cc_for_build -+ SUN_ARCH="i386" -+ # If there is a compiler, see if it is configured for 64-bit objects. -+ # Note that the Sun cc does not turn __LP64__ into 1 like gcc does. -+ # This test works for both compilers. -+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then -+ if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \ -+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ -+ grep IS_64BIT_ARCH >/dev/null -+ then -+ SUN_ARCH="x86_64" -+ fi -+ fi -+ echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit ;; - sun4*:SunOS:6*:*) - # According to config.sub, this is the proper way to canonicalize -@@ -375,23 +415,23 @@ - # MiNT. But MiNT is downward compatible to TOS, so this should - # be no problem. - atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) -- echo m68k-atari-mint${UNAME_RELEASE} -+ echo m68k-atari-mint${UNAME_RELEASE} - exit ;; - atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) - echo m68k-atari-mint${UNAME_RELEASE} -- exit ;; -+ exit ;; - *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) -- echo m68k-atari-mint${UNAME_RELEASE} -+ echo m68k-atari-mint${UNAME_RELEASE} - exit ;; - milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) -- echo m68k-milan-mint${UNAME_RELEASE} -- exit ;; -+ echo m68k-milan-mint${UNAME_RELEASE} -+ exit ;; - hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) -- echo m68k-hades-mint${UNAME_RELEASE} -- exit ;; -+ echo m68k-hades-mint${UNAME_RELEASE} -+ exit ;; - *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) -- echo m68k-unknown-mint${UNAME_RELEASE} -- exit ;; -+ echo m68k-unknown-mint${UNAME_RELEASE} -+ exit ;; - m68k:machten:*:*) - echo m68k-apple-machten${UNAME_RELEASE} - exit ;; -@@ -461,8 +501,8 @@ - echo m88k-motorola-sysv3 - exit ;; - AViiON:dgux:*:*) -- # DG/UX returns AViiON for all architectures -- UNAME_PROCESSOR=`/usr/bin/uname -p` -+ # DG/UX returns AViiON for all architectures -+ UNAME_PROCESSOR=`/usr/bin/uname -p` - if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] - then - if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ -@@ -475,7 +515,7 @@ - else - echo i586-dg-dgux${UNAME_RELEASE} - fi -- exit ;; -+ exit ;; - M88*:DolphinOS:*:*) # DolphinOS (SVR3) - echo m88k-dolphin-sysv3 - exit ;; -@@ -532,7 +572,7 @@ - echo rs6000-ibm-aix3.2 - fi - exit ;; -- *:AIX:*:[456]) -+ *:AIX:*:[4567]) - IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` - if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then - IBM_ARCH=rs6000 -@@ -575,52 +615,52 @@ - 9000/[678][0-9][0-9]) - if [ -x /usr/bin/getconf ]; then - sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` -- sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` -- case "${sc_cpu_version}" in -- 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 -- 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 -- 532) # CPU_PA_RISC2_0 -- case "${sc_kernel_bits}" in -- 32) HP_ARCH="hppa2.0n" ;; -- 64) HP_ARCH="hppa2.0w" ;; -+ sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` -+ case "${sc_cpu_version}" in -+ 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 -+ 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 -+ 532) # CPU_PA_RISC2_0 -+ case "${sc_kernel_bits}" in -+ 32) HP_ARCH="hppa2.0n" ;; -+ 64) HP_ARCH="hppa2.0w" ;; - '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 -- esac ;; -- esac -+ esac ;; -+ esac - fi - if [ "${HP_ARCH}" = "" ]; then - eval $set_cc_for_build -- sed 's/^ //' << EOF >$dummy.c -+ sed 's/^ //' << EOF >$dummy.c - -- #define _HPUX_SOURCE -- #include -- #include -- -- int main () -- { -- #if defined(_SC_KERNEL_BITS) -- long bits = sysconf(_SC_KERNEL_BITS); -- #endif -- long cpu = sysconf (_SC_CPU_VERSION); -- -- switch (cpu) -- { -- case CPU_PA_RISC1_0: puts ("hppa1.0"); break; -- case CPU_PA_RISC1_1: puts ("hppa1.1"); break; -- case CPU_PA_RISC2_0: -- #if defined(_SC_KERNEL_BITS) -- switch (bits) -- { -- case 64: puts ("hppa2.0w"); break; -- case 32: puts ("hppa2.0n"); break; -- default: puts ("hppa2.0"); break; -- } break; -- #else /* !defined(_SC_KERNEL_BITS) */ -- puts ("hppa2.0"); break; -- #endif -- default: puts ("hppa1.0"); break; -- } -- exit (0); -- } -+ #define _HPUX_SOURCE -+ #include -+ #include -+ -+ int main () -+ { -+ #if defined(_SC_KERNEL_BITS) -+ long bits = sysconf(_SC_KERNEL_BITS); -+ #endif -+ long cpu = sysconf (_SC_CPU_VERSION); -+ -+ switch (cpu) -+ { -+ case CPU_PA_RISC1_0: puts ("hppa1.0"); break; -+ case CPU_PA_RISC1_1: puts ("hppa1.1"); break; -+ case CPU_PA_RISC2_0: -+ #if defined(_SC_KERNEL_BITS) -+ switch (bits) -+ { -+ case 64: puts ("hppa2.0w"); break; -+ case 32: puts ("hppa2.0n"); break; -+ default: puts ("hppa2.0"); break; -+ } break; -+ #else /* !defined(_SC_KERNEL_BITS) */ -+ puts ("hppa2.0"); break; -+ #endif -+ default: puts ("hppa1.0"); break; -+ } -+ exit (0); -+ } - EOF - (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` - test -z "$HP_ARCH" && HP_ARCH=hppa -@@ -640,7 +680,7 @@ - # => hppa64-hp-hpux11.23 - - if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | -- grep __LP64__ >/dev/null -+ grep -q __LP64__ - then - HP_ARCH="hppa2.0w" - else -@@ -711,22 +751,22 @@ - exit ;; - C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) - echo c1-convex-bsd -- exit ;; -+ exit ;; - C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) - if getsysinfo -f scalar_acc - then echo c32-convex-bsd - else echo c2-convex-bsd - fi -- exit ;; -+ exit ;; - C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) - echo c34-convex-bsd -- exit ;; -+ exit ;; - C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) - echo c38-convex-bsd -- exit ;; -+ exit ;; - C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) - echo c4-convex-bsd -- exit ;; -+ exit ;; - CRAY*Y-MP:*:*:*) - echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit ;; -@@ -750,14 +790,14 @@ - exit ;; - F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) - FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` -- FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` -- FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` -- echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" -- exit ;; -+ FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` -+ FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` -+ echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" -+ exit ;; - 5000:UNIX_System_V:4.*:*) -- FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` -- FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` -- echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" -+ FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` -+ FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` -+ echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" - exit ;; - i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) - echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} -@@ -769,34 +809,39 @@ - echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} - exit ;; - *:FreeBSD:*:*) -- case ${UNAME_MACHINE} in -- pc98) -- echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; -+ UNAME_PROCESSOR=`/usr/bin/uname -p` -+ case ${UNAME_PROCESSOR} in - amd64) - echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - *) -- echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; -+ echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; - esac - exit ;; - i*:CYGWIN*:*) - echo ${UNAME_MACHINE}-pc-cygwin - exit ;; -+ *:MINGW64*:*) -+ echo ${UNAME_MACHINE}-pc-mingw64 -+ exit ;; - *:MINGW*:*) - echo ${UNAME_MACHINE}-pc-mingw32 - exit ;; -+ *:MSYS*:*) -+ echo ${UNAME_MACHINE}-pc-msys -+ exit ;; - i*:windows32*:*) -- # uname -m includes "-pc" on this system. -- echo ${UNAME_MACHINE}-mingw32 -+ # uname -m includes "-pc" on this system. -+ echo ${UNAME_MACHINE}-mingw32 - exit ;; - i*:PW*:*) - echo ${UNAME_MACHINE}-pc-pw32 - exit ;; -- *:Interix*:[3456]*) -- case ${UNAME_MACHINE} in -+ *:Interix*:*) -+ case ${UNAME_MACHINE} in - x86) - echo i586-pc-interix${UNAME_RELEASE} - exit ;; -- EM64T | authenticamd) -+ authenticamd | genuineintel | EM64T) - echo x86_64-unknown-interix${UNAME_RELEASE} - exit ;; - IA64) -@@ -806,6 +851,9 @@ - [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) - echo i${UNAME_MACHINE}-pc-mks - exit ;; -+ 8664:Windows_NT:*) -+ echo x86_64-pc-mks -+ exit ;; - i*:Windows_NT*:* | Pentium*:Windows_NT*:*) - # How do we know it's Interix rather than the generic POSIX subsystem? - # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we -@@ -826,210 +874,157 @@ - exit ;; - *:GNU:*:*) - # the GNU system -- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` -+ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` - exit ;; - *:GNU/*:*:*) - # other systems with GNU libc and userland -- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu -+ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} - exit ;; - i*86:Minix:*:*) - echo ${UNAME_MACHINE}-pc-minix - exit ;; -+ aarch64:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ aarch64_be:Linux:*:*) -+ UNAME_MACHINE=aarch64_be -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ alpha:Linux:*:*) -+ case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in -+ EV5) UNAME_MACHINE=alphaev5 ;; -+ EV56) UNAME_MACHINE=alphaev56 ;; -+ PCA56) UNAME_MACHINE=alphapca56 ;; -+ PCA57) UNAME_MACHINE=alphapca56 ;; -+ EV6) UNAME_MACHINE=alphaev6 ;; -+ EV67) UNAME_MACHINE=alphaev67 ;; -+ EV68*) UNAME_MACHINE=alphaev68 ;; -+ esac -+ objdump --private-headers /bin/sh | grep -q ld.so.1 -+ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ arc:Linux:*:* | arceb:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; - arm*:Linux:*:*) - eval $set_cc_for_build - if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ - | grep -q __ARM_EABI__ - then -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - else -- echo ${UNAME_MACHINE}-unknown-linux-gnueabi -+ if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ -+ | grep -q __ARM_PCS_VFP -+ then -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi -+ else -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf -+ fi - fi - exit ;; - avr32*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - cris:Linux:*:*) -- echo cris-axis-linux-gnu -+ echo ${UNAME_MACHINE}-axis-linux-${LIBC} - exit ;; - crisv32:Linux:*:*) -- echo crisv32-axis-linux-gnu -+ echo ${UNAME_MACHINE}-axis-linux-${LIBC} - exit ;; - frv:Linux:*:*) -- echo frv-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ hexagon:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ i*86:Linux:*:*) -+ echo ${UNAME_MACHINE}-pc-linux-${LIBC} - exit ;; - ia64:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - m32r*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - m68*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; -- mips:Linux:*:*) -- eval $set_cc_for_build -- sed 's/^ //' << EOF >$dummy.c -- #undef CPU -- #undef mips -- #undef mipsel -- #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) -- CPU=mipsel -- #else -- #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) -- CPU=mips -- #else -- CPU= -- #endif -- #endif --EOF -- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' -- /^CPU/{ -- s: ::g -- p -- }'`" -- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } -- ;; -- mips64:Linux:*:*) -+ mips:Linux:*:* | mips64:Linux:*:*) - eval $set_cc_for_build - sed 's/^ //' << EOF >$dummy.c - #undef CPU -- #undef mips64 -- #undef mips64el -+ #undef ${UNAME_MACHINE} -+ #undef ${UNAME_MACHINE}el - #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) -- CPU=mips64el -+ CPU=${UNAME_MACHINE}el - #else - #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) -- CPU=mips64 -+ CPU=${UNAME_MACHINE} - #else - CPU= - #endif - #endif - EOF -- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' -- /^CPU/{ -- s: ::g -- p -- }'`" -- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } -+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` -+ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } - ;; -- or32:Linux:*:*) -- echo or32-unknown-linux-gnu -+ openrisc*:Linux:*:*) -+ echo or1k-unknown-linux-${LIBC} - exit ;; -- ppc:Linux:*:*) -- echo powerpc-unknown-linux-gnu -+ or32:Linux:*:* | or1k*:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; -- ppc64:Linux:*:*) -- echo powerpc64-unknown-linux-gnu -+ padre:Linux:*:*) -+ echo sparc-unknown-linux-${LIBC} - exit ;; -- alpha:Linux:*:*) -- case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in -- EV5) UNAME_MACHINE=alphaev5 ;; -- EV56) UNAME_MACHINE=alphaev56 ;; -- PCA56) UNAME_MACHINE=alphapca56 ;; -- PCA57) UNAME_MACHINE=alphapca56 ;; -- EV6) UNAME_MACHINE=alphaev6 ;; -- EV67) UNAME_MACHINE=alphaev67 ;; -- EV68*) UNAME_MACHINE=alphaev68 ;; -- esac -- objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null -- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi -- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} -+ parisc64:Linux:*:* | hppa64:Linux:*:*) -+ echo hppa64-unknown-linux-${LIBC} - exit ;; - parisc:Linux:*:* | hppa:Linux:*:*) - # Look for CPU level - case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in -- PA7*) echo hppa1.1-unknown-linux-gnu ;; -- PA8*) echo hppa2.0-unknown-linux-gnu ;; -- *) echo hppa-unknown-linux-gnu ;; -+ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; -+ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; -+ *) echo hppa-unknown-linux-${LIBC} ;; - esac - exit ;; -- parisc64:Linux:*:* | hppa64:Linux:*:*) -- echo hppa64-unknown-linux-gnu -+ ppc64:Linux:*:*) -+ echo powerpc64-unknown-linux-${LIBC} -+ exit ;; -+ ppc:Linux:*:*) -+ echo powerpc-unknown-linux-${LIBC} -+ exit ;; -+ ppc64le:Linux:*:*) -+ echo powerpc64le-unknown-linux-${LIBC} -+ exit ;; -+ ppcle:Linux:*:*) -+ echo powerpcle-unknown-linux-${LIBC} - exit ;; - s390:Linux:*:* | s390x:Linux:*:*) -- echo ${UNAME_MACHINE}-ibm-linux -+ echo ${UNAME_MACHINE}-ibm-linux-${LIBC} - exit ;; - sh64*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - sh*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - sparc:Linux:*:* | sparc64:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} -+ exit ;; -+ tile*:Linux:*:*) -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - vax:Linux:*:*) -- echo ${UNAME_MACHINE}-dec-linux-gnu -+ echo ${UNAME_MACHINE}-dec-linux-${LIBC} - exit ;; - x86_64:Linux:*:*) -- echo x86_64-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; - xtensa*:Linux:*:*) -- echo ${UNAME_MACHINE}-unknown-linux-gnu -+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC} - exit ;; -- i*86:Linux:*:*) -- # The BFD linker knows what the default object file format is, so -- # first see if it will tell us. cd to the root directory to prevent -- # problems with other programs or directories called `ld' in the path. -- # Set LC_ALL=C to ensure ld outputs messages in English. -- ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ -- | sed -ne '/supported targets:/!d -- s/[ ][ ]*/ /g -- s/.*supported targets: *// -- s/ .*// -- p'` -- case "$ld_supported_targets" in -- elf32-i386) -- TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" -- ;; -- a.out-i386-linux) -- echo "${UNAME_MACHINE}-pc-linux-gnuaout" -- exit ;; -- coff-i386) -- echo "${UNAME_MACHINE}-pc-linux-gnucoff" -- exit ;; -- "") -- # Either a pre-BFD a.out linker (linux-gnuoldld) or -- # one that does not give us useful --help. -- echo "${UNAME_MACHINE}-pc-linux-gnuoldld" -- exit ;; -- esac -- # Determine whether the default compiler is a.out or elf -- eval $set_cc_for_build -- sed 's/^ //' << EOF >$dummy.c -- #include -- #ifdef __ELF__ -- # ifdef __GLIBC__ -- # if __GLIBC__ >= 2 -- LIBC=gnu -- # else -- LIBC=gnulibc1 -- # endif -- # else -- LIBC=gnulibc1 -- # endif -- #else -- #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) -- LIBC=gnu -- #else -- LIBC=gnuaout -- #endif -- #endif -- #ifdef __dietlibc__ -- LIBC=dietlibc -- #endif --EOF -- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' -- /^LIBC/{ -- s: ::g -- p -- }'`" -- test x"${LIBC}" != x && { -- echo "${UNAME_MACHINE}-pc-linux-${LIBC}" -- exit -- } -- test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; } -- ;; - i*86:DYNIX/ptx:4*:*) - # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. - # earlier versions are messed up and put the nodename in both -@@ -1037,11 +1032,11 @@ - echo i386-sequent-sysv4 - exit ;; - i*86:UNIX_SV:4.2MP:2.*) -- # Unixware is an offshoot of SVR4, but it has its own version -- # number series starting with 2... -- # I am not positive that other SVR4 systems won't match this, -+ # Unixware is an offshoot of SVR4, but it has its own version -+ # number series starting with 2... -+ # I am not positive that other SVR4 systems won't match this, - # I just have to hope. -- rms. -- # Use sysv4.2uw... so that sysv4* matches it. -+ # Use sysv4.2uw... so that sysv4* matches it. - echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} - exit ;; - i*86:OS/2:*:*) -@@ -1058,7 +1053,7 @@ - i*86:syllable:*:*) - echo ${UNAME_MACHINE}-pc-syllable - exit ;; -- i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) -+ i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*) - echo i386-unknown-lynxos${UNAME_RELEASE} - exit ;; - i*86:*DOS:*:*) -@@ -1073,7 +1068,7 @@ - fi - exit ;; - i*86:*:5:[678]*) -- # UnixWare 7.x, OpenUNIX and OpenServer 6. -+ # UnixWare 7.x, OpenUNIX and OpenServer 6. - case `/bin/uname -X | grep "^Machine"` in - *486*) UNAME_MACHINE=i486 ;; - *Pentium) UNAME_MACHINE=i586 ;; -@@ -1101,10 +1096,13 @@ - exit ;; - pc:*:*:*) - # Left here for compatibility: -- # uname -m prints for DJGPP always 'pc', but it prints nothing about -- # the processor, so we play safe by assuming i386. -- echo i386-pc-msdosdjgpp -- exit ;; -+ # uname -m prints for DJGPP always 'pc', but it prints nothing about -+ # the processor, so we play safe by assuming i586. -+ # Note: whatever this is, it MUST be the same as what config.sub -+ # prints for the "djgpp" host, or else GDB configury will decide that -+ # this is a cross-build. -+ echo i586-pc-msdosdjgpp -+ exit ;; - Intel:Mach:3*:*) - echo i386-pc-mach3 - exit ;; -@@ -1139,8 +1137,18 @@ - /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ - && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; - 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) -- /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ -- && { echo i486-ncr-sysv4; exit; } ;; -+ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ -+ && { echo i486-ncr-sysv4; exit; } ;; -+ NCR*:*:4.2:* | MPRAS*:*:4.2:*) -+ OS_REL='.3' -+ test -r /etc/.relid \ -+ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` -+ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ -+ && { echo i486-ncr-sysv4.3${OS_REL}; exit; } -+ /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ -+ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } -+ /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \ -+ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; - m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) - echo m68k-unknown-lynxos${UNAME_RELEASE} - exit ;; -@@ -1153,7 +1161,7 @@ - rs6000:LynxOS:2.*:*) - echo rs6000-unknown-lynxos${UNAME_RELEASE} - exit ;; -- PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) -+ PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*) - echo powerpc-unknown-lynxos${UNAME_RELEASE} - exit ;; - SM[BE]S:UNIX_SV:*:*) -@@ -1173,10 +1181,10 @@ - echo ns32k-sni-sysv - fi - exit ;; -- PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort -- # says -- echo i586-unisys-sysv4 -- exit ;; -+ PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort -+ # says -+ echo i586-unisys-sysv4 -+ exit ;; - *:UNIX_System_V:4*:FTX*) - # From Gerald Hewes . - # How about differentiating between stratus architectures? -djm -@@ -1202,11 +1210,11 @@ - exit ;; - R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) - if [ -d /usr/nec ]; then -- echo mips-nec-sysv${UNAME_RELEASE} -+ echo mips-nec-sysv${UNAME_RELEASE} - else -- echo mips-unknown-sysv${UNAME_RELEASE} -+ echo mips-unknown-sysv${UNAME_RELEASE} - fi -- exit ;; -+ exit ;; - BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. - echo powerpc-be-beos - exit ;; -@@ -1219,6 +1227,9 @@ - BePC:Haiku:*:*) # Haiku running on Intel PC compatible. - echo i586-pc-haiku - exit ;; -+ x86_64:Haiku:*:*) -+ echo x86_64-unknown-haiku -+ exit ;; - SX-4:SUPER-UX:*:*) - echo sx4-nec-superux${UNAME_RELEASE} - exit ;; -@@ -1245,9 +1256,31 @@ - exit ;; - *:Darwin:*:*) - UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown -- case $UNAME_PROCESSOR in -- unknown) UNAME_PROCESSOR=powerpc ;; -- esac -+ eval $set_cc_for_build -+ if test "$UNAME_PROCESSOR" = unknown ; then -+ UNAME_PROCESSOR=powerpc -+ fi -+ if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then -+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then -+ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ -+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ -+ grep IS_64BIT_ARCH >/dev/null -+ then -+ case $UNAME_PROCESSOR in -+ i386) UNAME_PROCESSOR=x86_64 ;; -+ powerpc) UNAME_PROCESSOR=powerpc64 ;; -+ esac -+ fi -+ fi -+ elif test "$UNAME_PROCESSOR" = i386 ; then -+ # Avoid executing cc on OS X 10.9, as it ships with a stub -+ # that puts up a graphical alert prompting to install -+ # developer tools. Any system running Mac OS X 10.7 or -+ # later (Darwin 11 and later) is required to have a 64-bit -+ # processor. This is not true of the ARM version of Darwin -+ # that Apple uses in portable devices. -+ UNAME_PROCESSOR=x86_64 -+ fi - echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} - exit ;; - *:procnto*:*:* | *:QNX:[0123456789]*:*) -@@ -1261,7 +1294,10 @@ - *:QNX:*:4*) - echo i386-pc-qnx - exit ;; -- NSE-?:NONSTOP_KERNEL:*:*) -+ NEO-?:NONSTOP_KERNEL:*:*) -+ echo neo-tandem-nsk${UNAME_RELEASE} -+ exit ;; -+ NSE-*:NONSTOP_KERNEL:*:*) - echo nse-tandem-nsk${UNAME_RELEASE} - exit ;; - NSR-?:NONSTOP_KERNEL:*:*) -@@ -1306,13 +1342,13 @@ - echo pdp10-unknown-its - exit ;; - SEI:*:*:SEIUX) -- echo mips-sei-seiux${UNAME_RELEASE} -+ echo mips-sei-seiux${UNAME_RELEASE} - exit ;; - *:DragonFly:*:*) - echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` - exit ;; - *:*VMS:*:*) -- UNAME_MACHINE=`(uname -p) 2>/dev/null` -+ UNAME_MACHINE=`(uname -p) 2>/dev/null` - case "${UNAME_MACHINE}" in - A*) echo alpha-dec-vms ; exit ;; - I*) echo ia64-dec-vms ; exit ;; -@@ -1327,158 +1363,13 @@ - i*86:rdos:*:*) - echo ${UNAME_MACHINE}-pc-rdos - exit ;; --esac -- --#echo '(No uname command or uname output not recognized.)' 1>&2 --#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 -- --eval $set_cc_for_build --cat >$dummy.c < --# include --#endif --main () --{ --#if defined (sony) --#if defined (MIPSEB) -- /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, -- I don't know.... */ -- printf ("mips-sony-bsd\n"); exit (0); --#else --#include -- printf ("m68k-sony-newsos%s\n", --#ifdef NEWSOS4 -- "4" --#else -- "" --#endif -- ); exit (0); --#endif --#endif -- --#if defined (__arm) && defined (__acorn) && defined (__unix) -- printf ("arm-acorn-riscix\n"); exit (0); --#endif -- --#if defined (hp300) && !defined (hpux) -- printf ("m68k-hp-bsd\n"); exit (0); --#endif -- --#if defined (NeXT) --#if !defined (__ARCHITECTURE__) --#define __ARCHITECTURE__ "m68k" --#endif -- int version; -- version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; -- if (version < 4) -- printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); -- else -- printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); -- exit (0); --#endif -- --#if defined (MULTIMAX) || defined (n16) --#if defined (UMAXV) -- printf ("ns32k-encore-sysv\n"); exit (0); --#else --#if defined (CMU) -- printf ("ns32k-encore-mach\n"); exit (0); --#else -- printf ("ns32k-encore-bsd\n"); exit (0); --#endif --#endif --#endif -- --#if defined (__386BSD__) -- printf ("i386-pc-bsd\n"); exit (0); --#endif -- --#if defined (sequent) --#if defined (i386) -- printf ("i386-sequent-dynix\n"); exit (0); --#endif --#if defined (ns32000) -- printf ("ns32k-sequent-dynix\n"); exit (0); --#endif --#endif -- --#if defined (_SEQUENT_) -- struct utsname un; -- -- uname(&un); -- -- if (strncmp(un.version, "V2", 2) == 0) { -- printf ("i386-sequent-ptx2\n"); exit (0); -- } -- if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ -- printf ("i386-sequent-ptx1\n"); exit (0); -- } -- printf ("i386-sequent-ptx\n"); exit (0); -- --#endif -- --#if defined (vax) --# if !defined (ultrix) --# include --# if defined (BSD) --# if BSD == 43 -- printf ("vax-dec-bsd4.3\n"); exit (0); --# else --# if BSD == 199006 -- printf ("vax-dec-bsd4.3reno\n"); exit (0); --# else -- printf ("vax-dec-bsd\n"); exit (0); --# endif --# endif --# else -- printf ("vax-dec-bsd\n"); exit (0); --# endif --# else -- printf ("vax-dec-ultrix\n"); exit (0); --# endif --#endif -- --#if defined (alliant) && defined (i860) -- printf ("i860-alliant-bsd\n"); exit (0); --#endif -- -- exit (1); --} --EOF -- --$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && -- { echo "$SYSTEM_NAME"; exit; } -- --# Apollos put the system type in the environment. -- --test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } -- --# Convex versions that predate uname can use getsysinfo(1) -- --if [ -x /usr/convex/getsysinfo ] --then -- case `getsysinfo -f cpu_type` in -- c1*) -- echo c1-convex-bsd -+ i*86:AROS:*:*) -+ echo ${UNAME_MACHINE}-pc-aros - exit ;; -- c2*) -- if getsysinfo -f scalar_acc -- then echo c32-convex-bsd -- else echo c2-convex-bsd -- fi -+ x86_64:VMkernel:*:*) -+ echo ${UNAME_MACHINE}-unknown-esx - exit ;; -- c34*) -- echo c34-convex-bsd -- exit ;; -- c38*) -- echo c38-convex-bsd -- exit ;; -- c4*) -- echo c4-convex-bsd -- exit ;; -- esac --fi -+esac - - cat >&2 <. - # - # As a special exception to the GNU General Public License, if you - # distribute this file as part of a program that contains a - # configuration script generated by Autoconf, you may include it under --# the same distribution terms that you use for the rest of that program. -+# the same distribution terms that you use for the rest of that -+# program. This Exception is an additional permission under section 7 -+# of the GNU General Public License, version 3 ("GPLv3"). - - --# Please send patches to . Submit a context --# diff and a properly formatted ChangeLog entry. -+# Please send patches with a ChangeLog entry to config-patches@gnu.org. - # - # Configuration subroutine to validate and canonicalize a configuration type. - # Supply the specified configuration type as an argument. - # If it is invalid, we print an error message on stderr and exit with code 1. - # Otherwise, we print the canonical config type on stdout and succeed. - -+# You can get the latest version of this script from: -+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD -+ - # This file is supposed to be the same for all GNU packages - # and recognize all the CPU types, system types and aliases - # that are meaningful with *any* GNU software. -@@ -72,8 +68,7 @@ - version="\ - GNU config.sub ($timestamp) - --Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, --2002, 2003, 2004, 2005, 2006, 2007, 2008,2009 Free Software Foundation, Inc. -+Copyright 1992-2014 Free Software Foundation, Inc. - - This is free software; see the source for copying conditions. There is NO - warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." -@@ -120,12 +115,18 @@ - # Here we must recognize all the valid KERNEL-OS combinations. - maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` - case $maybe_os in -- nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ -- uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \ -+ nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ -+ linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ -+ knetbsd*-gnu* | netbsd*-gnu* | \ -+ kopensolaris*-gnu* | \ - storm-chaos* | os2-emx* | rtmk-nova*) - os=-$maybe_os - basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` - ;; -+ android-linux) -+ os=-linux-android -+ basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown -+ ;; - *) - basic_machine=`echo $1 | sed 's/-[^-]*$//'` - if [ $basic_machine != $1 ] -@@ -148,10 +149,13 @@ - -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ - -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ - -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ -- -apple | -axis | -knuth | -cray) -+ -apple | -axis | -knuth | -cray | -microblaze*) - os= - basic_machine=$1 - ;; -+ -bluegene*) -+ os=-cnk -+ ;; - -sim | -cisco | -oki | -wec | -winbond) - os= - basic_machine=$1 -@@ -166,10 +170,10 @@ - os=-chorusos - basic_machine=$1 - ;; -- -chorusrdb) -- os=-chorusrdb -+ -chorusrdb) -+ os=-chorusrdb - basic_machine=$1 -- ;; -+ ;; - -hiux*) - os=-hiuxwe2 - ;; -@@ -214,6 +218,12 @@ - -isc*) - basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` - ;; -+ -lynx*178) -+ os=-lynxos178 -+ ;; -+ -lynx*5) -+ os=-lynxos5 -+ ;; - -lynx*) - os=-lynxos - ;; -@@ -238,19 +248,28 @@ - # Some are omitted here because they have special meanings below. - 1750a | 580 \ - | a29k \ -+ | aarch64 | aarch64_be \ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -+ | arc | arceb \ -+ | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \ -+ | avr | avr32 \ -+ | be32 | be64 \ - | bfin \ -- | c4x | clipper \ -+ | c4x | c8051 | clipper \ - | d10v | d30v | dlx | dsp16xx \ -+ | epiphany \ - | fido | fr30 | frv \ - | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ -+ | hexagon \ - | i370 | i860 | i960 | ia64 \ - | ip2k | iq2000 \ -+ | k1om \ -+ | le32 | le64 \ -+ | lm32 \ - | m32c | m32r | m32rle | m68000 | m68k | m88k \ -- | maxq | mb | microblaze | mcore | mep | metag \ -+ | maxq | mb | microblaze | microblazeel | mcore | mep | metag \ - | mips | mipsbe | mipseb | mipsel | mipsle \ - | mips16 \ - | mips64 | mips64el \ -@@ -264,35 +283,50 @@ - | mips64vr5900 | mips64vr5900el \ - | mipsisa32 | mipsisa32el \ - | mipsisa32r2 | mipsisa32r2el \ -+ | mipsisa32r6 | mipsisa32r6el \ - | mipsisa64 | mipsisa64el \ - | mipsisa64r2 | mipsisa64r2el \ -+ | mipsisa64r6 | mipsisa64r6el \ - | mipsisa64sb1 | mipsisa64sb1el \ - | mipsisa64sr71k | mipsisa64sr71kel \ -+ | mipsr5900 | mipsr5900el \ - | mipstx39 | mipstx39el \ - | mn10200 | mn10300 \ -+ | moxie \ - | mt \ - | msp430 \ -- | nios | nios2 \ -+ | nds32 | nds32le | nds32be \ -+ | nios | nios2 | nios2eb | nios2el \ - | ns16k | ns32k \ -- | or32 \ -+ | open8 | or1k | or1knd | or32 \ - | pdp10 | pdp11 | pj | pjl \ -- | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ -+ | powerpc | powerpc64 | powerpc64le | powerpcle \ - | pyramid \ -+ | rl78 | rx \ - | score \ -- | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ -+ | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ - | sh64 | sh64le \ - | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ - | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ -- | spu | strongarm \ -- | tahoe | thumb | tic4x | tic80 | tron \ -- | v850 | v850e \ -+ | spu \ -+ | tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ -+ | ubicom32 \ -+ | v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \ - | we32k \ -- | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ -- | z8k) -+ | x86 | xc16x | xstormy16 | xtensa \ -+ | z8k | z80) - basic_machine=$basic_machine-unknown - ;; -- m6811 | m68hc11 | m6812 | m68hc12) -- # Motorola 68HC11/12. -+ c54x) -+ basic_machine=tic54x-unknown -+ ;; -+ c55x) -+ basic_machine=tic55x-unknown -+ ;; -+ c6x) -+ basic_machine=tic6x-unknown -+ ;; -+ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip) - basic_machine=$basic_machine-unknown - os=-none - ;; -@@ -302,6 +336,21 @@ - basic_machine=mt-unknown - ;; - -+ strongarm | thumb | xscale) -+ basic_machine=arm-unknown -+ ;; -+ xgate) -+ basic_machine=$basic_machine-unknown -+ os=-none -+ ;; -+ xscaleeb) -+ basic_machine=armeb-unknown -+ ;; -+ -+ xscaleel) -+ basic_machine=armel-unknown -+ ;; -+ - # We use `pc' rather than `unknown' - # because (1) that's what they normally are, and - # (2) the word "unknown" tends to confuse beginning users. -@@ -316,24 +365,31 @@ - # Recognize the basic CPU types with company name. - 580-* \ - | a29k-* \ -+ | aarch64-* | aarch64_be-* \ - | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ - | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ -- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ -+ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \ - | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ - | avr-* | avr32-* \ -+ | be32-* | be64-* \ - | bfin-* | bs2000-* \ -- | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ -- | clipper-* | craynv-* | cydra-* \ -+ | c[123]* | c30-* | [cjt]90-* | c4x-* \ -+ | c8051-* | clipper-* | craynv-* | cydra-* \ - | d10v-* | d30v-* | dlx-* \ - | elxsi-* \ - | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ - | h8300-* | h8500-* \ - | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ -+ | hexagon-* \ - | i*86-* | i860-* | i960-* | ia64-* \ - | ip2k-* | iq2000-* \ -+ | k1om-* \ -+ | le32-* | le64-* \ -+ | lm32-* \ - | m32c-* | m32r-* | m32rle-* \ - | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ - | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \ -+ | microblaze-* | microblazeel-* \ - | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ - | mips16-* \ - | mips64-* | mips64el-* \ -@@ -347,35 +403,44 @@ - | mips64vr5900-* | mips64vr5900el-* \ - | mipsisa32-* | mipsisa32el-* \ - | mipsisa32r2-* | mipsisa32r2el-* \ -+ | mipsisa32r6-* | mipsisa32r6el-* \ - | mipsisa64-* | mipsisa64el-* \ - | mipsisa64r2-* | mipsisa64r2el-* \ -+ | mipsisa64r6-* | mipsisa64r6el-* \ - | mipsisa64sb1-* | mipsisa64sb1el-* \ - | mipsisa64sr71k-* | mipsisa64sr71kel-* \ -+ | mipsr5900-* | mipsr5900el-* \ - | mipstx39-* | mipstx39el-* \ - | mmix-* \ - | mt-* \ - | msp430-* \ -- | nios-* | nios2-* \ -+ | nds32-* | nds32le-* | nds32be-* \ -+ | nios-* | nios2-* | nios2eb-* | nios2el-* \ - | none-* | np1-* | ns16k-* | ns32k-* \ -+ | open8-* \ -+ | or1k*-* \ - | orion-* \ - | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ -- | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ -+ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ - | pyramid-* \ -- | romp-* | rs6000-* \ -- | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ -+ | rl78-* | romp-* | rs6000-* | rx-* \ -+ | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ - | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ - | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ - | sparclite-* \ -- | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \ -- | tahoe-* | thumb-* \ -- | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \ -+ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \ -+ | tahoe-* \ -+ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ -+ | tile*-* \ - | tron-* \ -- | v850-* | v850e-* | vax-* \ -+ | ubicom32-* \ -+ | v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \ -+ | vax-* \ - | we32k-* \ -- | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ -+ | x86-* | x86_64-* | xc16x-* | xps100-* \ - | xstormy16-* | xtensa*-* \ - | ymp-* \ -- | z8k-*) -+ | z8k-* | z80-*) - ;; - # Recognize the basic CPU types without company name, with glob match. - xtensa*) -@@ -397,7 +462,7 @@ - basic_machine=a29k-amd - os=-udi - ;; -- abacus) -+ abacus) - basic_machine=abacus-unknown - ;; - adobe68k) -@@ -443,6 +508,10 @@ - basic_machine=m68k-apollo - os=-bsd - ;; -+ aros) -+ basic_machine=i386-pc -+ os=-aros -+ ;; - aux) - basic_machine=m68k-apple - os=-aux -@@ -459,10 +528,27 @@ - basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'` - os=-linux - ;; -+ bluegene*) -+ basic_machine=powerpc-ibm -+ os=-cnk -+ ;; -+ c54x-*) -+ basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'` -+ ;; -+ c55x-*) -+ basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'` -+ ;; -+ c6x-*) -+ basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'` -+ ;; - c90) - basic_machine=c90-cray - os=-unicos - ;; -+ cegcc) -+ basic_machine=arm-unknown -+ os=-cegcc -+ ;; - convex-c1) - basic_machine=c1-convex - os=-bsd -@@ -491,7 +577,7 @@ - basic_machine=craynv-cray - os=-unicosmp - ;; -- cr16) -+ cr16 | cr16-*) - basic_machine=cr16-unknown - os=-elf - ;; -@@ -530,6 +616,10 @@ - basic_machine=m88k-motorola - os=-sysv3 - ;; -+ dicos) -+ basic_machine=i686-pc -+ os=-dicos -+ ;; - djgpp) - basic_machine=i586-pc - os=-msdosdjgpp -@@ -645,7 +735,6 @@ - i370-ibm* | ibm*) - basic_machine=i370-ibm - ;; --# I'm not sure what "Sysv32" means. Should this be sysv3.2? - i*86v32) - basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` - os=-sysv32 -@@ -703,8 +792,15 @@ - basic_machine=ns32k-utek - os=-sysv - ;; -+ microblaze*) -+ basic_machine=microblaze-xilinx -+ ;; -+ mingw64) -+ basic_machine=x86_64-pc -+ os=-mingw64 -+ ;; - mingw32) -- basic_machine=i386-pc -+ basic_machine=i686-pc - os=-mingw32 - ;; - mingw32ce) -@@ -739,10 +835,18 @@ - ms1-*) - basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` - ;; -+ msys) -+ basic_machine=i686-pc -+ os=-msys -+ ;; - mvs) - basic_machine=i370-ibm - os=-mvs - ;; -+ nacl) -+ basic_machine=le32-unknown -+ os=-nacl -+ ;; - ncr3000) - basic_machine=i486-ncr - os=-sysv4 -@@ -807,6 +911,9 @@ - np1) - basic_machine=np1-gould - ;; -+ neo-tandem) -+ basic_machine=neo-tandem -+ ;; - nse-tandem) - basic_machine=nse-tandem - ;; -@@ -892,9 +999,10 @@ - ;; - power) basic_machine=power-ibm - ;; -- ppc) basic_machine=powerpc-unknown -+ ppc | ppcbe) basic_machine=powerpc-unknown - ;; -- ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` -+ ppc-* | ppcbe-*) -+ basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` - ;; - ppcle | powerpclittle | ppc-le | powerpc-little) - basic_machine=powerpcle-unknown -@@ -919,7 +1027,11 @@ - basic_machine=i586-unknown - os=-pw32 - ;; -- rdos) -+ rdos | rdos64) -+ basic_machine=x86_64-pc -+ os=-rdos -+ ;; -+ rdos32) - basic_machine=i386-pc - os=-rdos - ;; -@@ -988,6 +1100,9 @@ - basic_machine=i860-stratus - os=-sysv4 - ;; -+ strongarm-* | thumb-*) -+ basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'` -+ ;; - sun2) - basic_machine=m68000-sun - ;; -@@ -1044,20 +1159,8 @@ - basic_machine=t90-cray - os=-unicos - ;; -- tic54x | c54x*) -- basic_machine=tic54x-unknown -- os=-coff -- ;; -- tic55x | c55x*) -- basic_machine=tic55x-unknown -- os=-coff -- ;; -- tic6x | c6x*) -- basic_machine=tic6x-unknown -- os=-coff -- ;; - tile*) -- basic_machine=tile-unknown -+ basic_machine=$basic_machine-unknown - os=-linux-gnu - ;; - tx39) -@@ -1127,6 +1230,9 @@ - xps | xps100) - basic_machine=xps100-honeywell - ;; -+ xscale-* | xscalee[bl]-*) -+ basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'` -+ ;; - ymp) - basic_machine=ymp-cray - os=-unicos -@@ -1135,6 +1241,10 @@ - basic_machine=z8k-unknown - os=-sim - ;; -+ z80-*-coff) -+ basic_machine=z80-unknown -+ os=-sim -+ ;; - none) - basic_machine=none-none - os=-none -@@ -1173,7 +1283,7 @@ - we32k) - basic_machine=we32k-att - ;; -- sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele) -+ sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele) - basic_machine=sh-unknown - ;; - sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) -@@ -1220,9 +1330,12 @@ - if [ x"$os" != x"" ] - then - case $os in -- # First match some system type aliases -- # that might get confused with valid system types. -+ # First match some system type aliases -+ # that might get confused with valid system types. - # -solaris* is a basic system type, with this one exception. -+ -auroraux) -+ os=-auroraux -+ ;; - -solaris1 | -solaris1.*) - os=`echo $os | sed -e 's|solaris1|sunos4|'` - ;; -@@ -1243,21 +1356,23 @@ - # Each alternative MUST END IN A *, to match a version number. - # -sysv* is not here because it comes later, after sysvr4. - -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ -- | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ -- | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ -+ | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\ -+ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \ -+ | -sym* | -kopensolaris* | -plan9* \ - | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ -- | -aos* \ -+ | -aos* | -aros* \ - | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ - | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ - | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ -- | -openbsd* | -solidbsd* \ -+ | -bitrig* | -openbsd* | -solidbsd* \ - | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ - | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ - | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ - | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ -- | -chorusos* | -chorusrdb* \ -- | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ -- | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \ -+ | -chorusos* | -chorusrdb* | -cegcc* \ -+ | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ -+ | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ -+ | -linux-newlib* | -linux-musl* | -linux-uclibc* \ - | -uxpv* | -beos* | -mpeix* | -udk* \ - | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ - | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ -@@ -1265,7 +1380,7 @@ - | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ - | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ - | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ -- | -skyos* | -haiku* | -rdos* | -toppers* | -drops*) -+ | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*) - # Remember, each alternative MUST END IN *, to match a version number. - ;; - -qnx*) -@@ -1304,7 +1419,7 @@ - -opened*) - os=-openedition - ;; -- -os400*) -+ -os400*) - os=-os400 - ;; - -wince*) -@@ -1353,7 +1468,7 @@ - -sinix*) - os=-sysv4 - ;; -- -tpf*) -+ -tpf*) - os=-tpf - ;; - -triton*) -@@ -1389,12 +1504,14 @@ - -aros*) - os=-aros - ;; -- -kaos*) -- os=-kaos -- ;; - -zvmoe) - os=-zvmoe - ;; -+ -dicos*) -+ os=-dicos -+ ;; -+ -nacl*) -+ ;; - -none) - ;; - *) -@@ -1417,10 +1534,10 @@ - # system, and we'll never get to this point. - - case $basic_machine in -- score-*) -+ score-*) - os=-elf - ;; -- spu-*) -+ spu-*) - os=-elf - ;; - *-acorn) -@@ -1432,8 +1549,23 @@ - arm*-semi) - os=-aout - ;; -- c4x-* | tic4x-*) -- os=-coff -+ c4x-* | tic4x-*) -+ os=-coff -+ ;; -+ c8051-*) -+ os=-elf -+ ;; -+ hexagon-*) -+ os=-elf -+ ;; -+ tic54x-*) -+ os=-coff -+ ;; -+ tic55x-*) -+ os=-coff -+ ;; -+ tic6x-*) -+ os=-coff - ;; - # This must come before the *-dec entry. - pdp10-*) -@@ -1453,14 +1585,11 @@ - ;; - m68000-sun) - os=-sunos3 -- # This also exists in the configure program, but was not the -- # default. -- # os=-sunos4 - ;; - m68*-cisco) - os=-aout - ;; -- mep-*) -+ mep-*) - os=-elf - ;; - mips*-cisco) -@@ -1487,7 +1616,7 @@ - *-ibm) - os=-aix - ;; -- *-knuth) -+ *-knuth) - os=-mmixware - ;; - *-wec) -@@ -1592,7 +1721,7 @@ - -sunos*) - vendor=sun - ;; -- -aix*) -+ -cnk*|-aix*) - vendor=ibm - ;; - -beos*) -diff -urN gdb-7.5.1-orig/readline/util.c gdb-7.5.1/readline/util.c ---- gdb-7.5.1-orig/readline/util.c 2011-05-11 16:38:39.000000000 -0700 -+++ gdb-7.5.1/readline/util.c 2015-08-18 16:53:44.102940800 -0700 -@@ -389,7 +389,7 @@ - break; - s2++; - } -- while (--count != 0) -+ while (--count != 0); - - return (0); - } diff --git a/1000-mforce-l32.patch b/1000-mforce-l32.patch new file mode 100644 index 000000000..a8859d81c --- /dev/null +++ b/1000-mforce-l32.patch @@ -0,0 +1,253 @@ +https://github.com/jcmvbkbc/gcc-xtensa/commit/6b0c9f92fb8e11c6be098febb4f502f6af37cd35.patch + +From 6b0c9f92fb8e11c6be098febb4f502f6af37cd35 Mon Sep 17 00:00:00 2001 +From: Max Filippov +Date: Thu, 11 Jun 2015 17:56:57 +0300 +Subject: [PATCH] WIP: xtensa: add -mforce-l32 + +Signed-off-by: Max Filippov +--- + gcc/config/xtensa/constraints.md | 15 ++++++++++++ + gcc/config/xtensa/xtensa.c | 53 +++++++++++++++++++++++++++++++++++++++- + gcc/config/xtensa/xtensa.md | 49 ++++++++++++++++++++----------------- + gcc/config/xtensa/xtensa.opt | 4 +++ + 4 files changed, 98 insertions(+), 23 deletions(-) + +diff --git a/gcc/config/xtensa/constraints.md b/gcc/config/xtensa/constraints.md +index 30f4c1f..5fd9337 100644 +--- a/gcc/config/xtensa/constraints.md ++++ b/gcc/config/xtensa/constraints.md +@@ -137,3 +137,18 @@ + (and (match_code "reg") + (match_test "reload_in_progress + && REGNO (op) >= FIRST_PSEUDO_REGISTER")))) ++ ++(define_constraint "Y" ++ "Memory that is not in a literal pool." ++ (ior (and (and (match_code "mem") ++ (match_test "! constantpool_mem_p (op)")) ++ (match_test "!TARGET_FORCE_L32")) ++ (and (match_code "reg") ++ (match_test "reload_in_progress ++ && REGNO (op) >= FIRST_PSEUDO_REGISTER")))) ++ ++(define_constraint "Z" ++ "Memory that is not in a literal pool." ++ (and (and (match_code "mem") ++ (match_test "! constantpool_mem_p (op)")) ++ (match_test "TARGET_FORCE_L32"))) +diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c +index d8c5b41..559b181 100644 +--- a/gcc/config/xtensa/xtensa.c ++++ b/gcc/config/xtensa/xtensa.c +@@ -1824,7 +1824,8 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict) + return true; + + /* Check for "register + offset" addressing. */ +- if (GET_CODE (addr) == PLUS) ++ if (GET_CODE (addr) == PLUS && ++ (!TARGET_FORCE_L32 || (mode != HImode && mode != QImode))) + { + rtx xplus0 = XEXP (addr, 0); + rtx xplus1 = XEXP (addr, 1); +@@ -2308,6 +2309,8 @@ printx (FILE *file, signed int val) + fprintf (file, "0x%x", val); + } + ++static void ++output_address_base (FILE *file, rtx addr); + + void + print_operand (FILE *file, rtx x, int letter) +@@ -2317,6 +2320,13 @@ print_operand (FILE *file, rtx x, int letter) + + switch (letter) + { ++ case 'B': ++ if (GET_CODE (x) == MEM) ++ output_address_base (file, XEXP (x, 0)); ++ else ++ output_operand_lossage ("invalid %%B value"); ++ break; ++ + case 'D': + if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) + fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]); +@@ -2450,6 +2460,47 @@ print_operand (FILE *file, rtx x, int letter) + } + } + ++static void ++output_address_base (FILE *file, rtx addr) ++{ ++ switch (GET_CODE (addr)) ++ { ++ default: ++ fatal_insn ("invalid address", addr); ++ break; ++ ++ case REG: ++ fprintf (file, "%s", reg_names [REGNO (addr)]); ++ break; ++ ++ case PLUS: ++ { ++ rtx reg = (rtx)0; ++ rtx offset = (rtx)0; ++ rtx arg0 = XEXP (addr, 0); ++ rtx arg1 = XEXP (addr, 1); ++ ++ if (GET_CODE (arg0) == REG) ++ { ++ reg = arg0; ++ offset = arg1; ++ } ++ else if (GET_CODE (arg1) == REG) ++ { ++ reg = arg1; ++ offset = arg0; ++ } ++ else ++ fatal_insn ("no register in address", addr); ++ ++ if (CONSTANT_P (offset)) ++ fprintf (file, "%s", reg_names [REGNO (reg)]); ++ else ++ fatal_insn ("address offset not a constant", addr); ++ } ++ break; ++ } ++} + + /* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand that is a memory +diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md +index a577aa3..f56c45e 100644 +--- a/gcc/config/xtensa/xtensa.md ++++ b/gcc/config/xtensa/xtensa.md +@@ -532,26 +532,28 @@ + ;; Zero-extend instructions. + + (define_insn "zero_extendhisi2" +- [(set (match_operand:SI 0 "register_operand" "=a,a") +- (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))] ++ [(set (match_operand:SI 0 "register_operand" "=a,a,a") ++ (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,Y,Z")))] + "" + "@ + extui\t%0, %1, 0, 16 +- l16ui\t%0, %1" +- [(set_attr "type" "arith,load") ++ l16ui\t%0, %1 ++ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 16" ++ [(set_attr "type" "arith,load,load") + (set_attr "mode" "SI") +- (set_attr "length" "3,3")]) ++ (set_attr "length" "3,3,18")]) + + (define_insn "zero_extendqisi2" +- [(set (match_operand:SI 0 "register_operand" "=a,a") +- (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))] ++ [(set (match_operand:SI 0 "register_operand" "=a,a,a") ++ (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,Y,Z")))] + "" + "@ + extui\t%0, %1, 0, 8 +- l8ui\t%0, %1" +- [(set_attr "type" "arith,load") ++ l8ui\t%0, %1 ++ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 8" ++ [(set_attr "type" "arith,load,load") + (set_attr "mode" "SI") +- (set_attr "length" "3,3")]) ++ (set_attr "length" "3,3,18")]) + + + ;; Sign-extend instructions. +@@ -569,15 +571,16 @@ + }) + + (define_insn "extendhisi2_internal" +- [(set (match_operand:SI 0 "register_operand" "=B,a") +- (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))] ++ [(set (match_operand:SI 0 "register_operand" "=B,a,a") ++ (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,r,Y")))] + "" + "@ + sext\t%0, %1, 15 ++ slli\t%0, %1, 16 ; srai\t%0, %0, 16 + l16si\t%0, %1" +- [(set_attr "type" "arith,load") ++ [(set_attr "type" "arith,arith,load") + (set_attr "mode" "SI") +- (set_attr "length" "3,3")]) ++ (set_attr "length" "3,6,3")]) + + (define_expand "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") +@@ -796,8 +799,8 @@ + }) + + (define_insn "movhi_internal" +- [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A") +- (match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))] ++ [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A") ++ (match_operand:HI 1 "move_operand" "M,d,r,I,Y,Z,r,*A,*r"))] + "xtensa_valid_move (HImode, operands)" + "@ + movi.n\t%0, %x1 +@@ -805,12 +808,13 @@ + mov\t%0, %1 + movi\t%0, %x1 + %v1l16ui\t%0, %1 ++ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; %v1l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 16 + %v0s16i\t%1, %0 + rsr\t%0, ACCLO + wsr\t%1, ACCLO" +- [(set_attr "type" "move,move,move,move,load,store,rsr,wsr") ++ [(set_attr "type" "move,move,move,move,load,load,store,rsr,wsr") + (set_attr "mode" "HI") +- (set_attr "length" "2,2,3,3,3,3,3,3")]) ++ (set_attr "length" "2,2,3,3,3,18,3,3,3")]) + + ;; 8-bit Integer moves + +@@ -824,8 +828,8 @@ + }) + + (define_insn "movqi_internal" +- [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A") +- (match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))] ++ [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A") ++ (match_operand:QI 1 "move_operand" "M,d,r,I,Y,Z,r,*A,*r"))] + "xtensa_valid_move (QImode, operands)" + "@ + movi.n\t%0, %x1 +@@ -833,12 +837,13 @@ + mov\t%0, %1 + movi\t%0, %x1 + %v1l8ui\t%0, %1 ++ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; %v1l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 8 + %v0s8i\t%1, %0 + rsr\t%0, ACCLO + wsr\t%1, ACCLO" +- [(set_attr "type" "move,move,move,move,load,store,rsr,wsr") ++ [(set_attr "type" "move,move,move,move,load,load,store,rsr,wsr") + (set_attr "mode" "QI") +- (set_attr "length" "2,2,3,3,3,3,3,3")]) ++ (set_attr "length" "2,2,3,3,3,18,3,3,3")]) + + ;; Sub-word reloads from the constant pool. + +diff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt +index 2fd6cee..02020d2 100644 +--- a/gcc/config/xtensa/xtensa.opt ++++ b/gcc/config/xtensa/xtensa.opt +@@ -41,3 +41,7 @@ Intersperse literal pools with code in the text section + mserialize-volatile + Target Report Mask(SERIALIZE_VOLATILE) + -mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions ++ ++mforce-l32 ++Target Report Mask(FORCE_L32) ++Use l32i to access 1- and 2-byte quantities in memory instead of l8ui/l16ui diff --git a/Makefile b/Makefile index acaa2fb97..72ba0bd55 100644 --- a/Makefile +++ b/Makefile @@ -1,12 +1,14 @@ TOP = $(PWD) TOOLCHAIN = $(TOP)/xtensa-lx106-elf -VENDOR_SDK = 1.5.2 +VENDOR_SDK = 2.0.0 UNZIP = unzip -q -o VENDOR_SDK_ZIP = $(VENDOR_SDK_ZIP_$(VENDOR_SDK)) VENDOR_SDK_DIR = $(VENDOR_SDK_DIR_$(VENDOR_SDK)) +VENDOR_SDK_ZIP_2.0.0 = ESP8266_NONOS_SDK_V2.0.0_16_07_19.zip +VENDOR_SDK_DIR_2.0.0 = ESP8266_NONOS_SDK VENDOR_SDK_ZIP_1.5.2 = ESP8266_NONOS_SDK_V1.5.2_16_01_29.zip VENDOR_SDK_DIR_1.5.2 = esp_iot_sdk_v1.5.2 VENDOR_SDK_ZIP_1.5.0 = esp_iot_sdk_v1.5.0_15_11_27.zip @@ -51,7 +53,7 @@ STANDALONE = y .PHONY: crosstool-NG toolchain libhal sdk LIBHAL := $(TOOLCHAIN)/xtensa-lx106-elf/sysroot/usr/lib/libhal.a -LIBGCC := $(TOOLCHAIN)/lib/gcc/xtensa-lx106-elf/4.8.2/libgcc.a +LIBGCC := $(TOOLCHAIN)/lib/gcc/xtensa-lx106-elf/4.8.5/libgcc.a all: esptool standalone sdk .sdk_patch $(LIBHAL) $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc @echo @@ -82,6 +84,11 @@ esptool: toolchain done @touch $@ +.sdk_patch_2.0.0: + echo -e "#undef ESP_SDK_VERSION\n#define ESP_SDK_VERSION 010502" >>$(VENDOR_SDK_DIR)/include/esp_sdk_ver.h + patch -N -d $(VENDOR_SDK_DIR_2.0.0) -p1 < c_types-c99_sdk_2.patch + @touch $@ + .sdk_patch_1.5.2: echo -e "#undef ESP_SDK_VERSION\n#define ESP_SDK_VERSION 010502" >>$(VENDOR_SDK_DIR)/include/esp_sdk_ver.h patch -N -d $(VENDOR_SDK_DIR_1.5.2) -p1 < c_types-c99.patch @@ -226,6 +233,9 @@ $(VENDOR_SDK_DIR)/.dir: $(VENDOR_SDK_ZIP) -mv License $(VENDOR_SDK_DIR) touch $@ +ESP8266_NONOS_SDK_V2.0.0_16_07_19.zip: + wget --content-disposition "http://bbs.espressif.com/download/file.php?id=1613" + ESP8266_NONOS_SDK_V1.5.2_16_01_29.zip: wget --content-disposition "http://bbs.espressif.com/download/file.php?id=1079" @@ -304,6 +314,7 @@ _libhal: toolchain: $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc .patch_libgcc $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc: crosstool-NG/ct-ng + cp -f 1000-mforce-l32.patch crosstool-NG/local-patches/gcc/4.8.5/ make -C crosstool-NG -f ../Makefile _toolchain .patch_libgcc: $(TOOLCHAIN)/bin/xtensa-lx106-elf-gcc @@ -318,7 +329,6 @@ _toolchain: sed -r -i s%CT_INSTALL_DIR_RO=y%"#"CT_INSTALL_DIR_RO=y% .config cat ../crosstool-config-overrides >> .config rm -f local-patches/gdb/7.5.1/* - cp ../0000-gdb-7.5.1-sysprogs.patch local-patches/gdb/7.5.1 ./ct-ng build diff --git a/c_types-c99_sdk_2.patch b/c_types-c99_sdk_2.patch new file mode 100644 index 000000000..6691130a3 --- /dev/null +++ b/c_types-c99_sdk_2.patch @@ -0,0 +1,34 @@ +--- ESP8266_NONOS_SDK/include/c_types.h.orig 2016-07-18 15:16:07.000000000 +0100 ++++ ESP8266_NONOS_SDK/include/c_types.h 2016-08-10 00:36:51.216294997 +0100 +@@ -6,17 +6,13 @@ + #ifndef _C_TYPES_H_ + #define _C_TYPES_H_ + +-typedef unsigned char uint8_t; ++#include ++#include ++ + typedef signed char sint8_t; +-typedef signed char int8_t; +-typedef unsigned short uint16_t; + typedef signed short sint16_t; +-typedef signed short int16_t; +-typedef unsigned int uint32_t; + typedef signed long sint32_t; +-typedef signed int int32_t; + typedef signed long long sint64_t; +-typedef unsigned long long uint64_t; + typedef unsigned long long u_int64_t; + typedef float real32_t; + typedef double real64_t; +@@ -82,10 +78,7 @@ + #define STORE_ATTR __attribute__((aligned(4))) + + #ifndef __cplusplus +-typedef unsigned char bool; + #define BOOL bool +-#define true (1) +-#define false (0) + #define TRUE true + #define FALSE false + diff --git a/crosstool-NG b/crosstool-NG index feb1fb829..ecfc19a59 160000 --- a/crosstool-NG +++ b/crosstool-NG @@ -1 +1 @@ -Subproject commit feb1fb829d5cb4f8739e488cbd2f0b72304705bb +Subproject commit ecfc19a597d76c0eea65148b08d7ccb505cdcac6 diff --git a/esptool b/esptool index 765cf23f8..4deca7033 160000 --- a/esptool +++ b/esptool @@ -1 +1 @@ -Subproject commit 765cf23f878a522db6bc34854d4a14bbae470ff6 +Subproject commit 4deca7033e17d9b8d3b947a2d8f7ec3700d7d276 diff --git a/lx106-hal b/lx106-hal index ecdc98953..e4bcc63c9 160000 --- a/lx106-hal +++ b/lx106-hal @@ -1 +1 @@ -Subproject commit ecdc98953f2fc5058a79168528387cd14b287636 +Subproject commit e4bcc63c9c016e4f8848e7e8f512438ca857531d From 2b6acd168c7794e9050aafaf63cc089d26570f58 Mon Sep 17 00:00:00 2001 From: Marko Mikulicic Date: Mon, 19 Sep 2016 17:07:56 +0200 Subject: [PATCH 09/10] Update to latest available SDK --- Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 72ba0bd55..2c32b44c0 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,8 @@ UNZIP = unzip -q -o VENDOR_SDK_ZIP = $(VENDOR_SDK_ZIP_$(VENDOR_SDK)) VENDOR_SDK_DIR = $(VENDOR_SDK_DIR_$(VENDOR_SDK)) -VENDOR_SDK_ZIP_2.0.0 = ESP8266_NONOS_SDK_V2.0.0_16_07_19.zip +VENDOR_SDK_ZIP_2.0.0 = ESP8266_NONOS_SDK_V2.0.0_16_08_10.zip +VENDOR_SDK_ZIP_2.0.0dead1 = ESP8266_NONOS_SDK_V2.0.0_16_07_19.zip VENDOR_SDK_DIR_2.0.0 = ESP8266_NONOS_SDK VENDOR_SDK_ZIP_1.5.2 = ESP8266_NONOS_SDK_V1.5.2_16_01_29.zip VENDOR_SDK_DIR_1.5.2 = esp_iot_sdk_v1.5.2 @@ -233,6 +234,9 @@ $(VENDOR_SDK_DIR)/.dir: $(VENDOR_SDK_ZIP) -mv License $(VENDOR_SDK_DIR) touch $@ +ESP8266_NONOS_SDK_V2.0.0_16_08_10.zip: + wget --content-disposition "http://bbs.espressif.com/download/file.php?id=1690" + ESP8266_NONOS_SDK_V2.0.0_16_07_19.zip: wget --content-disposition "http://bbs.espressif.com/download/file.php?id=1613" From 3ba2b5a505dadadbf6c045a609c5b1115fc14f0a Mon Sep 17 00:00:00 2001 From: Deomid Ryabkov Date: Thu, 16 Feb 2017 12:32:14 +0800 Subject: [PATCH 10/10] Disable some functions that can be found in ROM --- 9001-newlib-disable-rom-funcs.patch | 170 ++++++++++++++++++++++++++++ 9001-newlib-strcmp-literals.patch | 22 ---- 9002-libgcc-disable-rom-funcs.patch | 63 +++++++++++ Makefile | 1 + 4 files changed, 234 insertions(+), 22 deletions(-) create mode 100644 9001-newlib-disable-rom-funcs.patch delete mode 100644 9001-newlib-strcmp-literals.patch create mode 100644 9002-libgcc-disable-rom-funcs.patch diff --git a/9001-newlib-disable-rom-funcs.patch b/9001-newlib-disable-rom-funcs.patch new file mode 100644 index 000000000..b63d68ad8 --- /dev/null +++ b/9001-newlib-disable-rom-funcs.patch @@ -0,0 +1,170 @@ +diff -ru a/newlib/libc/machine/xtensa/memcpy.S b/newlib/libc/machine/xtensa/memcpy.S +--- a/newlib/libc/machine/xtensa/memcpy.S 2015-08-25 09:37:13.871717025 +0800 ++++ b/newlib/libc/machine/xtensa/memcpy.S 2015-08-25 10:00:03.000000000 +0800 +@@ -1,3 +1,5 @@ ++/* esp8266 has this function in rom */ ++#if 1 + /* ANSI C standard library function memcpy. + + Copyright (c) 2002-2008 Tensilica Inc. +@@ -287,3 +289,4 @@ + .end schedule + + .size memcpy, . - memcpy ++#endif +diff -ru a/newlib/libc/machine/xtensa/memset.S b/newlib/libc/machine/xtensa/memset.S +--- a/newlib/libc/machine/xtensa/memset.S 2015-08-25 09:37:13.855716648 +0800 ++++ b/newlib/libc/machine/xtensa/memset.S 2015-08-25 09:59:51.000000000 +0800 +@@ -1,3 +1,5 @@ ++/* esp8266 has this function in rom */ ++#if 0 + /* ANSI C standard library function memset. + + Copyright (c) 2001-2008 Tensilica Inc. +@@ -168,3 +170,4 @@ + .end schedule + + .size memset, . - memset ++#endif +diff -ru a/newlib/libc/machine/xtensa/strcmp.S b/newlib/libc/machine/xtensa/strcmp.S +--- a/newlib/libc/machine/xtensa/strcmp.S 2015-08-25 09:37:13.871717025 +0800 ++++ b/newlib/libc/machine/xtensa/strcmp.S 2015-08-25 09:58:38.000000000 +0800 +@@ -1,3 +1,5 @@ ++/* esp8266 has this function in rom */ ++#if 0 + /* ANSI C standard library function strcmp. + + Copyright (c) 2001-20012 Tensilica Inc. +@@ -776,3 +778,4 @@ + #endif /* FLIX3*/ + + .size strcmp, . - strcmp ++#endif +diff -ru a/newlib/libc/machine/xtensa/strcpy.S b/newlib/libc/machine/xtensa/strcpy.S +--- a/newlib/libc/machine/xtensa/strcpy.S 2015-08-25 09:37:13.855716648 +0800 ++++ b/newlib/libc/machine/xtensa/strcpy.S 2015-08-25 09:59:08.000000000 +0800 +@@ -1,3 +1,5 @@ ++/* esp8266 has this function in rom */ ++#if 0 + /* ANSI C standard library function strcpy. + + Copyright (c) 2001-2008 Tensilica Inc. +@@ -233,3 +235,4 @@ + .end schedule + + .size strcpy, . - strcpy ++#endif +diff -ru a/newlib/libc/machine/xtensa/strlen.S b/newlib/libc/machine/xtensa/strlen.S +--- a/newlib/libc/machine/xtensa/strlen.S 2015-08-25 09:37:13.871717025 +0800 ++++ b/newlib/libc/machine/xtensa/strlen.S 2015-08-25 09:59:22.000000000 +0800 +@@ -1,3 +1,5 @@ ++/* esp8266 has this function in rom */ ++#if 0 + /* ANSI C standard library function strlen. + + Copyright (c) 2001-2008 Tensilica Inc. +@@ -113,3 +115,4 @@ + .end schedule + + .size strlen, . - strlen ++#endif +diff -ru a/newlib/libc/machine/xtensa/strncpy.S b/newlib/libc/machine/xtensa/strncpy.S +--- a/newlib/libc/machine/xtensa/strncpy.S 2015-08-25 09:37:13.859716742 +0800 ++++ b/newlib/libc/machine/xtensa/strncpy.S 2015-08-25 09:59:37.000000000 +0800 +@@ -1,3 +1,5 @@ ++/* esp8266 has this function in rom */ ++#if 0 + /* ANSI C standard library function strncpy. + + Copyright (c) 2001-2008 Tensilica Inc. +@@ -256,3 +258,4 @@ + .end schedule + + .size strncpy, . - strncpy ++#endif +diff -ru a/newlib/libc/string/bzero.c b/newlib/libc/string/bzero.c +--- a/newlib/libc/string/bzero.c 2015-08-25 09:37:10.851645991 +0800 ++++ b/newlib/libc/string/bzero.c 2015-08-25 09:56:18.000000000 +0800 +@@ -32,6 +32,8 @@ + + #include + ++/* esp8266 has this function in rom */ ++#if 0 + _VOID + _DEFUN (bzero, (b, length), + void *b _AND +@@ -41,3 +43,4 @@ + while (length--) + *ptr++ = 0; + } ++#endif +diff -ru a/newlib/libc/string/memcmp.c b/newlib/libc/string/memcmp.c +--- a/newlib/libc/string/memcmp.c 2015-08-25 09:37:10.859646179 +0800 ++++ b/newlib/libc/string/memcmp.c 2015-08-25 09:57:13.000000000 +0800 +@@ -49,6 +49,8 @@ + /* Threshhold for punting to the byte copier. */ + #define TOO_SMALL(LEN) ((LEN) < LBLOCKSIZE) + ++/* esp8266 has this function in rom */ ++#if 0 + int + _DEFUN (memcmp, (m1, m2, n), + _CONST _PTR m1 _AND +@@ -110,4 +112,5 @@ + return 0; + #endif /* not PREFER_SIZE_OVER_SPEED */ + } ++#endif + +diff -ru a/newlib/libc/string/memmove.c b/newlib/libc/string/memmove.c +--- a/newlib/libc/string/memmove.c 2015-08-25 09:37:10.855646086 +0800 ++++ b/newlib/libc/string/memmove.c 2015-08-25 09:56:46.000000000 +0800 +@@ -53,6 +53,8 @@ + /* Threshhold for punting to the byte copier. */ + #define TOO_SMALL(LEN) ((LEN) < BIGBLOCKSIZE) + ++/* esp8266 has this function in rom */ ++#if 0 + /*SUPPRESS 20*/ + _PTR + _DEFUN (memmove, (dst_void, src_void, length), +@@ -140,3 +142,4 @@ + return dst_void; + #endif /* not PREFER_SIZE_OVER_SPEED */ + } ++#endif +diff -ru a/newlib/libc/string/strncmp.c b/newlib/libc/string/strncmp.c +--- a/newlib/libc/string/strncmp.c 2015-08-25 09:37:10.851645991 +0800 ++++ b/newlib/libc/string/strncmp.c 2015-08-25 09:55:31.000000000 +0800 +@@ -58,6 +58,8 @@ + #error long int is not a 32bit or 64bit byte + #endif + ++/* esp8266 has this function in rom */ ++#if 0 + int + _DEFUN (strncmp, (s1, s2, n), + _CONST char *s1 _AND +@@ -120,3 +122,4 @@ + return (*(unsigned char *) s1) - (*(unsigned char *) s2); + #endif /* not PREFER_SIZE_OVER_SPEED */ + } ++#endif +diff -ru a/newlib/libc/string/strstr.c b/newlib/libc/string/strstr.c +--- a/newlib/libc/string/strstr.c 2015-08-25 09:37:10.859646179 +0800 ++++ b/newlib/libc/string/strstr.c 2015-08-25 09:55:56.000000000 +0800 +@@ -44,6 +44,8 @@ + # include "str-two-way.h" + #endif + ++/* esp8266 has this function in rom */ ++#if 0 + char * + _DEFUN (strstr, (searchee, lookfor), + _CONST char *searchee _AND +@@ -119,3 +121,4 @@ + (const unsigned char *) lookfor, needle_len); + #endif /* compilation for speed */ + } ++#endif diff --git a/9001-newlib-strcmp-literals.patch b/9001-newlib-strcmp-literals.patch deleted file mode 100644 index 2a2299cf4..000000000 --- a/9001-newlib-strcmp-literals.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/newlib/libc/machine/xtensa/strcmp.S 2015-11-12 16:23:00.623220071 +0000 -+++ b/newlib/libc/machine/xtensa/strcmp.S 2015-11-12 18:00:14.995375550 +0000 -@@ -26,6 +26,8 @@ - #define MASK4 0x40404040 - - -+ .align 4 -+ .literal_position - #if XCHAL_HAVE_L32R - .literal .Lmask0, MASK0 - .literal .Lmask1, MASK1 -@@ -33,10 +35,6 @@ - .literal .Lmask3, MASK3 - .literal .Lmask4, MASK4 - #endif /* XCHAL_HAVE_L32R */ -- -- .text -- .align 4 -- .literal_position - .global strcmp - .type strcmp, @function - strcmp: diff --git a/9002-libgcc-disable-rom-funcs.patch b/9002-libgcc-disable-rom-funcs.patch new file mode 100644 index 000000000..0bf9aff73 --- /dev/null +++ b/9002-libgcc-disable-rom-funcs.patch @@ -0,0 +1,63 @@ +diff -ru a/libgcc/config/xtensa/t-xtensa b/libgcc/config/xtensa/t-xtensa +--- a/libgcc/config/xtensa/t-xtensa 2015-08-25 10:24:19.439057512 +0800 ++++ b/libgcc/config/xtensa/t-xtensa 2015-08-25 10:26:34.462308416 +0800 +@@ -1,13 +1,12 @@ + LIB1ASMSRC = xtensa/lib1funcs.S +-LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 _udivsi3 _umodsi3 \ +- _umulsidi3 _clz _clzsi2 _ctzsi2 _ffssi2 \ ++LIB1ASMFUNCS = _mulsi3 _modsi3 \ ++ _clz _clzsi2 _ctzsi2 _ffssi2 \ + _ashldi3 _ashrdi3 _lshrdi3 \ +- _negsf2 _addsubsf3 _mulsf3 _divsf3 _cmpsf2 _fixsfsi _fixsfdi \ +- _fixunssfsi _fixunssfdi _floatsisf _floatunsisf \ ++ _negsf2 _mulsf3 _divsf3 _cmpsf2 _fixsfsi _fixsfdi \ ++ _fixunssfdi \ + _floatdisf _floatundisf \ +- _negdf2 _addsubdf3 _muldf3 _divdf3 _cmpdf2 _fixdfsi _fixdfdi \ +- _fixunsdfsi _fixunsdfdi _floatsidf _floatunsidf \ +- _floatdidf _floatundidf \ +- _truncdfsf2 _extendsfdf2 ++ _negdf2 _cmpdf2 _fixdfdi \ ++ _fixunsdfdi \ ++ _floatdidf _floatundidf + + LIB2ADD = $(srcdir)/config/xtensa/lib2funcs.S +diff -ru a/libgcc/Makefile.in b/libgcc/Makefile.in +--- a/libgcc/Makefile.in 2015-08-25 10:24:19.427057223 +0800 ++++ b/libgcc/Makefile.in 2015-08-25 10:27:39.511874029 +0800 +@@ -245,7 +245,7 @@ + + # These might cause a divide overflow trap and so are compiled with + # unwinder info. +-LIB2_DIVMOD_FUNCS = _divdi3 _moddi3 _udivdi3 _umoddi3 _udiv_w_sdiv _udivmoddi4 ++LIB2_DIVMOD_FUNCS = _moddi3 _udiv_w_sdiv _udivmoddi4 + + # List of extra C and assembler files to add to static and shared libgcc2. + # Assembler files should have names ending in `.S'. +@@ -401,7 +401,7 @@ + LIB2ADDEHSHARED += $(srcdir)/emutls.c + + # Library members defined in libgcc2.c. +-lib2funcs = _muldi3 _negdi2 _lshrdi3 _ashldi3 _ashrdi3 _cmpdi2 _ucmpdi2 \ ++lib2funcs = _negdi2 _lshrdi3 _ashldi3 _ashrdi3 _cmpdi2 _ucmpdi2 \ + _clear_cache _trampoline __main _absvsi2 \ + _absvdi2 _addvsi3 _addvdi3 _subvsi3 _subvdi3 _mulvsi3 _mulvdi3 \ + _negvsi2 _negvdi2 _ctors _ffssi2 _ffsdi2 _clz _clzsi2 _clzdi2 \ +@@ -412,7 +412,7 @@ + + # The floating-point conversion routines that involve a single-word integer. + # XX stands for the integer mode. +-swfloatfuncs = $(patsubst %,_fixuns%XX,sf df xf) ++swfloatfuncs = $(patsubst %,_fixuns%XX,xf) + + # Likewise double-word routines. + dwfloatfuncs = $(patsubst %,_fix%XX,sf df xf tf) \ +@@ -427,7 +427,7 @@ + + # These might cause a divide overflow trap and so are compiled with + # unwinder info. +-LIB2_DIVMOD_FUNCS = _divdi3 _moddi3 _udivdi3 _umoddi3 _udiv_w_sdiv _udivmoddi4 ++LIB2_DIVMOD_FUNCS = _moddi3 _udiv_w_sdiv _udivmoddi4 + + # Remove any objects from lib2funcs and LIB2_DIVMOD_FUNCS that are + # defined as optimized assembly code in LIB1ASMFUNCS or as C code diff --git a/Makefile b/Makefile index 2c32b44c0..b4f9e842b 100644 --- a/Makefile +++ b/Makefile @@ -340,6 +340,7 @@ crosstool-NG: crosstool-NG/ct-ng crosstool-NG/ct-ng: crosstool-NG/bootstrap cp *-newlib-*.patch crosstool-NG/local-patches/newlib/2.0.0 + cp *-libgcc-*.patch crosstool-NG/local-patches/gcc/4.8.5 make -C crosstool-NG -f ../Makefile _ct-ng _ct-ng: