battleship.xml

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE document SYSTEM "file:///C:/Xilinx/14.3/ISE_DS/ISE/xbr/data/xmlReportxbr.dtd">
<document><ascFile>battleship.rpt</ascFile><devFile>C:/Xilinx/14.3/ISE_DS/ISE/xbr/data/xc2c64a.chp</devFile><mfdFile>battleship.mfd</mfdFile><htmlFile logic_legend="logiclegend.htm" logo="coolrunnerII_logo.jpg" pin_legend="pinlegend.htm"/><header date=" 6- 7-2015" design="battleship" device="XC2C64A" eqnType="1" pkg="VQ44" speed="-7" status="1" statusStr="Successful" swVersion="P.40xd" time="  9:17PM" version="1.0"/><inputs id="col0" userloc="P18"/><inputs id="col1" userloc="P19"/><inputs id="col2" userloc="P20"/><inputs id="count0" userloc="P21"/><inputs id="count1" userloc="P22"/><inputs id="count2" userloc="P23"/><inputs id="row2" userloc="P14"/><inputs id="row1" userloc="P13"/><inputs id="row0" userloc="P12"/><pin id="FB1_MC1_PIN38" pinnum="38"/><pin id="FB1_MC2_PIN37" pinnum="37"/><pin id="FB1_MC3_PIN36" iostd="LVCMOS18" pinnum="36" signal="outG0_SPECSIG" use="O"/><pin id="FB1_MC9_PIN34" iostd="LVCMOS18" pinnum="34" signal="outG1_SPECSIG" use="O"/><pin id="FB1_MC10_PIN33" iostd="LVCMOS18" pinnum="33" signal="outG2_SPECSIG" use="O"/><pin id="FB1_MC11_PIN32" iostd="LVCMOS18" pinnum="32" signal="outG3_SPECSIG" use="O"/><pin id="FB1_MC12_PIN31" iostd="LVCMOS18" pinnum="31" signal="outG4_SPECSIG" use="O"/><pin id="FB1_MC13_PIN30" pinnum="30"/><pin id="FB2_MC1_PIN39" pinnum="39"/><pin id="FB2_MC2_PIN40" pinnum="40"/><pin id="FB2_MC5_PIN41" pinnum="41"/><pin id="FB2_MC6_PIN42" iostd="LVCMOS18" pinnum="42" signal="outR7_SPECSIG" use="O"/><pin id="FB2_MC7_PIN43" iostd="LVCMOS18" pinnum="43" signal="outR6_SPECSIG" use="O"/><pin id="FB2_MC8_PIN44" iostd="LVCMOS18" pinnum="44" signal="outR5_SPECSIG" use="O"/><pin id="FB2_MC10_PIN1" iostd="LVCMOS18" pinnum="1" signal="outR4_SPECSIG" use="O"/><pin id="FB2_MC12_PIN2" iostd="LVCMOS18" pinnum="2" signal="outR3_SPECSIG" use="O"/><pin id="FB2_MC13_PIN3" iostd="LVCMOS18" pinnum="3" signal="outR2_SPECSIG" use="O"/><pin id="FB3_MC1_PIN29" iostd="LVCMOS18" pinnum="29" signal="outG5_SPECSIG" use="O"/><pin id="FB3_MC2_PIN28" iostd="LVCMOS18" pinnum="28" signal="outG6_SPECSIG" use="O"/><pin id="FB3_MC3_PIN27" iostd="LVCMOS18" pinnum="27" signal="outG7_SPECSIG" use="O"/><pin id="FB3_MC6_PIN23" iostd="LVCMOS18" iostyle="KPR" pinnum="23" signal="count2" use="I"/><pin id="FB3_MC10_PIN22" iostd="LVCMOS18" iostyle="KPR" pinnum="22" signal="count1" use="I"/><pin id="FB3_MC11_PIN21" iostd="LVCMOS18" iostyle="KPR" pinnum="21" signal="count0" use="I"/><pin id="FB3_MC12_PIN20" iostd="LVCMOS18" iostyle="KPR" pinnum="20" signal="col2" use="I"/><pin id="FB3_MC14_PIN19" iostd="LVCMOS18" iostyle="KPR" pinnum="19" signal="col1" use="I"/><pin id="FB3_MC15_PIN18" iostd="LVCMOS18" iostyle="KPR" pinnum="18" signal="col0" use="I"/><pin id="FB4_MC1_PIN5" iostd="LVCMOS18" pinnum="5" signal="outR1_SPECSIG" use="O"/><pin id="FB4_MC2_PIN6" iostd="LVCMOS18" pinnum="6" signal="outR0_SPECSIG" use="O"/><pin id="FB4_MC7_PIN8" pinnum="8"/><pin id="FB4_MC11_PIN12" iostd="LVCMOS18" iostyle="KPR" pinnum="12" signal="row0" use="I"/><pin id="FB4_MC13_PIN13" iostd="LVCMOS18" iostyle="KPR" pinnum="13" signal="row1" use="I"/><pin id="FB4_MC14_PIN14" iostd="LVCMOS18" iostyle="KPR" pinnum="14" signal="row2" use="I"/><pin id="FB4_MC15_PIN16" pinnum="16"/><pin id="FB_PIN35" pinnum="35" use="VCCAUX"/><pin id="FB_PIN7" pinnum="7" use="VCCIO-1.8"/><pin id="FB_PIN15" pinnum="15" use="VCC"/><pin id="FB_PIN26" pinnum="26" use="VCCIO-1.8"/><fblock id="FB1" pinUse="5"><macrocell id="FB1_MC1" pin="FB1_MC1_PIN38"/><macrocell id="FB1_MC2" pin="FB1_MC2_PIN37"/><macrocell id="FB1_MC3" pin="FB1_MC3_PIN36" sigUse="4" signal="outG0_SPECSIG"><eq_pterm ptindx="FB1_16"/></macrocell><macrocell id="FB1_MC4"/><macrocell id="FB1_MC5"/><macrocell id="FB1_MC6"/><macrocell id="FB1_MC7"/><macrocell id="FB1_MC8"/><macrocell id="FB1_MC9" pin="FB1_MC9_PIN34" sigUse="4" signal="outG1_SPECSIG"><eq_pterm ptindx="FB1_34"/></macrocell><macrocell id="FB1_MC10" pin="FB1_MC10_PIN33" sigUse="4" signal="outG2_SPECSIG"><eq_pterm ptindx="FB1_37"/></macrocell><macrocell id="FB1_MC11" pin="FB1_MC11_PIN32" sigUse="4" signal="outG3_SPECSIG"><eq_pterm ptindx="FB1_40"/></macrocell><macrocell id="FB1_MC12" pin="FB1_MC12_PIN31" sigUse="4" signal="outG4_SPECSIG"><eq_pterm ptindx="FB1_43"/></macrocell><macrocell id="FB1_MC13" pin="FB1_MC13_PIN30"/><macrocell id="FB1_MC14"/><macrocell id="FB1_MC15"/><macrocell id="FB1_MC16" sigUse="6" signal="N_PZ_25"><eq_pterm ptindx="FB1_1"/><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_3"/><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_5"/><eq_pterm ptindx="FB1_4"/></macrocell><fbinput id="FB1_I1" signal="N_PZ_25"/><fbinput id="FB1_I2" signal="col0"/><fbinput id="FB1_I3" signal="col1"/><fbinput id="FB1_I4" signal="col2"/><fbinput id="FB1_I5" signal="count0"/><fbinput id="FB1_I6" signal="count1"/><fbinput id="FB1_I7" signal="count2"/><fbinput id="FB1_I8" signal="row0"/><fbinput id="FB1_I9" signal="row1"/><fbinput id="FB1_I10" signal="row2"/><PAL><pterm id="FB1_0"><signal id="col0" negated="ON"/><signal id="count0"/></pterm><pterm id="FB1_1"><signal id="col0"/><signal id="count0" negated="ON"/></pterm><pterm id="FB1_2"><signal id="col1" negated="ON"/><signal id="count1"/></pterm><pterm id="FB1_3"><signal id="col1"/><signal id="count1" negated="ON"/></pterm><pterm id="FB1_4"><signal id="col2" negated="ON"/><signal id="count2"/></pterm><pterm id="FB1_5"><signal id="col2"/><signal id="count2" negated="ON"/></pterm><pterm id="FB1_16"><signal id="row2" negated="ON"/><signal id="row1" negated="ON"/><signal id="row0" negated="ON"/><signal id="N_PZ_25" negated="ON"/></pterm><pterm id="FB1_34"><signal id="row2" negated="ON"/><signal id="row1" negated="ON"/><signal id="row0"/><signal id="N_PZ_25" negated="ON"/></pterm><pterm id="FB1_37"><signal id="row2" negated="ON"/><signal id="row1"/><signal id="row0" negated="ON"/><signal id="N_PZ_25" negated="ON"/></pterm><pterm id="FB1_40"><signal id="row2" negated="ON"/><signal id="row1"/><signal id="row0"/><signal id="N_PZ_25" negated="ON"/></pterm><pterm id="FB1_43"><signal id="row2"/><signal id="row1" negated="ON"/><signal id="row0" negated="ON"/><signal id="N_PZ_25" negated="ON"/></pterm></PAL><equation id="outG0_SPECSIG"><d1><eq_pterm ptindx="FB1_16"/></d1></equation><equation id="outG1_SPECSIG"><d1><eq_pterm ptindx="FB1_34"/></d1></equation><equation id="outG2_SPECSIG"><d1><eq_pterm ptindx="FB1_37"/></d1></equation><equation id="outG3_SPECSIG"><d1><eq_pterm ptindx="FB1_40"/></d1></equation><equation id="outG4_SPECSIG"><d1><eq_pterm ptindx="FB1_43"/></d1></equation><equation id="N_PZ_25"><d2><eq_pterm ptindx="FB1_1"/><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_3"/><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_5"/><eq_pterm ptindx="FB1_4"/></d2></equation></fblock><fblock id="FB2" pinUse="6"><macrocell id="FB2_MC1" pin="FB2_MC1_PIN39"/><macrocell id="FB2_MC2" pin="FB2_MC2_PIN40"/><macrocell id="FB2_MC3"/><macrocell id="FB2_MC4"/><macrocell id="FB2_MC5" pin="FB2_MC5_PIN41"/><macrocell id="FB2_MC6" pin="FB2_MC6_PIN42" sigUse="0" signal="outR7_SPECSIG"/><macrocell id="FB2_MC7" pin="FB2_MC7_PIN43" sigUse="0" signal="outR6_SPECSIG"/><macrocell id="FB2_MC8" pin="FB2_MC8_PIN44" sigUse="0" signal="outR5_SPECSIG"/><macrocell id="FB2_MC9"/><macrocell id="FB2_MC10" pin="FB2_MC10_PIN1" sigUse="0" signal="outR4_SPECSIG"/><macrocell id="FB2_MC11"/><macrocell id="FB2_MC12" pin="FB2_MC12_PIN2" sigUse="0" signal="outR3_SPECSIG"/><macrocell id="FB2_MC13" pin="FB2_MC13_PIN3" sigUse="0" signal="outR2_SPECSIG"/><macrocell id="FB2_MC14"/><macrocell id="FB2_MC15"/><macrocell id="FB2_MC16"/><PAL/><equation id="outR7_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="outR6_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="outR5_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="outR4_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="outR3_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="outR2_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation></fblock><fblock id="FB3" pinUse="9"><macrocell id="FB3_MC1" pin="FB3_MC1_PIN29" sigUse="4" signal="outG5_SPECSIG"><eq_pterm ptindx="FB3_10"/></macrocell><macrocell id="FB3_MC2" pin="FB3_MC2_PIN28" sigUse="4" signal="outG6_SPECSIG"><eq_pterm ptindx="FB3_13"/></macrocell><macrocell id="FB3_MC3" pin="FB3_MC3_PIN27" sigUse="4" signal="outG7_SPECSIG"><eq_pterm ptindx="FB3_16"/></macrocell><macrocell id="FB3_MC4"/><macrocell id="FB3_MC5"/><macrocell id="FB3_MC6" pin="FB3_MC6_PIN23"/><macrocell id="FB3_MC7"/><macrocell id="FB3_MC8"/><macrocell id="FB3_MC9"/><macrocell id="FB3_MC10" pin="FB3_MC10_PIN22"/><macrocell id="FB3_MC11" pin="FB3_MC11_PIN21"/><macrocell id="FB3_MC12" pin="FB3_MC12_PIN20"/><macrocell id="FB3_MC13"/><macrocell id="FB3_MC14" pin="FB3_MC14_PIN19"/><macrocell id="FB3_MC15" pin="FB3_MC15_PIN18"/><macrocell id="FB3_MC16"/><fbinput id="FB3_I1" signal="N_PZ_25"/><fbinput id="FB3_I2" signal="row0"/><fbinput id="FB3_I3" signal="row1"/><fbinput id="FB3_I4" signal="row2"/><PAL><pterm id="FB3_10"><signal id="row2"/><signal id="row1" negated="ON"/><signal id="row0"/><signal id="N_PZ_25" negated="ON"/></pterm><pterm id="FB3_13"><signal id="row2"/><signal id="row1"/><signal id="row0" negated="ON"/><signal id="N_PZ_25" negated="ON"/></pterm><pterm id="FB3_16"><signal id="row2"/><signal id="row1"/><signal id="row0"/><signal id="N_PZ_25" negated="ON"/></pterm></PAL><equation id="outG5_SPECSIG"><d1><eq_pterm ptindx="FB3_10"/></d1></equation><equation id="outG6_SPECSIG"><d1><eq_pterm ptindx="FB3_13"/></d1></equation><equation id="outG7_SPECSIG"><d1><eq_pterm ptindx="FB3_16"/></d1></equation></fblock><fblock id="FB4" pinUse="5"><macrocell id="FB4_MC1" pin="FB4_MC1_PIN5" sigUse="0" signal="outR1_SPECSIG"/><macrocell id="FB4_MC2" pin="FB4_MC2_PIN6" sigUse="0" signal="outR0_SPECSIG"/><macrocell id="FB4_MC3"/><macrocell id="FB4_MC4"/><macrocell id="FB4_MC5"/><macrocell id="FB4_MC6"/><macrocell id="FB4_MC7" pin="FB4_MC7_PIN8"/><macrocell id="FB4_MC8"/><macrocell id="FB4_MC9"/><macrocell id="FB4_MC10"/><macrocell id="FB4_MC11" pin="FB4_MC11_PIN12"/><macrocell id="FB4_MC12"/><macrocell id="FB4_MC13" pin="FB4_MC13_PIN13"/><macrocell id="FB4_MC14" pin="FB4_MC14_PIN14"/><macrocell id="FB4_MC15" pin="FB4_MC15_PIN16"/><macrocell id="FB4_MC16"/><PAL/><equation id="outR1_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="outR0_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation></fblock><vcc/><gnd/><messages><warning>Cpld - Unable to retrieve the path to the iSE Project Repository. Will   use the default filename of 'battleship.ise'.</warning><warning>Cpld:1007 - Removing unused input(s) 'fire'.  The input(s) are unused   after optimization. Please verify functionality via simulation.</warning></messages><compOpts blkfanin="38" datagate="ON" exhaust="OFF" gclkopt="ON" gsropt="ON" gtsopt="ON" ignoredg="OFF" ignorets="OFF" inputs="32" inreg="ON" iostd="LVCMOS18" keepio="OFF" loc="ON" mlopt="ON" optimize="DENSITY" part="xc2c64a-7-VQ44" prld="LOW" pterms="28" slew="FAST" terminate="KEEPER" unused="KEEPER" wysiwyg="OFF"/><specSig signal="outG0_SPECSIG" value="outG[0]"/><specSig signal="outG1_SPECSIG" value="outG[1]"/><specSig signal="outG2_SPECSIG" value="outG[2]"/><specSig signal="outG3_SPECSIG" value="outG[3]"/><specSig signal="outG4_SPECSIG" value="outG[4]"/><specSig signal="outR7_SPECSIG" value="outR[7]"/><specSig signal="outR6_SPECSIG" value="outR[6]"/><specSig signal="outR5_SPECSIG" value="outR[5]"/><specSig signal="outR4_SPECSIG" value="outR[4]"/><specSig signal="outR3_SPECSIG" value="outR[3]"/><specSig signal="outR2_SPECSIG" value="outR[2]"/><specSig signal="outG5_SPECSIG" value="outG[5]"/><specSig signal="outG6_SPECSIG" value="outG[6]"/><specSig signal="outG7_SPECSIG" value="outG[7]"/><specSig signal="outR1_SPECSIG" value="outR[1]"/><specSig signal="outR0_SPECSIG" value="outR[0]"/></document>