battleship.pnx

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (LVTTL|SSTL3_I|LVCMOS33|LVCMOS25|SSTL2_I|LVCMOS18|LVCMOS15|HSTL_I|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW"
  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part arch="xbr" device="XC2C64A" pkg="VQ44" spg="-7"/><pin dir="input" iostd="LVCMOS18" nm="col0" no="18"/><pin dir="input" iostd="LVCMOS18" nm="col1" no="19"/><pin dir="input" iostd="LVCMOS18" nm="col2" no="20"/><pin dir="input" iostd="LVCMOS18" nm="count0" no="21"/><pin dir="input" iostd="LVCMOS18" nm="count1" no="22"/><pin dir="input" iostd="LVCMOS18" nm="count2" no="23"/><pin dir="input" iostd="LVCMOS18" nm="row2" no="14"/><pin dir="input" iostd="LVCMOS18" nm="row1" no="13"/><pin dir="input" iostd="LVCMOS18" nm="row0" no="12"/><pin dir="output" iostd="LVCMOS18" nm="outG[0]" no="36" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outG[1]" no="34" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outG[2]" no="33" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outG[3]" no="32" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outG[4]" no="31" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outG[5]" no="29" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outG[6]" no="28" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outG[7]" no="27" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[0]" no="6" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[1]" no="5" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[2]" no="3" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[3]" no="2" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[4]" no="1" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[5]" no="44" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[6]" no="43" sr="fast"/><pin dir="output" iostd="LVCMOS18" nm="outR[7]" no="42" sr="fast"/></ibis>