Indirect register accessing

[nadiga-ventana]

Need help is having an Address and Data register pair which is used for Indirect addressing of multiple actual registers in the design. i.e Data register points to different registers in the design depending on the value of Address register. Would having multiple address maps with bridge property help here?

[RasmusGOlsen]

Yes, I believe that would be the right way to specify it. Unfortunately, issue #72 is not resolved. I also use indirect addressing in my design and to work around issue #72 I specify an address map for each memory space and elaborate each of them. It works for me, but I lose the information about the relation between maps by not specifying the bridge.

[nadiga-ventana]

So how do you pass the Address register content as index for the Data register?

[RasmusGOlsen]

I think it's up to the implementation of how the indirect addressing is done. It depends on your interface/bus protocol.

[amykyta3]

Dang. Looks like i should go fix #72 then 😆

[amykyta3]

Fix to #72 published in v1.19.0

[nadiga-ventana]

For my indirect addressing requirement, I have created this example where taddr.index[1:0] is used select between the 4 different RTL registers A0.RegQ-A3.RegQ. So when tdata is written or read, the actual RTL register being accessed depends on taddr.index value.
In the RDL file, is there as was to indicate into the tdata_map that taddr.index[1:0] will be used for selecting between tdata0-tdata3?
Should we pass some parameter here? Any help would be appreciated, thanks.

reg taddr_t {
field {
} index[1:0];
};
reg tdata_t {
field {
} data[63:0];
};
addrmap main_reg {
bridge;
external taddr_t taddr @100;
external tdata_map tdata @108;
}

addrmap tdata_map {
external tdata_t tdata0;
tdata0.data->hdl_path_slice = '{"A0.RegQ"}'
external tdata_t tdata1;
tdata1.data->hdl_path_slice = '{"A1.RegQ"}'
external tdata_t tdata2;
tdata2.data->hdl_path_slice = '{"A2.RegQ"}'
external tdata_t tdata3;
tdata3.data->hdl_path_slice = '{"A3.RegQ"}'
}

[RasmusGOlsen]

SystemRDL is a register description language, not a hardware description such as VHDL and Verilog. In your example, you specify all registers as external. It means you need to implement these registers in your preferred hardware description language.

I think your indirect access registers are the tdata_t registers, therefore it is the tdata_map address map that is the bridge.

reg taddr_t {
    default hw = r;
    field {} index[1:0];
};

reg tdata_t {
    regwidth = 64;
    default hw = r;
    field {} data[63:0];
};

addrmap tdata_map {
    bridge;
    external tdata_t tdata0;
    tdata0.data->hdl_path_slice = '{"A0", ".RegQ"};
    external tdata_t tdata1;
    tdata1.data->hdl_path_slice = '{"A1", ".RegQ"};
    external tdata_t tdata2;
    tdata2.data->hdl_path_slice = '{"A2", ".RegQ"};
    external tdata_t tdata3;
    tdata3.data->hdl_path_slice = '{"A3", ".RegQ"};
};

addrmap main_reg {
    external taddr_t taddr @100;
    external tdata_map tdata @108;
};

The implementation could look something like this.

module taddr_t (
    input         clk_i,
    input         write_i,
    input  [63:0] write_data_i,
    output [63:0] read_data_o,
    output [1:0]  index_o,
    input  [1:0]  index_i);

    logic [1:0] index;

    assign index_o <= index;
    assign read_data_o <= {62'0, index};

    always_ff @(posedge clk_i) begin
        if write_i begin
            index <= write_data_i[1:0];
        end
    end

endmodule


module tdata_t (
    input         clk_i,
    input         write_i,
    input  [63:0] write_data_i,
    output [63:0] read_data_o,
    input  [63:0] data_i,
    output [63:0] data_o,

    logic [63:0] RegQ;

    assign data_o <= RegQ;
    assign read_data_o <= RegQ;

    always_ff @(posedge clk_i) begin
        if write_i begin
            RegQ <= write_data_i;
        end
    end

endmodule


module main_reg (
    // you register interface
    input clk_i,
    input addr_i,
    input data_i,
    output data_o,
    input read_i,
    input write_i);

    // address decoding
    always_ff @(posedge clk_i) begin
        case (addr_i) 
            100: begin
            end
            108: begin
            end
        endcase
    end

    // indeirect address decoding
    always_ff @(posedge clk_i) begin
        case (index) 
            0: begin // address 0
            end
            1: begin // address 8
            end
            2: begin // address 16
            end
            3: begin // address 24
            end
        endcase
    end


    taddr_t addr();

    tdata A0();
    tdata A1();
    tdata A2();
    tdata A3();

endmodule