How to modify the value of a register through wuser attribute

[tenaliram]

I have a register reg_cfg[3:0] which is SW programmable. Based on an internal signal (cfg_mode) in the hardware, I want to do one of the following:

1. If cfg_mode=0, allow SW to program reg_cfg[3:0]; if cfg_mode=1, then only allow SW to program reg_cfg[1:0] and keep cfg[3:2] at a reset value of 0. If this is not possible, then:
2. Let SW program cfg_mode[3:0]. However, when SW reads back the cfg_mode value, then if cfg_mode=0, reg_cfg_readback_SW[3:0] = reg_cfg[3:0], else if cfg_mode=1, then reg_cfg_readback_SW[3:0] = {2'b0, reg_cfg[1:0]}

Thanks in advance for the help.

[amykyta3]

Yes you can definitely accomplish this with regular SystemRDL semantics.
Here is how I would do it:

// Declare a hardware signal that can be used to control your register's behavior
signal {
    activehigh;
} cfg_mode;

reg {
    // Define a register with two fields. One for each part of the bit-range.

    field {
        sw=rw;
        hw=r;

        // when cfg_mode == 0, this field is writable by software, otherwise it is read-only
        swwel = cfg_mode;

        // when cfg_mode == 1, clear this field to 0
        hwclr = cfg_mode;
    } cfg_b[3:2] = 0;

    field {
        // this field is always writable by software
        sw=rw;
        hw=r;
    } cfg_a[1:0] = 0;
} reg_cfg;

The RTL generator PeakRDL-regblock should support this.

[tenaliram]

Thanks Alex. Unfortunately I cant split up the field into two groups. I can break it into 4 independent bits in which case I can use this solution, but then I lose backward compatibility in the registers. Is there any way to keep the bitwidth of this field as 4 and still achieve the same result? Do you if I can use "wuser" to achieve this? I cant find any example of how to use "wuser".

…

On Tue, Feb 7, 2023 at 7:15 PM Alex Mykyta ***@***.***> wrote: Yes you can definitely accomplish this with regular SystemRDL semantics. Here is how I would do it: // Declare a hardware signal that can be used to control your register's behavior signal { activehigh; } cfg_mode; reg { // Define a register with two fields. One for each part of the bit-range. field { sw=rw; hw=r; // when cfg_mode == 0, this field is writable by software, otherwise it is read-only swwel = cfg_mode; // when cfg_mode == 1, clear this field to 0 hwclr = cfg_mode; } cfg_b[3:2] = 0; field { // this field is always writable by software sw=rw; hw=r; } cfg_a[1:0] = 0; } reg_cfg; The RTL generator PeakRDL-regblock <https://peakrdl-regblock.readthedocs.io> should support this. — Reply to this email directly, view it on GitHub <#149 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AQUEVKPIDA66LJTPPV4M4XLWWMFULANCNFSM6AAAAAAUPYQ37U> . You are receiving this because you authored the thread.Message ID: ***@***.*** .com>

[amykyta3]

The SystemRDL spec does not make any effort to describe how wuser should be used. It is intentionally open-ended to allow users to extend the funtionality beyond the spec. I suppose some user-defined properties could be used to describe the specific behavior of wuser.

That said, it is still possible to do what you described in your option 2 in your original question using built-in RDL rules. Its a little more of a hack since its not possible to change sw access of part of a field, but this would work:

signal {
    activehigh;
} cfg_mode;

reg {
    field {
        sw=rw;
        hw=r;

        // clear if cfg_mode == 1
        hwclr = cfg_mode;
        // Ensure only bits [3:2] get cleared
        hwenable = 4'b1100;
        // Ensure that the hwclr action takes precedence over software writes
        precendence = hw;
    } cfg[3:0] = 0;
} reg_cfg;