From 75576ee472be3d491de212194a0b3b7290fad490 Mon Sep 17 00:00:00 2001 From: Mamzi Bayatpour Date: Wed, 3 Jul 2024 15:03:34 -0700 Subject: [PATCH] TL/MLX5: Addressing Sergey's comments --- src/components/tl/mlx5/alltoall/alltoall.c | 2 +- src/components/tl/mlx5/alltoall/alltoall.h | 2 +- .../tl/mlx5/alltoall/alltoall_mkeys.c | 2 +- .../tl/mlx5/alltoall/alltoall_mkeys.h | 2 +- src/components/tl/mlx5/mcast/tl_mlx5_mcast.h | 2 +- .../tl/mlx5/mcast/tl_mlx5_mcast_allgather.c | 164 +++++++++--------- .../tl/mlx5/mcast/tl_mlx5_mcast_coll.c | 6 +- .../tl/mlx5/mcast/tl_mlx5_mcast_context.c | 12 ++ src/components/tl/mlx5/tl_mlx5.c | 4 +- src/components/tl/mlx5/tl_mlx5_coll.c | 9 +- src/components/tl/mlx5/tl_mlx5_coll.h | 2 +- src/components/tl/mlx5/tl_mlx5_context.c | 2 +- src/components/tl/mlx5/tl_mlx5_dm.c | 2 +- src/components/tl/mlx5/tl_mlx5_dm.h | 2 +- src/components/tl/mlx5/tl_mlx5_lib.c | 2 +- src/components/tl/mlx5/tl_mlx5_pd.c | 2 +- src/components/tl/mlx5/tl_mlx5_pd.h | 2 +- src/components/tl/mlx5/tl_mlx5_team.c | 2 +- src/components/tl/mlx5/tl_mlx5_wqe.c | 2 +- src/components/tl/mlx5/tl_mlx5_wqe.h | 2 +- 20 files changed, 119 insertions(+), 106 deletions(-) diff --git a/src/components/tl/mlx5/alltoall/alltoall.c b/src/components/tl/mlx5/alltoall/alltoall.c index 5afc7c7d30..7b1f2e3ce6 100644 --- a/src/components/tl/mlx5/alltoall/alltoall.c +++ b/src/components/tl/mlx5/alltoall/alltoall.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/alltoall/alltoall.h b/src/components/tl/mlx5/alltoall/alltoall.h index c2bb39b62f..9fd9d787cc 100644 --- a/src/components/tl/mlx5/alltoall/alltoall.h +++ b/src/components/tl/mlx5/alltoall/alltoall.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/alltoall/alltoall_mkeys.c b/src/components/tl/mlx5/alltoall/alltoall_mkeys.c index 0fa197e6c7..e8b3052501 100644 --- a/src/components/tl/mlx5/alltoall/alltoall_mkeys.c +++ b/src/components/tl/mlx5/alltoall/alltoall_mkeys.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/alltoall/alltoall_mkeys.h b/src/components/tl/mlx5/alltoall/alltoall_mkeys.h index 0ea7b38a0c..e2e8432dc4 100644 --- a/src/components/tl/mlx5/alltoall/alltoall_mkeys.h +++ b/src/components/tl/mlx5/alltoall/alltoall_mkeys.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/mcast/tl_mlx5_mcast.h b/src/components/tl/mlx5/mcast/tl_mlx5_mcast.h index 023fd7e473..9d032eb5ed 100644 --- a/src/components/tl/mlx5/mcast/tl_mlx5_mcast.h +++ b/src/components/tl/mlx5/mcast/tl_mlx5_mcast.h @@ -163,6 +163,7 @@ typedef struct ucc_tl_mlx5_mcast_coll_context { struct rdma_cm_id *id; struct rdma_event_channel *channel; ucc_mpool_t compl_objects_mp; + ucc_mpool_t mcast_req_mp; ucc_list_link_t pending_nacks_list; ucc_rcache_t *rcache; ucc_tl_mlx5_mcast_ctx_params_t params; @@ -179,7 +180,6 @@ typedef struct ucc_tl_mlx5_mcast_context { ucc_thread_mode_t tm; ucc_tl_mlx5_mcast_coll_context_t mcast_context; ucc_tl_mlx5_mcast_context_config_t cfg; - ucc_mpool_t req_mp; int mcast_enabled; int mcast_ctx_ready; ucc_tl_mlx5_mcast_oob_ctx_t oob_ctx; diff --git a/src/components/tl/mlx5/mcast/tl_mlx5_mcast_allgather.c b/src/components/tl/mlx5/mcast/tl_mlx5_mcast_allgather.c index edc0522402..ecd4650bc7 100644 --- a/src/components/tl/mlx5/mcast/tl_mlx5_mcast_allgather.c +++ b/src/components/tl/mlx5/mcast/tl_mlx5_mcast_allgather.c @@ -145,7 +145,7 @@ static inline ucc_status_t ucc_tl_mlx5_mcast_reset_reliablity(ucc_tl_mlx5_mcast_ static inline void ucc_tl_mlx5_mcast_init_async_reliability_slots(ucc_tl_mlx5_mcast_coll_req_t *req) { ucc_tl_mlx5_mcast_coll_comm_t *comm = req->comm; - void *dest; + char *dest; ucc_assert(req->ag_counter == comm->allgather_comm.under_progress_counter); @@ -219,33 +219,34 @@ static inline ucc_status_t ucc_tl_mlx5_mcast_do_staging_based_allgather(ucc_tl_m if (MCAST_ALLGATHER_IN_PROGRESS(req, comm)) { return UCC_INPROGRESS; - } else { - if (ONE_SIDED_SYNCHRONOUS_PROTO == req->one_sided_reliability_scheme) { - if (!req->barrier_req) { - // mcast operations are done and now go to barrier - status = comm->service_coll.barrier_post(comm->p2p_ctx, &req->barrier_req); - if (status != UCC_OK) { - return status; - } - tl_trace(comm->lib, "mcast operations are done and now go to barrier"); - return UCC_INPROGRESS; - } else { - status = comm->service_coll.coll_test(req->barrier_req); - if (status == UCC_OK) { - req->barrier_req = NULL; - tl_trace(comm->lib, "barrier at the end of mcast allgather is completed"); - } else { - return status; - } - } + } + + if (ONE_SIDED_SYNCHRONOUS_PROTO == req->one_sided_reliability_scheme) { + /* mcast operations are all done, now wait until all the processes + * are done with their mcast operations */ + if (!req->barrier_req) { + // mcast operations are done and now go to barrier + status = comm->service_coll.barrier_post(comm->p2p_ctx, &req->barrier_req); + if (status != UCC_OK) { + return status; + } + tl_trace(comm->lib, "mcast operations are done and now go to barrier"); } - /* this task is completed */ - return UCC_OK; + status = comm->service_coll.coll_test(req->barrier_req); + if (status == UCC_OK) { + req->barrier_req = NULL; + tl_trace(comm->lib, "barrier at the end of mcast allgather is completed"); + } else { + return status; + } } + + /* this task is completed */ + return UCC_OK; } -static inline ucc_status_t ucc_tl_mlx5_mcast_test_allgather(ucc_tl_mlx5_mcast_coll_req_t* req) +static inline ucc_status_t ucc_tl_mlx5_mcast_allgather_test(ucc_tl_mlx5_mcast_coll_req_t* req) { ucc_status_t status; @@ -272,7 +273,49 @@ static inline ucc_status_t ucc_tl_mlx5_mcast_test_allgather(ucc_tl_mlx5_mcast_co ucc_status_t ucc_tl_mlx5_mcast_allgather_start(ucc_coll_task_t *coll_task) { - ucc_tl_mlx5_task_t *task = ucc_derived_of(coll_task, ucc_tl_mlx5_task_t); + return UCC_OK; +} + +void ucc_tl_mlx5_mcast_allgather_progress(ucc_coll_task_t *coll_task) +{ + ucc_tl_mlx5_task_t *task = ucc_derived_of(coll_task, ucc_tl_mlx5_task_t); + ucc_tl_mlx5_mcast_coll_req_t *req = task->coll_mcast.req_handle; + ucc_status_t status; + + ucc_assert(req != NULL); + + if (req->ag_counter != req->comm->allgather_comm.under_progress_counter) { + /* it is not this task's turn for progress */ + ucc_assert(req->comm->allgather_comm.under_progress_counter < req->ag_counter); + return; + } + + status = ucc_tl_mlx5_mcast_allgather_test(task->coll_mcast.req_handle); + if (UCC_INPROGRESS == status) { + return; + } else if (UCC_OK == status) { + coll_task->status = UCC_OK; + req->comm->allgather_comm.under_progress_counter++; + ucc_mpool_put(req); + task->coll_mcast.req_handle = NULL; + } else { + tl_error(UCC_TASK_LIB(task), "progress mcast allgather failed:%d", status); + coll_task->status = status; + if (req->rreg) { + ucc_tl_mlx5_mcast_mem_deregister(req->comm->ctx, req->rreg); + req->rreg = NULL; + } + if (req->recv_rreg) { + ucc_tl_mlx5_mcast_mem_deregister(req->comm->ctx, req->recv_rreg); + req->recv_rreg = NULL; + } + ucc_mpool_put(req); + } +} + +ucc_status_t ucc_tl_mlx5_mcast_allgather_init(ucc_tl_mlx5_task_t *task) +{ + ucc_coll_task_t *coll_task = &(task->super); ucc_tl_mlx5_team_t *mlx5_team = TASK_TEAM(task); ucc_tl_mlx5_mcast_team_t *team = mlx5_team->mcast; ucc_coll_args_t *args = &TASK_ARGS(task); @@ -286,7 +329,6 @@ ucc_status_t ucc_tl_mlx5_mcast_allgather_start(ucc_coll_task_t *coll_task) ucc_tl_mlx5_mcast_reg_t *reg = NULL; ucc_tl_mlx5_mcast_coll_req_t *req; - if (!data_size) { coll_task->status = UCC_OK; return ucc_task_complete(coll_task); @@ -294,15 +336,17 @@ ucc_status_t ucc_tl_mlx5_mcast_allgather_start(ucc_coll_task_t *coll_task) task->coll_mcast.req_handle = NULL; - tl_trace(comm->lib, "MCAST allgather start, sbuf %p, rbuf %p, size %ld, comm %d, " + tl_trace(comm->lib, "MCAST allgather init, sbuf %p, rbuf %p, size %ld, comm %d, " "comm_size %d, counter %d", sbuf, rbuf, data_size, comm->comm_id, comm->commsize, comm->allgather_comm.coll_counter); - req = ucc_calloc(1, sizeof(ucc_tl_mlx5_mcast_coll_req_t), "mcast_req"); + req = ucc_mpool_get(&comm->ctx->mcast_req_mp); if (!req) { - tl_warn(comm->lib, "malloc failed"); + tl_error(comm->lib, "failed to get a mcast req"); + status = UCC_ERR_NO_MEMORY; goto failed; } + memset(req, 0, sizeof(ucc_tl_mlx5_mcast_coll_req_t)); req->comm = comm; req->ptr = sbuf; @@ -331,7 +375,7 @@ ucc_status_t ucc_tl_mlx5_mcast_allgather_start(ucc_coll_task_t *coll_task) goto failed; } - req->last_pkt_len = req->length - (req->num_packets - 1)*comm->max_per_packet; + req->last_pkt_len = req->length % comm->max_per_packet; ucc_assert(req->last_pkt_len > 0 && req->last_pkt_len <= comm->max_per_packet); @@ -339,7 +383,7 @@ ucc_status_t ucc_tl_mlx5_mcast_allgather_start(ucc_coll_task_t *coll_task) /* register the send buffer */ status = ucc_tl_mlx5_mcast_mem_register(comm->ctx, req->ptr, req->length, ®); if (UCC_OK != status) { - ucc_free(req); + tl_error(comm->lib, "sendbuf registeration failed"); goto failed; } req->rreg = reg; @@ -362,63 +406,15 @@ ucc_status_t ucc_tl_mlx5_mcast_allgather_start(ucc_coll_task_t *coll_task) task->coll_mcast.req_handle = req; coll_task->status = UCC_INPROGRESS; + task->super.post = ucc_tl_mlx5_mcast_allgather_start; + task->super.progress = ucc_tl_mlx5_mcast_allgather_progress; return ucc_progress_queue_enqueue(UCC_TL_CORE_CTX(mlx5_team)->pq, &task->super); failed: - tl_warn(UCC_TASK_LIB(task), "mcast start allgather failed:%d", status); - coll_task->status = status; - return ucc_task_complete(coll_task); -} - -void ucc_tl_mlx5_mcast_allgather_progress(ucc_coll_task_t *coll_task) -{ - ucc_tl_mlx5_task_t *task = ucc_derived_of(coll_task, ucc_tl_mlx5_task_t); - ucc_tl_mlx5_mcast_coll_req_t *req = task->coll_mcast.req_handle; - ucc_status_t status; - - if (req != NULL) { - if (req->ag_counter != req->comm->allgather_comm.under_progress_counter) { - /* it is not this task's turn for progress */ - ucc_assert(req->comm->allgather_comm.under_progress_counter < req->ag_counter); - return; - } - - status = ucc_tl_mlx5_mcast_test_allgather(task->coll_mcast.req_handle); - if (UCC_INPROGRESS == status) { - return; - } else if (UCC_OK == status) { - coll_task->status = UCC_OK; - req->comm->allgather_comm.under_progress_counter++; - ucc_free(req); - task->coll_mcast.req_handle = NULL; - } else { - tl_error(UCC_TASK_LIB(task), "progress mcast allgather failed:%d", status); - coll_task->status = status; - if (req->rreg) { - ucc_tl_mlx5_mcast_mem_deregister(req->comm->ctx, req->rreg); - req->rreg = NULL; - } - if (req->recv_rreg) { - ucc_tl_mlx5_mcast_mem_deregister(req->comm->ctx, req->recv_rreg); - req->recv_rreg = NULL; - } - ucc_free(req); - ucc_task_complete(coll_task); - } - } else { - tl_error(UCC_TASK_LIB(task), "progress mcast allgather failed, mcast coll not initialized"); - coll_task->status = UCC_ERR_NO_RESOURCE; - ucc_task_complete(coll_task); + tl_warn(UCC_TASK_LIB(task), "mcast init allgather failed:%d", status); + if (req) { + ucc_mpool_put(req); } - - return; -} - -ucc_status_t ucc_tl_mlx5_mcast_allgather_init(ucc_tl_mlx5_task_t *task) -{ - task->super.post = ucc_tl_mlx5_mcast_allgather_start; - task->super.progress = ucc_tl_mlx5_mcast_allgather_progress; - - return UCC_OK; + return status; } diff --git a/src/components/tl/mlx5/mcast/tl_mlx5_mcast_coll.c b/src/components/tl/mlx5/mcast/tl_mlx5_mcast_coll.c index 00c3765be9..83668b582d 100644 --- a/src/components/tl/mlx5/mcast/tl_mlx5_mcast_coll.c +++ b/src/components/tl/mlx5/mcast/tl_mlx5_mcast_coll.c @@ -227,14 +227,16 @@ ucc_status_t ucc_tl_mlx5_mcast_coll_do_bcast(void* buf, size_t size, ucc_rank_t buf, size, root, comm->comm_id, comm->commsize, comm->rank == root, comm->psn ); - req = ucc_calloc(1, sizeof(ucc_tl_mlx5_mcast_coll_req_t), "mcast_req"); + req = ucc_mpool_get(&comm->ctx->mcast_req_mp); if (!req) { + tl_error(comm->lib, "failed to get mcast req"); return UCC_ERR_NO_MEMORY; } + memset(req, 0, sizeof(ucc_tl_mlx5_mcast_coll_req_t)); status = ucc_tl_mlx5_mcast_prepare_bcast(buf, size, root, comm, req); if (UCC_OK != status) { - ucc_free(req); + ucc_mpool_put(req); return status; } diff --git a/src/components/tl/mlx5/mcast/tl_mlx5_mcast_context.c b/src/components/tl/mlx5/mcast/tl_mlx5_mcast_context.c index 0756ac142d..6c9ac92e4c 100644 --- a/src/components/tl/mlx5/mcast/tl_mlx5_mcast_context.c +++ b/src/components/tl/mlx5/mcast/tl_mlx5_mcast_context.c @@ -238,6 +238,7 @@ ucc_status_t ucc_tl_mlx5_mcast_context_init(ucc_tl_mlx5_mcast_context_t *cont device_attr.max_cq, device_attr.max_cqe); ctx->max_qp_wr = device_attr.max_qp_wr; + status = ucc_mpool_init(&ctx->compl_objects_mp, 0, sizeof(ucc_tl_mlx5_mcast_p2p_completion_obj_t), 0, UCC_CACHE_LINE_SIZE, 8, UINT_MAX, &ucc_coll_task_mpool_ops, @@ -249,6 +250,17 @@ ucc_status_t ucc_tl_mlx5_mcast_context_init(ucc_tl_mlx5_mcast_context_t *cont goto error; } + status = ucc_mpool_init(&ctx->mcast_req_mp, 0, sizeof(ucc_tl_mlx5_mcast_coll_req_t), 0, + UCC_CACHE_LINE_SIZE, 8, UINT_MAX, + &ucc_coll_task_mpool_ops, + UCC_THREAD_SINGLE, + "ucc_tl_mlx5_mcast_coll_req_t"); + if (ucc_unlikely(UCC_OK != status)) { + tl_warn(lib, "failed to initialize mcast_req_mp mpool"); + status = UCC_ERR_NO_MEMORY; + goto error; + } + ctx->rcache = NULL; status = ucc_tl_mlx5_mcast_setup_rcache(ctx); if (UCC_OK != status) { diff --git a/src/components/tl/mlx5/tl_mlx5.c b/src/components/tl/mlx5/tl_mlx5.c index a9067e911c..7301dc42dd 100644 --- a/src/components/tl/mlx5/tl_mlx5.c +++ b/src/components/tl/mlx5/tl_mlx5.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ @@ -98,7 +98,7 @@ static ucc_config_field_t ucc_tl_mlx5_lib_config_table[] = { {"MCAST_ONE_SIDED_RELIABILITY_ENABLE", "1", "Enable one sided reliability for mcast", ucc_offsetof(ucc_tl_mlx5_lib_config_t, mcast_conf.one_sided_reliability_enable), - UCC_CONFIG_TYPE_INT}, + UCC_CONFIG_TYPE_BOOL}, {NULL}}; diff --git a/src/components/tl/mlx5/tl_mlx5_coll.c b/src/components/tl/mlx5/tl_mlx5_coll.c index d0dcc59433..a786d3fc2a 100644 --- a/src/components/tl/mlx5/tl_mlx5_coll.c +++ b/src/components/tl/mlx5/tl_mlx5_coll.c @@ -16,8 +16,9 @@ ucc_status_t ucc_tl_mlx5_coll_mcast_init(ucc_base_coll_args_t *coll_args, ucc_status_t status = UCC_OK; ucc_tl_mlx5_task_t *task = NULL; - if (UCC_COLL_ARGS_ACTIVE_SET(&coll_args->args)) { - tl_trace(team->context->lib, "mcast collective not supported for active sets"); + if (UCC_COLL_ARGS_ACTIVE_SET(&coll_args->args) || + UCC_IS_INPLACE(coll_args->args)) { + tl_trace(team->context->lib, "mcast collective not supported"); return UCC_ERR_NOT_SUPPORTED; } @@ -44,6 +45,8 @@ ucc_status_t ucc_tl_mlx5_coll_mcast_init(ucc_base_coll_args_t *coll_args, break; default: status = UCC_ERR_NOT_SUPPORTED; + tl_trace(team->context->lib, "mcast not supported for this collective type"); + goto free_task; } *task_h = &(task->super); @@ -64,7 +67,7 @@ ucc_status_t ucc_tl_mlx5_task_finalize(ucc_coll_task_t *coll_task) if (req != NULL) { ucc_assert(coll_task->status != UCC_INPROGRESS); - ucc_free(req); + ucc_mpool_put(req); tl_trace(UCC_TASK_LIB(task), "finalizing an mcast task %p", task); task->coll_mcast.req_handle = NULL; } diff --git a/src/components/tl/mlx5/tl_mlx5_coll.h b/src/components/tl/mlx5/tl_mlx5_coll.h index 4c0711adfc..8ffe3eaf64 100644 --- a/src/components/tl/mlx5/tl_mlx5_coll.h +++ b/src/components/tl/mlx5/tl_mlx5_coll.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_context.c b/src/components/tl/mlx5/tl_mlx5_context.c index 67a3d21525..16dc9a7ba1 100644 --- a/src/components/tl/mlx5/tl_mlx5_context.c +++ b/src/components/tl/mlx5/tl_mlx5_context.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_dm.c b/src/components/tl/mlx5/tl_mlx5_dm.c index 541273ff7a..2a0c474a39 100644 --- a/src/components/tl/mlx5/tl_mlx5_dm.c +++ b/src/components/tl/mlx5/tl_mlx5_dm.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_dm.h b/src/components/tl/mlx5/tl_mlx5_dm.h index 3b611e44b3..05738bf539 100644 --- a/src/components/tl/mlx5/tl_mlx5_dm.h +++ b/src/components/tl/mlx5/tl_mlx5_dm.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_lib.c b/src/components/tl/mlx5/tl_mlx5_lib.c index 11829f066f..509af869a4 100644 --- a/src/components/tl/mlx5/tl_mlx5_lib.c +++ b/src/components/tl/mlx5/tl_mlx5_lib.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_pd.c b/src/components/tl/mlx5/tl_mlx5_pd.c index bf98352883..551a945169 100644 --- a/src/components/tl/mlx5/tl_mlx5_pd.c +++ b/src/components/tl/mlx5/tl_mlx5_pd.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_pd.h b/src/components/tl/mlx5/tl_mlx5_pd.h index 2462cf1383..9ea925781a 100644 --- a/src/components/tl/mlx5/tl_mlx5_pd.h +++ b/src/components/tl/mlx5/tl_mlx5_pd.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_team.c b/src/components/tl/mlx5/tl_mlx5_team.c index edc0b95d90..213f2cb952 100644 --- a/src/components/tl/mlx5/tl_mlx5_team.c +++ b/src/components/tl/mlx5/tl_mlx5_team.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_wqe.c b/src/components/tl/mlx5/tl_mlx5_wqe.c index e8e36a27f6..cf4d590658 100644 --- a/src/components/tl/mlx5/tl_mlx5_wqe.c +++ b/src/components/tl/mlx5/tl_mlx5_wqe.c @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */ diff --git a/src/components/tl/mlx5/tl_mlx5_wqe.h b/src/components/tl/mlx5/tl_mlx5_wqe.h index a0a015c310..012dc74fc4 100644 --- a/src/components/tl/mlx5/tl_mlx5_wqe.h +++ b/src/components/tl/mlx5/tl_mlx5_wqe.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * See file LICENSE for terms. */