diff --git a/data/de1_soc_revF.sdc b/data/de1_soc_revF.sdc
new file mode 100644
index 00000000..7a5fceff
--- /dev/null
+++ b/data/de1_soc_revF.sdc
@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "clk" -period 20.000ns [get_ports {i_clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
diff --git a/data/de1_soc_revF.tcl b/data/de1_soc_revF.tcl
new file mode 100644
index 00000000..5604911c
--- /dev/null
+++ b/data/de1_soc_revF.tcl
@@ -0,0 +1,11 @@
+set_location_assignment PIN_AF14 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+set_location_assignment PIN_AA14 -to i_rst_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n
+
+set_location_assignment PIN_V16 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
+
+set_location_assignment PIN_AC18 -to uart_txd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart*
diff --git a/doc/servant.rst b/doc/servant.rst
index 6d11f9d3..23eef668 100644
--- a/doc/servant.rst
+++ b/doc/servant.rst
@@ -83,6 +83,14 @@ FPGA Pin Y15 (Connector JP7, pin 1) is used for UART output with 57600 baud rate
 
     fusesoc run --target=de10_nano servant
 
+
+DE1 SoC revF
+^^^^^^^^^^^^
+
+FPGA PIN_AC18 (Connector GPIO0, pin 0) is used for UART output with 57600 baud rate. DE1 SoC revF needs an external 3.3V UART to connect to this pin. The UART pin has not been tested.
+
+    fusesoc run --target=de1_soc_revF servant
+
 DECA development kit
 ^^^^^^^^^^^^^^^^^^^^
 
diff --git a/servant.core b/servant.core
index ef602a68..83025146 100644
--- a/servant.core
+++ b/servant.core
@@ -115,6 +115,14 @@ filesets:
       - servant/servive_clock_gen.v : {file_type : verilogSource}
       - servant/servive.v : {file_type : verilogSource}
 
+  de1_soc_revF:
+    files:
+      - data/de1_soc_revF.sdc : {file_type : SDC}
+      - data/de1_soc_revF.tcl : {file_type : tclSource}
+      - servant/servde1_soc_revF_clock_gen.v : {file_type : verilogSource}
+      - servant/servde1_soc_revF.v : {file_type : verilogSource}
+
+
   de10_nano:
     files:
       - data/de10_nano.sdc : {file_type : SDC}
diff --git a/servant/servde1_soc_revF.v b/servant/servde1_soc_revF.v
new file mode 100644
index 00000000..19d46bd6
--- /dev/null
+++ b/servant/servde1_soc_revF.v
@@ -0,0 +1,31 @@
+`default_nettype none
+module servde1_soc_revF
+(
+ input wire 	   i_clk,
+ input wire 	   i_rst_n,
+ output wire 	   q,
+ output wire 	   uart_txd);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   assign uart_txd = q;
+
+   servde1_soc_revF_clock_gen clock_gen
+     (.i_clk (i_clk),
+      .i_rst (!i_rst_n),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule
diff --git a/servant/servde1_soc_revF_clock_gen.v b/servant/servde1_soc_revF_clock_gen.v
new file mode 100644
index 00000000..eb7a1dd9
--- /dev/null
+++ b/servant/servde1_soc_revF_clock_gen.v
@@ -0,0 +1,34 @@
+`default_nettype none
+module servde1_soc_revF_clock_gen
+  (input wire i_clk,
+   input wire i_rst,
+   output wire o_clk,
+   output wire o_rst);
+
+   wire        locked;
+   reg [9:0]   r;
+
+   assign o_rst = r[9];
+
+   always @(posedge o_clk)
+     if (locked)
+       r <= {r[8:0],1'b0};
+     else
+       r <= 10'b1111111111;
+
+   wire [5:0] 	  clk;
+
+   assign 	  o_clk = clk[0];
+
+   altpll
+     #(.operation_mode         ("NORMAL"),
+       .clk0_divide_by         (25),
+       .clk0_multiply_by       (8),
+       .inclk0_input_frequency (20000))
+   pll
+     (.areset       (i_rst),
+      .inclk        ({1'b0, i_clk}),
+      .clk          (clk),
+      .locked       (locked));
+
+endmodule