From 5d296c548cc9067439fd2c6e5c0286bae109fa1a Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sat, 5 Oct 2024 12:02:34 +0200 Subject: [PATCH] Introduce width parameter Expose the width (or W internally) parameter to set the SERV datapath width. Note: Only width=1 is function at this time. --- bench/servant_sim.v | 2 ++ bench/servant_tb.v | 8 ++++- data/verilator_waiver.vlt | 6 ++-- rtl/serv_rf_top.v | 17 ++++++---- rtl/serv_top.v | 68 +++++++++++++++++++++------------------ servant.core | 7 ++++ servant/servant.v | 7 ++-- servile/servile.v | 14 +++++--- 8 files changed, 78 insertions(+), 51 deletions(-) diff --git a/bench/servant_sim.v b/bench/servant_sim.v index c5e2f65b..dc744d15 100644 --- a/bench/servant_sim.v +++ b/bench/servant_sim.v @@ -8,6 +8,7 @@ module servant_sim parameter memfile = ""; parameter memsize = 8192; + parameter width = 1; parameter with_csr = 1; parameter compressed = 0; parameter align = compressed; @@ -22,6 +23,7 @@ module servant_sim servant #(.memfile (memfile), .memsize (memsize), + .width (width), .sim (1), .with_csr (with_csr), .compress (compressed[0:0]), diff --git a/bench/servant_tb.v b/bench/servant_tb.v index 19525204..be42a980 100644 --- a/bench/servant_tb.v +++ b/bench/servant_tb.v @@ -3,8 +3,13 @@ module servant_tb; parameter memfile = "hello_uart.hex"; parameter memsize = 8192; + parameter width = 1; parameter with_csr = 1; + localparam baud_rate = + (width == 4) ? 57600*3 : + 57600; + reg wb_clk = 1'b0; reg wb_rst = 1'b1; @@ -15,11 +20,12 @@ module servant_tb; vlog_tb_utils vtu(); - uart_decoder #(57600) uart_decoder (q); + uart_decoder #(baud_rate) uart_decoder (q); servant_sim #(.memfile (memfile), .memsize (memsize), + .width (width), .with_csr (with_csr)) dut (.wb_clk (wb_clk), diff --git a/data/verilator_waiver.vlt b/data/verilator_waiver.vlt index 212044fd..0e9d1dc0 100644 --- a/data/verilator_waiver.vlt +++ b/data/verilator_waiver.vlt @@ -1,14 +1,12 @@ `verilator_config // Bits [1:0] in i_wb_rdt are not used at all -lint_off -rule UNUSED -file "*/serv_top.v" -lines 179 +lint_off -rule UNUSED -file "*/serv_top.v" -lines 181 //Some bits in the instruction word are not used in serv_decode but it's easier //to just send in the whole word than picking out bits lint_off -rule UNUSED -file "*/serv_decode.v" -lines 8 -lint_off -rule UNUSED -file "*/serv_top.v" -lines 177 - //Some variables are only used when we connect an Extension with serv_decode -lint_off -rule UNUSED -file "*/serv_top.v" -lines 67 +lint_off -rule UNUSED -file "*/serv_top.v" -lines 69 diff --git a/rtl/serv_rf_top.v b/rtl/serv_rf_top.v index da81c7b4..8eeaa42c 100644 --- a/rtl/serv_rf_top.v +++ b/rtl/serv_rf_top.v @@ -28,7 +28,8 @@ module serv_rf_top */ parameter RESET_STRATEGY = "MINI", parameter WITH_CSR = 1, - parameter RF_WIDTH = 2, + parameter W = 1, + parameter RF_WIDTH = W * 2, parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH)) ( input wire clk, @@ -86,13 +87,13 @@ module serv_rf_top wire [4+WITH_CSR:0] wreg1; wire wen0; wire wen1; - wire wdata0; - wire wdata1; + wire [W-1:0] wdata0; + wire [W-1:0] wdata1; wire [4+WITH_CSR:0] rreg0; wire [4+WITH_CSR:0] rreg1; wire rf_ready; - wire rdata0; - wire rdata1; + wire [W-1:0] rdata0; + wire [W-1:0] rdata1; wire [RF_L2D-1:0] waddr; wire [RF_WIDTH-1:0] wdata; @@ -104,7 +105,8 @@ module serv_rf_top serv_rf_ram_if #(.width (RF_WIDTH), .reset_strategy (RESET_STRATEGY), - .csr_regs (CSR_REGS)) + .csr_regs (CSR_REGS), + .W(W)) rf_ram_if (.i_clk (clk), .i_rst (i_rst), @@ -147,7 +149,8 @@ module serv_rf_top .WITH_CSR (WITH_CSR), .MDU(MDU), .COMPRESSED(COMPRESSED), - .ALIGN(ALIGN)) + .ALIGN(ALIGN), + .W(W)) cpu ( .clk (clk), diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 37a9f03a..e01324de 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -2,6 +2,8 @@ module serv_top #(parameter WITH_CSR = 1, + parameter W = 1, + parameter B = W-1, parameter PRE_REGISTER = 1, parameter RESET_STRATEGY = "MINI", parameter RESET_PC = 32'd0, @@ -43,12 +45,12 @@ module serv_top output wire [4+WITH_CSR:0] o_wreg1, output wire o_wen0, output wire o_wen1, - output wire o_wdata0, - output wire o_wdata1, + output wire [B:0] o_wdata0, + output wire [B:0] o_wdata1, output wire [4+WITH_CSR:0] o_rreg0, output wire [4+WITH_CSR:0] o_rreg1, - input wire i_rdata0, - input wire i_rdata1, + input wire [B:0] i_rdata0, + input wire [B:0] i_rdata1, output wire [31:0] o_ibus_adr, output wire o_ibus_cyc, @@ -92,10 +94,10 @@ module serv_top wire rd_alu_en; wire rd_csr_en; wire rd_mem_en; - wire ctrl_rd; - wire alu_rd; - wire mem_rd; - wire csr_rd; + wire [B:0] ctrl_rd; + wire [B:0] alu_rd; + wire [B:0] mem_rd; + wire [B:0] csr_rd; wire mtval_pc; wire ctrl_pc_en; @@ -103,7 +105,7 @@ module serv_top wire jal_or_jalr; wire utype; wire mret; - wire imm; + wire [B:0] imm; wire trap; wire pc_rel; wire iscomp; @@ -127,8 +129,8 @@ module serv_top wire bufreg_rs1_en; wire bufreg_imm_en; wire bufreg_clr_lsb; - wire bufreg_q; - wire bufreg2_q; + wire [B:0] bufreg_q; + wire [B:0] bufreg2_q; wire [31:0] dbus_rdt; wire dbus_ack; @@ -139,11 +141,11 @@ module serv_top wire alu_cmp; wire [2:0] alu_rd_sel; - wire rs1; - wire rs2; + wire [B:0] rs1; + wire [B:0] rs2; wire rd_en; - wire op_b; + wire [B:0] op_b; wire op_b_sel; wire mem_signed; @@ -156,20 +158,20 @@ module serv_top wire mem_misalign; - wire bad_pc; + wire [B:0] bad_pc; wire csr_mstatus_en; wire csr_mie_en; wire csr_mcause_en; wire [1:0] csr_source; - wire csr_imm; + wire [B:0] csr_imm; wire csr_d_sel; wire csr_en; wire [1:0] csr_addr; - wire csr_pc; + wire [B:0] csr_pc; wire csr_imm_en; - wire csr_in; - wire rf_csr_out; + wire [B:0] csr_in; + wire [B:0] rf_csr_out; wire dbus_en; wire new_irq; @@ -226,7 +228,8 @@ module serv_top #(.RESET_STRATEGY (RESET_STRATEGY), .WITH_CSR (WITH_CSR[0:0]), .MDU(MDU), - .ALIGN(ALIGN)) + .ALIGN(ALIGN), + .W(W)) state ( .i_clk (clk), @@ -420,7 +423,8 @@ module serv_top serv_ctrl #(.RESET_PC (RESET_PC), .RESET_STRATEGY (RESET_STRATEGY), - .WITH_CSR (WITH_CSR)) + .WITH_CSR (WITH_CSR), + .W (W)) ctrl ( .clk (clk), @@ -447,7 +451,7 @@ module serv_top //External .o_ibus_adr (wb_ibus_adr)); - serv_alu alu + serv_alu #(.W (W)) alu ( .clk (clk), //State @@ -467,7 +471,7 @@ module serv_top .o_rd (alu_rd)); serv_rf_if - #(.WITH_CSR (WITH_CSR)) + #(.WITH_CSR (WITH_CSR), .W(W)) rf_if (//RF interface .i_cnt_en (cnt_en), @@ -485,7 +489,7 @@ module serv_top //Trap interface .i_trap (trap), .i_mret (mret), - .i_mepc (wb_ibus_adr[0]), + .i_mepc (wb_ibus_adr[B:0]), .i_mtval_pc (mtval_pc), .i_bufreg_q (bufreg_q), .i_bad_pc (bad_pc), @@ -516,7 +520,8 @@ module serv_top .o_csr (rf_csr_out)); serv_mem_if - #(.WITH_CSR (WITH_CSR[0:0])) + #(.WITH_CSR (WITH_CSR[0:0]), + .W (W)) mem_if ( .i_clk (clk), @@ -539,7 +544,8 @@ module serv_top generate if (|WITH_CSR) begin : gen_csr serv_csr - #(.RESET_STRATEGY (RESET_STRATEGY)) + #(.RESET_STRATEGY (RESET_STRATEGY), + .W(W)) csr ( .i_clk (clk), @@ -574,8 +580,8 @@ module serv_top .i_rs1 (rs1), .o_q (csr_rd)); end else begin : gen_no_csr - assign csr_in = 1'b0; - assign csr_rd = 1'b0; + assign csr_in = {W{1'b0}}; + assign csr_rd = {W{1'b0}}; assign new_irq = 1'b0; end endgenerate @@ -597,7 +603,7 @@ module serv_top /* Store data written to rd */ if (o_wen0) - rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]}; + rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:W]}; if (cnt_done & ctrl_pc_en) begin rvfi_pc_rdata <= pc; @@ -626,8 +632,8 @@ module serv_top rvfi_rd_addr <= rd_addr; end if (rs_en) begin - rvfi_rs1_rdata <= {!immdec_en[1] & rs1,rvfi_rs1_rdata[31:1]}; - rvfi_rs2_rdata <= {!immdec_en[2] & rs2,rvfi_rs2_rdata[31:1]}; + rvfi_rs1_rdata <= {(!immdec_en[1] ? rs1 : {W{1'b0}}),rvfi_rs1_rdata[31:W]}; + rvfi_rs2_rdata <= {(!immdec_en[2] ? rs2 : {W{1'b0}}),rvfi_rs2_rdata[31:W]}; end if (i_dbus_ack) begin diff --git a/servant.core b/servant.core index cf1d47eb..8f1f908a 100644 --- a/servant.core +++ b/servant.core @@ -580,6 +580,7 @@ targets: filesets : [soc, servant_tb] parameters : - RISCV_FORMAL + - width - "mdu? (MDU=1)" - SERV_CLEAR_RAM=true - firmware @@ -649,6 +650,7 @@ targets: - uart_baudrate - vcd - vcd_start + - width - compressed - align - with_csr=1 @@ -744,6 +746,11 @@ parameters: description : Delay start of VCD dumping until the specified time paramtype : plusarg + width: + datatype : int + description : Interal datapath width (1=SERV, 4=QERV) + paramtype : vlogparam + with_csr: datatype : int description : Enable/Disable CSR support diff --git a/servant/servant.v b/servant/servant.v index 0ced369a..34cbc912 100644 --- a/servant/servant.v +++ b/servant/servant.v @@ -8,6 +8,7 @@ module servant parameter memfile = "zephyr_hello.hex"; parameter memsize = 8192; parameter reset_strategy = "MINI"; + parameter width = 1; parameter sim = 0; parameter with_csr = 1; parameter [0:0] compress = 0; @@ -23,7 +24,7 @@ module servant localparam aw = $clog2(memsize); localparam csr_regs = with_csr*4; - localparam rf_width = 2; + localparam rf_width = width * 2; localparam rf_l2d = $clog2((32+csr_regs)*32/rf_width); wire timer_irq; @@ -133,7 +134,7 @@ module servant .o_rdata (rf_rdata)); servile - #(.rf_width (rf_width), + #(.width (width), .sim (sim[0]), .with_c (compress[0]), .with_csr (with_csr[0]), @@ -159,7 +160,7 @@ module servant .o_wb_ext_stb (wb_ext_stb), .i_wb_ext_rdt (wb_ext_rdt), .i_wb_ext_ack (wb_ext_ack), - + .o_rf_waddr (rf_waddr), .o_rf_wdata (rf_wdata), .o_rf_wen (rf_wen), diff --git a/servile/servile.v b/servile/servile.v index a6f5af7b..157b07d1 100644 --- a/servile/servile.v +++ b/servile/servile.v @@ -8,14 +8,16 @@ `default_nettype none module servile #( + parameter width = 1, parameter reset_pc = 32'h00000000, parameter reset_strategy = "MINI", - parameter rf_width = 8, + parameter rf_width = 2*width, parameter [0:0] sim = 1'b0, parameter [0:0] with_c = 1'b0, parameter [0:0] with_csr = 1'b0, parameter [0:0] with_mdu = 1'b0, //Internally calculated. Do not touch + parameter B = width-1, parameter regs = 32+with_csr*4, parameter rf_l2d = $clog2(regs*32/rf_width)) ( @@ -78,13 +80,13 @@ module servile wire [$clog2(regs)-1:0] wreg1; wire wen0; wire wen1; - wire wdata0; - wire wdata1; + wire [B:0] wdata0; + wire [B:0] wdata1; wire [$clog2(regs)-1:0] rreg0; wire [$clog2(regs)-1:0] rreg1; wire rf_ready; - wire rdata0; - wire rdata1; + wire [B:0] rdata0; + wire [B:0] rdata1; wire [31:0] mdu_rs1; wire [31:0] mdu_rs2; @@ -149,6 +151,7 @@ module servile serv_rf_ram_if #(.width (rf_width), + .W (width), .reset_strategy (reset_strategy), .csr_regs (with_csr*4)) rf_ram_if @@ -196,6 +199,7 @@ module servile serv_top #( .WITH_CSR (with_csr?1:0), + .W (width), .PRE_REGISTER (1'b1), .RESET_STRATEGY (reset_strategy), .RESET_PC (reset_pc),