From 03d11f4b4413836dd72f3d68af7f9861da106723 Mon Sep 17 00:00:00 2001
From: Ng Zhi An <zhin@google.com>
Date: Tue, 2 Feb 2021 16:53:58 -0800
Subject: [PATCH] [spectext] Add i64x2.all_true

This instruction was accepted into the proposal in #415.
---
 document/core/appendix/gen-index-instructions.py | 1 +
 document/core/appendix/index-instructions.rst    | 1 +
 document/core/binary/instructions.rst            | 1 +
 document/core/syntax/instructions.rst            | 4 +---
 document/core/text/instructions.rst              | 1 +
 5 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py
index ebab2f730..5daed1211 100755
--- a/document/core/appendix/gen-index-instructions.py
+++ b/document/core/appendix/gen-index-instructions.py
@@ -474,6 +474,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
     Instruction(r'\I64X2.\VSHR\K{\_s}', r'\hex{FD}~~204', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
     Instruction(r'\I64X2.\VSHR\K{\_u}', r'\hex{FD}~~205', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
     Instruction(r'\I64X2.\VADD', r'\hex{FD}~~206', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-iadd'),
+    Instruction(r'\I64X2.\ALLTRUE', r'\hex{FD}~~207', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'),
     Instruction(r'\I64X2.\VSUB', r'\hex{FD}~~209', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-isub'),
     Instruction(r'\I64X2.\VMUL', r'\hex{FD}~~213', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imul'),
     Instruction(r'\F32X4.\VABS', r'\hex{FD}~~224', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fabs'),
diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst
index 790cbe823..46055cda9 100644
--- a/document/core/appendix/index-instructions.rst
+++ b/document/core/appendix/index-instructions.rst
@@ -422,6 +422,7 @@ Instruction                                  Binary Opcode          Type
 :math:`\I64X2.\VSHR\K{\_s}`                  :math:`\hex{FD}~~204`  :math:`[\V128~\I32] \to [\V128]`               :ref:`validation <valid-vshiftop>`           :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_s>`    
 :math:`\I64X2.\VSHR\K{\_u}`                  :math:`\hex{FD}~~205`  :math:`[\V128~\I32] \to [\V128]`               :ref:`validation <valid-vshiftop>`           :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_u>`    
 :math:`\I64X2.\VADD`                         :math:`\hex{FD}~~206`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <valid-vbinop>`             :ref:`execution <exec-vbinop>`, :ref:`operator <op-iadd>`        
+:math:`\I64X2.\ALLTRUE`                      :math:`\hex{FD}~~207`  :math:`[\V128] \to [\I32]`                     :ref:`validation <valid-vitestop>`           :ref:`execution <exec-vitestop>`                                 
 :math:`\I64X2.\VSUB`                         :math:`\hex{FD}~~209`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <valid-vbinop>`             :ref:`execution <exec-vbinop>`, :ref:`operator <op-isub>`        
 :math:`\I64X2.\VMUL`                         :math:`\hex{FD}~~213`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <valid-vbinop>`             :ref:`execution <exec-vbinop>`, :ref:`operator <op-imul>`        
 :math:`\F32X4.\VABS`                         :math:`\hex{FD}~~224`  :math:`[\V128] \to [\V128]`                    :ref:`validation <valid-vunop>`              :ref:`execution <exec-vunop>`, :ref:`operator <op-fabs>`         
diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst
index a0f5fc4d2..523522936 100644
--- a/document/core/binary/instructions.rst
+++ b/document/core/binary/instructions.rst
@@ -670,6 +670,7 @@ All other SIMD instructions are plain opcodes without any immediates.
      \hex{FD}~~204{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_s} \\ &&|&
      \hex{FD}~~205{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_u} \\ &&|&
      \hex{FD}~~206{:}\Bu32 &\Rightarrow& \I64X2.\VADD \\ &&|&
+     \hex{FD}~~207{:}\Bu32 &\Rightarrow& \I64X2.\ALLTRUE \\ &&|&
      \hex{FD}~~209{:}\Bu32 &\Rightarrow& \I64X2.\VSUB \\ &&|&
      \hex{FD}~~213{:}\Bu32 &\Rightarrow& \I64X2.\VMUL \\
   \end{array}
diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst
index c24b1e997..e5e1cb037 100644
--- a/document/core/syntax/instructions.rst
+++ b/document/core/syntax/instructions.rst
@@ -228,9 +228,7 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
      \K{i32x4.}\viunop \\&&|&
      \K{i64x2.}\NEG \\&&|&
      \fshape\K{.}\vfunop \\&&|&
-     \K{i8x16.}\vitestop ~|~
-     \K{i16x8.}\vitestop ~|~
-     \K{i32x4.}\vitestop \\&&|&
+     \ishape\K{.}\vitestop \\ &&|&
      \K{i8x16.}\BITMASK ~|~
      \K{i16x8.}\BITMASK ~|~
      \K{i32x4.}\BITMASK ~|~
diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst
index 6084291e5..e9eabe834 100644
--- a/document/core/text/instructions.rst
+++ b/document/core/text/instructions.rst
@@ -699,6 +699,7 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
    \begin{array}{llclll}
    \phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
      \text{i64x2.neg} &\Rightarrow& \I64X2.\VNEG\\ &&|&
+     \text{i64x2.all\_true} &\Rightarrow& \I64X2.\ALLTRUE\\ &&|&
      \text{i64x2.bitmask} &\Rightarrow& \I64X2.\BITMASK\\ &&|&
      \text{i64x2.shl} &\Rightarrow& \I64X2.\VSHL\\ &&|&
      \text{i64x2.shr\_s} &\Rightarrow& \I64X2.\VSHR\K{\_s}\\ &&|&