README.md

Verilog Lab Designs

Welcome to the Verilog Lab Designs repository! This repository contains Verilog code for various design projects created as part of labs at the Indian Institute of Technology (IIT) Jodhpur.

Table of Contents

• Introduction
• Lab Projects
• Getting Started
• License

Introduction

This repository hosts a collection of Verilog code and associated files for lab projects completed during academic coursework at IIT Jodhpur. These projects cover a range of topics in digital design and Verilog programming.

Lab Projects

1. Lab Project 1: Sequence Detector using Python
2. Lab Project 2: Adder using Pipelining
3. Lab Project 3: Maxpooler in Verilog
4. Lab Project 4: UVM verification of FIFO
5. Lab Project 5: Matrix adder and subtractor in verilog
6. Lab Project 6(Formal Verification Course) : Router Design Assertions
7. Lab Project 7 : 8*8 Multiplier
8. Ungraded Lab Project 1: Memory in verilog
9. Ungraded Lab Project 2: One counter and Detector
10. Ungraded Lab Project 3: 2*2 Adder Each lab project folder contains the Verilog source code, testbenches, and any other relevant files needed for the project. You can explore each project by clicking on the provided links.

Getting Started

To get started with these Verilog projects, you will need a Verilog simulator or synthesis tool. You can use tools like Xilinx Vivado, ModelSim, or other Verilog development environments.

1. Clone this repository to your local machine:

   git clone https://github.com/minecraftdixit/verilog-lab-designs.git

2. Navigate to a specific lab project directory, e.g., Lab1.

3. Use your Verilog tool to open and work with the Verilog files within the chosen project folder.

4. Follow the instructions in the project's README or documentation to simulate or synthesize the design.

License

This repository is licensed under the MIT License. You are free to use, modify, and distribute the code within the terms of this license.

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Happy coding! 💻: