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use critical_section::{set_impl, Impl, RawRestoreState}; | ||
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use crate::interrupt; | ||
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struct SingleCoreCriticalSection; | ||
set_impl!(SingleCoreCriticalSection); | ||
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unsafe impl Impl for SingleCoreCriticalSection { | ||
unsafe fn acquire() -> RawRestoreState { | ||
let was_active = interrupt::enabled(); | ||
// NOTE: Fence guarantees are provided by interrupt::disable(), which performs a `compiler_fence(SeqCst)`. | ||
interrupt::disable(); | ||
was_active | ||
} | ||
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unsafe fn release(was_active: RawRestoreState) { | ||
// Only re-enable interrupts if they were enabled before the critical section. | ||
if was_active { | ||
// NOTE: Fence guarantees are provided by interrupt::enable(), which performs a | ||
// `compiler_fence(SeqCst)`. | ||
interrupt::enable() | ||
} | ||
} | ||
} |
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//! Interrupts | ||
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#[cfg(target_arch = "aarch64")] | ||
use crate::registers::{Readable, Writeable, DAIF}; | ||
#[cfg(target_arch = "aarch64")] | ||
use core::sync::atomic::{compiler_fence, Ordering}; | ||
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/// Disables all interrupts in the current core. | ||
#[cfg(target_arch = "aarch64")] | ||
#[inline] | ||
pub fn disable() { | ||
compiler_fence(Ordering::SeqCst); | ||
DAIF.write(DAIF::I::Masked + DAIF::F::Masked); | ||
compiler_fence(Ordering::SeqCst); | ||
} | ||
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/// Enables all the interrupts in the current core. | ||
/// | ||
/// # Safety | ||
/// | ||
/// - Do not call this function inside a critical section. | ||
#[cfg(target_arch = "aarch64")] | ||
#[inline] | ||
pub unsafe fn enable() { | ||
compiler_fence(Ordering::SeqCst); | ||
DAIF.write(DAIF::I::Unmasked + DAIF::F::Unmasked); | ||
compiler_fence(Ordering::SeqCst); | ||
} | ||
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#[cfg(target_arch = "aarch64")] | ||
#[inline] | ||
pub unsafe fn enabled() -> bool { | ||
if DAIF.read(DAIF::I) == 0 || DAIF.read(DAIF::F) == 0 { | ||
return true; | ||
} | ||
false | ||
} |
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