diff --git a/.gitignore b/.gitignore index 04908e0e0c6..ca9d950d3f9 100644 --- a/.gitignore +++ b/.gitignore @@ -12,7 +12,6 @@ mbed_settings.py # Default Build Directory .build/ -BUILD/ .mbed venv/ diff --git a/platform/include/platform/mbed_stats.h b/platform/include/platform/mbed_stats.h index f331c655be3..fcf9f37678a 100644 --- a/platform/include/platform/mbed_stats.h +++ b/platform/include/platform/mbed_stats.h @@ -161,10 +161,10 @@ typedef struct { uint32_t cpu_id; /**< CPUID register data (Cortex-M only supported) */ mbed_compiler_id_t compiler_id; /**< Compiler ID \ref mbed_compiler_id_t */ uint32_t compiler_version; /**< Compiler version */ - uint32_t ram_start[MBED_MAX_MEM_REGIONS]; /**< Start addresses of all internal RAM memories */ - uint32_t ram_size[MBED_MAX_MEM_REGIONS]; /**< Size of all internal RAM memories in target */ - uint32_t rom_start[MBED_MAX_MEM_REGIONS]; /**< Start addresses of all internal ROM memories */ - uint32_t rom_size[MBED_MAX_MEM_REGIONS]; /**< Size of all internal ROM memories in target */ + uint32_t ram_start[MBED_MAX_MEM_REGIONS]; /**< Configured start addresses of all internal RAM memories */ + uint32_t ram_size[MBED_MAX_MEM_REGIONS]; /**< Configured sizes of all internal RAM memories in target */ + uint32_t rom_start[MBED_MAX_MEM_REGIONS]; /**< Configured start addresses of all internal ROM memories */ + uint32_t rom_size[MBED_MAX_MEM_REGIONS]; /**< Configured sizes of all internal ROM memories in target */ } mbed_stats_sys_t; /** diff --git a/platform/source/mbed_stats.c b/platform/source/mbed_stats.c index f7d9ad101d1..9f550f9ee60 100644 --- a/platform/source/mbed_stats.c +++ b/platform/source/mbed_stats.c @@ -146,37 +146,37 @@ void mbed_stats_sys_get(mbed_stats_sys_t *stats) #if defined(MBED_SYS_STATS_ENABLED) stats->os_version = MBED_VERSION; -#if defined(MBED_RAM_START) && defined(MBED_RAM_SIZE) - stats->ram_start[0] = MBED_RAM_START; - stats->ram_size[0] = MBED_RAM_SIZE; +#if defined(MBED_CONFIGURED_RAM_START) && defined(MBED_CONFIGURED_RAM_SIZE) + stats->ram_start[0] = MBED_CONFIGURED_RAM_START; + stats->ram_size[0] = MBED_CONFIGURED_RAM_SIZE; #endif -#if defined(MBED_ROM_START) && defined(MBED_ROM_SIZE) - stats->rom_start[0] = MBED_ROM_START; - stats->rom_size[0] = MBED_ROM_SIZE; +#if defined(MBED_CONFIGURED_ROM_START) && defined(MBED_CONFIGURED_ROM_SIZE) + stats->rom_start[0] = MBED_CONFIGURED_ROM_START; + stats->rom_size[0] = MBED_CONFIGURED_ROM_SIZE; #endif -#if defined(MBED_RAM1_START) && defined(MBED_RAM1_SIZE) - stats->ram_start[1] = MBED_RAM1_START; - stats->ram_size[1] = MBED_RAM1_SIZE; +#if defined(MBED_CONFIGURED_RAM1_START) && defined(MBED_CONFIGURED_RAM1_SIZE) + stats->ram_start[1] = MBED_CONFIGURED_RAM1_START; + stats->ram_size[1] = MBED_CONFIGURED_RAM1_SIZE; #endif -#if defined(MBED_RAM2_START) && defined(MBED_RAM2_SIZE) - stats->ram_start[2] = MBED_RAM2_START; - stats->ram_size[2] = MBED_RAM2_SIZE; +#if defined(MBED_CONFIGURED_RAM2_START) && defined(MBED_CONFIGURED_RAM2_SIZE) + stats->ram_start[2] = MBED_CONFIGURED_RAM2_START; + stats->ram_size[2] = MBED_CONFIGURED_RAM2_SIZE; #endif -#if defined(MBED_RAM3_START) && defined(MBED_RAM3_SIZE) - stats->ram_start[3] = MBED_RAM3_START; - stats->ram_size[3] = MBED_RAM3_SIZE; +#if defined(MBED_CONFIGURED_RAM3_START) && defined(MBED_CONFIGURED_RAM3_SIZE) + stats->ram_start[3] = MBED_CONFIGURED_RAM3_START; + stats->ram_size[3] = MBED_CONFIGURED_RAM3_SIZE; #endif -#if defined(MBED_ROM1_START) && defined(MBED_ROM1_SIZE) - stats->rom_start[1] = MBED_ROM1_START; - stats->rom_size[1] = MBED_ROM1_SIZE; +#if defined(MBED_CONFIGURED_ROM1_START) && defined(MBED_CONFIGURED_ROM1_SIZE) + stats->rom_start[1] = MBED_CONFIGURED_ROM1_START; + stats->rom_size[1] = MBED_CONFIGURED_ROM1_SIZE; #endif -#if defined(MBED_ROM2_START) && defined(MBED_ROM2_SIZE) - stats->rom_start[2] = MBED_ROM2_START; - stats->rom_size[2] = MBED_ROM2_SIZE; +#if defined(MBED_CONFIGURED_ROM2_START) && defined(MBED_CONFIGURED_ROM2_SIZE) + stats->rom_start[2] = MBED_CONFIGURED_ROM2_START; + stats->rom_size[2] = MBED_CONFIGURED_ROM2_SIZE; #endif -#if defined(MBED_ROM3_START) && defined(MBED_ROM3_SIZE) - stats->rom_start[3] = MBED_ROM3_START; - stats->rom_size[3] = MBED_ROM3_SIZE; +#if defined(MBED_CONFIGURED_ROM3_START) && defined(MBED_CONFIGURED_ROM3_SIZE) + stats->rom_start[3] = MBED_CONFIGURED_ROM3_START; + stats->rom_size[3] = MBED_CONFIGURED_ROM3_SIZE; #endif #if defined(__CORTEX_M) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld index ce0ec38c783..e15a8475be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld @@ -50,36 +50,14 @@ FLASH_CM0P_SIZE = 0x10000; /* The size of the MCU boot header area at the start of FLASH */ BOOT_HEADER_SIZE = 0x400; -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000E8000 + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08001800 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000DE800 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -108,8 +86,8 @@ MEMORY * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', * where 'xx' is the device group; for example, 'cyb06xxa_cm0plus.ld'. */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - cm0p_image (rx) : ORIGIN = (MBED_ROM_START + BOOT_HEADER_SIZE), LENGTH = FLASH_CM0P_SIZE + ram (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_IRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_BANK_IROM1_START + BOOT_HEADER_SIZE, LENGTH = FLASH_CM0P_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. @@ -443,8 +421,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x001D0000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 1c33d606e31..f502632f105 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -47,36 +47,14 @@ ENTRY(Reset_Handler) /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00200000 + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000FD800 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -106,8 +84,8 @@ MEMORY * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + ram (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_IRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE + cm0p_image (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = FLASH_CM0P_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. @@ -440,8 +418,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00200000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 6d51891f5eb..b989a955b5a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -51,32 +51,14 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_ROM_START 0x10000000 #endif -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00045800 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -106,8 +88,8 @@ MEMORY * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + ram (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_IRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE + cm0p_image (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = FLASH_CM0P_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. @@ -440,8 +422,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 6d51891f5eb..4e95682dd70 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -47,36 +47,14 @@ ENTRY(Reset_Handler) /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00045800 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -440,8 +418,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld index 4ce34d8138c..5f85bd55526 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld @@ -47,36 +47,14 @@ ENTRY(Reset_Handler) /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00080000 + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0003D800 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -106,8 +84,8 @@ MEMORY * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + ram (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_IRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE + cm0p_image (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = FLASH_CM0P_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. @@ -440,8 +418,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00080000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 1c33d606e31..f502632f105 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -47,36 +47,14 @@ ENTRY(Reset_Handler) /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00200000 + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000FD800 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -106,8 +84,8 @@ MEMORY * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + ram (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_IRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE + cm0p_image (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = FLASH_CM0P_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. @@ -440,8 +418,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00200000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 6d51891f5eb..82495f0c768 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -47,40 +47,14 @@ ENTRY(Reset_Handler) /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00045800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif /* The size of the stack section at the end of CM4 SRAM */ @@ -106,8 +80,8 @@ MEMORY * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + ram (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_IRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE + cm0p_image (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = FLASH_CM0P_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. @@ -440,8 +414,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld index 6d51891f5eb..4e95682dd70 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -47,36 +47,14 @@ ENTRY(Reset_Handler) /* The size of the Cortex-M0+ application image at the start of FLASH */ FLASH_CM0P_SIZE = 0x2000; -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ +/* + * Figure out start address and size of application, unless overridden by definitions + */ #if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x00100000 + #define MBED_APP_START (MBED_CONFIGURED_ROM_BANK_IROM1_START + FLASH_CM0P_SIZE) #endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08002000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00045800 + #define MBED_APP_SIZE (MBED_CONFIGURED_ROM_BANK_IROM1_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -440,8 +418,8 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; +__cy_memory_0_start = MBED_ROM_BANK_IROM1_START; +__cy_memory_0_length = MBED_ROM_BANK_IROM1_SIZE; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_LPC176X/device/cmsis_nvic.h index 24d51c6d227..2ea4323b43b 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/cmsis_nvic.h +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/cmsis_nvic.h @@ -34,6 +34,4 @@ #define NVIC_NUM_VECTORS (16 + 33) #define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Location of vectors in RAM -#define MBED_RAM_SIZE 0x7F18 // Linker script defines main RAM as 32K - 0xC8 - 32 - #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt index 7440274559c..74f95d48d10 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt @@ -42,4 +42,7 @@ elseif("STM32H7_550MHZ" IN_LIST MBED_TARGET_LABELS) target_sources(mbed-stm32h7 INTERFACE clock_cfg/TARGET_STM32H7_550MHZ/system_clock.c) elseif("STM32H7_280MHZ" IN_LIST MBED_TARGET_LABELS) target_sources(mbed-stm32h7 INTERFACE clock_cfg/TARGET_STM32H7_280MHZ/system_clock.c) -endif() \ No newline at end of file +endif() + +# Add linker scripts +add_subdirectory(linker_scripts) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/CMakeLists.txt index dc72eaeca5c..feb8dd9096b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h745xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/STM32H745xI_CM4.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h745xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h745xI_CM4.sct) endif() add_library(mbed-stm32h745xi-cm4 INTERFACE) @@ -16,11 +14,4 @@ target_sources(mbed-stm32h745xi-cm4 ${STARTUP_FILE} ) -target_include_directories(mbed-stm32h745xi-cm4 - INTERFACE - . -) - -mbed_set_linker_script(mbed-stm32h745xi-cm4 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h745xi-cm4 INTERFACE mbed-stm32h745xi) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/cmsis_nvic.h deleted file mode 100644 index 82b9862fcc7..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/cmsis_nvic.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0x8100000 -#endif - -#if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x100000 // 1.0 MB -#endif - -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x48000 // 288 KB -#endif - - -#define NVIC_NUM_VECTORS 166 -#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/CMakeLists.txt index 2fed652bc2e..23adc8c057d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h745xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/STM32H745xI_CM7.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h745xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h745xI_CM7.sct) endif() add_library(mbed-stm32h745xi-cm7 INTERFACE) @@ -16,11 +14,4 @@ target_sources(mbed-stm32h745xi-cm7 ${STARTUP_FILE} ) -target_include_directories(mbed-stm32h745xi-cm7 - INTERFACE - . -) - -mbed_set_linker_script(mbed-stm32h745xi-cm7 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h745xi-cm7 INTERFACE mbed-stm32h745xi) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/CMakeLists.txt index d864cbf0c25..db11d267cc2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h747xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h747xI_CM4.sct) endif() add_library(mbed-stm32h747xi-cm4 INTERFACE) @@ -16,11 +14,4 @@ target_sources(mbed-stm32h747xi-cm4 ${STARTUP_FILE} ) -target_include_directories(mbed-stm32h747xi-cm4 - INTERFACE - . -) - -mbed_set_linker_script(mbed-stm32h747xi-cm4 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h747xi-cm4 INTERFACE mbed-stm32h747xi) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld deleted file mode 100644 index ea81a18b117..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld +++ /dev/null @@ -1,204 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE - RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/CMakeLists.txt index 942283c79fb..ede32cfd641 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h747xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h747xI_CM7.sct) endif() add_library(mbed-stm32h747xi-cm7 INTERFACE) @@ -16,11 +14,4 @@ target_sources(mbed-stm32h747xi-cm7 ${STARTUP_FILE} ) -target_include_directories(mbed-stm32h747xi-cm7 - INTERFACE - . -) - -mbed_set_linker_script(mbed-stm32h747xi-cm7 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h747xi-cm7 INTERFACE mbed-stm32h747xi) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld deleted file mode 100644 index 68280f47574..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ /dev/null @@ -1,222 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - DTCMRAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_ADDRESS + VECTORS_SIZE, LENGTH = 128K - VECTORS_SIZE - RAM (xrw) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K - RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K - ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - .lwip_sec (NOLOAD) : { - . = ABSOLUTE(0x30040000); - *(.RxDecripSection) - - . = ABSOLUTE(0x30040100); - *(.TxDecripSection) - - . = ABSOLUTE(0x30040400); - *(.RxArraySection) - - . = ABSOLUTE(0x30044000); - *(.ethusbram) - - } >RAM_D2 AT> FLASH -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/cmsis_nvic.h deleted file mode 100644 index dfb59a2114c..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/cmsis_nvic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0x8000000 -#endif - -#if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x100000 // 1.0 MB -#endif - -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x24000000 -#endif - -#if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x80000 // 512 KB -#endif - -// DON'T USE MBED_RAM1_START and MBED_RAM1_SIZE (wrong values in tools/arm_pack_manager/index.json) - -#define NVIC_NUM_VECTORS 166 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/CMakeLists.txt new file mode 100644 index 00000000000..d292a06ac76 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(STM32H745_47_FAMILY) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/CMakeLists.txt new file mode 100644 index 00000000000..50d6742040d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/CMakeLists.txt @@ -0,0 +1,8 @@ +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-stm32h745xi-cm4 STM32H745_H747_CM4.ld) + mbed_set_linker_script(mbed-stm32h747xi-cm4 STM32H745_H747_CM4.ld) +endif() + +# Pick up cmsis-nvic.h +target_include_directories(mbed-stm32h745xi-cm4 INTERFACE .) +target_include_directories(mbed-stm32h747xi-cm4 INTERFACE .) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/TOOLCHAIN_GCC_ARM/STM32H745xI_CM4.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/STM32H745_H747_CM4.ld similarity index 83% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/TOOLCHAIN_GCC_ARM/STM32H745xI_CM4.ld rename to targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/STM32H745_H747_CM4.ld index f0bfaba9147..074a5955d87 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM4/TOOLCHAIN_GCC_ARM/STM32H745xI_CM4.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/STM32H745_H747_CM4.ld @@ -15,16 +15,7 @@ ****************************************************************************** */ -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif +#include "cmsis_nvic.h" #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) /* This value is normally defined by the tools @@ -37,8 +28,12 @@ MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_START, LENGTH = MBED_CONFIGURED_ROM_SIZE + DTCMRAM (rwx) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START + VECTORS_SIZE, LENGTH = 128K - MBED_RAM_BANK_SRAM_DTC_SIZE + RAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D1_START, LENGTH = MBED_RAM_BANK_SRAM_D1_SIZE + RAM_D2 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D2_START, LENGTH = MBED_RAM_BANK_SRAM_D2_SIZE + RAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE + ITCMRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE } /* Linker script to place sections and symbol values. Should be used together @@ -147,7 +142,7 @@ SECTIONS __data_end__ = .; _edata = .; - } > RAM + } > RAM_D2 /* Uninitialized data section * This region is not initialized by the C/C++ library and can be used to @@ -160,7 +155,7 @@ SECTIONS KEEP(*(.keep.uninitialized)) . = ALIGN(32); __uninitialized_end = .; - } > RAM + } > RAM_D2 .bss : { @@ -172,16 +167,16 @@ SECTIONS . = ALIGN(8); __bss_end__ = .; _ebss = .; - } > RAM + } > RAM_D2 .heap (COPY): { __end__ = .; PROVIDE(end = .); *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + . = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - MBED_CONF_TARGET_BOOT_STACK_SIZE; __HeapLimit = .; - } > RAM + } > RAM_D2 /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign @@ -189,11 +184,11 @@ SECTIONS .stack_dummy (COPY): { *(.stack*) - } > RAM + } > RAM_D2 - /* Set stack top to end of RAM, and stack limit move down by + /* Set stack top to end of RAM_D2, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackTop = ORIGIN(RAM_D2) + LENGTH(RAM_D2); _estack = __StackTop; __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; PROVIDE(__stack = __StackTop); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/cmsis_nvic.h similarity index 67% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/cmsis_nvic.h index 9cbfeabf394..56ce36459bb 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/cmsis_nvic.h @@ -17,24 +17,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0x8000000 -#endif - -#if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x100000 // 1.0 MB -#endif - -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x24000000 -#endif - -#if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x80000 // 512 KB -#endif - - #define NVIC_NUM_VECTORS 166 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_BANK_SRAM_D2_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/CMakeLists.txt new file mode 100644 index 00000000000..a683d366764 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/CMakeLists.txt @@ -0,0 +1,8 @@ +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-stm32h745xi-cm7 STM32H745_H747_CM7.ld) + mbed_set_linker_script(mbed-stm32h747xi-cm7 STM32H745_H747_CM7.ld) +endif() + +# Pick up cmsis-nvic.h +target_include_directories(mbed-stm32h745xi-cm7 INTERFACE .) +target_include_directories(mbed-stm32h747xi-cm7 INTERFACE .) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/TOOLCHAIN_GCC_ARM/STM32H745xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld similarity index 86% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/TOOLCHAIN_GCC_ARM/STM32H745xI_CM7.ld rename to targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld index 68280f47574..57c2dc9e043 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_STM32H745xI_CM7/TOOLCHAIN_GCC_ARM/STM32H745xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld @@ -15,16 +15,7 @@ ****************************************************************************** */ -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif +#include "cmsis_nvic.h" #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) /* This value is normally defined by the tools @@ -37,12 +28,12 @@ MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - DTCMRAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_ADDRESS + VECTORS_SIZE, LENGTH = 128K - VECTORS_SIZE - RAM (xrw) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K - RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K - ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_START, LENGTH = MBED_CONFIGURED_ROM_SIZE + DTCMRAM (rwx) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START + VECTORS_SIZE, LENGTH = 128K - MBED_RAM_BANK_SRAM_DTC_SIZE + RAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D1_START, LENGTH = MBED_RAM_BANK_SRAM_D1_SIZE + RAM_D2 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D2_START, LENGTH = MBED_RAM_BANK_SRAM_D2_SIZE + RAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE + ITCMRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE } /* Linker script to place sections and symbol values. Should be used together @@ -206,16 +197,16 @@ SECTIONS ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") .lwip_sec (NOLOAD) : { - . = ABSOLUTE(0x30040000); + . = ABSOLUTE(0x10040000); *(.RxDecripSection) - . = ABSOLUTE(0x30040100); + . = ABSOLUTE(0x10040100); *(.TxDecripSection) - . = ABSOLUTE(0x30040400); + . = ABSOLUTE(0x10040400); *(.RxArraySection) - . = ABSOLUTE(0x30044000); + . = ABSOLUTE(0x10044000); *(.ethusbram) } >RAM_D2 AT> FLASH diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/cmsis_nvic.h similarity index 67% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/cmsis_nvic.h index 82b9862fcc7..9eb1b99bead 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/cmsis_nvic.h @@ -17,24 +17,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0x8100000 -#endif - -#if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x100000 // 1.0 MB -#endif - -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x48000 // 288 KB -#endif - - #define NVIC_NUM_VECTORS 166 -#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_BANK_SRAM_DTC_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CMakeLists.txt new file mode 100644 index 00000000000..3430dff8aa7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CMakeLists.txt @@ -0,0 +1,2 @@ +add_subdirectory(CM7) +add_subdirectory(CM4) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/TOOLCHAIN_GCC_ARM/stm32wb10xc.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/TOOLCHAIN_GCC_ARM/stm32wb10xc.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/TOOLCHAIN_GCC_ARM/stm32wb10xc.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/TOOLCHAIN_GCC_ARM/stm32wb10xc.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/cmsis_nvic.h index 9d55636da21..3a744981bd8 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB10xC/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x0 // 0 B #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld index ed217f3d9db..3552d40decc 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld @@ -24,8 +24,8 @@ #if !defined(MBED_APP_SIZE) /* MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH */ -/* Size is defined in json with "mbed_rom_size" */ -#define MBED_APP_SIZE MBED_ROM_SIZE +/* Size is defined in json with "memory_bank_config" */ +#define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h index 38da1db06f5..081f4c30655 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h @@ -21,10 +21,10 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) // MBED_ROM_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH -// Size is defined in json with "mbed_rom_size" -#error "mbed_rom_size is missing" +// Size is defined in json with "memory_bank_config" +#error "memory_bank_config is missing" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/TOOLCHAIN_GCC_ARM/stm32wb30xe.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/TOOLCHAIN_GCC_ARM/stm32wb30xe.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/TOOLCHAIN_GCC_ARM/stm32wb30xe.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/TOOLCHAIN_GCC_ARM/stm32wb30xe.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/cmsis_nvic.h index 9d55636da21..3a744981bd8 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB30xE/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x0 // 0 B #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/TOOLCHAIN_GCC_ARM/stm32wb35xc.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/TOOLCHAIN_GCC_ARM/stm32wb35xc.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/TOOLCHAIN_GCC_ARM/stm32wb35xc.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/TOOLCHAIN_GCC_ARM/stm32wb35xc.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/cmsis_nvic.h index 9d55636da21..3a744981bd8 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xC/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x0 // 0 B #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/TOOLCHAIN_GCC_ARM/stm32wb35xe.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/TOOLCHAIN_GCC_ARM/stm32wb35xe.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/TOOLCHAIN_GCC_ARM/stm32wb35xe.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/TOOLCHAIN_GCC_ARM/stm32wb35xe.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/cmsis_nvic.h index 9d55636da21..3a744981bd8 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB35xE/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x0 // 0 B #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/TOOLCHAIN_GCC_ARM/stm32wb50xg.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/TOOLCHAIN_GCC_ARM/stm32wb50xg.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/TOOLCHAIN_GCC_ARM/stm32wb50xg.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/TOOLCHAIN_GCC_ARM/stm32wb50xg.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/cmsis_nvic.h index 94baef07e1b..09e2f64f35d 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB50xG/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x100000 #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/TOOLCHAIN_GCC_ARM/stm32wb55xc.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/TOOLCHAIN_GCC_ARM/stm32wb55xc.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/TOOLCHAIN_GCC_ARM/stm32wb55xc.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/TOOLCHAIN_GCC_ARM/stm32wb55xc.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/cmsis_nvic.h index 37c808cb151..0ac74face27 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xC/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x40000 // 256 KB #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/TOOLCHAIN_GCC_ARM/stm32wb55xe.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/TOOLCHAIN_GCC_ARM/stm32wb55xe.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/TOOLCHAIN_GCC_ARM/stm32wb55xe.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/TOOLCHAIN_GCC_ARM/stm32wb55xe.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/cmsis_nvic.h index 37e88c39cc5..ca45527e66b 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xE/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x80000 // 512 KB #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld index e29ce7789d7..2a970dfc31a 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld @@ -24,8 +24,8 @@ #if !defined(MBED_APP_SIZE) // MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH -// Size is defined in json with "mbed_rom_size" -#define MBED_APP_SIZE MBED_ROM_SIZE +// Size is defined in json with "memory_bank_config" +#define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h index e434ab60007..ccf54e4ac90 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h @@ -21,10 +21,10 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) // MBED_ROM_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH -// Size is defined in json with "mbed_rom_size" -#error "mbed_rom_size is missing" +// Size is defined in json with "memory_bank_config" +#error "memory_bank_config is missing" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/TOOLCHAIN_GCC_ARM/stm32wb55xy.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/TOOLCHAIN_GCC_ARM/stm32wb55xy.ld index 5f479936c85..46517811112 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/TOOLCHAIN_GCC_ARM/stm32wb55xy.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/TOOLCHAIN_GCC_ARM/stm32wb55xy.ld @@ -23,7 +23,7 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/cmsis_nvic.h index 9d55636da21..3a744981bd8 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xY/cmsis_nvic.h @@ -21,7 +21,7 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) #define MBED_ROM_SIZE 0x0 // 0 B #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld index e29ce7789d7..2a970dfc31a 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld @@ -24,8 +24,8 @@ #if !defined(MBED_APP_SIZE) // MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH -// Size is defined in json with "mbed_rom_size" -#define MBED_APP_SIZE MBED_ROM_SIZE +// Size is defined in json with "memory_bank_config" +#define MBED_APP_SIZE MBED_CONFIGURED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h index e434ab60007..ccf54e4ac90 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h @@ -21,10 +21,10 @@ #define MBED_ROM_START 0x8000000 #endif -#if !defined(MBED_ROM_SIZE) +#if !defined(MBED_CONFIGURED_ROM_SIZE) // MBED_ROM_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH -// Size is defined in json with "mbed_rom_size" -#error "mbed_rom_size is missing" +// Size is defined in json with "memory_bank_config" +#error "memory_bank_config is missing" #endif #if !defined(MBED_RAM_START) diff --git a/targets/cmsis_mcu_descriptions.json5 b/targets/cmsis_mcu_descriptions.json5 index 641a65f03e6..5dd1b5a932a 100644 --- a/targets/cmsis_mcu_descriptions.json5 +++ b/targets/cmsis_mcu_descriptions.json5 @@ -327,8 +327,8 @@ "write": true }, "default": true, - "size": 262144, - "start": 134217728, + "size": 0x40000, + "start": 0x08000000, "startup": false }, "IROM1": { @@ -461,8 +461,8 @@ "write": true }, "default": true, - "size": 294912, - "start": 134217728, + "size": 0x48000, + "start": 0x08000000, "startup": false }, "IROM1": { @@ -595,8 +595,8 @@ "write": true }, "default": true, - "size": 294912, - "start": 134217728, + "size": 0x48000, + "start": 0x08000000, "startup": false }, "IROM1": { @@ -729,8 +729,8 @@ "write": true }, "default": true, - "size": 1048576, - "start": 134217728, + "size": 0x100000, + "start": 0x08000000, "startup": false }, "IROM1": { @@ -744,8 +744,8 @@ "write": false }, "default": true, - "size": 2097152, - "start": 268435456, + "size": 0x200000, + "start": 0x10000000, "startup": true } }, @@ -980,8 +980,8 @@ }, "default": true, "p_name": null, - "size": 1048576, - "start": 134217728, + "size": 0x100000, + "start": 0x08000000, "startup": false }, "IROM1": { @@ -7552,7 +7552,7 @@ "version": "2.7.0" }, "memories": { - "IRAM1": { + "SRAM_D2": { "access": { "execute": true, "non_secure": false, @@ -7563,13 +7563,13 @@ "write": true }, "default": true, - "size": 131072, - "start": 536870912, + "size": 0x8000, + "start": 0x30000000, "startup": false }, - "IRAM2": { + "SRAM_D1": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -7578,8 +7578,8 @@ "write": true }, "default": true, - "size": 327680, - "start": 603979776, + "size": 0x50000, + "start": 0x24000000, "startup": false }, "IROM1": { @@ -7593,13 +7593,13 @@ "write": false }, "default": true, - "size": 1048576, - "start": 134217728, + "size": 0x200000, + "start": 0x08000000, "startup": true }, - "RAM_D2": { + "SRAM_D3": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -7608,11 +7608,26 @@ "write": true }, "default": true, - "size": 32768, - "start": 805306368, + "size": 0x4000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, "startup": false }, - "RAM_D3": { + "SRAM_ITC": { "access": { "execute": true, "non_secure": false, @@ -7622,9 +7637,23 @@ "secure": false, "write": true }, - "default": true, - "size": 16384, - "start": 939524096, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, "startup": false } }, @@ -7665,7 +7694,7 @@ "version": "2.7.0" }, "memories": { - "IRAM1": { + "SRAM_D2": { "access": { "execute": true, "non_secure": false, @@ -7676,13 +7705,13 @@ "write": true }, "default": true, - "size": 131072, - "start": 536870912, + "size": 0x8000, + "start": 0x30000000, "startup": false }, - "IRAM2": { + "SRAM_D1": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -7691,8 +7720,8 @@ "write": true }, "default": true, - "size": 131072, - "start": 603979776, + "size": 0x50000, + "start": 0x24000000, "startup": false }, "IROM1": { @@ -7706,13 +7735,13 @@ "write": false }, "default": true, - "size": 524288, - "start": 134217728, + "size": 0x200000, + "start": 0x08000000, "startup": true }, - "RAM_D2": { + "SRAM_D3": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -7721,11 +7750,26 @@ "write": true }, "default": true, - "size": 16384, - "start": 805306368, + "size": 0x4000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, "startup": false }, - "RAM_D3": { + "SRAM_ITC": { "access": { "execute": true, "non_secure": false, @@ -7735,9 +7779,23 @@ "secure": false, "write": true }, - "default": true, - "size": 16384, - "start": 805322752, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, "startup": false } }, @@ -7759,15 +7817,142 @@ "sub_family": "STM32H725", "vendor": "STMicroelectronics:13" }, - "STM32H743ZITx": { + "STM32H735AGIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "file_name": "CMSIS/Flash/STM32H72x-73x_1024.FLM", "ram_size": 32768, "ram_start": 536870912, - "size": 2097152, - "start": 134217728 + "size": 1048576, + "start": 134217728, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7B3I_EVAL_FMC-NOR.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 1610612736, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H747I-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MTFC4GACAJCN_STM32H750B-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 536870912, + "start": 2684354560, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 16777216, + "start": 1610612736, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B3I-EVAL.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B3I-Disco.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B0-EVAL.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B0-Disco.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H735-Disco.FLM", + "ram_size": 65524, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H747I-EVAL.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" } ], "family": "STM32H7 Series", @@ -7775,10 +7960,10 @@ "pack": "STM32H7xx_DFP", "url": "https://www.keil.com/pack/", "vendor": "Keil", - "version": "2.3.1" + "version": "3.1.1" }, "memories": { - "IRAM1": { + "SRAM_D2": { "access": { "execute": true, "non_secure": false, @@ -7789,13 +7974,13 @@ "write": true }, "default": true, - "size": 131072, - "start": 536870912, + "size": 0x8000, + "start": 0x30000000, "startup": false }, - "IRAM2": { + "SRAM_D1": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -7804,8 +7989,8 @@ "write": true }, "default": true, - "size": 524288, - "start": 603979776, + "size": 0x50000, + "start": 0x24000000, "startup": false }, "IROM1": { @@ -7819,13 +8004,13 @@ "write": false }, "default": true, - "size": 2097152, - "start": 134217728, + "size": 0x200000, + "start": 0x08000000, "startup": true }, - "RAM_D2": { + "SRAM_D3": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -7834,11 +8019,26 @@ "write": true }, "default": true, - "size": 294912, - "start": 805306368, + "size": 0x4000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, "startup": false }, - "RAM_D3": { + "SRAM_ITC": { "access": { "execute": true, "non_secure": false, @@ -7848,9 +8048,166 @@ "secure": false, "write": true }, - "default": true, - "size": 65536, - "start": 939524096, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, + "startup": false + } + }, + "name": "STM32H735AGIx", + "processors": [ + { + "address": null, + "ap": 0, + "apid": null, + "core": "CortexM7", + "default_reset_sequence": null, + "dp": 0, + "fpu": "DoublePrecision", + "mpu": "Present", + "name": null, + "svd": "CMSIS/SVD/STM32H735.svd", + "unit": 0 + } + ], + "sub_family": "STM32H735", + "vendor": "STMicroelectronics:13" + }, + "STM32H743ZITx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.3.1" + }, + "memories": { + "SRAM_D2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x48000, + "start": 0x30000000, + "startup": false + }, + "SRAM_D1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x80000, + "start": 0x24000000, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x200000, + "start": 0x08000000, + "startup": true + }, + "SRAM_D3": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x10000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, + "startup": false + }, + "SRAM_ITC": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, "startup": false } }, @@ -7959,7 +8316,9 @@ "version": "2.3.1" }, "memories": { - "IRAM1": { + // SRAM_D2 normally exists at 0x30000000 but apparently to use it from the M4 CPU, + // we need to use its alias at 0x10000000 + "SRAM_D2": { "access": { "execute": false, "non_secure": false, @@ -7970,11 +8329,11 @@ "write": true }, "default": true, - "size": 294912, - "start": 268435456, + "size": 0x48000, + "start": 0x10000000, "startup": false }, - "IRAM2": { + "SRAM_D1": { "access": { "execute": false, "non_secure": false, @@ -7985,8 +8344,8 @@ "write": true }, "default": true, - "size": 524288, - "start": 603979776, + "size": 0x80000, + "start": 0x24000000, "startup": false }, "IROM1": { @@ -8000,11 +8359,11 @@ "write": false }, "default": true, - "size": 1048576, - "start": 135266304, + "size": 0x200000, + "start": 0x08000000, "startup": true }, - "RAM_D3": { + "SRAM_D3": { "access": { "execute": false, "non_secure": false, @@ -8015,8 +8374,52 @@ "write": true }, "default": true, - "size": 65536, - "start": 939524096, + "size": 0x10000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, + "startup": false + }, + "SRAM_ITC": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, "startup": false } }, @@ -8077,56 +8480,771 @@ "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", "ram_size": 32768, "ram_start": 536870912, - "size": 2097152, - "start": 134217728 + "size": 2097152, + "start": 134217728 + }, + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 268435456, + "size": 2097152, + "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 67108864, + "start": 2415919104 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104 + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104 + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 16777216, + "start": 1610612736 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.3.1" + }, + "memories": { + // SRAM_D2 normally exists at 0x30000000 but apparently to use it from the M4 CPU, + // we need to use its alias at 0x10000000 + "SRAM_D2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x48000, + "start": 0x10000000, + "startup": false + }, + "SRAM_D1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x80000, + "start": 0x24000000, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x200000, + "start": 0x08000000, + "startup": true + }, + "SRAM_D3": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x10000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, + "startup": false + }, + "SRAM_ITC": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, + "startup": false + } + }, + "name": "STM32H747XIHx:CM7", + "processor": { + "Asymmetric": { + "CM4": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + }, + "CM7": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + } + }, + "sectors": [ + [ + 134217728, + 131072 + ], + [ + 134217728, + 131072 + ], + [ + 1610612736, + 131072 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 131072 + ], + [ + 2415919104, + 131072 + ] + ], + "sub_family": "STM32H747", + "vendor": "STMicroelectronics:13" + }, + "STM32H750ZBTx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_128k.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 131072, + "start": 134217728, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7B3I_EVAL_FMC-NOR.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 1610612736, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H747I-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MTFC4GACAJCN_STM32H750B-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 536870912, + "start": 2684354560, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 16777216, + "start": 1610612736, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B3I-EVAL.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B3I-Disco.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B0-EVAL.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B0-Disco.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H735-Disco.FLM", + "ram_size": 65524, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H747I-EVAL.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "3.1.1" + }, + "memories": { + "SRAM_D2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x48000, + "start": 0x30000000, + "startup": false + }, + "SRAM_D1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x80000, + "start": 0x24000000, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x20000, + "start": 0x08000000, + "startup": true + }, + "SRAM_D3": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x10000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, + "startup": false + }, + "SRAM_ITC": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, + "startup": false + } + }, + "name": "STM32H750ZBTx", + "processors": [ + { + "address": null, + "ap": 0, + "apid": null, + "core": "CortexM7", + "default_reset_sequence": null, + "dp": 0, + "fpu": "DoublePrecision", + "mpu": "Present", + "name": null, + "svd": "CMSIS/SVD/STM32H750.svd", + "unit": 0 + } + ], + "sub_family": "STM32H750", + "vendor": "STMicroelectronics:13" + }, + "STM32H7A3ZITxQ": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.7.0" + }, + "memories": { + "SRAM_AHB": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x20000, + "start": 0x30000000, + "startup": false + }, + "SRAM_AXI": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x100000, + "start": 0x24000000, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x20000, + "start": 0x08000000, + "startup": true + }, + "SRAM_D3": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 0x8000, + "start": 0x38000000, + "startup": false + }, + "SRAM_DTC": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x20000, + "start": 0x20000000, + "startup": false + }, + "SRAM_ITC": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x10000, + "start": 0, + "startup": false + }, + "SRAM_BKUP": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "size": 0x1000, + "start": 0x38800000, + "startup": false + } + }, + "name": "STM32H7A3ZITxQ", + "processor": { + "Symmetric": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 131072 + ] + ], + "sub_family": "STM32H7A3", + "vendor": "STMicroelectronics:13" + }, + "STM32H7B3ZITxQ": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7A-B3_Flash_2M.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7B3I_EVAL_FMC-NOR.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 1610612736, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H747I-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MTFC4GACAJCN_STM32H750B-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 536870912, + "start": 2684354560, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 134217728, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", + "ram_size": 65524, + "ram_start": 536870912, + "size": 16777216, + "start": 1610612736, + "style": "Keil" }, { - "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 268435456, - "size": 2097152, - "start": 134217728 + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B3I-EVAL.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" }, { "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B3I-Disco.FLM", + "ram_size": 655360, + "ram_start": 603979776, "size": 67108864, - "start": 2415919104 + "start": 2415919104, + "style": "Keil" }, { "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B0-EVAL.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" }, { "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H7B0-Disco.FLM", + "ram_size": 655360, + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" + }, + { + "default": false, + "file_name": "CMSIS/Flash/MX25LM51245G_STM32H735-Disco.FLM", "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 + "ram_start": 603979776, + "size": 67108864, + "start": 2415919104, + "style": "Keil" }, { "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", + "file_name": "CMSIS/Flash/MT25TL01G_STM32H747I-EVAL.FLM", "ram_size": 65524, "ram_start": 536870912, "size": 134217728, - "start": 2415919104 + "start": 2415919104, + "style": "Keil" }, { "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", + "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", "ram_size": 65524, "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 + "size": 134217728, + "start": 2415919104, + "style": "Keil" } ], "family": "STM32H7 Series", @@ -8134,12 +9252,12 @@ "pack": "STM32H7xx_DFP", "url": "https://www.keil.com/pack/", "vendor": "Keil", - "version": "2.3.1" + "version": "3.1.1" }, "memories": { - "IRAM1": { + "SRAM_AHB": { "access": { - "execute": false, + "execute": true, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -8148,11 +9266,11 @@ "write": true }, "default": true, - "size": 294912, - "start": 268435456, + "size": 0x20000, + "start": 0x30000000, "startup": false }, - "IRAM2": { + "SRAM_AXI": { "access": { "execute": false, "non_secure": false, @@ -8163,8 +9281,8 @@ "write": true }, "default": true, - "size": 524288, - "start": 603979776, + "size": 0x100000, + "start": 0x24000000, "startup": false }, "IROM1": { @@ -8178,11 +9296,11 @@ "write": false }, "default": true, - "size": 1048576, - "start": 135266304, + "size": 0x20000, + "start": 0x08000000, "startup": true }, - "RAM_D3": { + "SRAM_D3": { "access": { "execute": false, "non_secure": false, @@ -8193,83 +9311,13 @@ "write": true }, "default": true, - "size": 65536, - "start": 939524096, + "size": 0x8000, + "start": 0x38000000, "startup": false - } - }, - "name": "STM32H747XIHx:CM7", - "processor": { - "Asymmetric": { - "CM4": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - }, - "CM7": { - "core": "CortexM7", - "fpu": "DoublePrecision", - "mpu": "Present", - "units": 1 - } - } - }, - "sectors": [ - [ - 134217728, - 131072 - ], - [ - 134217728, - 131072 - ], - [ - 1610612736, - 131072 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 131072 - ], - [ - 2415919104, - 131072 - ] - ], - "sub_family": "STM32H747", - "vendor": "STMicroelectronics:13" - }, - "STM32H7A3ZITxQ": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 536870912, - "size": 2097152, - "start": 134217728 - } - ], - "family": "STM32H7 Series", - "from_pack": { - "pack": "STM32H7xx_DFP", - "url": "https://www.keil.com/pack/", - "vendor": "Keil", - "version": "2.7.0" - }, - "memories": { - "IRAM1": { + }, + "SRAM_DTC": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -8277,12 +9325,12 @@ "secure": false, "write": true }, - "default": true, - "size": 1048576, - "start": 603979776, + "default": false, + "size": 0x20000, + "start": 0x20000000, "startup": false }, - "IRAM2": { + "SRAM_ITC": { "access": { "execute": true, "non_secure": false, @@ -8292,43 +9340,43 @@ "secure": false, "write": true }, - "default": true, - "size": 131072, - "start": 536870912, + "default": false, + "size": 0x10000, + "start": 0, "startup": false }, - "IROM1": { + "SRAM_BKUP": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, "read": true, "secure": false, - "write": false + "write": true }, - "default": true, - "size": 2097152, - "start": 134217728, - "startup": true + "size": 0x1000, + "start": 0x38800000, + "startup": false } }, - "name": "STM32H7A3ZITxQ", - "processor": { - "Symmetric": { + "name": "STM32H7B3ZITxQ", + "processors": [ + { + "address": null, + "ap": 0, + "apid": null, "core": "CortexM7", + "default_reset_sequence": null, + "dp": 0, "fpu": "DoublePrecision", "mpu": "Present", - "units": 1 + "name": null, + "svd": "CMSIS/SVD/STM32H7B3.svd", + "unit": 0 } - }, - "sectors": [ - [ - 134217728, - 131072 - ] ], - "sub_family": "STM32H7A3", + "sub_family": "STM32H7B3", "vendor": "STMicroelectronics:13" }, "STM32L072CZTx": { @@ -12932,6 +13980,78 @@ "sub_family": "STM32WL55", "vendor": "STMicroelectronics:13" }, + "STM32WLE5JCIx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32WLxx_CM4.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 262144, + "start": 134217728, + "style": "Keil" + } + ], + "family": "STM32WL Series", + "from_pack": { + "pack": "STM32WLxx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.2.0" + }, + "memories": { + "FLASH": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "p_name": null, + "size": 0x40000, + "start": 0x08000000, + "startup": true + }, + "SRAM": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 0x10000, + "start": 0x20000000, + "startup": false + }, + }, + "name": "STM32WLE5JCIx", + "processors": [ + { + "address": null, + "ap": 0, + "apid": null, + "core": "CortexM4", + "default_reset_sequence": null, + "dp": 0, + "fpu": "None", + "mpu": "Present", + "name": null, + "svd": "CMSIS/SVD/STM32WLE5_CM4.svd", + "unit": 0 + } + ], + "sub_family": "STM32WLE5", + "vendor": "STMicroelectronics:13" + }, "TMPM46BF10FG": { "algorithms": [ { diff --git a/targets/targets.json5 b/targets/targets.json5 index b5e2d4a2053..3a7ed73a463 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3311,10 +3311,6 @@ ], "public": false, "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x100000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x50000", "extra_labels_add": [ "STM32H735xG", "STM32H7_550MHZ" @@ -3324,7 +3320,8 @@ ], "overrides": { "system_power_supply": "PWR_LDO_SUPPLY" - } + }, + "device_name": "STM32H735AGIx" }, "MCU_STM32H743xI": { "inherits": [ @@ -3426,7 +3423,8 @@ "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", // Cannot enable overdrive mode because the default power supply is SMPS "enable-overdrive-mode": 0 - } + }, + "device_name": "STM32H745ZITx" }, "MCU_STM32H745xI_CM4": { "inherits": [ @@ -3437,10 +3435,13 @@ "STM32H745xI_CM4" ], "core": "Cortex-M4F", - "mbed_rom_start": "0x08100000", - "mbed_rom_size": "0x100000", - "mbed_ram_start": "0x10000000", - "mbed_ram_size": "0x48000", + "memory_bank_config": { + // Select flash bank 2 + "IROM1": { + "start": 0x08100000, + "size": 0x100000 + } + }, "macros_add": [ "CORE_CM4" ] @@ -3454,10 +3455,13 @@ "STM32H745xI_CM7" ], "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x100000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x80000", + "memory_bank_config": { + // Select flash bank 1 + "IROM1": { + "start": 0x08000000, + "size": 0x100000 + } + }, "macros_add": [ "CORE_CM7" ] @@ -3487,7 +3491,6 @@ "overrides": { "network-default-interface-type": "ETHERNET" }, - "device_name": "STM32H745ZITx", "image_url": "https://www.st.com/bin/ecommerce/api/image.PF262651.en.feature-description-include-personalized-no-cpn-medium.jpg" }, "NUCLEO_H745ZI_Q_CM4": { @@ -3515,7 +3518,6 @@ "overrides": { "network-default-interface-type": "ETHERNET" }, - "device_name": "STM32H745ZITx", "image_url": "https://www.st.com/bin/ecommerce/api/image.PF262651.en.feature-description-include-personalized-no-cpn-medium.jpg" }, "NUCLEO_H745ZI_Q" : { @@ -3550,10 +3552,13 @@ "STM32H747xI_CM7" ], "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x100000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x80000", + "memory_bank_config": { + // Select flash bank 1 + "IROM1": { + "start": 0x08000000, + "size": 0x100000 + } + }, "macros_add": [ "CORE_CM7" ] @@ -3598,10 +3603,13 @@ "STM32H747xI_CM4" ], "core": "Cortex-M4F", - "mbed_rom_start": "0x08100000", - "mbed_rom_size": "0x100000", - "mbed_ram_start": "0x10000000", - "mbed_ram_size": "0x48000", + "memory_bank_config": { + // Select flash bank 2 + "IROM1": { + "start": 0x08100000, + "size": 0x100000 + } + }, "macros_add": [ "CORE_CM4" ], @@ -3690,10 +3698,13 @@ "ARDUINO_PORTENTA_H7_M7": { "inherits": ["ARDUINO_PORTENTA_H7"], "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size" : "0x100000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size" : "0x80000", + "memory_bank_config": { + // Select flash bank 1 + "IROM1": { + "start": 0x08000000, + "size": 0x100000 + } + }, "extra_labels_add": [ "STM32H747xI_CM7" ], @@ -3704,10 +3715,13 @@ "ARDUINO_PORTENTA_H7_M4": { "inherits": ["ARDUINO_PORTENTA_H7"], "core": "Cortex-M4F", - "mbed_rom_start": "0x08100000", - "mbed_rom_size" : "0x100000", - "mbed_ram_start": "0x10000000", - "mbed_ram_size" : "0x48000", + "memory_bank_config": { + // Select flash bank 2 + "IROM1": { + "start": 0x08100000, + "size": 0x100000 + } + }, "extra_labels_add": [ "STM32H747xI_CM4" ], @@ -3725,10 +3739,6 @@ ], "public": false, "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x20000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x80000", "extra_labels_add": [ "STM32H750xB", "STM32H7_480MHZ" @@ -3738,7 +3748,8 @@ ], "overrides": { "system_power_supply": "PWR_LDO_SUPPLY" - } + }, + "device_name": "STM32H750ZBTx" }, "MCU_STM32H753xI": { "inherits": [ @@ -3763,10 +3774,6 @@ ], "public": false, "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x200000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x100000", "extra_labels_add": [ "STM32H7A3xIQ" ], @@ -3774,6 +3781,7 @@ "STM32H7A3xxQ", "STM32H7_280MHZ" ], + "device_name": "STM32H7A3ZITxQ", "overrides": { "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", // Cannot enable overdrive mode because the default power supply is SMPS @@ -3787,7 +3795,6 @@ "supported_form_factors": [ "ARDUINO_UNO" ], - "device_name": "STM32H7A3ZITxQ", "detect_code": [ "0860" ], @@ -3799,10 +3806,6 @@ ], "public": false, "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x200000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x100000", "extra_labels_add": [ "STM32H7B3xIQ", "STM32H7_280MHZ" @@ -3810,6 +3813,7 @@ "macros_add": [ "STM32H7B3xxQ" ], + "device_name": "STM32H7B3ZITxQ", "overrides": { "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", // Cannot enable overdrive mode because the default power supply is SMPS @@ -4934,16 +4938,13 @@ "MCU_STM32U5" ], "public": false, - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x80000", - "mbed_ram_start": "0x20000000", - "mbed_ram_size": "0x40000", "extra_labels_add": [ "STM32U545xE" ], "macros_add": [ "STM32U545xx" - ] + ], + "device_name": "STM32U545RETx" }, "NUCLEO_U545RE_Q": { "inherits": [ @@ -4953,7 +4954,7 @@ "supported_form_factors": [ "ARDUINO_UNO" ], - "device_name": "STM32U545RETx", + "overrides": { // As shipped, this nucleo board connects VREFP to VDD_MCU, and connects VDD_MCU to 3.3V. // Jumper JP5 can be used to switch VDD_MCU to 1.8V in which case you should override this setting to 1.8. @@ -4966,10 +4967,7 @@ "MCU_STM32U5" ], "public": false, - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x400000", - "mbed_ram_start": "0x20000000", - "mbed_ram_size": "0x270000", + "device_name": "STM32U5A5ZJTx", "extra_labels_add": [ "STM32U5A5xJ" ], @@ -4985,7 +4983,6 @@ "supported_form_factors": [ "ARDUINO_UNO" ], - "device_name": "STM32U5A5ZJTx", "overrides": { // As shipped, this nucleo board connects VREFP to VDD_MCU, and connects VDD_MCU to 3.3V. // Jumper JP4 can be used to switch VDD_MCU to 1.8V in which case you should override this setting to 1.8. @@ -5005,7 +5002,6 @@ "STM32WB", "CORDIO" ], - "mbed_rom_start": "0x08000000", "config": { "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", @@ -5051,7 +5047,14 @@ "extra_labels_add": [ "STM32WB15xC" ], - "mbed_rom_size": "0x32800", + "device_name": "STM32WB15CCUx", + + // Reduce used flash to make room for the M0 core firmware + "memory_bank_config": { + "IROM1": { + "size": 0x32800 // 202kiB + } + }, "overrides": { "boot-stack-size": "0x400" }, @@ -5069,7 +5072,6 @@ "detect_code": [ "0883" ], - "device_name": "STM32WB15CCUx", "image_url": "https://www.mouser.com/images/stmicroelectronics/hd/NUCLEO-WB15CC_SPL.jpg" }, "MCU_STM32WB55xG": { @@ -5080,7 +5082,14 @@ "extra_labels_add": [ "STM32WB55xG" ], - "mbed_rom_size": "0xCA000", + "device_name": "STM32WB55RGVx", + + // Reduce used flash to make room for the M0 core firmware + "memory_bank_config": { + "IROM1": { + "size": 0xCA000 // 808kiB + } + }, "macros_add": [ "STM32WB55xx", "MBEDTLS_CONFIG_HW_SUPPORT" @@ -5099,7 +5108,6 @@ "device_has_add": [ "USBDEVICE" ], - "device_name": "STM32WB55RGVx", "image_url": "https://www.mouser.com/images/stmicroelectronics/hd/NUCLEO-WB15CC_SPL.jpg" }, "MCU_STM32WB5MxG": { @@ -5110,7 +5118,15 @@ "extra_labels_add": [ "STM32WB5MxG" ], - "mbed_rom_size": "0xCA000", + "device_name": "STM32WB55VGYx", + + // Reduce used flash to make room for the M0 core firmware + "memory_bank_config": { + "IROM1": { + "size": 0xCA000 // 808kiB + } + }, + "macros_add": [ "STM32WB5Mxx", "MBEDTLS_CONFIG_HW_SUPPORT" @@ -5126,7 +5142,6 @@ "detect_code": [ "0884" ], - "device_name": "STM32WB55VGYx", "image_url": "https://www.st.com/bin/ecommerce/api/image.PF271050.en.feature-description-include-personalized-no-cpn-large.jpg" }, @@ -5182,7 +5197,8 @@ ], "macros_add": [ "STM32WL55xx" - ] + ], + "device_name": "STM32WL55JCIx" }, "NUCLEO_WL55JC": { "inherits": [ @@ -5194,7 +5210,6 @@ "detect_code": [ "0866" ], - "device_name": "STM32WL55JCIx", "image_url": "https://www.mouser.com/images/marketingid/2020/img/114771861.png?v=012324.0355" }, "MCU_STM32WLE5xC": { @@ -5208,10 +5223,7 @@ "extra_labels_add": [ "STM32WLE5xC" ], - "mbed_rom_start": "0x8000000", - "mbed_rom_size": "0x40000", - "mbed_ram_start": "0x20000000", - "mbed_ram_size": "0x10000" + "device_name": "STM32WLE5JCIx" }, // NXP i.MX RT Targets --------------------------------------------------------------------------------------------- @@ -5309,6 +5321,35 @@ "overrides": { "network-default-interface-type": "ETHERNET" }, + "memory_banks": { + "SDRAM": { + "access": { + "execute": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x10000000, // 256MiB + "start": 0x80000000, + "startup": false + }, + // MIMXRT1050 EVK uses hyperflash by default + "EXT_FLASH": { + "access": { + "execute": true, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x4000000, // 64MiB + "start": 0x60000000, + "startup": true + } + }, "bootloader_supported": true, "device_name": "MIMXRT1052DVL6A", "image_url": "https://www.nxp.com/assets/images/en/dev-board-image/IMX_RT1050-EVKB_TOP-LR.jpg" @@ -5335,6 +5376,35 @@ "overrides": { "network-default-interface-type": "ETHERNET" }, + "memory_banks": { + "SDRAM": { + "access": { + "execute": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x10000000, // 256MiB + "start": 0x80000000, + "startup": false + }, + // MIMXRT1050 EVK uses QSPI flash by default + "EXT_FLASH": { + "access": { + "execute": true, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x800000, // 8MiB + "start": 0x60000000, + "startup": true + } + }, "device_name": "MIMXRT1062DVL6B", "image_url": "https://www.nxp.com/assets/images/en/dev-board-image/X-MIMXRT1060-EVK-BOARD-BOTTOM.jpg" }, @@ -6105,8 +6175,22 @@ ], "device_name": "R7S72100", "bootloader_supported": true, - "mbed_rom_start": "0x18000000", - "mbed_rom_size": "0x800000", + // 8MB serial flash on the board + "memory_banks": { + "EXT_FLASH": { + "access": { + "execute": true, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x800000, // 8MiB + "start": 0x18000000, + "startup": true + } + }, "sectors": [ [ 402653184, @@ -6146,8 +6230,21 @@ ], "device_name": "R7S72103", "bootloader_supported": true, - "mbed_rom_start": "0x18000000", - "mbed_rom_size": "0x800000", + "memory_banks": { + "EXT_FLASH": { + "access": { + "execute": true, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x800000, // 8MiB + "start": 0x18000000, + "startup": true + } + }, "sectors": [ [ 402653184, @@ -6212,8 +6309,23 @@ "release_versions": ["5"], "device_name": "R7S921053", "bootloader_supported": true, - "mbed_rom_start" : "0x50000000", - "mbed_rom_size" : "0x1000000", + + // 16MiB OSPI flash on PCB + "memory_banks": { + "EXT_FLASH": { + "access": { + "execute": true, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x1000000, // 16MiB + "start": 0x50000000, + "startup": true + } + }, "sectors": [[1342177280,4096]], "overrides": { "network-default-interface-type": "ETHERNET" @@ -8315,6 +8427,155 @@ }, "image_url": "https://os.mbed.com/media/cache/platforms/NuMaker-LoRaD-M252_V1.0_dAwfIUu.jpg.250x250_q85.jpg" }, + "MCU_M261": { + "core": "Cortex-M23", + "default_toolchain": "ARMC6", + "public": false, + "extra_labels": [ + "NUVOTON", + "M261", + "FLASH_CMSIS_ALGO" + ], + "macros": [ + "LPTICKER_DELAY_TICKS=4" + ], + "is_disk_virtual": true, + "supported_toolchains": [ + "GCC_ARM" + ], + "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, + "usb-uart": { + "help": "Configure USB_UART. USB_UART and USB_UART_TX/USB_UART_RX must be consistent.", + "value": null + }, + "usb-uart-tx": { + "help": "Configure CONSOLE_TX. USB_UART and CONSOLE_TX/CONSOLE_RX must be consistent.", + "value": null + }, + "usb-uart-rx": { + "help": "Configure CONSOLE_RX. USB_UART and CONSOLE_TX/CONSOLE_RX must be consistent.", + "value": null + }, + "stdio-uart": { + "help": "Configure STDIO_UART. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART defaults to USB_UART.", + "value": null + }, + "stdio-uart-tx": { + "help": "Configure STDIO_UART_TX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_TX defaults to CONSOLE_TX.", + "value": null + }, + "stdio-uart-rx": { + "help": "Configure STDIO_UART_RX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_RX defaults to CONSOLE_RX.", + "value": null + }, + "gpio-irq-debounce-enable": { + "help": "Enable GPIO IRQ debounce", + "value": 0 + }, + "gpio-irq-debounce-enable-list": { + "help": "Comma separated pin list to enable GPIO IRQ debounce", + "value": "NC" + }, + "gpio-irq-debounce-clock-source": { + "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC", + "value": "GPIO_DBCTL_DBCLKSRC_LIRC" + }, + "gpio-irq-debounce-sample-rate": { + "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", + "value": "GPIO_DBCTL_DBCLKSEL_16" + }, + "eadc-extsmpt-list": { + "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." + } + }, + "inherits": [ + "Target" + ], + "device_has": [ + "USTICKER", + "LPTICKER", + "RTC", + "ANALOGIN", + "ANALOGOUT", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SERIAL_ASYNCH", + "SERIAL_FC", + "SLEEP", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "TRNG", + "FLASH", + "MPU", + "WATCHDOG", + "USBDEVICE", + "CAN" + ], + "release_versions": [ + "5" + ], + "sectors": [ + [ + 0, + 2048 + ] + ], + "bootloader_supported": true, + "overrides": { + "hxt-present": false, + "lxt-present": true, + "deep-sleep-latency": 1, + "tickless-from-us-ticker": true + }, + "forced_reset_timeout": 3, + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ] + }, + "supported_application_profiles": [ + "full", "bare-metal" + ], + "is_mcu_family_target": true + }, + "NUMAKER_IOT_M263A": { + "inherits": [ + "MCU_M261" + ], + "device_name": "M263KIAAE", + "detect_code": [ + "1310" + ], + "overrides": { + "usb-uart": "UART_0", + "usb-uart-tx": "PB_13", + "usb-uart-rx": "PB_12" + }, + "image_url": "https://mm.digikey.com/Volume0/opasdata/d220001/medias/images/3720/MFG_NuMaker-IoT-M263A_V2%28F%29.jpg" + }, // ARM Fast Model (FM) Fixed Virtual Platforms (FVPs) -------------------------------------------------------------- // Unlike the MPS2 targets, which are real targets that can be run on an FPGA, Fast Models are entirely @@ -8567,8 +8828,15 @@ "CYBSP_WIFI_CAPABLE" ], "device_name": "CY8C624ABZI-D44", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x000FD800", + + // Leave 0x2000 bytes at the start of RAM for the CM0+ application + "memory_bank_config": { + "IRAM1": { + "start": 0x08002000, + "size": 0x000FD800 + } + }, + "detect_code": [ "1901" ], @@ -8612,8 +8880,15 @@ "CYBSP_WIFI_CAPABLE" ], "device_name": "CY8C624ABZI-D44", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x000FD800", + + // Leave 0x2000 bytes at the start of RAM for the CM0+ application + "memory_bank_config": { + "IRAM1": { + "start": 0x08002000, + "size": 0x000FD800 + } + }, + "detect_code": [ "190B" ], @@ -8648,8 +8923,15 @@ "CYBSP_WIFI_CAPABLE" ], "device_name": "CY8C6245LQI-S3D72", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x0003D800", + + // Leave 0x2000 bytes at the start of RAM for the CM0+ application + "memory_bank_config": { + "IRAM1": { + "start": 0x08002000, + "size": 0x0003D800 + } + }, + "detect_code": [ "190E" ], @@ -8685,8 +8967,15 @@ "CYBSP_WIFI_CAPABLE" ], "device_name": "CY8C6247BZI-D54", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x00045800", + + // Leave 0x2000 bytes at the start of RAM for the CM0+ application + "memory_bank_config": { + "IRAM1": { + "start": 0x08002000, + "size": 0x00045800 + } + }, + "detect_code": [ "1900" ], @@ -8721,8 +9010,15 @@ "CY8C6347BZI_BLD53" ], "device_name": "CY8C6347BZI-BLD53", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x00045800", + + // Leave 0x2000 bytes at the start of RAM for the CM0+ application + "memory_bank_config": { + "IRAM1": { + "start": 0x08002000, + "size": 0x00045800 + } + }, + "detect_code": [ "1902" ], @@ -8762,8 +9058,15 @@ "CYBSP_WIFI_CAPABLE" ], "device_name": "CY8C6247BZI-D54", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x00045800", + + // Leave 0x2000 bytes at the start of RAM for the CM0+ application + "memory_bank_config": { + "IRAM1": { + "start": 0x08002000, + "size": 0x00045800 + } + }, + "detect_code": [ "1900" ], @@ -8812,8 +9115,15 @@ "CYBSP_WIFI_CAPABLE" ], "device_name": "CY8C6247FDI-D52", - "mbed_ram_start": "0x08002000", - "mbed_ram_size": "0x00045800", + + // Leave 0x2000 bytes at the start of RAM for the CM0+ application + "memory_bank_config": { + "IRAM1": { + "start": 0x08002000, + "size": 0x00045800 + } + }, + "detect_code": [ "1903" ], @@ -8945,155 +9255,6 @@ "device_name": "CYB0644ABZI-S2D44", "image_url": "https://os.mbed.com/media/cache/platforms/SSP_8683_Ywwh0ix.jpg.250x250_q85.jpg" }, - "MCU_M261": { - "core": "Cortex-M23", - "default_toolchain": "ARMC6", - "public": false, - "extra_labels": [ - "NUVOTON", - "M261", - "FLASH_CMSIS_ALGO" - ], - "macros": [ - "LPTICKER_DELAY_TICKS=4" - ], - "is_disk_virtual": true, - "supported_toolchains": [ - "GCC_ARM" - ], - "config": { - "hxt-present": { - "help": "High-speed external crystal oscillator HXT is present", - "options": [false, true], - "value": false - }, - "lxt-present": { - "help": "Low-speed external crystal oscillator LXT is present", - "options": [false, true], - "value": true - }, - "usb-uart": { - "help": "Configure USB_UART. USB_UART and USB_UART_TX/USB_UART_RX must be consistent.", - "value": null - }, - "usb-uart-tx": { - "help": "Configure CONSOLE_TX. USB_UART and CONSOLE_TX/CONSOLE_RX must be consistent.", - "value": null - }, - "usb-uart-rx": { - "help": "Configure CONSOLE_RX. USB_UART and CONSOLE_TX/CONSOLE_RX must be consistent.", - "value": null - }, - "stdio-uart": { - "help": "Configure STDIO_UART. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART defaults to USB_UART.", - "value": null - }, - "stdio-uart-tx": { - "help": "Configure STDIO_UART_TX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_TX defaults to CONSOLE_TX.", - "value": null - }, - "stdio-uart-rx": { - "help": "Configure STDIO_UART_RX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_RX defaults to CONSOLE_RX.", - "value": null - }, - "gpio-irq-debounce-enable": { - "help": "Enable GPIO IRQ debounce", - "value": 0 - }, - "gpio-irq-debounce-enable-list": { - "help": "Comma separated pin list to enable GPIO IRQ debounce", - "value": "NC" - }, - "gpio-irq-debounce-clock-source": { - "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC", - "value": "GPIO_DBCTL_DBCLKSRC_LIRC" - }, - "gpio-irq-debounce-sample-rate": { - "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", - "value": "GPIO_DBCTL_DBCLKSEL_16" - }, - "eadc-extsmpt-list": { - "help": "For EADC, comma separated {pin, value} list to extend sampling time in EADC clocks on per-pin basis. Value must be in the range [0, 255]." - } - }, - "inherits": [ - "Target" - ], - "device_has": [ - "USTICKER", - "LPTICKER", - "RTC", - "ANALOGIN", - "ANALOGOUT", - "I2C", - "I2CSLAVE", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE", - "SPI_ASYNCH", - "TRNG", - "FLASH", - "MPU", - "WATCHDOG", - "USBDEVICE", - "CAN" - ], - "release_versions": [ - "5" - ], - "sectors": [ - [ - 0, - 2048 - ] - ], - "bootloader_supported": true, - "overrides": { - "hxt-present": false, - "lxt-present": true, - "deep-sleep-latency": 1, - "tickless-from-us-ticker": true - }, - "forced_reset_timeout": 3, - "supported_c_libs": { - "arm": [ - "std", - "small" - ], - "gcc_arm": [ - "std", - "small" - ] - }, - "supported_application_profiles": [ - "full", "bare-metal" - ], - "is_mcu_family_target": true - }, - "NUMAKER_IOT_M263A": { - "inherits": [ - "MCU_M261" - ], - "device_name": "M263KIAAE", - "detect_code": [ - "1310" - ], - "overrides": { - "usb-uart": "UART_0", - "usb-uart-tx": "PB_13", - "usb-uart-rx": "PB_12" - }, - "image_url": "https://mm.digikey.com/Volume0/opasdata/d220001/medias/images/3720/MFG_NuMaker-IoT-M263A_V2%28F%29.jpg" - }, // GigaDevices Targets --------------------------------------------------------------------------------------------- "GD32_Target": { diff --git a/tools/cmake/mbed_generate_configuration.cmake b/tools/cmake/mbed_generate_configuration.cmake index 977306ea044..17b5593f127 100644 --- a/tools/cmake/mbed_generate_configuration.cmake +++ b/tools/cmake/mbed_generate_configuration.cmake @@ -97,7 +97,7 @@ if(MBED_NEED_TO_RECONFIGURE) file(REMOVE ${CMAKE_CURRENT_BINARY_DIR}/mbed_config.cmake) set(MBEDTOOLS_CONFIGURE_COMMAND ${Python3_EXECUTABLE} - -c "import mbed_tools.cli.main\; exit(mbed_tools.cli.main.cli())" # This is used instead of invoking mbed_tools as a script, because it might not be on the user's PATH. + -m mbed_tools.cli.main -v # without -v, warnings (e.g. "you have tried to override a nonexistent parameter") do not get printed configure -t GCC_ARM # GCC_ARM is currently the only supported toolchain @@ -120,7 +120,7 @@ if(MBED_NEED_TO_RECONFIGURE) if((NOT MBEDTOOLS_CONFIGURE_RESULT EQUAL 0) OR (NOT EXISTS ${CMAKE_CURRENT_BINARY_DIR}/mbed_config.cmake)) string(JOIN " " MBEDTOOLS_COMMAND_SPC_SEP ${MBEDTOOLS_CONFIGURE_COMMAND}) - message(FATAL_ERROR "mbedtools configure failed! Cannot build this project. Command was ${MBEDTOOLS_COMMAND_SPC_SEP}") + message(FATAL_ERROR "mbedtools configure failed! Cannot build this project. Command was cd ${CMAKE_CURRENT_LIST_DIR}/../python && ${MBEDTOOLS_COMMAND_SPC_SEP}") endif() endif() diff --git a/tools/python/mbed_tools/build/_internal/memory_banks.py b/tools/python/mbed_tools/build/_internal/memory_banks.py new file mode 100644 index 00000000000..1edeff223e6 --- /dev/null +++ b/tools/python/mbed_tools/build/_internal/memory_banks.py @@ -0,0 +1,253 @@ +# +# Copyright (c) 2024 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 +# + +from __future__ import annotations + +from typing import TYPE_CHECKING +if TYPE_CHECKING: + from typing import Dict, Any, Set, TypedDict, NotRequired + +import copy +import logging + +import humanize + +from mbed_tools.lib.json_helpers import decode_json_file +from mbed_tools.project import MbedProgram + +from mbed_tools.build.exceptions import MbedBuildError +from mbed_tools.build._internal.config.config import Config + +logger = logging.getLogger(__name__) + + +if TYPE_CHECKING: + # Type hints for memory bank config + class MemoryBankInfo(TypedDict): + """ + Info about one memory bank + """ + size: int + start: int + default: NotRequired[bool] + startup: NotRequired[bool] + access: Dict[str, bool] + + + class BanksByType(TypedDict): + """ + Info about all memory banks, ROM and RAM + """ + ROM: Dict[str, MemoryBankInfo] + RAM: Dict[str, MemoryBankInfo] + + +# Deprecated memory configuration properties from old (Mbed CLI 1) configuration system +DEPRECATED_MEM_CONFIG_PROPERTIES = { + "mbed_rom_start", + "mbed_rom_size", + "mbed_ram_start", + "mbed_ram_size", + "mbed_rom1_start", + "mbed_rom1_size", + "mbed_ram1_start", + "mbed_ram1_size", +} + + +BANK_TYPES = ("RAM", "ROM") + + +def incorporate_memory_bank_data_from_cmsis(target_attributes: Dict[str, Any], + program: MbedProgram) -> None: + """ + Incorporate the memory bank information from the CMSIS JSON file into + the target attributes. + + :param target_attributes: Merged targets.json content for this target + """ + + if "device_name" not in target_attributes: + # No CMSIS device name for this target + return + + cmsis_mcu_descriptions = decode_json_file(program.mbed_os.cmsis_mcu_descriptions_json_file) + + if target_attributes["device_name"] not in cmsis_mcu_descriptions: + raise MbedBuildError( +f"""Target specifies device_name {target_attributes["device_name"]} but this device is not +listed in {program.mbed_os.cmsis_mcu_descriptions_json_file}. Perhaps you need to use +the 'python -m mbed_tools.cli.main cmsis-mcu-descr fetch-missing' command to download +the missing MCU description?""") + + mcu_description = cmsis_mcu_descriptions[target_attributes["device_name"]] + mcu_memory_description: Dict[str, Dict[str, Any]] = mcu_description["memories"] + + # If a memory bank is not already described in targets.json, import its description from the CMSIS + # MCU description. + target_memory_banks_section = target_attributes.get("memory_banks", {}) + for memory_bank_name, memory_bank in mcu_memory_description.items(): + if memory_bank_name not in target_memory_banks_section: + target_memory_banks_section[memory_bank_name] = memory_bank + target_attributes["memory_banks"] = target_memory_banks_section + + +def _apply_configured_overrides(banks_by_type: BanksByType, bank_config: Dict[str, Dict[str, int]]) -> BanksByType: + + """ + Apply overrides from configuration to the physical memory bank information, producing the configured + memory bank information. + :param bank_config: memory_bank_config element from target JSON + :param banks_by_type: Physical memory bank information + """ + + configured_memory_banks = copy.deepcopy(banks_by_type) + + for bank_name, bank_data in bank_config.items(): + + if bank_name not in configured_memory_banks["RAM"] and bank_name not in configured_memory_banks["ROM"]: + raise MbedBuildError(f"Attempt to configure memory bank {bank_name} which does not exist for this device.") + bank_type = "RAM" if bank_name in configured_memory_banks["RAM"] else "ROM" + + if len(set(bank_data.keys()) - {"size", "start"}): + raise MbedBuildError("Only the size and start properties of a memory bank can be " + "configured in memory_bank_config") + + for property_name, property_value in bank_data.items(): + if not isinstance(property_value, int): + raise MbedBuildError(f"Memory bank '{bank_name}': configured {property_name} must be an integer") + + configured_memory_banks[bank_type][bank_name][property_name] = property_value + + return configured_memory_banks + + +def _print_mem_bank_summary(banks_by_type: BanksByType, configured_banks_by_type: BanksByType) -> None: + + """ + Print a summary of the memory banks to the console + :param banks_by_type: Physical memory bank information + :param configured_banks_by_type: Configured memory bank information + """ + + print("Summary of available memory banks:") + for bank_type in BANK_TYPES: + banks = banks_by_type[bank_type] + + if len(banks) == 0: + logger.warning("No %s banks are known to the Mbed configuration system! This can cause problems with " + "features like Mbed Stats and FlashIAPBlockDevice! To fix this, define a 'device_name'" + " property or specify 'memory_banks' in your target JSON.", bank_type) + continue + + print(f"Target {bank_type} banks: -----------------------------------------------------------") + + for bank_index, (bank_name, bank_data) in enumerate(banks.items()): + + bank_size = bank_data["size"] + bank_start = bank_data["start"] + + configured_size = configured_banks_by_type[bank_type][bank_name]["size"] + configured_start_addr = configured_banks_by_type[bank_type][bank_name]["start"] + + # If the configured sizes are different, add info to the summary + configured_size_str = "" + configured_start_addr_str = "" + if configured_size != bank_size: + configured_size_str = f" (configured to {humanize.naturalsize(configured_size, binary=True)})" + if configured_start_addr != bank_start: + configured_start_addr_str = f" (configured to 0x{configured_start_addr:08x})" + + print(f"{bank_index}. {bank_name}, " + f"start addr 0x{bank_start:08x}{configured_start_addr_str}, " + f"size {humanize.naturalsize(bank_size, binary=True)}{configured_size_str}") + + print() + + +def _generate_macros_for_memory_banks(banks_by_type: BanksByType, + configured_banks_by_type: BanksByType) -> Set[str]: + + """ + Generate a set of macros to define to pass the memory bank information into Mbed. + :param banks_by_type: Physical memory bank information + :param configured_banks_by_type: Configured memory bank information + """ + all_macros: Set[str] = set() + + for bank_type in BANK_TYPES: + banks = banks_by_type[bank_type] + + for bank_index, (bank_name, bank_data) in enumerate(banks.items()): + + bank_number_str = "" if bank_index == 0 else str(bank_index) + + configured_bank_data = configured_banks_by_type[bank_type][bank_name] + + # Legacy numbered definitions + all_macros.add(f"MBED_{bank_type}{bank_number_str}_START=0x{bank_data['start']:x}") + all_macros.add(f"MBED_{bank_type}{bank_number_str}_SIZE=0x{bank_data['size']:x}") + + # New style named definitions + all_macros.add(f"MBED_{bank_type}_BANK_{bank_name}_START=0x{bank_data['start']:x}") + all_macros.add(f"MBED_{bank_type}_BANK_{bank_name}_SIZE=0x{bank_data['size']:x}") + + # Same as above but for configured bank + all_macros.add(f"MBED_CONFIGURED_{bank_type}{bank_number_str}_START=0x{configured_bank_data['start']:x}") + all_macros.add(f"MBED_CONFIGURED_{bank_type}{bank_number_str}_SIZE=0x{configured_bank_data['size']:x}") + all_macros.add(f"MBED_CONFIGURED_{bank_type}_BANK_{bank_name}_START=0x{configured_bank_data['start']:x}") + all_macros.add(f"MBED_CONFIGURED_{bank_type}_BANK_{bank_name}_SIZE=0x{configured_bank_data['size']:x}") + + return all_macros + + +def process_memory_banks(config: Config) -> Dict[str, BanksByType]: + """ + Process memory bank information in the config. Reads the 'memory_banks' and + 'memory_bank_config' sections and adds the memory_bank_macros section accordingly. + + :param config: Config structure containing merged data from every JSON file (app, lib, and targets) + :return: Memory bank information structure that shall be written to memory_banks.json + """ + + memory_banks = config.get("memory_banks", {}) + + # Check for deprecated properties + for property_name in DEPRECATED_MEM_CONFIG_PROPERTIES: + if property_name in config: + logger.warning("Configuration uses old-style memory bank configuration property %s. " + "This is deprecated and is not processed anymore, replace it with a " + "'memory_bank_config' section. See here for more: " + "https://github.com/mbed-ce/mbed-os/wiki/Mbed-Memory-Bank-Information", property_name) + + # Check attributes, sort into rom and ram + banks_by_type: BanksByType = {"ROM": {}, "RAM": {}} + for bank_name, bank_data in memory_banks.items(): + if "access" not in bank_data or "start" not in bank_data or "size" not in bank_data: + raise MbedBuildError(f"Memory bank '{bank_name}' must contain 'access', 'size', and 'start' elements") + if not isinstance(bank_data["size"], int) or not isinstance(bank_data["start"], int): + raise MbedBuildError(f"Memory bank '{bank_name}': start and size must be integers") + + if bank_data["access"]["read"] and bank_data["access"]["write"]: + banks_by_type["RAM"][bank_name] = bank_data + elif bank_data["access"]["read"] and bank_data["access"]["execute"]: + banks_by_type["ROM"][bank_name] = bank_data + + # Create configured memory bank structure + memory_bank_config = config.get("memory_bank_config", {}) + configured_banks_by_type = _apply_configured_overrides(banks_by_type, memory_bank_config) + + # Print summary + _print_mem_bank_summary(banks_by_type, configured_banks_by_type) + + # Generate define macros + config["memory_bank_macros"] = _generate_macros_for_memory_banks(banks_by_type, configured_banks_by_type) + + # Write out JSON file + return { + "memory_banks": banks_by_type, + "configured_memory_banks": configured_banks_by_type + } + diff --git a/tools/python/mbed_tools/build/_internal/templates/mbed_config.tmpl b/tools/python/mbed_tools/build/_internal/templates/mbed_config.tmpl index 3250a523704..f358225a2a0 100644 --- a/tools/python/mbed_tools/build/_internal/templates/mbed_config.tmpl +++ b/tools/python/mbed_tools/build/_internal/templates/mbed_config.tmpl @@ -57,24 +57,14 @@ set(MBED_TARGET_DEFINITIONS{% for component in components %} {% for form_factor in supported_form_factors %} TARGET_FF_{{form_factor}} {%- endfor %} -{% if mbed_rom_start is defined %} - MBED_ROM_START={{ mbed_rom_start | to_hex }} -{%- endif %} -{% if mbed_rom_size is defined %} - MBED_ROM_SIZE={{ mbed_rom_size | to_hex }} -{%- endif %} -{% if mbed_ram_start is defined %} - MBED_RAM_START={{ mbed_ram_start | to_hex }} -{%- endif %} -{% if mbed_ram_size is defined %} - MBED_RAM_SIZE={{ mbed_ram_size | to_hex }} -{%- endif %} TARGET_LIKE_MBED __MBED__=1 ) # config set(MBED_CONFIG_DEFINITIONS + + # Config settings {% for setting in config %} {%- if setting.macro_name -%} {%- set setting_name = setting.macro_name -%} @@ -90,7 +80,14 @@ set(MBED_CONFIG_DEFINITIONS "{{setting_name}}={{value}}" {% endif -%} {%- endfor -%} + + # Macros from JSON {% for macro in macros %} "{{macro|replace("\"", "\\\"")}}" {%- endfor %} + + # Memory bank macros +{% for macro in memory_bank_macros | sort %} + {{macro}} +{%- endfor %} ) diff --git a/tools/python/mbed_tools/build/config.py b/tools/python/mbed_tools/build/config.py index e40856410d0..7c3b7e61a9f 100644 --- a/tools/python/mbed_tools/build/config.py +++ b/tools/python/mbed_tools/build/config.py @@ -6,16 +6,19 @@ import pathlib from typing import Any, Tuple +import json from mbed_tools.lib.json_helpers import decode_json_file from mbed_tools.project import MbedProgram from mbed_tools.targets import get_target_by_name from mbed_tools.build._internal.cmake_file import render_mbed_config_cmake_template from mbed_tools.build._internal.config.assemble_build_config import Config, assemble_config +from mbed_tools.build._internal.memory_banks import incorporate_memory_bank_data_from_cmsis, process_memory_banks from mbed_tools.build._internal.write_files import write_file from mbed_tools.build.exceptions import MbedBuildError CMAKE_CONFIG_FILE = "mbed_config.cmake" +MEMORY_BANKS_JSON_FILE = "memory_banks.json" MBEDIGNORE_FILE = ".mbedignore" @@ -33,9 +36,16 @@ def generate_config(target_name: str, toolchain: str, program: MbedProgram) -> T """ targets_data = _load_raw_targets_data(program) target_build_attributes = get_target_by_name(target_name, targets_data) + incorporate_memory_bank_data_from_cmsis(target_build_attributes, program) config = assemble_config( target_build_attributes, [program.root, program.mbed_os.root], program.files.app_config_file ) + + # Process memory banks and save JSON data for other tools (e.g. memap) to use + memory_banks_json_content = process_memory_banks(config) + program.files.cmake_build_dir.mkdir(parents=True, exist_ok=True) + (program.files.cmake_build_dir / MEMORY_BANKS_JSON_FILE).write_text(json.dumps(memory_banks_json_content, indent=4)) + cmake_file_contents = render_mbed_config_cmake_template( target_name=target_name, config=config, toolchain_name=toolchain, ) diff --git a/tools/python/mbed_tools/lib/json_helpers.py b/tools/python/mbed_tools/lib/json_helpers.py index d53eeb4c1d0..740f81b92b2 100644 --- a/tools/python/mbed_tools/lib/json_helpers.py +++ b/tools/python/mbed_tools/lib/json_helpers.py @@ -4,7 +4,7 @@ # """Helpers for json related functions.""" import json -import json5 +import pyjson5 import logging from pathlib import Path @@ -25,7 +25,8 @@ def decode_json_file(path: Path) -> Any: elif path.suffix == '.json5': try: logger.debug(f"Loading JSON file {path}") - return json5.loads(path.read_text()) + with path.open() as json_file: + return pyjson5.decode_io(json_file) except ValueError: logger.error(f"Failed to decode JSON data in the file located at '{path}'") raise diff --git a/tools/python/mbed_tools/project/_internal/project_data.py b/tools/python/mbed_tools/project/_internal/project_data.py index 63a4c27e4da..e8873b97c19 100644 --- a/tools/python/mbed_tools/project/_internal/project_data.py +++ b/tools/python/mbed_tools/project/_internal/project_data.py @@ -27,6 +27,7 @@ MBED_OS_REFERENCE_FILE_NAME = "mbed-os.lib" MBED_OS_DIR_NAME = "mbed-os" TARGETS_JSON_FILE_PATH = Path("targets", "targets.json5") +CMSIS_MCU_DESCRIPTIONS_JSON_FILE_PATH = Path("targets", "cmsis_mcu_descriptions.json5") CUSTOM_TARGETS_JSON_FILE_NAME = "custom_targets.json" CUSTOM_TARGETS_JSON5_FILE_NAME = "custom_targets.json5" @@ -149,21 +150,29 @@ class MbedOS: root: Path targets_json_file: Path + cmsis_mcu_descriptions_json_file: Path @classmethod def from_existing(cls, root_path: Path, check_root_path_exists: bool = True) -> "MbedOS": """Create MbedOS from a directory containing an existing MbedOS installation.""" targets_json_file = root_path / TARGETS_JSON_FILE_PATH + cmsis_mcu_descriptions_json_file = root_path / CMSIS_MCU_DESCRIPTIONS_JSON_FILE_PATH if check_root_path_exists and not root_path.exists(): raise ValueError("The mbed-os directory does not exist.") if root_path.exists() and not targets_json_file.exists(): - raise ValueError("This MbedOS copy does not contain a targets.json file.") + raise ValueError(f"This MbedOS copy does not contain a {TARGETS_JSON_FILE_PATH} file.") - return cls(root=root_path, targets_json_file=targets_json_file) + if root_path.exists() and not cmsis_mcu_descriptions_json_file.exists(): + raise ValueError(f"This MbedOS copy does not contain a " + f"{CMSIS_MCU_DESCRIPTIONS_JSON_FILE_PATH.name} file.") + + return cls(root=root_path, targets_json_file=targets_json_file, + cmsis_mcu_descriptions_json_file=cmsis_mcu_descriptions_json_file) @classmethod def from_new(cls, root_path: Path) -> "MbedOS": """Create MbedOS from an empty or new directory.""" - return cls(root=root_path, targets_json_file=root_path / TARGETS_JSON_FILE_PATH) + return cls(root=root_path, targets_json_file=root_path / TARGETS_JSON_FILE_PATH, + cmsis_mcu_descriptions_json_file=root_path / CMSIS_MCU_DESCRIPTIONS_JSON_FILE_PATH) diff --git a/tools/python/mbed_tools/targets/_internal/targets_json_parsers/overriding_attribute_parser.py b/tools/python/mbed_tools/targets/_internal/targets_json_parsers/overriding_attribute_parser.py index 9954a846795..158f0f71036 100644 --- a/tools/python/mbed_tools/targets/_internal/targets_json_parsers/overriding_attribute_parser.py +++ b/tools/python/mbed_tools/targets/_internal/targets_json_parsers/overriding_attribute_parser.py @@ -24,7 +24,7 @@ from mbed_tools.targets._internal.targets_json_parsers.accumulating_attribute_parser import ALL_ACCUMULATING_ATTRIBUTES -MERGING_ATTRIBUTES = ("config", "overrides") +MERGING_ATTRIBUTES = ("config", "overrides", "memory_banks", "memory_overrides") NON_OVERRIDING_ATTRIBUTES = ALL_ACCUMULATING_ATTRIBUTES + ("public", "inherits") diff --git a/tools/python/pytest.ini b/tools/python/pytest.ini new file mode 100644 index 00000000000..0e7ba49fdf5 --- /dev/null +++ b/tools/python/pytest.ini @@ -0,0 +1,4 @@ +[pytest] +# Allow pytest to recurse into directories called 'build'. +# That path is ignored by default. +norecursedirs = \ No newline at end of file diff --git a/tools/python/python_tests/mbed_tools/build/__init__.py b/tools/python/python_tests/mbed_tools/build/__init__.py new file mode 100644 index 00000000000..9c276726b5f --- /dev/null +++ b/tools/python/python_tests/mbed_tools/build/__init__.py @@ -0,0 +1,4 @@ +# +# Copyright (c) 2024 Jamie Smith. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# \ No newline at end of file diff --git a/tools/python/python_tests/mbed_tools/build/_internal/__init__.py b/tools/python/python_tests/mbed_tools/build/_internal/__init__.py new file mode 100644 index 00000000000..9c276726b5f --- /dev/null +++ b/tools/python/python_tests/mbed_tools/build/_internal/__init__.py @@ -0,0 +1,4 @@ +# +# Copyright (c) 2024 Jamie Smith. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# \ No newline at end of file diff --git a/tools/python/python_tests/mbed_tools/build/_internal/test_memory_banks.py b/tools/python/python_tests/mbed_tools/build/_internal/test_memory_banks.py new file mode 100644 index 00000000000..01bc2f352b9 --- /dev/null +++ b/tools/python/python_tests/mbed_tools/build/_internal/test_memory_banks.py @@ -0,0 +1,260 @@ +# +# Copyright (c) 2024 Jamie Smith. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# + +from mbed_tools.build._internal.memory_banks import process_memory_banks + + +class TestMemoryBankProcessing: + def test_simple_memory_layout(self): + """ + Test a simple memory layout to ensure we process it correctly. + """ + + # Note: process_memory_banks() accepts a Config object, but that's just a + # subclass of Dict, so we can pass in a dict in the test and get away with it. + config = { + # Real snippet from cmsis_mcu_descriptions.json + "memory_banks": { + "IRAM1": { + "access": { + "execute": True, + "non_secure": False, + "non_secure_callable": False, + "peripheral": False, + "read": True, + "secure": False, + "write": True + }, + "default": True, + "size": 0x100000, + "start": 0x08000000, + "startup": False + }, + "IROM1": { + "access": { + "execute": True, + "non_secure": False, + "non_secure_callable": False, + "peripheral": False, + "read": True, + "secure": False, + "write": False + }, + "default": True, + "size": 0x200000, + "start": 0x10000000, + "startup": True + } + } + } + + process_memory_banks(config) + + assert config["memory_bank_macros"] == { + # New style definitions (ROM) + 'MBED_ROM_BANK_IROM1_START=0x10000000', + 'MBED_ROM_BANK_IROM1_SIZE=0x200000', + 'MBED_CONFIGURED_ROM_BANK_IROM1_START=0x10000000', + 'MBED_CONFIGURED_ROM_BANK_IROM1_SIZE=0x200000', + + # Old style definitions (ROM) + 'MBED_ROM_START=0x10000000', + 'MBED_ROM_SIZE=0x200000', + 'MBED_CONFIGURED_ROM_START=0x10000000', + 'MBED_CONFIGURED_ROM_SIZE=0x200000', + + # New style definitions (RAM) + 'MBED_RAM_BANK_IRAM1_START=0x8000000', + 'MBED_RAM_BANK_IRAM1_SIZE=0x100000', + 'MBED_CONFIGURED_RAM_BANK_IRAM1_START=0x8000000', + 'MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE=0x100000', + + # Old style definitions (RAM) + 'MBED_RAM_START=0x8000000', + 'MBED_RAM_SIZE=0x100000', + 'MBED_CONFIGURED_RAM_START=0x8000000', + 'MBED_CONFIGURED_RAM_SIZE=0x100000', + } + + def test_memory_configuration(self): + """ + Test configuring the size and address of a memory bank + """ + + # Note: process_memory_banks() accepts a Config object, but that's just a + # subclass of Dict, so we can pass in a dict in the test and get away with it. + config = { + # Real snippet from cmsis_mcu_descriptions.json + "memory_banks": { + "IRAM1": { + "access": { + "execute": True, + "non_secure": False, + "non_secure_callable": False, + "peripheral": False, + "read": True, + "secure": False, + "write": True + }, + "default": True, + "size": 0x100000, + "start": 0x08000000, + "startup": False + }, + "IROM1": { + "access": { + "execute": True, + "non_secure": False, + "non_secure_callable": False, + "peripheral": False, + "read": True, + "secure": False, + "write": False + }, + "default": True, + "size": 0x200000, + "start": 0x10000000, + "startup": True + } + }, + "memory_bank_config": { + "IRAM1": { + # Configure size only + "size": 0xa0000, + }, + "IROM1": { + # Configure size and address + "size": 0x1f0000, + "start": 0x10010000 + } + } + } + + process_memory_banks(config) + + assert config["memory_bank_macros"] == { + # New style definitions (ROM) + 'MBED_ROM_BANK_IROM1_START=0x10000000', + 'MBED_ROM_BANK_IROM1_SIZE=0x200000', + 'MBED_CONFIGURED_ROM_BANK_IROM1_START=0x10010000', + 'MBED_CONFIGURED_ROM_BANK_IROM1_SIZE=0x1f0000', + + # Old style definitions (ROM) + 'MBED_ROM_START=0x10000000', + 'MBED_ROM_SIZE=0x200000', + 'MBED_CONFIGURED_ROM_START=0x10010000', + 'MBED_CONFIGURED_ROM_SIZE=0x1f0000', + + # New style definitions (RAM) + 'MBED_RAM_BANK_IRAM1_START=0x8000000', + 'MBED_RAM_BANK_IRAM1_SIZE=0x100000', + 'MBED_CONFIGURED_RAM_BANK_IRAM1_START=0x8000000', + 'MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE=0xa0000', + + # Old style definitions (RAM) + 'MBED_RAM_START=0x8000000', + 'MBED_RAM_SIZE=0x100000', + 'MBED_CONFIGURED_RAM_START=0x8000000', + 'MBED_CONFIGURED_RAM_SIZE=0xa0000', + } + + def test_two_ram_banks(self): + """ + Test to see if two RAM banks are handled correctly. + """ + + # Note: process_memory_banks() accepts a Config object, but that's just a + # subclass of Dict, so we can pass in a dict in the test and get away with it. + config = { + "memory_banks": { + "IRAM1": { + "access": { + "execute": True, + "non_secure": False, + "non_secure_callable": False, + "peripheral": False, + "read": True, + "secure": False, + "write": True + }, + "default": True, + "size": 0x100000, + "start": 0x08000000, + "startup": False + }, + "IRAM2": { + "access": { + "execute": True, + "non_secure": False, + "non_secure_callable": False, + "peripheral": False, + "read": True, + "secure": False, + "write": True + }, + "default": False, + "size": 0x400000, + "start": 0x08100000, + "startup": False + }, + "IROM1": { + "access": { + "execute": True, + "non_secure": False, + "non_secure_callable": False, + "peripheral": False, + "read": True, + "secure": False, + "write": False + }, + "default": True, + "size": 0x200000, + "start": 0x10000000, + "startup": True + } + } + } + + process_memory_banks(config) + + # Note: IRAM2 should become MBED_RAM1 because it is listed second + # in the dictionary + assert config["memory_bank_macros"] == { + # New style definitions (ROM) + 'MBED_ROM_BANK_IROM1_START=0x10000000', + 'MBED_ROM_BANK_IROM1_SIZE=0x200000', + 'MBED_CONFIGURED_ROM_BANK_IROM1_START=0x10000000', + 'MBED_CONFIGURED_ROM_BANK_IROM1_SIZE=0x200000', + + # Old style definitions (ROM) + 'MBED_ROM_START=0x10000000', + 'MBED_ROM_SIZE=0x200000', + 'MBED_CONFIGURED_ROM_START=0x10000000', + 'MBED_CONFIGURED_ROM_SIZE=0x200000', + + # New style definitions (RAM) + 'MBED_RAM_BANK_IRAM1_START=0x8000000', + 'MBED_RAM_BANK_IRAM1_SIZE=0x100000', + 'MBED_CONFIGURED_RAM_BANK_IRAM1_START=0x8000000', + 'MBED_CONFIGURED_RAM_BANK_IRAM1_SIZE=0x100000', + + # Old style definitions (RAM) + 'MBED_RAM_START=0x8000000', + 'MBED_RAM_SIZE=0x100000', + 'MBED_CONFIGURED_RAM_START=0x8000000', + 'MBED_CONFIGURED_RAM_SIZE=0x100000', + + # New style definitions (RAM 2) + 'MBED_RAM_BANK_IRAM2_START=0x8100000', + 'MBED_RAM_BANK_IRAM2_SIZE=0x400000', + 'MBED_CONFIGURED_RAM_BANK_IRAM2_START=0x8100000', + 'MBED_CONFIGURED_RAM_BANK_IRAM2_SIZE=0x400000', + + # Old style definitions (RAM 2) + 'MBED_RAM1_START=0x8100000', + 'MBED_RAM1_SIZE=0x400000', + 'MBED_CONFIGURED_RAM1_START=0x8100000', + 'MBED_CONFIGURED_RAM1_SIZE=0x400000', + } diff --git a/tools/python/python_tests/mbed_tools/lib/test_json_helpers.py b/tools/python/python_tests/mbed_tools/lib/test_json_helpers.py index 6f99a011409..4882c88fd39 100644 --- a/tools/python/python_tests/mbed_tools/lib/test_json_helpers.py +++ b/tools/python/python_tests/mbed_tools/lib/test_json_helpers.py @@ -3,6 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 # import json +from pyjson5 import pyjson5 import pytest @@ -21,5 +22,5 @@ def test_invalid_json5(tmp_path): lib_json_path = tmp_path / "mbed_lib.json5" lib_json_path.write_text("name") - with pytest.raises(ValueError): + with pytest.raises(pyjson5.Json5Exception): decode_json_file(lib_json_path) diff --git a/tools/python/python_tests/mbed_tools/project/factories.py b/tools/python/python_tests/mbed_tools/project/factories.py index 34402c619e7..8a188b918d9 100644 --- a/tools/python/python_tests/mbed_tools/project/factories.py +++ b/tools/python/python_tests/mbed_tools/project/factories.py @@ -43,3 +43,4 @@ def make_mbed_os_files(root): targets_dir = root / "targets" targets_dir.mkdir() (targets_dir / "targets.json5").touch() + (targets_dir / "cmsis_mcu_descriptions.json5").touch() diff --git a/tools/python/python_tests/mbed_tools/regression/test_configure.py b/tools/python/python_tests/mbed_tools/regression/test_configure.py index a538ebec172..859bea97058 100644 --- a/tools/python/python_tests/mbed_tools/regression/test_configure.py +++ b/tools/python/python_tests/mbed_tools/regression/test_configure.py @@ -52,6 +52,7 @@ def test_generate_config_called_with_correct_arguments(self): pathlib.Path(tmpDirPath / "mbed-os").mkdir() pathlib.Path(tmpDirPath / "mbed-os" / "targets").mkdir() pathlib.Path(tmpDirPath / "mbed-os" / "targets" / "targets.json5").write_text(target_json) + pathlib.Path(tmpDirPath / "mbed-os" / "targets" / "cmsis_mcu_descriptions.json5").write_text("{}") result = CliRunner().invoke( configure, ["-m", "Target", "-t", "gcc_arm", "-p", tmpDir], catch_exceptions=False diff --git a/tools/requirements.txt b/tools/requirements.txt index e72058494cd..37ea676da57 100644 --- a/tools/requirements.txt +++ b/tools/requirements.txt @@ -20,7 +20,7 @@ junit-xml>=1.0,<2.0 lockfile six>=1.0,<2.0 colorama>=0.3,<0.5 -json5 +pyjson5~=1.6 humanize~=4.9.0 # Install pyocd so that it's available in the venv if the user chooses to use it